CN112582479A - Thin film transistor with top gate structure and manufacturing method - Google Patents

Thin film transistor with top gate structure and manufacturing method Download PDF

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Publication number
CN112582479A
CN112582479A CN202011607516.4A CN202011607516A CN112582479A CN 112582479 A CN112582479 A CN 112582479A CN 202011607516 A CN202011607516 A CN 202011607516A CN 112582479 A CN112582479 A CN 112582479A
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layer
hole
gate
region
source
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温质康
乔小平
苏智昱
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Abstract

The invention discloses a thin film transistor with a top gate structure and a manufacturing method thereof, wherein the thin film transistor comprises an active layer, a gate insulating layer, a gate layer, a dielectric layer, a source layer, a drain layer and a gate compensation layer; the gate insulating layer is disposed on the active layer; the top of the gate insulating layer comprises a first region, a second region and a third region, the gate layer is arranged on the first region, and the gate compensation layer is arranged on the third region; the dielectric layer is arranged on the grid electrode layer and the grid electrode insulating layer, and a first hole and a second hole are formed in the dielectric layer; the source electrode layer and the drain electrode layer are respectively arranged on the dielectric layer, the source electrode layer is connected with the source layer through a first hole in the dielectric layer, and the drain electrode layer is connected with the source layer through a second hole in the dielectric layer. The technical scheme optimizes the electrical characteristics of the thin film transistor, improves the stability of the thin film transistor, and improves the regulation and control of the gate layer on the lower active layer.

Description

Thin film transistor with top gate structure and manufacturing method
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor with a top gate structure and a manufacturing method thereof.
Background
An Organic Light Emitting Diode (abbreviated as OLED) display device has the characteristics of low power consumption, wide viewing angle, fast response speed, ultra-Light and thin profile, good shock resistance, and the like, and is considered as a display device with the most potential development by the industry.
A driving Thin Film Transistor (abbreviated TFT) of the OLED display device is frequently used for a Thin Film Transistor of a top gate structure because the Thin Film Transistor of the top gate structure has a low parasitic capacitance and excellent electrical characteristics.
In the manufacturing process of the traditional thin film transistor device with the top gate structure, a self-alignment process of a gate layer and a gate insulating layer is adopted. The pattern of the gate electrode layer is usually made by a wet etching process, and the pattern of the gate insulating layer is usually made by a dry etching process. When the grid metal layer is etched by the wet etching process, the grid electrode layer exposed at the side edge can be etched by the etching liquid, and when the grid insulating layer is etched by the dry method, the process gas Cl is used2The gate layer without the photoresist covering the side edges is also corroded, so that the gate layer is shorter than the gate insulating layer in a direction parallel to the substrate by a certain distance, namely the orthographic projections of the gate layer and the gate insulating layer on the substrate cannot be completely overlapped. Because the two sides above the gate insulating layer are provided with a small section of gate layer, for the active layer below the gate insulating layer which is not covered by the gate layer, the gate layer is not easy to regulate and control the active layer, so that the starting current of the thin film transistor of the top gate structure is insufficient, the stability of the thin film transistor is influenced, and the display effect of the display device is also influenced.
Disclosure of Invention
Therefore, it is desirable to provide a thin film transistor with a top gate structure and a method for fabricating the same, which solve the problem of insufficient control force of the gate layer on the active layer due to the fact that the gate layer is shorter than the gate insulating layer by a distance in a direction parallel to the substrate.
In order to achieve the above object, the present embodiment provides a thin film transistor with a top gate structure, which includes an active layer, a gate insulating layer, a gate layer, a dielectric layer, a source layer, a drain layer, and a gate compensation layer;
the grid electrode insulating layer is arranged on the active layer, the projection of the grid electrode insulating layer is positioned in the projection of the active layer, and the direction of the projection is perpendicular to the active layer;
the top of the gate insulating layer comprises a first region, a second region and a third region, the first region is arranged in the middle of the top of the gate insulating layer, the second region surrounds the second region, the third region surrounds the second region, the gate layer is arranged on the first region, and the gate compensation layer is arranged on the third region;
the dielectric layer is arranged on the gate electrode layer and the gate insulating layer, a first hole and a second hole are arranged on the dielectric layer, the first hole is positioned on one side of the gate insulating layer, the hole bottom of the first hole is a source electrode layer, the second hole is positioned on the other side of the gate insulating layer, and the hole bottom of the second hole is a drain electrode layer;
the source electrode layer and the drain electrode layer are respectively arranged on the dielectric layer, the source electrode layer is connected with the source layer through a first hole in the dielectric layer, and the drain electrode layer is connected with the source layer through a second hole in the dielectric layer.
Further, the light-shielding layer comprises a substrate, a light-shielding layer and a buffer layer;
the light shielding layer is arranged on the substrate, and the projection of the active layer is positioned in the projection of the light shielding layer;
the buffer layer is disposed on the light-shielding layer, and the active layer is disposed on the buffer layer.
Further, the source layer is connected with the light shielding layer; or: the drain electrode layer is connected with the shading layer.
Further, a flat layer is also included;
the planarization layer is disposed on the gate compensation layer, the gate layer, the dielectric layer, the source layer, and the drain layer.
Further, the electrode layer is also included;
a third hole is formed in the flat layer, and a source electrode layer or a drain electrode layer is arranged at the bottom of the third hole;
the electrode layer is disposed on the planarization layer, and the electrode layer is connected to the source electrode layer or the drain electrode layer through a third hole.
Further, a sum of a projection of the gate compensation layer, a projection of the gate layer, and a projection of the second region is equal to a projection of the gate insulating layer.
The embodiment also provides a manufacturing method of a thin film transistor with a top gate structure, which comprises the following steps:
manufacturing an active layer on a substrate;
depositing an insulating layer, etching the insulating layer through dry etching, and forming a gate insulating layer on an active layer, wherein the gate insulating layer is arranged on the active layer, the projection of the gate insulating layer is positioned in the projection of the active layer, and the direction of the projection is vertical to the active layer;
depositing a grid metal layer, etching the grid metal layer through wet etching, and forming a grid layer on a grid insulating layer, wherein the grid layer is arranged in the middle of the grid insulating layer;
manufacturing a dielectric layer, wherein the dielectric layer covers the grid electrode layer, the grid electrode insulating layer and the active layer;
manufacturing a first hole, a second hole and a fourth hole on a dielectric layer, wherein the first hole is positioned on one side of a gate insulating layer, the bottom of the first hole is a source electrode layer, the second hole is positioned on the other side of the gate insulating layer, the bottom of the second hole is a drain electrode layer, the fourth hole is positioned on one side of a gate electrode layer, the bottom of the fourth hole is the gate insulating layer, and a gap is formed between the fourth hole and the gate electrode layer;
and simultaneously manufacturing a source electrode layer, a drain electrode layer and a grid electrode compensation layer, wherein the source electrode layer is connected with an active layer through a first hole in the dielectric layer, the drain electrode layer is connected with the active layer through a second hole in the dielectric layer, and the grid electrode compensation layer is connected with the grid electrode insulation layer through a fourth hole in the dielectric layer.
Further, before the step of manufacturing the active layer on the substrate, the method further comprises the following steps:
firstly, manufacturing a shading layer on a substrate, wherein the projection of the active layer is positioned in the projection of the shading layer;
then, manufacturing a buffer layer, wherein the buffer layer covers the shading layer;
and finally, manufacturing an active layer on the buffer layer.
Further, the source layer is connected with the light shielding layer; or: the drain electrode layer is connected with the shading layer.
Further, the method also comprises the following steps:
manufacturing a flat layer, wherein the flat layer is arranged on the grid compensation layer, the source electrode layer, the drain electrode layer and the dielectric layer;
manufacturing a third hole on the flat layer, wherein the bottom of the third hole is a source electrode layer or a drain electrode layer;
and manufacturing an electrode layer which is connected with the source electrode layer or the drain electrode layer through the third hole.
Different from the prior art, according to the technical scheme, the grid electrode compensation layer is added outside the grid electrode layer, the grid electrode layer is arranged in the inner circle area of the grid electrode insulation layer, the grid electrode compensation layer covers the outer circle area of the grid electrode insulation layer, and the grid electrode insulation layer is prevented from exposing the outer side wall of the grid electrode compensation layer. The structure optimizes the electrical characteristics of the thin film transistor, improves the stability of the thin film transistor, improves the regulation and control of the gate layer on the lower active layer, and solves the problem that the thin film transistor cannot be started due to too low starting current.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a thin film transistor according to the present embodiment;
FIG. 2 is a schematic cross-sectional view illustrating a gate insulating layer formed on a substrate according to the present embodiment;
FIG. 3 is a schematic cross-sectional view illustrating a gate layer formed on a substrate according to the present embodiment;
FIG. 4 is a schematic cross-sectional view illustrating a dielectric layer formed on a substrate according to the present embodiment;
fig. 5 is a schematic cross-sectional view illustrating a source layer, a drain layer and a gate compensation layer formed on a substrate according to the present embodiment.
Description of reference numerals:
1. a substrate;
2. a light-shielding layer;
3. a buffer layer;
4. an active layer;
5. a gate insulating layer;
51. a first region;
52. a third region;
6. a gate layer;
7. a dielectric layer;
71. a first hole;
72. a second hole;
8. a gate compensation layer;
9. a source layer;
10. a drain layer;
11. a planarization layer;
12. and an electrode layer.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1, the present embodiment provides a thin film transistor with a top gate structure, which includes an active layer 4, a gate insulating layer 5, a gate layer 6, a dielectric layer 7, a source layer 9, a drain layer 10, and a gate compensation layer 8. The gate insulating layer 5 is disposed on the active layer 4, and the gate insulating layer 5 serves as an insulator. The projection of the gate insulating layer 5 is located in the projection of the active layer 4, the direction of the projection being perpendicular to the active layer 4, which is also perpendicular to the substrate 1. The size of the gate insulating layer 5 is smaller than that of the active layer 4, and the outer side of the active layer 4 is the outer side wall where the gate insulating layer 5 is exposed in the direction perpendicular to the active layer. The gate electrode layer 6 and the gate compensation layer 8 are both disposed on the gate insulating layer 5. The top of the gate insulating layer 5 comprises a first region 51, a second region and a third region 52, the first region 51 is arranged in the middle of the top of the gate insulating layer 5, the second region is arranged around the second region, the third region 52 is arranged around the second region, the gate layer 6 is arranged on the first region 51, and the gate compensation layer 8 is arranged on the third region 52. Namely, the gate compensation layer 8 surrounds the gate layer 6, and the gate compensation layer 8 and the gate layer 6 have a space. The dielectric layer 7 is disposed on the gate electrode layer 6 and the gate insulating layer 5. The dielectric layer 7 is provided with a first hole 71 and a second hole 72, and the first hole 71 and the second hole 72 serve as connection points between the film layers. The first hole 71 is located at one side of the gate insulating layer 5, the first hole 71 is located in the region of the active layer 4 beyond the gate insulating layer 5, and the bottom of the first hole 71 is the source layer 9. The second hole 72 is located at the other side of the gate insulating layer 5, the second hole 72 is also located in the region of the active layer 4 beyond the gate insulating layer 5, and the bottom of the second hole 72 is the drain layer 10. The source layer 9 and the drain layer 10 are respectively disposed on the dielectric layer 7, the source layer 9 is connected to the source layer 4 through a first hole 71 on the dielectric layer 7, and the drain layer 10 is connected to the source layer 4 through a second hole 72 on the dielectric layer 7.
Because the size of the gate insulating layer is larger than that of the gate layer due to the influence of the manufacturing process, for the active layer below the gate insulating layer which is not covered by the gate layer, the gate layer is not easy to regulate and control to the active layer, so that the starting current of the thin film transistor with the top gate structure is insufficient, and the stability of the thin film transistor is influenced. According to the technical scheme, the grid electrode compensation layer is added outside the grid electrode layer, the grid electrode layer is arranged in the inner ring area of the grid electrode insulation layer, the grid electrode compensation layer covers the outer ring area of the grid electrode insulation layer, and the grid electrode insulation layer is prevented from being exposed out of the outer side wall of the grid electrode compensation layer. The structure optimizes the electrical characteristics of the thin film transistor, improves the stability of the thin film transistor, improves the regulation and control of the gate layer on the lower active layer, and solves the problem that the thin film transistor cannot be started due to too low starting current.
The cross section of the first region is circular, rectangular, oval, triangular, polygonal, or the like. The shape of the second area is adapted to the shape of the first area in that the inner side of the second area is the outer side of the first area. Similarly, the inner side of the third region is the outer side of the second region, and the outer side of the third region is the boundary of the top of the gate insulating layer. Preferably, the first region has a circular cross-sectional shape, in which case the second and third regions are both annular.
In the present embodiment, the width of the second region is 16um (micrometers) to 32um (micrometers). Preferably, the width of the second region is 24 um.
It should be noted that the material of the active layer may be a metal oxide, such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Titanium Oxide (IGZTO), graphene, and the like, but is not limited thereto. The thickness of the active layer is 0.03um (micrometer) to 0.06um (micrometer). Preferably, the thickness of the active layer is 0.04 um.
The material of the gate insulating layer may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), or the like. The thickness of the gate insulating layer is 0.3um (micrometer) to 0.5um (micrometer). Preferably, the thickness of the gate insulating layer is 0.4 um.
The material of the gate layer may be a Mo (molybdenum)/Cu (copper) stack, a MoTi (molybdenum titanium)/Cu (copper) stack, or a metal having excellent conductivity, such as aluminum, silver, or chromium, but is not limited thereto. If the grid layer is a Mo/Cu laminated layer, the thickness of Mo is 0.02 um-0.05 um, the thickness of Cu is 0.4 um-0.6 um, preferably, the thickness of Mo is 0.03um, and the thickness of Cu is 0.5 um. If the gate layer is a stack of MoTi/Cu, the thickness of MoTi is 0.02um to 0.05um and the thickness of Cu is 0.4um to 0.6um, preferably, the thickness of MoTi is 0.03um and the thickness of Cu is 0.5 um.
Note that the source layer and the drain layer are commonly provided, and the material of both the source layer and the drain layer is the same. The material of the source layer may be a Mo (molybdenum)/Cu (copper) stack, a MoTi (molybdenum titanium)/Cu (copper) stack, or a metal having excellent conductivity, such as aluminum, silver, or chromium, but is not limited thereto. If the source layer is a Mo/Cu stack, the thickness of Mo is 0.02 um-0.05 um, the thickness of Cu is 0.4 um-0.6 um, preferably, the thickness of Mo is 0.03um, and the thickness of Cu is 0.5 um. If the source layer is a stack of MoTi/Cu, the thickness of MoTi is 0.02um to 0.05um and the thickness of Cu is 0.4um to 0.6um, preferably, the thickness of MoTi is 0.03um and the thickness of Cu is 0.5 um.
The material of the dielectric layer may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), or the like. The dielectric layer has a thickness of 0.3um (micrometers) to 0.5um (micrometers). Preferably, the dielectric layer has a thickness of 0.4 um.
In a preferred embodiment, the sum of the projection of the gate compensation layer, the projection of the gate layer and the projection of the second region is equal to the projection of the gate insulating layer. The gate insulating layer may have an inclined outer sidewall or a vertical outer sidewall due to the etching process, and preferably the gate insulating layer has an outer sidewall perpendicular to the substrate. Similarly, the gate compensation layer preferably has an outer sidewall perpendicular to the substrate.
In the present embodiment, the substrate 1 is a member carrying a thin film transistor, and the material of the substrate 1 may be gallium arsenide, glass, or the like. The thin film transistor is arranged on the substrate 1, and the active layer can be directly arranged on the substrate 1, and the structure is shown in fig. 1. The dielectric layer covers the active layer, the drain layer and the source layer below, and the dielectric layer can be arranged on the substrate 1.
In this embodiment, because the stability of the thin film transistor is reduced after the active layer is exposed to light, the thin film transistor further includes a light shielding layer 2 and a buffer layer 3, the buffer layer 3 plays an insulating role, the light shielding layer 2 plays a role in preventing light from irradiating the active layer 4, and the structure is as shown in fig. 1. The light shielding layer 2 is arranged on the substrate 1, and the projection of the active layer 4 is positioned in the projection of the light shielding layer 2, and the projection direction is also vertical to the active layer. The size of the light shielding layer is larger than that of the active layer, and the light shielding layer can shield the light emitted from the substrate direction and prevent the active layer from being irradiated by the light emitted from the substrate direction. The buffer layer 3 is disposed on the light-shielding layer, and the active layer is disposed on the buffer layer 3. The active layer and the dielectric layer are disposed on the buffer layer 3.
The light shielding layer may be a metal film layer, such as molybdenum, aluminum, silver, copper, etc., but is not limited thereto. The metal film layer has better light shielding performance and can shield light. The thickness of the light-shielding layer is 0.1um (micrometer) to 0.2um (micrometer). Preferably, the light-shielding layer has a thickness of 0.15 um.
The material of the buffer layer may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), or the like. The buffer layer has a thickness of 0.3um (micrometers) to 0.5um (micrometers). Preferably, the buffer layer has a thickness of 0.4 um.
The source layer is connected to the light-shielding layer; or: the drain electrode layer is connected with the shading layer. One of the source layer and the drain layer is connected to the light-shielding layer, and the structure is shown in fig. 1.
In the present embodiment, in order to protect the underlying gate layer, source layer, and drain layer, a planarization layer 11 is further included, and the structure is shown in fig. 1. The planarization layer 11 is disposed on the gate compensation layer, the gate layer, the dielectric layer, the source layer, and the drain layer. The planarization layer 11 may be made of an insulating material, thereby serving as an electrical connection between the isolation metals. By covering a flat layer, the film layer which is already manufactured below can be protected from being influenced by subsequent processes.
The material of the planarization layer may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), or the like. The thickness of the flat layer is 0.3um (micrometer) to 0.5um (micrometer). Preferably, the buffer layer has a thickness of 0.4 um.
In a further embodiment, in order to connect the thin film transistor to an external structure, an electrode layer 12 is further included, and the structure is shown in fig. 1. A third hole is arranged on the flat layer 11, and the bottom of the third hole is a source electrode layer 9 or a drain electrode layer 10. The electrode layer 12 is disposed on the planarization layer 11, and the electrode layer 12 is connected to the source electrode layer 9 or the drain electrode layer 10 through a third hole. If the source layer 9 is connected with the light shielding layer, the drain layer 10 is connected with the electrode layer 12, and the structure is shown in FIG. 1; if the drain layer 10 is already connected to the light-shielding layer, it is connected by the source layer 9 and the electrode layer 12. The external structure is communicated with the thin film transistor through the electrode layer, and the thin film transistor is used as a switch to drive the liquid crystal pixel point to achieve high speed, high brightness and high contrast.
The material of the electrode layer may be Indium Tin Oxide (ITO), zinc aluminum oxide (AZO), Indium Zinc Oxide (IZO), but is not limited thereto. The thickness of the electrode layer is 0.05 um-0.08 um, preferably, the thickness of the electrode layer is 0.075 um.
This embodiment provides a display device including the thin film transistor with the top gate structure according to any one of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator and the like. Preferably, the display device is an OLED display device. In certain embodiments, the display device is an LCD display device.
Referring to fig. 1 to 5, the present embodiment further provides a method for fabricating a thin film transistor with a top gate structure, wherein the method is fabricated on a substrate 1. The material of the substrate 1 may be gallium arsenide, glass, or the like. The method comprises the following steps: a light-shielding layer is formed on the substrate to prevent light from irradiating the active layer, and the structure is shown in fig. 2. A layer of metal is deposited on the substrate 1 by evaporation, sputtering, etc. The material of the layer of metal may be molybdenum, aluminum, silver, copper, etc., but is not limited thereto. This layer metal forms light shield layer 2 through the etching, and light shield layer 2 has better light shielding nature, can shelter from light, avoids the active layer to suffer to make thin-film transistor's stability decline after the illumination.
After the light shielding layer is manufactured, a buffer layer is manufactured on the light shielding layer and used for isolating the electric connection between the light shielding layer and other irrelevant metal film layers, and the structure is shown in fig. 2. Specifically, a layer of insulating material is deposited on the substrate, and the insulating material is exposed and etched as appropriate, forming the buffer layer 3 on the light-shielding layer. The buffer layer 3 covers the light-shielding layer and extends to the substrate. The material of the buffer layer may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), or the like. The buffer layer has a thickness of 0.3um (micrometers) to 0.5um (micrometers). Preferably, the buffer layer has a thickness of 0.4 um.
After the buffer layer is manufactured, an active layer is manufactured on the buffer layer, and the structure is shown in fig. 2. Specifically, a layer of metal oxide is plated on the substrate by physical vapor deposition, and the metal oxide may be Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Titanium Oxide (IGZTO), graphene, or the like, but is not limited thereto. The metal oxide is etched to form an active layer 4, and the active layer 4 is located on the buffer layer. The projection of the active layer 4 is located in the projection of the light-shielding layer 2, the projection direction being perpendicular to the active layer. The light-shielding layer can shield the active layer. The thickness of the active layer is 0.03um (micrometer) to 0.06um (micrometer). Preferably, the thickness of the active layer is 0.04 um.
After the active layer is manufactured, a gate insulating layer is manufactured on the active layer and used for isolating the electrical connection between the gate layer and the active layer, and the structure is shown in fig. 3. Specifically, a layer of insulating material (i.e., an insulating layer) which may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), etc., is deposited on the substrate by a vapor deposition method of plasma enhanced chemical. The insulating material is exposed to light and etched, which may be dry etching, to form a gate insulating layer 5 on the active layer. The projection of the gate insulating layer 5 is located in the projection of the active layer 4, the direction of the projection being perpendicular to the active layer. The thickness of the gate insulating layer is 0.3um (micrometer) to 0.5um (micrometer). Preferably, the thickness of the gate insulating layer is 0.4 um.
In a preferred embodiment, the gate insulating layer may be etched by means of anisotropic etching such that the sidewalls of the gate insulating layer are perpendicular to the active layer.
After the gate insulating layer is formed, a gate layer is formed on the gate insulating layer, and the structure is shown in fig. 3. Specifically, a metal layer (i.e., a gate metal layer) is plated on the substrate by a physical vapor deposition method, and then the gate metal layer is wet-etched to form the gate electrode layer 6. The gate layer 6 is not covered by the gate insulating layer due to wet etching, so that the peripheral region of the gate insulating layer 5 is exposed to the outer sidewall of the gate layer 6, which results in insufficient on-current of the top-gate tft, and the stability of the tft is affected.
The material of the gate layer may be a Mo (molybdenum)/Cu (copper) stack, a MoTi (molybdenum titanium)/Cu (copper) stack, or a metal having excellent conductivity, such as aluminum, silver, or chromium, but is not limited thereto. If the grid layer is a Mo/Cu laminated layer, the thickness of Mo is 0.02 um-0.05 um, the thickness of Cu is 0.4 um-0.6 um, preferably, the thickness of Mo is 0.03um, and the thickness of Cu is 0.5 um. If the gate layer is a stack of MoTi/Cu, the thickness of MoTi is 0.02um to 0.05um and the thickness of Cu is 0.4um to 0.6um, preferably, the thickness of MoTi is 0.03um and the thickness of Cu is 0.5 um.
After the gate layer is manufactured, a dielectric layer is covered, and the dielectric layer also plays an isolation role, and the structure is shown in fig. 4. Specifically, a layer of insulating material, which may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), etc., is deposited on the substrate by a plasma enhanced chemical vapor deposition method. The insulating material is exposed and etched to form a dielectric layer 7 on the active layer. For effective protection, the dielectric layer 7 covers the gate electrode layer, the gate insulating layer, the active layer and the buffer layer. The dielectric layer has a thickness of 0.3um (micrometers) to 0.5um (micrometers). Preferably, the dielectric layer has a thickness of 0.4 um.
After the dielectric layer is formed, a first hole, a second hole, a fourth hole and a fifth hole are formed in the dielectric layer, the first hole serves as a connection point between the source layer and the active layer, the second hole serves as a connection point between the drain layer and the active layer, the fourth hole serves as a connection point between the gate compensation layer and the gate insulating layer, and the fifth hole serves as a connection point between the source layer or the drain layer and the light-shielding layer, and the structure is as shown in fig. 4. The step of forming the hole may be etching the dielectric layer by an etching process using the photoresist as a mask. Or the holes may be made by laser drilling. The first hole 71 is located at one side of the gate insulating layer, the first hole 71 is located in a region where the active layer exceeds the gate insulating layer, and the bottom of the first hole 71 is the source layer 9. The second hole 72 is located at the other side of the gate insulating layer, the second hole 72 is also located in a region where the active layer exceeds the gate insulating layer, and the bottom of the second hole 72 is the drain layer 10. The fourth hole is located at one side of the gate electrode layer, and the bottom of the fourth hole is a peripheral region of the gate insulating layer (i.e., corresponds to the third region on the gate insulating layer). The fifth hole is positioned on one side of the grid insulating layer, and the bottom of the fifth hole is a light shielding layer.
It should be noted that the first hole, the second hole, the fourth hole, and the fifth hole may be simultaneously formed.
After the first hole, the second hole and the fourth hole are formed, the source electrode layer, the drain electrode layer and the gate compensation layer are formed, and the structure is shown in fig. 5. Specifically, a photoresist is coated and then patterned, that is, the portions where the source layer 9, the drain layer 10 and the gate compensation layer 8 are to be formed are opened after exposure and development. Then, a metal layer is plated on the substrate by physical vapor deposition, and a source electrode layer 9, a drain electrode layer 10 and a gate compensation layer 8 are formed on the dielectric layer. After the films are manufactured, the photoresist is removed. The source layer 9 is connected to the source layer through a first hole in the dielectric layer, the drain layer 10 is connected to the source layer through a second hole in the dielectric layer, and the gate compensation layer 8 is connected to the gate insulating layer through a fourth hole.
The top of the gate insulating layer comprises a first region 51, a second region and a third region 52, the first region 51 is arranged in the middle of the top of the gate insulating layer, the second region is arranged around the second region, the third region 52 is arranged around the second region, the gate layer is arranged on the first region 51, and the gate compensation layer 8 is arranged on the third region 52. I.e. the gate compensation layer 8 surrounds the gate layer, the gate compensation layer 8 and the gate layer having a spacing being the width of the second area.
The cross section of the first region is circular, rectangular, oval, triangular, polygonal, or the like. The shape of the second area is adapted to the shape of the first area in that the inner side of the second area is the outer side of the first area. Similarly, the inner side of the third region is the outer side of the second region, and the outer side of the third region is the boundary of the top of the gate insulating layer. Preferably, the first region has a circular cross-sectional shape, in which case the second and third regions are both annular.
In the present embodiment, the width of the second region is 16um (micrometers) to 32um (micrometers). Preferably, the width of the second region is 24 um.
The gate compensation layer and the gate compensation layer, and the drain layer and the source layer are made of the same material. The material of the source layer may be a Mo (molybdenum)/Cu (copper) stack, a MoTi (molybdenum titanium)/Cu (copper) stack, or a metal having excellent conductivity, such as aluminum, silver, or chromium, but is not limited thereto. If the source layer is a Mo/Cu stack, the thickness of Mo is 0.02 um-0.05 um, the thickness of Cu is 0.4 um-0.6 um, preferably, the thickness of Mo is 0.03um, and the thickness of Cu is 0.5 um. If the source layer is a stack of MoTi/Cu, the thickness of MoTi is 0.02um to 0.05um and the thickness of Cu is 0.4um to 0.6um, preferably, the thickness of MoTi is 0.03um and the thickness of Cu is 0.5 um.
After the source layer, the drain layer and the gate compensation layer are manufactured, a flat layer is manufactured, and the flat layer is used for electrically connecting the isolation electrode layer and other irrelevant film layers, and the structure is shown in fig. 1. Specifically, a layer of insulating material, which may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), etc., is deposited on the substrate by a plasma enhanced chemical vapor deposition method, thereby forming the planarization layer 11 on the source layer, the drain layer, and the gate compensation layer. The flat layer 11 covers the film layer below, so that the film layer below which the manufacturing process is performed can be protected from being affected by the subsequent process.
The material of the planarization layer may be, but is not limited to, nitride (silicon nitride, etc.), oxide (silicon oxide, etc.), or the like. The thickness of the flat layer is 0.3um (micrometer) to 0.5um (micrometer). Preferably, the buffer layer has a thickness of 0.4 um.
And after the flat layer is manufactured, a third hole is manufactured on the flat layer and is used as a connection point between the electrode layer and the source electrode layer or the drain electrode layer. Specifically, a photoresist is coated first, and then the photoresist is patterned, i.e., the portion to be formed with the third hole is opened after exposure and development. The planarization layer is then etched to the source layer or the drain layer using the photoresist as a mask to form a third hole. The bottom of the third hole is a source layer or a drain layer. After the third hole is formed, the photoresist is removed.
After the flat layer is manufactured, in order to realize the connection between the thin film transistor and the external structure, an electrode layer is manufactured, and the structure is as shown in fig. 1. An electrode layer 12 is deposited by physical vapor deposition, the electrode layer 12 being connected to the source electrode layer or the drain electrode layer through a third hole. If the source layer 9 is connected with the shading layer 2, the drain layer 10 is connected with the electrode layer 12, and the structure is shown in FIG. 1; if the drain layer 10 is already connected to the light-shielding layer 2, it is connected by the source layer 9 and the electrode layer 12. The external structure is communicated with the thin film transistor through the electrode layer 12, and the thin film transistor is used as a switch to drive the liquid crystal pixel point to achieve high speed, high brightness and high contrast.
The material of the electrode layer may be Indium Tin Oxide (ITO), zinc aluminum oxide (AZO), Indium Zinc Oxide (IZO), but is not limited thereto. The thickness of the electrode layer is 0.05 um-0.08 um, preferably, the thickness of the electrode layer is 0.075 um.
The manufacturing method is based on the existing dry etching for manufacturing the grid insulating layer and wet etching for manufacturing the grid layer, and the grid compensation layer is manufactured on the outer side of the grid layer under the condition of maintaining the original manufacturing steps and controlling the number of the light shades as much as possible, so that the problem of insufficient control force of the original grid layer on the active layer is solved.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present patent.

Claims (10)

1. A thin film transistor with a top gate structure is characterized by comprising an active layer, a gate insulating layer, a gate layer, a dielectric layer, a source layer, a drain layer and a gate compensation layer;
the grid electrode insulating layer is arranged on the active layer, the projection of the grid electrode insulating layer is positioned in the projection of the active layer, and the direction of the projection is perpendicular to the active layer;
the top of the gate insulating layer comprises a first region, a second region and a third region, the first region is arranged in the middle of the top of the gate insulating layer, the second region surrounds the second region, the third region surrounds the second region, the gate layer is arranged on the first region, and the gate compensation layer is arranged on the third region;
the dielectric layer is arranged on the gate electrode layer and the gate insulating layer, a first hole and a second hole are arranged on the dielectric layer, the first hole is positioned on one side of the gate insulating layer, the hole bottom of the first hole is a source electrode layer, the second hole is positioned on the other side of the gate insulating layer, and the hole bottom of the second hole is a drain electrode layer;
the source electrode layer and the drain electrode layer are respectively arranged on the dielectric layer, the source electrode layer is connected with the source layer through a first hole in the dielectric layer, and the drain electrode layer is connected with the source layer through a second hole in the dielectric layer.
2. The thin film transistor of claim 1, further comprising a substrate, a light-shielding layer and a buffer layer;
the light shielding layer is arranged on the substrate, and the projection of the active layer is positioned in the projection of the light shielding layer;
the buffer layer is disposed on the light-shielding layer, and the active layer is disposed on the buffer layer.
3. The thin film transistor of claim 2, wherein the source layer is connected to the light-shielding layer; or: the drain electrode layer is connected with the shading layer.
4. The thin film transistor of claim 1, further comprising a planarization layer;
the planarization layer is disposed on the gate compensation layer, the gate layer, the dielectric layer, the source layer, and the drain layer.
5. The thin film transistor of claim 4, further comprising an electrode layer;
a third hole is formed in the flat layer, and a source electrode layer or a drain electrode layer is arranged at the bottom of the third hole;
the electrode layer is disposed on the planarization layer, and the electrode layer is connected to the source electrode layer or the drain electrode layer through a third hole.
6. The thin film transistor of a top-gate structure according to any one of claims 1 to 5, wherein the sum of the projection of the gate compensation layer, the projection of the gate layer, and the projection of the second region is equal to the projection of the gate insulating layer.
7. A method for manufacturing a thin film transistor with a top gate structure is characterized by comprising the following steps:
manufacturing an active layer on a substrate;
depositing an insulating layer, etching the insulating layer through dry etching, and forming a gate insulating layer on an active layer, wherein the gate insulating layer is arranged on the active layer, the projection of the gate insulating layer is positioned in the projection of the active layer, and the direction of the projection is vertical to the active layer;
depositing a grid metal layer, etching the grid metal layer through wet etching, and forming a grid layer on a grid insulating layer, wherein the grid layer is arranged in the middle of the grid insulating layer;
manufacturing a dielectric layer, wherein the dielectric layer covers the grid electrode layer, the grid electrode insulating layer and the active layer;
manufacturing a first hole, a second hole and a fourth hole on a dielectric layer, wherein the first hole is positioned on one side of a gate insulating layer, the bottom of the first hole is a source electrode layer, the second hole is positioned on the other side of the gate insulating layer, the bottom of the second hole is a drain electrode layer, the fourth hole is positioned on one side of a gate electrode layer, the bottom of the fourth hole is the gate insulating layer, and a gap is formed between the fourth hole and the gate electrode layer;
and simultaneously manufacturing a source electrode layer, a drain electrode layer and a grid electrode compensation layer, wherein the source electrode layer is connected with an active layer through a first hole in the dielectric layer, the drain electrode layer is connected with the active layer through a second hole in the dielectric layer, and the grid electrode compensation layer is connected with the grid electrode insulation layer through a fourth hole in the dielectric layer.
8. The method for manufacturing a thin film transistor with a top gate structure according to claim 7, further comprising the following steps before "manufacturing an active layer on the substrate":
firstly, manufacturing a shading layer on a substrate, wherein the projection of the active layer is positioned in the projection of the shading layer;
then, manufacturing a buffer layer, wherein the buffer layer covers the shading layer;
and finally, manufacturing an active layer on the buffer layer.
9. The method as claimed in claim 8, wherein the source layer is connected to the light-shielding layer; or: the drain electrode layer is connected with the shading layer.
10. The method for manufacturing a thin film transistor with a top gate structure according to claim 7, further comprising the steps of:
manufacturing a flat layer, wherein the flat layer is arranged on the grid compensation layer, the source electrode layer, the drain electrode layer and the dielectric layer;
manufacturing a third hole on the flat layer, wherein the bottom of the third hole is a source electrode layer or a drain electrode layer;
and manufacturing an electrode layer which is connected with the source electrode layer or the drain electrode layer through the third hole.
CN202011607516.4A 2020-12-30 2020-12-30 Thin film transistor with top gate structure and manufacturing method Pending CN112582479A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646713A (en) * 2011-05-13 2012-08-22 京东方科技集团股份有限公司 Pixel structure of thin film transistor liquid crystal display and manufacturing method thereof
US20160064421A1 (en) * 2014-08-29 2016-03-03 Lg Display Co., Ltd. Thin film transistor substrate and display device using the same
JP2016167636A (en) * 2016-06-08 2016-09-15 株式会社半導体エネルギー研究所 Semiconductor device
CN110651373A (en) * 2017-05-11 2020-01-03 普兰西股份有限公司 Flexible component comprising a layer structure with metallic plies
CN213845282U (en) * 2020-12-30 2021-07-30 福建华佳彩有限公司 Thin film transistor with top gate structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646713A (en) * 2011-05-13 2012-08-22 京东方科技集团股份有限公司 Pixel structure of thin film transistor liquid crystal display and manufacturing method thereof
US20160064421A1 (en) * 2014-08-29 2016-03-03 Lg Display Co., Ltd. Thin film transistor substrate and display device using the same
JP2016167636A (en) * 2016-06-08 2016-09-15 株式会社半導体エネルギー研究所 Semiconductor device
CN110651373A (en) * 2017-05-11 2020-01-03 普兰西股份有限公司 Flexible component comprising a layer structure with metallic plies
CN213845282U (en) * 2020-12-30 2021-07-30 福建华佳彩有限公司 Thin film transistor with top gate structure

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