JP2020504525A5 - - Google Patents

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JP2020504525A5
JP2020504525A5 JP2019536263A JP2019536263A JP2020504525A5 JP 2020504525 A5 JP2020504525 A5 JP 2020504525A5 JP 2019536263 A JP2019536263 A JP 2019536263A JP 2019536263 A JP2019536263 A JP 2019536263A JP 2020504525 A5 JP2020504525 A5 JP 2020504525A5
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user equipment
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JP7132222B2 (ja
JP2020504525A (ja
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JP2019536263A 2017-01-04 2017-12-29 Dciブラインド検出のためにue idを凍結ビットに埋め込むスクランブル系列設計 Active JP7132222B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US201762442225P 2017-01-04 2017-01-04
US62/442,225 2017-01-04
US201762455448P 2017-02-06 2017-02-06
US62/455,448 2017-02-06
US201762501493P 2017-05-04 2017-05-04
US62/501,493 2017-05-04
US201762521946P 2017-06-19 2017-06-19
US62/521,946 2017-06-19
US15/852,632 2017-12-22
US15/852,632 US10327235B2 (en) 2017-01-04 2017-12-22 Scrambling sequence design for multi-mode block discrimination on DCI blind detection
PCT/US2017/068972 WO2018128928A1 (en) 2017-01-04 2017-12-29 Scrambling sequence design for multi-mode block discrimination on dci blind detection

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JP2020504525A JP2020504525A (ja) 2020-02-06
JP2020504525A5 true JP2020504525A5 (enExample) 2021-02-12
JP7132222B2 JP7132222B2 (ja) 2022-09-06

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JP2019536298A Active JP7364466B2 (ja) 2017-01-04 2017-12-29 Dciブラインド検出のためにue idを凍結ビットに埋め込むスクランブル系列設計
JP2019536263A Active JP7132222B2 (ja) 2017-01-04 2017-12-29 Dciブラインド検出のためにue idを凍結ビットに埋め込むスクランブル系列設計

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US (5) US10327235B2 (enExample)
EP (2) EP3566345B1 (enExample)
JP (2) JP7364466B2 (enExample)
CN (2) CN110463093B (enExample)
WO (2) WO2018128932A1 (enExample)

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