JP2020173692A - Control method and control apparatus - Google Patents

Abstract

To provide a control apparatus which carries out diagnosis by using a configured circuit, reduces a time required for diagnosis upon booting or rebooting, and secures reliability.SOLUTION: A control apparatus according to the present invention has a storage unit, and a reconfigurable FPGA (field programmable gate array), wherein the FPGA configures a boot control unit upon booting and rebooting, the boot control unit configures a diagnosis unit in the FPGA, and the diagnosis unit carries out diagnosis of the storage unit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a control device and a control method.

In various industrial fields, a controller equipped with a control device is used to construct a control system. In such a control system, the control device mounted on the controller acquires the state quantities such as current, temperature, and pressure from the field device, and outputs the control data (signal) to the operating device while measuring the state quantities. Control the operating equipment in real time.

As a result, desired operations such as adjustment of the flow rate and emergency stop when the state quantity becomes abnormal are executed, and safety and reliability are ensured as well as convenience.

In recent years, in these industrial fields, in order to output better control data to operating devices, operating data (state quantity) is collected (measured) from a large number of field devices distributed in the real world, and operating data is collected in the virtual world. Efforts are being made to IoT (Internet of Things) that analyzes and feeds back to the real world.

By implementing IoT initiatives for control systems in this way, it is possible to visualize, analyze, and utilize operational data that was not previously handled, and create new value such as maintenance services. it can.

On the other hand, in order to implement IoT initiatives for control systems, it is necessary to process a large amount of operational data acquired from field equipment using algorithms and AI (Artificial Intelligence) implemented in the control system. There is.

Therefore, the control device is equipped with a high-performance CPU (Central Processing Unit), OS (Operating System), application program, etc., and the circuit configuration can be dynamically changed (reconfigurable) FPGA (reconfigurable). Field Programmable Gate Array) is used.

As a result, it takes a long time to start the control system due to the initialization of the large-capacity storage unit (memory) and the FPGA, and it is difficult to secure the reliability required for the control system.

As a background technology in this technical field, there is Japanese Patent Application Laid-Open No. 2015-106751 (Patent Document 1). In Patent Document 1, an FPGA in which at least a part of a circuit is dynamically reconstructed, a ROM for storing circuit configuration information for reconstructing at least a part of a circuit in the FPGA, and a circuit configuration stored in the ROM are described. An image processing apparatus having a RAM that can store a copy of information and can be read at a speed higher than that of a ROM is described. Then, at least a part of the FPGA is reconfigured into a circuit that can execute the processing required by the job by using the circuit configuration information according to the job to be executed, and the real-time processing using the RAM is not being executed. When the FPGA is reconfigured using the circuit configuration information stored in the RAM, and when real-time processing using the RAM is in progress, the FPGA is reconfigured using the circuit configuration information stored in the ROM. It is stated that it will be reconstructed (see summary).

Further, as a background technique in this technical field, there is Japanese Patent Application Laid-Open No. 2018-109907 (Patent Document 2). In Patent Document 2, in order to shorten the restart time of the FPGA having a built-in CPU, the FPGA configuration device includes a first memory that holds initial configuration data for configuring a startup circuit in the FPGA. The FPGA has a second memory that holds the configuration data for the main circuit for configuring the main circuit, and a data update unit that updates the configuration data for the main circuit based on the state of the FPGA in operation. It is described that the initial configuration data is provided to the FPGA when the power is turned on, and the configuration data for the main circuit is provided in response to the operation of the startup circuit (see summary).

Japanese Unexamined Patent Publication No. 2015-106751 JP-A-2018-109907

Patent Document 1 describes a technique for reconstructing at least a part of FPGA into a circuit capable of executing a process required by a job according to a job to be executed. Further, Patent Document 2 describes a technique for shortening the restart time of an FPGA having a built-in CPU.

However, Patent Document 1 and Patent Document 2 do not describe that a diagnosis is performed using the configured circuit. Further, in Patent Document 1 and Patent Document 2, for example, when an OS or an application program is applied to a control device, a predetermined time is required for diagnosis at startup or restart, so that the reliability as a control device is required. There is no mention of the issue of difficulty in securing the above.

Therefore, the present invention provides a control device and a control method that execute a diagnosis using the configured circuit, shorten the time required for the diagnosis at the time of start-up or restart, and ensure reliability. ..

In order to solve the above problems, the control device of the present invention includes a storage unit and a reconfigurable FPGA (field programmable gate array), and the FPGA constitutes a start control unit at startup or restart. The activation control unit constitutes an FPGA with a diagnostic unit, and the diagnostic unit executes a diagnosis of the storage unit.

Further, the control method of the present invention is a control method for executing a diagnosis of a storage unit, and a start control unit is configured in an FPGA that can be reconfigured at startup or restart, and the start control unit is in the FPGA. , The diagnostic unit constitutes the diagnostic unit, and the diagnostic unit executes the diagnosis of the storage unit.

According to the present invention, there is provided a control device and a control method that perform a diagnosis by using the configured circuit, reduce the time required for the diagnosis at startup and restart, and ensure reliability. be able to.

Issues, configurations and effects other than those described above will be clarified by the explanation of the following examples.

It is a block diagram explaining the control device 100 which concerns on Example 1. FIG. It is a block diagram explaining the activation control part 11 which concerns on Example 1. FIG. It is a block diagram explaining the diagnosis unit 12 which concerns on Example 1. FIG. It is a flowchart explaining the control method which concerns on Example 1. FIG. It is a timing chart diagram explaining the flow until the control device is activated. It is a timing chart diagram explaining the flow until the control device which concerns on Example 1 starts. It is a block diagram explaining the control device 200 which concerns on Example 2. FIG. It is a block diagram explaining the diagnosis transfer part 14 which concerns on Example 2. FIG. It is a timing chart diagram explaining the flow until the control device which concerns on Example 2 starts. It is a block diagram explaining the control device 300 which concerns on Example 3. FIG. It is a block diagram explaining the diagnosis part 16 which concerns on Example 3. FIG. It is a block diagram explaining the control device 400 which concerns on Example 4. FIG. It is a block diagram explaining the parallel diagnosis unit 17 which concerns on Example 4. FIG. It is explanatory drawing explaining the case where the control device which concerns on this Example is applied to a plant P1. It is explanatory drawing explaining the case where the control device which concerns on this Example is applied to a plant P2.

Hereinafter, examples of the present invention will be described with reference to the drawings. In the specification and drawings, elements having substantially the same function or configuration are designated by the same reference numerals, and if the description is duplicated, the description may be omitted.

First, the control device 100 according to the first embodiment will be described.

FIG. 1 is a block diagram illustrating a control device 100 according to a first embodiment.

The control device 100 described in the first embodiment includes an FPGA (field programmable gate array) 101, a CPU (central processing unit) 2, a memory controller 3, a memory 4 as a storage unit, and a non-volatile memory 5.

The memory controller 3 is connected to the CPU 2, the memory 4, and the dynamic partial reconstruction unit 181 of the FPGA 101, respectively. The CPU 2 executes various operations and controls for operating the OS and application programs. The non-volatile memory 5 stores data and the like necessary for the FPGA 101 to operate. The memory 4 stores temporary data and the like for operating the OS and application programs. The memory controller 3 executes control for temporarily storing data or the like in the memory 4.

The FPGA 101 has a start control unit 11 and a dynamic partial reconstruction unit 181. The start control unit 11 is connected to the non-volatile memory 5 and the dynamic partial reconstruction unit 181 respectively. The dynamic partial reconstruction unit 181 is a portion that constitutes a circuit based on an instruction from the start control unit 11.

The start control unit 11 has a function of reading bitstream data stored in the non-volatile memory 5 and forming a circuit for FPGA 101, and the start control unit 11 is configured at the time of designing the control device 100. , Will be implemented.

In this embodiment, the dynamic partial reconstruction unit 181 constitutes the diagnosis unit 12 which is a circuit, and the diagnosis result 91 is output from the diagnosis unit 12 to the outside of the control device 100.

As described above, the control device 100 described in the present embodiment has the FPGA 101 having the activation control unit 11 and the dynamic partial reconstruction unit 181, and the FPGA 101 is at startup (hereinafter, also including “restart”). The activation control unit 11 is configured, the activation control unit 11 configures the diagnosis unit 12 in the dynamic partial reconstruction unit 181 of the FPGA 101, and the diagnosis unit 12 executes the diagnosis of the memory 4.

The control device 100 described in this embodiment has a memory 4 and an FPGA 101, and when the FPGA 101 is started, the start control unit 11 and the start control unit 11 configured in the FPGA 101 dynamically partially reconfigure the FPGA 101. It has a diagnostic unit 12 configured in the unit 181 and the diagnostic unit 12 executes the diagnosis of the memory 4.

That is, the control device 100 described in this embodiment, which is equipped with the CPU 2 and the memory 4 and operates the OS and the application program, needs to execute the diagnosis of the memory 4 in order to ensure reliability. However, it does not require a long time to execute the diagnosis of the memory 4, the OS and the application program can be operated at high speed, and the startup time of the control device 100 can be shortened.

As a result, for example, the start-up time of a system such as a plant can be shortened, and reliability can be ensured.

Next, the activation control unit 11 according to the first embodiment will be described.

FIG. 2 is a block diagram illustrating an activation control unit 11 according to the first embodiment.

The start control unit 11 includes a state transition unit 20, a control signal generation unit 21, a multiplexer 22, a data buffer 23, and an output control unit 24, and is implemented at the time of designing the control device 100.

When the power of the control device 100 is turned on, the state transition unit 20 is in a state (mode) of outputting an instruction signal (control signal) for generating the diagnosis unit 12. The control signal generation unit 21 outputs two control signals, a control signal for generating the diagnosis unit 12 and a control signal for instructing the diagnosis result, to the multiplexer 22.

The multiplexer 22 is a control signal that generates the diagnostic unit 12 among the two control signals output by the control signal generation unit 21 based on the control signal (control signal that generates the diagnostic unit 12) output by the state transition unit 20. Is output to the non-volatile memory 5 as a circuit generation control signal 70.

The data buffer 23 stores the bitstream data 71 for generating the diagnostic unit 12, which is output by the non-volatile memory 5. The bitstream data 71 stored in the data buffer 23 is output to the dynamic partial reconstruction unit 181 as bitstream data 72 via the output control unit 24.

The dynamic partial reconstruction unit 181 is composed of the configuration RAM (Random Access Memory) of the FPGA 101.

That is, the activation control unit 11 has a data buffer 23 for storing the bitstream data 71 for generating the diagnosis unit 12, and an output control unit 24 for controlling the output of the bitstream data 71.

The state transition unit 20 receives the diagnosis end signal 73 output by the dynamic partial reconstruction unit 181. Here, the value of the diagnosis end signal 73 is "0" when the memory diagnosis is not completed, and "1" when the memory diagnosis is completed.

When the value of the diagnosis end signal 73 is not "1", that is, when the memory diagnosis is not completed, the output control unit 24 sequentially bitstreams the bitstream data 71 stored in the data buffer 23. The data 72 is output to the dynamic partial reconstruction unit 181.

As a result, the control device 100 (FPGA101) described in this embodiment constitutes the diagnostic unit 12 in the dynamic partial reconstruction unit 181.

When the diagnosis of the memory 4 is completed, the state (mode) of outputting the instruction signal (control signal) instructing the end of the diagnosis is set.

Next, the diagnostic unit 12 according to the first embodiment will be described.

FIG. 3 is a block diagram illustrating the diagnosis unit 12 according to the first embodiment.

The diagnostic unit 12 has a diagnostic area register 30, a diagnostic data generation unit 32, a diagnostic write buffer 34, a diagnostic read buffer 35, and a comparison unit 33.

In the diagnosis area register 30, an address to be diagnosed in the memory 4 (for example, address information such as an address or a range, which may be hereinafter referred to as a “diagnosis target address”) is set in advance. .. This address information (diagnosis target address) is input to the diagnostic data generation unit 32 as the diagnostic address 76.

Address information (diagnosis target address) is set and stored as a fixed value in the diagnosis area register 30 when the control device 100 is designed. Further, the memory controller 3 and the memory 4 can be shared, set, and stored from the software running on the CPU 2.

The diagnostic data generation unit 32 diagnoses the memory 4 in the range of the diagnostic address 76 based on the diagnostic target address set by the diagnostic area register 30 when its operation is set at the time of designing the control device 100. A data value (diagnostic data) to be executed is generated and output to the diagnostic write buffer 34.

As the data value (diagnosis data) for executing the diagnosis here, the value of all bits of the data is "0", the value of all the bits of the data is "1", or any other value is set. Can be done. The data value used in the diagnosis may be selected when designing the control device 100.

The diagnostic write buffer 34 stores the data value output by the diagnostic data generation unit 32, and outputs this data value as the diagnostic write data 74 to the memory controller 3. The diagnostic light data 74 is written to the memory 4.

The memory controller 3 writes (writes) the input data value to the diagnosis target address of the memory 4. After writing, the data value is read (read) from the diagnosis target address of the written memory 4. After reading, the read data value is output to the diagnostic read buffer 35 as diagnostic read data 75. That is, the memory controller 3 writes and reads the data value to the diagnosis target address of the memory 4 with respect to the memory 4.

The diagnostic read buffer 35 stores the data value output by the memory controller 3 (read from the memory 4) as the diagnostic read data 75.

That is, the diagnostic unit 12 outputs the data value as the diagnostic write data 74 to the memory controller 3, and inputs the data value as the diagnostic read data 75 from the memory controller 3.

In this way, the data value is output from the diagnostic write buffer 34 via the memory controller 3, is written to the diagnostic target address of the memory 4, is read from the written diagnostic target address of the memory 4, and is read from the diagnostic read buffer. It is output to 35 via the memory controller 3.

Then, in the comparison unit 33, the read value (data value which is the diagnostic read data 75) stored in the diagnostic read buffer 35 and the write value (data value which is the diagnostic write data 74) stored in the diagnostic write buffer 34 are , Are compared (diagnosed).

If the write value and the read value match, it means that the diagnosis target address of the memory 4 is operating normally. However, if the write value and the read value do not match (if they do not match), the diagnosis target address of the memory 4 does not operate normally.

For example, when operating normally, the value (signal) of the diagnosis result 91 outputs "0", and when not operating normally, the value (signal) of the diagnosis result 91 outputs "1". To do.

Next, the control method according to the first embodiment will be described.

The control method described in this embodiment executes the diagnosis of the memory 4, and at the time of startup, the start control unit 11 is configured in the reconfigurable FPGA 101, and the start control unit 11 diagnoses the FPGA 101. The unit 12 is configured, and the diagnostic unit 12 executes the diagnosis of the memory 4.

FIG. 4 is a flowchart illustrating a control method according to the first embodiment.

Step S01 is a step in which the power of the control device 100 is turned on.

Step S02 is a step in which the activation control unit 11 configures the diagnostic unit 12 in the dynamic partial reconstruction unit 181.

Step S03 is a step of comparing the memory diagnosis address (diagnosis target address) with the OS area. For example, the OS area is a start address or end address of a memory area used by the OS, which is stored in the diagnosis area register 30 of the diagnosis unit 12. That is, the comparison unit 33 compares the write value and the read value of the memory diagnostic address with respect to the OS area.

Step S04 is a step of determining whether or not the memory diagnosis of the OS area has been completed. For example, it is determined whether or not the memory diagnostic address exceeds the end address of the OS area. If it does not exceed (NO), it is determined that the memory diagnosis has not been completed, and the process proceeds to step S05. If it exceeds (YES), it is determined that the memory diagnosis has been completed, and the process proceeds to step S07.

Step S05 executes the memory diagnosis.

Step S06 increases the memory diagnostic address and transitions to step S03.

Step S07 is a step of comparing the memory diagnosis address (diagnosis target address) with the application area. For example, the application area is a start address or end address of a memory area used by the application program, which is stored in the diagnosis area register 30 of the diagnosis unit 12. That is, the comparison unit 33 compares the write value and the read value of the memory diagnostic address with respect to the application area.

Step S08 is a step of determining whether or not the memory diagnosis of the application area is completed. For example, it is determined whether or not the memory diagnostic address exceeds the end address of the application area.
If it does not exceed (NO), it is determined that the memory diagnosis has not been completed, and the process proceeds to step S09. If it exceeds (YES), it is determined that the memory diagnosis has been completed, and the process proceeds to step S11.

Step S09 executes the memory diagnosis.

Step S10 increases the memory diagnostic address and transitions to step S07.

In step S11, the OS data is transferred to the memory 4.

Step S12 boots the OS.

In step S13, the application data is transferred to the memory 4.

Step S14 starts the application program.

Through these series of steps, the control device 100 described in this embodiment is activated. The OS can be started when step S11 is completed, and the application program can be started when step S13 is completed.

Next, the flow until the control device is activated will be described using a timing chart diagram.

FIG. 5 is a timing chart diagram illustrating a flow until the control device is activated.

First, the flow until the control device (comparative example) when the FPGA 101 described in this embodiment is not used is started will be described. In this control device (comparative example), a series of steps are processed by the CPU. That is, this control device (comparative example) executes the startup process by the CPU. In FIG. 5, the horizontal axis represents the time t.

The power of the control device (comparative example) is turned on, and the CPU executes a memory diagnosis of the OS area and the application area. That is, the CPU (software) sequentially executes the memory diagnosis.

After completing these memory diagnoses, the OS data is transferred to the memory, and then the application data is transferred to the memory. After completing these series of steps required to start the system, that is, after the transfer of these data to the memory is completed, the OS is started, and then the application program is started.

5, the time from power ON until the memory diagnosis is finished t _m, time t _o from the power ON to the OS startup is _completed, the time from power ON until the application activation is completed with t _a .. Generally, the size of the memory area OS and application programs used are large, it tends to require more time to diagnosis time t _m of the memory area.

FIG. 6 is a timing chart for explaining the flow until the control device according to the first embodiment is activated.

Next, the flow until the control device 100 is activated when the FPGA 101 described in this embodiment is used will be described.

In the control device 100, the power ON, OS startup, and application program startup are processed by the CPU 2. However, the memory area diagnostic process and the data transfer process to the memory area are processed by the FPGA 101. That is, the control device 100 is started by the CPU 2 and the FPGA 101. In FIG. 6, the horizontal axis represents the time t.

The power of the control device 100 is turned on, and the diagnostic unit 12 is configured in the dynamic partial reconstruction unit 181 of the FPGA 101. The diagnostic unit 12 executes a memory diagnosis between the OS area and the application area. After the memory diagnosis is completed, the OS data is transferred to the memory 4, and then the application data is transferred to the memory 4.

Then, after transferring the OS data to the memory 4, the OS is started. Further, after transferring the application data to the memory 4, the application program is started.

In FIG. 6, the time from power ON until the memory diagnosis is finished t _m, time t _o from the power ON to the OS startup is _completed, the time from power ON until the application activation is completed with t _a ..

In this embodiment, the diagnostic unit 12 configured in the dynamic partial reconstruction unit 181 of the FPGA 101 executes the memory diagnosis by hardware (according to the hardware, in parallel for each memory lane, that is, for each memory line). perform memory diagnosis) for the time t _m from the power oN to the memory diagnosis is finished, as compared with the case of FIG. 5, is reduced. As a result, the time t _a up to the time t _o and application start-up until the OS start-up is finished is finished is also shortened.

Further, in this embodiment, the OS can be started after the OS data is transferred to the memory 4, and the application program is started after the application data is transferred to the memory 4. In other words, a transfer to the memory 4 of the boot and application data OS can be executed in parallel (simultaneously), the time of the time until the OS startup ends up t _o and application startup is completed t _a Is further shortened.

According to this embodiment, a memory diagnosis is executed at startup or restart in order to ensure high reliability in a control device or control method in which a CPU 2 and a memory 4 are mounted and an OS or an application program is operated. Even when it is necessary, it is possible to provide a control device and a control method capable of starting an OS or an application program at high speed without spending a long time on memory diagnosis. Then, for example, a control system having high performance corresponding to IoT and high expandability can be realized.

First, the control device 200 according to the second embodiment will be described.

FIG. 7 is a block diagram illustrating the control device 200 according to the second embodiment.

The control device 200 described in this embodiment executes a memory area diagnostic process and a data transfer process to the memory area in parallel.

The control device 200 described in this embodiment has a diagnostic transfer unit 14 in the dynamic partial reconstruction unit 182 as compared with the control device 100 described in the first embodiment (FIG. 1), and the dual port memory controller 50. And the dual port memory 51 are different.

The dual port memory 51 stores temporary data for operating the OS and application programs, allows a plurality of accesses at a time, and can execute a plurality of reads and a plurality of writes at the same time. It is a thing. Further, the dual port memory controller 50 executes control for temporarily storing data or the like in the dual port memory 51.

Next, the diagnosis transfer unit 14 according to the second embodiment will be described.

FIG. 8 is a block diagram illustrating the diagnosis transfer unit 14 according to the second embodiment.

The diagnostic transfer unit 14 configured in the dynamic partial reconstruction unit 182 of the FPGA 102 has a transfer address generation unit 37, a transfer data buffer 38, and transfer data as compared with the diagnostic unit 12 described in the first embodiment (FIG. 3). The difference is that it has a buffer 39 and a dual port interface 52.

The transfer address generation unit 37 inputs the data value generated by the diagnostic data generation unit 32, generates a transfer address (for example, an address), and outputs the generated transfer address to the transfer data buffer 38.

The transfer data buffer 38 inputs and stores the OS data (or application data) 88 (bit stream data 72) output by the start control unit 11 and the transfer address output by the transfer address generation unit 37, and stores the OS data 88. The transfer address and the transfer address are output to the transfer data buffer 39.

The transfer data buffer 39 inputs and stores the OS data 88 and the transfer address output by the transfer data buffer 38, and outputs the OS data (or application data) 86 to the dual port interface 52.

The dual port interface 52 has two sets of memory interfaces, inputs diagnostic write data 74 and OS data 86, and makes diagnostic write data 85 (value of diagnostic write buffer 34) and OS data (or application data) 87 ( The value of the transfer data buffer 39) is output to the dual port memory controller 50.

Then, the dual port memory controller 50 outputs the diagnostic read data 75 to the diagnostic read buffer 35.

That is, in this embodiment, regarding the diagnostic processing of the OS (memory) area and the transfer processing of OS data to the dual port memory 50, for example, line A, line B, line C, and line D are provided as the OS area. Then, when the line A, the line B, the line C, and the line D are transferred to the dual port memory 50 as the OS data, the line A is diagnosed and the line A is transferred. Then, when the line A is transferred, the line B is diagnosed at the same time, when the line B is transferred, the line C is diagnosed at the same time, and when the line C is transferred, the line D is diagnosed at the same time. Transfer D.

Further, the diagnostic process of the application (memory) area and the transfer process of the application data to the dual port memory 50 are the same as the diagnostic process of the OS area and the transfer process of the OS data to the dual port memory 50.

When the line D is transferred as OS data, the line E as the application area can be diagnosed at the same time.

As a result, the control device 200 described in this embodiment can execute the diagnosis process of the memory area and the data transfer process to the memory area in parallel.

FIG. 9 is a timing chart for explaining the flow until the control device according to the second embodiment is activated.

Next, the flow until the control device 200 is activated when the FPGA 102 described in this embodiment is used will be described.

In the control device 200, the power ON, OS startup, and application program startup are processed by the CPU 2. However, the memory area diagnostic process and the data transfer process to the memory area are processed by the FPGA 102. That is, the control device 200 is started by the CPU 2 and the FPGA 102. In FIG. 9, the horizontal axis represents the time t.

The power of the control device 200 is turned on, and the diagnostic transfer unit 14 is configured in the dynamic partial reconstruction unit 182 of the FPGA 102. The diagnostic transfer unit 14 executes a memory diagnosis between the OS area and the application area.

After the memory diagnosis for each line in these areas is completed, the data for each line is transferred to the dual port memory 50 for each line. Then, after transferring the OS data to the dual port memory 50, the OS is started. Further, after transferring the application data to the dual port memory 50, the application program is started.

The timing chart diagram described in the present embodiment (FIG. 9) is compared with the timing chart diagram described in the first embodiment (FIG. 6), and the diagnostic transfer unit 14 configured in the dynamic partial reconstruction unit 182 of the FPGA 102. The OS area diagnostic process and the OS data transfer process to the dual port memory 50 overlap, and the application area diagnostic process and the application data transfer process to the dual port memory 50 overlap. The point to make is different.

9, the time from power ON until the memory diagnosis is finished t _m, time t _o from the power ON to the OS startup is _completed, the time from power ON until the application activation is completed with t _a .. These times are all shortened as compared with Example 1.

According to this embodiment, in order to ensure high reliability in a control device and a control method in which a CPU 2 and a dual port memory 50 are mounted and an OS or an application program is operated, memory diagnosis is performed at startup or restart. Even if it is necessary to execute it, the memory area diagnostic processing and the data transfer processing can be executed in an overlapping manner, and the OS and application programs can be started at high speed. A method can be provided.

First, the control device 300 according to the third embodiment will be described.

FIG. 10 is a block diagram illustrating the control device 300 according to the third embodiment.

When the control device 300 described in this embodiment is equipped with a plurality of CPUs and a plurality of OSs (or application programs), the memory area is given priority and the memory area diagnostic process is executed.

The control device 300 described in this embodiment is connected to the memory controller 3 by adding a CPU 6 as compared with the control device 100 described in the first embodiment (FIG. 1), and the diagnostic unit 16 determines the priority. Is different in that it determines.

For example, the CPU 6 operates a second OS (or a second application program) having a higher priority than the OS (or application program) that operates on the CPU 2. The priority is determined in consideration of, for example, high real-time performance.

Next, the transfer unit 16 according to the third embodiment will be described.

FIG. 11 is a block diagram illustrating the diagnosis unit 16 according to the third embodiment.

The diagnostic unit 16 configured in the dynamic partial reconstruction unit 183 of the FPGA 103 has a diagnostic area register 31 and a priority area determination unit 36 as compared with the diagnostic unit 12 described in the first embodiment (FIG. 3). Is different.

The diagnostic area register (first diagnostic area register) 30 sets the diagnostic address 76 of the memory area used by the OS (or application program) operating in the CPU 2. Further, the diagnostic area register (second diagnostic area register) 31 sets the diagnostic address 77 of the memory area used by the second OS (or the second application program) operating in the CPU 6.

The priority area determination unit 36 preferentially selects the diagnostic address 77 used by the second OS (or the second application program) from the diagnostic address 76 or the diagnostic address 77. That is, the priority area is determined from the diagnosis area register 30 and the second diagnosis area register 31, and the determination result is output to the diagnosis data generation unit 32.

Then, the priority area determination unit 36 causes the diagnostic data generation unit 32 to execute the memory diagnosis of the memory area specified by the diagnostic address 76 after the memory diagnosis of the memory area specified by the diagnostic address 77 is completed. On the other hand, the judgment result is output and instructed.

According to this embodiment, a specific OS or application program is installed in order to realize high reliability in a control device or control method in which a plurality of CPUs, a plurality of OSs or application programs are installed and the OSs or application programs are operated. It is possible to provide a control device and a control method capable of preferentially diagnosing a priority memory area and starting a specific OS or application program at high speed even when the priority is started.

First, the control device 400 according to the fourth embodiment will be described.

FIG. 12 is a block diagram illustrating the control device 400 according to the fourth embodiment.

The control device 400 described in this embodiment executes a memory area diagnostic process when a plurality of memories are mounted.

The control device 400 described in this embodiment has a plurality of memories 7, a memory 8, and a memory 9 as compared with the control device 100 described in the first embodiment (FIG. 1), and can be connected to these memories. It is different in that it has a memory controller 10 capable of being able to perform, and the parallel diagnosis unit 17 executes a diagnosis process of a plurality of memory areas of these memories.

Next, FIG. 13 for explaining the parallel diagnosis unit 17 according to the fourth embodiment is a block diagram for explaining the parallel diagnosis unit 17 according to the fourth embodiment.

The parallel diagnostic unit 17 configured in the dynamic partial reconstruction unit 184 of the FPGA 104 has a plurality of diagnostic units 12, a diagnostic unit 40, and a diagnostic unit 41 as compared with the diagnostic unit 12 described in Example 1 (FIG. 3). , A logical product calculation unit 42 that calculates a logical product, and a logical sum calculation unit 43 that calculates a logical sum are different.

The diagnostic unit 12, the diagnostic unit 40, and the diagnostic unit 41 have the same configuration as the diagnostic unit 12 described in Example 1 (FIG. 3). Further, the diagnostic unit 12, the diagnostic unit 40, and the diagnostic unit 41 are connected to the memory 7, the memory 8, and the memory 9 via the memory controller 10.

That is, the diagnostic unit 12 connects to the memory 7 via the memory controller 10. Similarly, the diagnostic unit 40 connects to the memory 8 via the memory controller 10. Similarly, the diagnostic unit 41 connects to the memory 9 via the memory controller 10.

Then, the diagnostic unit 12 outputs the diagnostic write data 74 to the memory controller 10 and inputs the diagnostic read data 75 from the memory controller 10. Similarly, the diagnostic unit 40 outputs the diagnostic write data 80 to the memory controller 10 and inputs the diagnostic read data 81 from the memory controller 10. Similarly, the diagnostic unit 41 outputs the diagnostic write data 82 to the memory controller 10 and inputs the diagnostic read data 83 from the memory controller 10.

Further, the diagnosis unit 12 outputs a diagnosis result (signal) 91. Similarly, the diagnosis unit 40 outputs the diagnosis result (signal) 92. Similarly, the diagnosis unit 41 outputs the diagnosis result (signal) 93.

Further, the diagnosis unit 12 outputs a diagnosis end (signal) 73. Similarly, the diagnosis unit 40 outputs the diagnosis end (signal) 78. Similarly, the diagnosis unit 41 outputs the diagnosis end (signal) 79.

The OR unit 43 inputs the diagnosis result 91 output from the diagnosis unit 12, the diagnosis result 92 output from the diagnosis unit 40, and the diagnosis result 93 output from the diagnosis unit 41, and puts them together. The diagnosis result (signal) 94 is output.

If the value of the diagnostic read data 75 and the value of the diagnostic write data 74 in the diagnostic unit 12 match, the diagnostic target address of the memory 7 is operating normally. However, if these values do not match, the diagnosis target address of the memory 7 is not operating normally. Then, for example, when the operation is normal, the value of the diagnosis result 91 is output as "0", and when the operation is not normal, the value of the diagnosis result 91 is output as "1".

Similarly, in the diagnosis unit 40, when the value of the diagnosis read data 80 and the value of the diagnosis write data 81 match, the diagnosis target address of the memory 8 is operating normally. However, if these values do not match, the diagnosis target address of the memory 8 is not operating normally. Then, for example, when the operation is normal, the value of the diagnosis result 92 is output as "0", and when the operation is not normal, the value of the diagnosis result 92 is output as "1".

Similarly, in the diagnosis unit 41, when the value of the diagnosis read data 82 and the value of the diagnosis write data 83 match, the diagnosis target address of the memory 9 is operating normally. However, if these values do not match, the diagnosis target address of the memory 9 is not operating normally. Then, for example, when the operation is normal, the value of the diagnosis result 93 is output as "0", and when the operation is not normal, the value of the diagnosis result 93 is output as "1".

When all of the memory 7, the memory 8 and the memory 9 are operating normally, the values of the diagnosis result 91, the diagnosis result 92 and the diagnosis result 93 are 0 + 0 + 0 because "0" is output respectively, and the diagnosis is made. As the value of the result 94, "0" is output. On the other hand, if any of the memory 7, the memory 8 and the memory 9 is not operating normally, "1" is output as the diagnosis result, and therefore "0" is output as the value of the diagnosis result 94. Not done.

In this embodiment, "0" is output as the values of the diagnosis result 91, the diagnosis result 92, and the diagnosis result 93 when the operation is normal, and the diagnosis result 91 and the diagnosis result 92 are output when the operation is not normal. , "1" is output as the value of the diagnosis result 93. When all of the memory 7, the memory 8 and the memory 9 are operating normally, the value of the diagnosis result 94 is "0", and any of the memory 7, the memory 8 and the memory 9 is normal. If it is not operating, the value of the diagnosis result 94 is "1".

Further, although not shown, it is possible to determine which memory (memory 7, memory 8, memory 9) is not operating normally from the diagnosis result 91, the diagnosis result 92, and the diagnosis result 93.

The AND calculation unit 42 inputs the diagnosis end 73 output from the diagnosis unit 12, the diagnosis end 78 output from the diagnosis unit 40, and the diagnosis end 79 output from the diagnosis unit 41, and puts them together. The diagnosis end (signal) 84 is output.

In this embodiment, "0" is output as the values of the diagnosis end 73, the diagnosis end 78, and the diagnosis end 79 when the memory diagnosis is not completed, and the diagnosis is completed when the memory diagnosis is completed. "1" is output for each of the values 73, the end of diagnosis 78, and the end of diagnosis 79.

Therefore, if the memory diagnosis of any of the memory 7, the memory 8, and the memory 9 is not completed, "0" is output as the value of the diagnosis end 84, and all the memories of the memory 7, the memory 8, and the memory 9 are output. When the diagnosis is completed, "1" is output as the value of the diagnosis end 84.

According to this embodiment, in a control device or control method equipped with a CPU and a plurality of memories, a plurality of memories can be diagnosed in parallel, and an OS or an application program can be started at high speed. Further, by allocating one diagnostic unit to one memory, it is possible to explicitly determine which memory is not operating normally as a result of the diagnosis.

Here, a case where the control device according to this embodiment is applied to the plant P1 will be described.

FIG. 14 is an explanatory diagram illustrating a case where the control device according to this embodiment is applied to the plant P1.

In the plant P1 described in this embodiment, the input / output device 1030 to which the field device 301 and the valve 302 (an example of the operating device) are connected is connected to the controller 1010 via the field network 121. Further, the input / output device 1060 to which the field device 305 and the pump 306 (an example of the operating device) are connected is connected to the controller 1040 via the field network 122.

Further, the controller 1010 and the controller 1040 are connected to the HMI (Human Machine Interface) 107 and the computer 108 via the control network 124.

The controller 1010 includes the control device 501 described in the first embodiment and the like, and the controller 1040 contains the control device 502 described in the first embodiment and the like.

In this embodiment, a case where the plant P1 is started will be described.

When the power of the system is turned on, the HMI 107 and the computer 108 are started. Then, the controller 1010 and the controller 1040 are activated via the control network 124. Then, the input / output device 1030 and the input / output device 1060 are activated via the field network 121 and the field network 122. Then, the field device 301 and the field device 305 are activated.

Here, the controller 1010 that has received the start signal via the control network 124 executes the memory diagnosis and the start of the OS and the application program at high speed by the control device 501 built in the controller 1010. Similarly, the controller 1040 that has received the start signal via the control network 124 executes the memory diagnosis and the start of the OS and the application program at high speed by the control device 502 built in the controller 1040.

According to this embodiment, in a system such as a plant composed of a plurality of controllers and computers, the memory diagnosis and the startup of the OS and the application program can be accelerated, and the startup of the system such as the plant can be accelerated. Can be done.

And even if a system such as a plant has a power outage or a momentary power failure, it can be started up with high reliability and speed, shorten the time required for restarting, and speed up the system. Recovery can be realized and better service can be provided.

Here, FIG. 15 for explaining the case where the control device according to the present embodiment is applied to the plant P2 is an explanatory diagram for explaining the case where the control device according to the present embodiment is applied to the plant P2.

The plant P2 described in this embodiment is compared with the plant P1 described in Example 5 (FIG. 14).
The difference is that the HMI 107 and the computer 108 are connected to the monitoring server 109 via the information network 125. Then, the monitoring server 109 monitors the state of the plant P2 and issues a command in the event of an abnormality or an emergency.

Although not shown, a further controller is installed between the input / output device 1030 to which the field device 301 and the valve 302 are connected and the controller 1010, and the controller and the input / output device 1030 form a field network. It may be connected via. Similarly, a further controller is installed between the input / output device 1060 to which the field device 305 and the pump 306 are connected and the controller 1040, and the controller and the input / output device 1060 are connected via the field network. May be done.

In the plant P2 described in this embodiment, the monitoring server 109 is the control device 505, the HMI 107 is the control device 503, the computer 108 is the control device 504, the controller 1010 is the control device 501, and the controller 1040 is the control device 502. The input / output device 1030 control device 507 and the input / output device 1060 have a control device 508 built-in.

In this embodiment, a case where the plant P2 is started will be described.

When the power of the system is turned on, the control device 505 executes the memory diagnosis of the monitoring server 109 and the startup of the OS and the application program.

Then, via the information network 125, the control device 503 executes the memory diagnosis of the HMI 107 and starts the OS and the application program, and the control device 504 executes the memory diagnosis of the computer 108 and starts the OS and the application program. Will be done.

Next, the control device 501 executes the memory diagnosis of the controller 1010 and starts the OS and the application program via the control network 124, and the control device 502 executes the memory diagnosis of the controller 1040 and starts the OS and the application program. Is executed.

Next, the control device 507 executes the memory diagnosis of the input / output device 1030 and starts the OS and the application program via the field network 121, and the control device 508 executes the memory diagnosis of the input / output device 1030 and the input / output device via the field network 122. The memory diagnosis of 1060 and the startup of the OS and application programs are executed.

According to this embodiment, in a system such as a plant composed of a plurality of controllers, computers, servers, etc., it is possible to speed up memory diagnosis and startup of an OS or an application program. In particular, even in a system in which a plurality of devices (input / output devices, controllers, HMIs, computers, servers, etc.) are layered and connected by a network, the startup can be speeded up.

And even if a power failure or momentary power failure occurs in the system, the startup can be made faster with high reliability, the time required for restarting can be shortened, and the system can be restored quickly. It can be realized and better service can be provided.

Further, even when the system is distributed over a wide area, the time required for restarting can be shortened, the system can be quickly restored, and better service can be provided.

The control devices and control methods described in these examples can be used in various systems such as elevator control systems, railway control systems, automobile control systems, construction machine control systems, and power generation control systems.

Further, the present invention is not limited to the above-described examples, and includes various modifications. For example, the above-described embodiment describes the control device and the control method in detail and concretely in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to those having all the components described. It is also possible to replace some of the components of one embodiment with some of the components of another example. It is also possible to add the constituent requirements of another embodiment to the constituent requirements of one embodiment. It is also possible to add, delete, or replace some of the other components with respect to some of the components of each embodiment.

100, 200, 300, 400, 501, 502, 503, 504, 505, 507, 508 ... Control device, 101, 102, 103, 104 ... FPGA, 2, 6 ... CPU, 3, 10 ... Memory controller, 4, 7, 8, 9 ... memory, 5 ... non-volatile memory, 11 ... start control unit, 12, 16, 40, 41 ... diagnostic unit, 14 ... diagnostic transfer unit, 17 ... parallel diagnostic unit, 181, 182, 183, 184 ... Dynamic partial reconstruction unit, 20 ... state transition unit, 21 ... control signal generation unit, 22 ... multiplexer, 23 ... data buffer, 24 ... output control unit, 30, 31 ... diagnostic area register, 32 ... diagnostic data generation unit, 33 ... Comparison unit, 34 ... Diagnostic write buffer, 35 ... Diagnostic read buffer, 36 ... Priority area determination unit, 37 ... Transfer address generation unit, 38, 39 ... Transfer data buffer, 42 ... Logical product calculation unit, 43 ... Logical sum Computational unit, 50 ... dual port memory controller, 51 ... dual port memory, 52 ... dual port interface, 1010, 1040 ... controller, 1030, 1060 ... input / output device, 107 ... HMI, 108 ... computer, 109 ... monitoring server, 301 , 305 ... Field equipment 302 ... Valve, 306 ... Pump, P1, P2 ... Plant.

Claims (7)

It has a storage unit and a reconfigurable field programmable gate array, the field programmable gate array constitutes a start-up control unit at startup, and the start-up control unit provides a diagnostic unit in the field programmable gate array. A control device that is configured and the diagnostic unit executes a diagnosis of the storage unit. The first aspect of claim 1, wherein the activation control unit includes a data buffer for storing bitstream data for generating the diagnosis unit and an output control unit for controlling the output of the bitstream data. Control device. The diagnostic unit writes to the storage unit, a diagnostic area register that sets the diagnostic target address of the storage unit, a diagnostic data generation unit that generates diagnostic data based on the diagnostic target address set by the diagnostic area register, and the storage unit. It has a diagnostic write buffer for storing diagnostic write data, a diagnostic read buffer for storing diagnostic read data read from the storage unit, and a comparison unit for comparing the diagnostic write data with the diagnostic read data. The control device according to claim 1, which is characterized. The control according to claim 1, wherein the storage unit is a dual port memory, the activation control unit constitutes a diagnostic transfer unit, and the diagnostic transfer unit executes a diagnosis of the storage unit. apparatus. The diagnostic unit has a first diagnostic area register and a second diagnostic area register, determines a priority area from the first diagnostic area register and the second diagnostic area register, and makes the diagnosis. The control device according to claim 3, wherein the data generation unit includes a priority area determination unit that outputs the determination result. The first aspect of the present invention is characterized in that the storage unit is a plurality of storage units, the activation control unit constitutes a parallel diagnosis unit, and the parallel diagnosis unit executes a diagnosis of the plurality of storage units. The control device to be described. A control method for performing memory diagnosis
At startup, a reconfigurable field programmable gate array is configured with a start control unit, the start control unit configures a diagnostic unit in the field programmable gate array, and the diagnostic unit executes a diagnosis of the storage unit. A control method characterized by doing.

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