JP2020161675A - Power semiconductor device - Google Patents

Abstract

To solve such a problem that thermal warpage occurs in a lamination structure part with an insulation board in the manufacturing process of power semiconductor device, and exfoliation occurs in the lamination structure part to decrease reliability.SOLUTION: In a first conductor 3, a penetration part 3a is formed in a portion corresponding to a crevice region 30. On the first conductor 3, an insulation board 50 is laminated. Since a region where only the first conductor 3 is connected with the insulation board 50 decreases, by providing the penetration part 3a in the first conductor 3, thermal warpage can be restrained, and stress generated in a connection material 2b of a first power semiconductor element 1a and a second conductor interface, and stress generated in the connection material 2b of a second power semiconductor element 1b and the second conductor interface are also reduced. Consequently, crack and exfoliation of a lamination structure of the first conductor 3 and the insulation board 50 can be prevented, resulting in a highly reliable power semiconductor device.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power semiconductor device.

Power semiconductor devices are applied to power conversion devices that control motors for driving vehicles. It is also applied not only to vehicle driving but also to power conversion devices that control motors of railways, elevators, industrial equipment, aircraft, and the like.

For example, in a power conversion device for a hybrid vehicle or an electric vehicle, a power semiconductor device having a high operating voltage is desired for the purpose of shortening the charging time. In a power semiconductor device having a high operating voltage, a ceramic material having a high dielectric strength may be used as an insulating substrate. On the other hand, double-sided direct cooling type power semiconductor devices are known due to the demand for miniaturization and cooling performance. Patent Document 1 discloses a power semiconductor device that cools a plurality of semiconductor elements constituting the upper and lower arms of the power conversion device from both sides.

Japanese Unexamined Patent Publication No. 2012-257369

In the manufacturing process of the power semiconductor device, thermal warpage may occur in the laminated structure portion with the insulating substrate, causing peeling or the like in the laminated structure portion, which may reduce reliability.

The power semiconductor device according to the present invention is connected to the first semiconductor element and the second semiconductor element, and the first semiconductor element and the second semiconductor element are arranged side by side so as to be separated from each other with a gap region between them. On a surface opposite to the surface of the semiconductor element and the first conductor and the second conductor arranged so as to sandwich the second semiconductor element, and the surface of the first conductor connected to the first semiconductor element and the second semiconductor element. A first insulating substrate to be laminated is provided, and the first conductor has a penetrating portion formed in a portion corresponding to the gap region.

According to the present invention, it is possible to provide a highly reliable power semiconductor device by preventing peeling of a laminated structure portion from an insulating substrate.

It is sectional drawing of the power semiconductor device which concerns on 1st Embodiment. It is a developed perspective view of the power semiconductor device which concerns on 1st Embodiment. It is an external view of the power semiconductor device which concerns on 1st Embodiment. It is a top view which shows the 1st conductor which concerns on 1st Embodiment. It is a figure which shows the manufacturing process of a power semiconductor device. It is a figure which shows the manufacturing process of a power semiconductor device. It is a figure which shows the manufacturing process of a power semiconductor device. It is a figure which shows the manufacturing process of a power semiconductor device. It is sectional drawing of the power semiconductor device which concerns on 1st Embodiment, and is the figure which showed the width. It is a top view which shows the 1st conductor which concerns on 2nd Embodiment. It is a top view which shows the 1st conductor which concerns on 3rd Embodiment. It is sectional drawing of the power semiconductor device which concerns on other embodiment. It is sectional drawing of the power semiconductor device which concerns on other embodiment.

[First Embodiment]
The power semiconductor device 100 according to this embodiment will be described with reference to FIGS. 1 to 9. FIG. 1 is a cross-sectional view of the power semiconductor device 100. FIG. 2 is a developed perspective view of the power semiconductor device 100. FIG. 3 is an external view of the power semiconductor device 100. Note that FIG. 1 shows a cross-sectional view taken along the line AA'in FIG.

As shown in FIG. 1, in the power semiconductor device 100, the power semiconductor element 1a and the power semiconductor element 1b are arranged side by side. That is, the power semiconductor element 1a and the power semiconductor element 1b are arranged side by side so as to be separated from each other with the gap region 30 interposed therebetween. Each electrode of the power semiconductor element 1a and the power semiconductor element 1b is sandwiched between the first conductor 3 and the second conductor 4 arranged so as to face each electrode surface. The first power semiconductor element 1a and the second power semiconductor element 1b are joined to the first conductor 3 and the second conductor 4 by connecting materials 2a and 2b, respectively. The first conductor 3 and the second conductor 4 are formed of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. The connecting materials 2a and 2b are formed of a solder material, a sintered material, or the like.

A penetrating portion 3a is formed in the first conductor 3 at a portion corresponding to the gap region 30. Further, a wiring board 11 is provided between the first power semiconductor element 1a and the second power semiconductor element 1b on the second conductor 4, that is, in the gap region 30. The wiring substrate 11 has, for example, a pattern wiring in which a copper electrode is provided on a glass epoxy resin, and is electrically connected to the first power semiconductor element 1a and the second power semiconductor element 1b by a wiring 12. For the wiring 12, for example, an aluminum wire or a copper wire can be used.

An insulating substrate 50 is laminated on the first conductor 3 on a surface opposite to the surface of the first conductor 3 connected to the first power semiconductor element 1a and the second power semiconductor element 1b. The insulating substrate 50 is composed of an insulating member 50a, a first conductor layer 50b, and a second conductor layer 50c. The first conductor layer 50b is arranged on one surface of the insulating member 50a, and the second conductor layer 50c is arranged on the other surface. To. The surface of the first conductor 3 opposite to the surface connected to the first power semiconductor element 1a and the second power semiconductor element 1b is connected to the first conductor layer 50b via the connecting material 6. The second conductor layer 50c is connected to the heat radiating member 8 via the connecting material 7. A heat radiating fin 9 is formed on the surface of the heat radiating member 8.

The insulating substrate 5 is laminated on the second conductor 4. The insulating substrate 5 is composed of an insulating member 5a, a first conductor layer 5b, and a second conductor layer 5c. The first conductor layer 5b is arranged on one surface of the insulating member 5a, and the second conductor layer 5c is arranged on the other surface. To. The surface of the second conductor 4 opposite to the surface connected to the first power semiconductor element 1a and the second power semiconductor element 1b is connected to the first conductor layer 5b via the connecting material 6. The second conductor layer 5c is connected to the heat radiating member 8 via the connecting material 7. A heat radiating fin 9 is formed on the surface of the heat radiating member 8.

The insulating member 5a and the insulating member 50a conduct the heat generated from the first power semiconductor element 1a and the second power semiconductor element 1b to the heat radiating member 8, and have high thermal conductivity and high insulation withstand voltage. A ceramic material is used as the material. For example, ceramic materials such as aluminum oxide (alumina), aluminum nitride, and silicon nitride are used. The connecting material 6 and the connecting material 7 are formed of a solder material, a sintered material, or the like. The heat radiating member 8 and the heat radiating fin 9 are members having electrical conductivity, for example, a composite material such as Cu, Cu alloy, Cu-C, Cu-CuO, or a composite material such as Al, Al alloy, AlSiC, Al-C, etc. Is formed from.

As shown in FIG. 2, five first power semiconductor elements 1a and five second power semiconductor elements 1b are provided in one row, and two rows are provided in parallel. Two first conductors 3, two second conductors 4, and two wiring boards 11 are provided corresponding to the first power semiconductor element 1a and the second power semiconductor element 1b provided in parallel in two rows. The first conductor 3 is provided with a through portion 3a corresponding to the gap region between the first power semiconductor element 1a and the second power semiconductor element 1b shown by AA in FIG. .. The terminal 14 shown in FIG. 2 is connected to the first conductor layer 5b of the insulating substrate 5 and the first conductor layer 50b of the insulating substrate 50.

FIG. 3 is an external view of the power semiconductor device 100. As shown in FIG. 3, except for the heat radiating surface 8a and the terminal 14 on which the heat radiating fins 9 are formed, the heat radiating surface 8a and the terminal 14 are sealed with the sealing resin 10.

FIG. 4 is a top view showing the first conductor 3. That is, it is a top view of only the first conductor 3 taken out and viewed from the connection surface side with the insulating substrate 50. As shown in FIG. 4, the first conductor 3 is provided with a penetrating portion 3a. The penetrating portion 3a is provided elongated along the arrangement direction of the first power semiconductor element 1a and the second power semiconductor element 1b. The position of the penetrating portion 3a corresponds to the gap region 30 between the first power semiconductor element 1a and the second power semiconductor element 1b, that is, the wiring substrate between the first power semiconductor element 1a and the second power semiconductor element 1b. It is provided at a position facing the 11. By providing the through portion 3a in the first conductor 3 in this way, the joint area between the insulating substrate 5 and the first conductor 3 can be reduced. Here, when the length of the first power semiconductor element 1a and the second power semiconductor element 1b in the arrangement direction is L10 and the length of the penetrating portion 3a is L11, it is desirable that L11 ≧ L10.

5 to 8 are diagrams showing a manufacturing process of the power semiconductor device 100.
First, as shown in FIG. 5, the first power semiconductor element 1a and the second power semiconductor element 1b are connected to the second conductor 4 via a connecting material 2a. A wiring board 11 is provided on the second conductor 4, and a first power semiconductor element 1a and a second power semiconductor element 1b are arranged so as to sandwich the wiring board 11. The first power semiconductor element 1a and the second power semiconductor element 1b are each connected to the pattern wiring on the wiring board 11 by the wiring 12. The second conductor 4 is formed of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. The connecting material 2a is formed of a solder material, a sintered material, or the like.

Next, as shown in FIG. 6, the first conductor 3 is placed on the surface opposite to the surface of the first power semiconductor element 1a and the second power semiconductor element 1b to which the second conductor 4 is connected via the connecting material 2b. To connect. The first conductor 3 is formed of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. The connecting material 2b is formed of a solder material, a sintered material, or the like.

Next, as shown in FIG. 7, the first conductor 3 and the second conductor 4 are connected to the first conductor layer 50b of the insulating substrate 50 and the first conductor layer 5b of the insulating substrate 5 via the connecting material 6, respectively. To. In the insulating substrate 5, the first conductor layer 5b is arranged on one surface of the insulating member 5a, and the second conductor layer 5c is arranged on the other surface. The insulating substrate 50 and the insulating substrate 5 may be connected to the first conductor 3 and the second conductor 4 at the same time. By connecting at the same time, symmetry can be maintained and warpage deformation during assembly can be suppressed.

Next, as shown in FIG. 8, the heat radiating member 8 is connected to the insulating substrate 50 and the insulating substrate 5 via the connecting material 7. At this time, the heat radiating members 8 on both sides may be connected at the same time. By connecting at the same time, it is possible to suppress warpage deformation during assembly. Heat dissipation fins 9 are formed on the surface of the heat dissipation member 8. Finally, the heat radiating surface 8a on which the heat radiating fins 9 of the heat radiating member 8 are formed is sealed with the sealing resin 10.

Generally, in the case of a power semiconductor device that drives a plurality of power semiconductor elements using a SiC chip in parallel, it is necessary to provide a wiring board for connecting the gate wiring of the power semiconductor elements. Specifically, the wiring board 11 is provided between the first power semiconductor element 1a and the second power semiconductor element 1b. As a result, the distance between the first power semiconductor element 1a and the second power semiconductor element 1b becomes longer. When the first conductor 3 is not provided with the penetrating portion 3a, the insulating substrate and the conductor are laminated due to the difference in linear expansion coefficient between the insulating substrate and the conductor in the process of connecting at a high temperature and cooling to room temperature in the manufacturing process of the power semiconductor device 100. The warp deformation of the structure becomes large. As a result, stress is generated in the connecting material 2b at the interface between the first power semiconductor element 1a and the second conductor and the connecting material 2b at the interface between the second power semiconductor element 1b and the second conductor, which have a small bonding area, and cracks are likely to occur. Become. In particular, in a power semiconductor device having a double-sided cooling structure in which the first conductor 3 and the second conductor 4 are connected to both sides of the power semiconductor element and the insulating substrate is connected to the outside thereof, the first conductor 3 and the second conductor 4 and the insulating substrate are connected. Due to the thermal warp of the laminated structure, the laminated structure portion may be peeled off and the reliability may be lowered.

However, as in the present embodiment, the first power is provided by providing the penetrating portion 3a at a position facing the wiring board 11 between the first power semiconductor element 1a and the second power semiconductor element 1b of the first conductor 3. Between the semiconductor element 1a and the second power semiconductor element 1b, the lengths L1 and L2 (see FIG. 9) in which only the first conductor 3 is connected to the insulating substrate 50, which is an insulating substrate, can be shortened. As a result, the region where only the first conductor 3 is connected to the insulating substrate 50 is reduced, so that thermal warpage can be suppressed, and the connecting material 2b at the interface between the first power semiconductor element 1a and the second conductor and the second The stress generated in the connecting material 2b at the interface between the power semiconductor element 1b and the second conductor is also reduced. Therefore, it is possible to prevent cracks and peeling of the laminated structure of the first conductor 3 and the insulating substrate 50, and it is possible to provide a highly reliable power semiconductor device.

Further, when the power semiconductor device 100 is installed and used in a vehicle or the like, the power semiconductor device 100 repeatedly operates and stops, and as a result, repeatedly generates heat and cools. Since the power semiconductor device 100 repeatedly applies a large strain to the laminated portion of the insulating substrate and the conductor, there is a concern that the laminated portion may be peeled off. In the present embodiment, the penetrating portion 3a is provided at a position facing the wiring board 11 between the first power semiconductor element 1a and the second power semiconductor element 1b of the first conductor 3. As a result, the stress that occurs repeatedly is reduced, and the fatigue life is improved. As a result, a highly reliable power semiconductor device 100 can be realized.

Although the shape of the heat radiating fin 9 of the heat radiating member 8 has been described with the example of the pin fin, other shapes such as straight fins and corrugated fins may be used. Further, in this description, an example is shown in which the sealing resin 10 includes the heat radiating member 8 and the heat radiating surface 8a is sealed, but the insulating substrate 5 may be resin-sealed. In this case, if the second conductor layer 50c of the insulating substrate 50 and the heat radiating member 8 are connected and the second conductor layer 5c of the insulating substrate 5 and the heat radiating member 8 are connected, the same effect can be obtained.

FIG. 9 is a cross-sectional view of the power semiconductor device 100 similar to that shown in FIG.
As shown in FIG. 9, when the width of the penetrating portion is L3 and the width of the wiring board 11 is L4, it is desirable that L3 ≧ L4. Further, the distance between the first power semiconductor element 1a and the second power semiconductor element 1b is L5. That is, when the side surface of the first power semiconductor element 1a on the wiring board 11 side is 1c and the side surface of the second power semiconductor element 1b on the wiring board side is 1d, the distance between the side surface 1c and the side surface 1d is L5. , L3 ≦ L5.

In the present embodiment, as shown in FIG. 2, an example in which five first power semiconductor elements 1a and five second power semiconductor elements 1b are provided is shown, but the first power semiconductor element 1a and the second power It is sufficient that there is one or more semiconductor elements 1b each. The penetrating portion 3a may be provided at least between the first power semiconductor element 1a and the second power semiconductor element 1b. This has the same effect.

[Second Embodiment]
The second embodiment will be described with reference to FIG. FIG. 10 is a top view showing the first conductor 3'. The cross-sectional view of the power semiconductor device 100 in AA'in FIG. 10 including the first conductor 3'is the same as that in FIG. 1, and the developed perspective view of the power semiconductor device 100 including the first conductor 3'is shown in FIG. It is the same as 2.

As shown in FIG. 10, the first conductor 3'in the present embodiment is provided with a penetrating portion 3a'between the first power semiconductor element 1a and the second power semiconductor element 1b. A plurality of penetrating portions 3a'are provided in the arrangement direction of the first power semiconductor element 1a and the second power semiconductor element 1b. A connecting portion 3b'connecting between the first power semiconductor element side and the second power semiconductor element side of the first conductor 3'is provided at intervals of each first power semiconductor element 1a and each second power semiconductor element 1b. There is.

Here, when the length of the first power semiconductor element 1a and the second power semiconductor element 1b in the arrangement direction is L10'and the length of the penetrating portion 3a is L11', it is desirable that L11'≥ L10'.
According to this embodiment, in addition to having the effect described in the first embodiment, an effect of reducing the electric resistance in the first conductor 3'can be obtained.

[Third Embodiment]
A third embodiment will be described with reference to FIG. FIG. 11 is a top view showing the first conductor 3 ″. The cross-sectional view of the power semiconductor device 100 in AA'in FIG. 11 including the first conductor 3 ″ is the same as that in FIG. 1, and a developed perspective view of the power semiconductor device 100 including the first conductor 3 ″. Is the same as in FIG.

As shown in FIG. 11, the first conductor 3 ″ in the present embodiment is provided with a connecting portion 3b ″ connecting between the first power semiconductor element side and the second power semiconductor element side at only one place. There is. A penetrating portion 3a ″ is formed between the first power semiconductor element 1a and the second power semiconductor element 1b excluding the connecting portion 3b ″.

According to the present embodiment, in addition to having the effects described in the first embodiment, the bonding area of the first conductor 3 ″ connected to the insulating substrate 50 can be reduced, and the first conductor 3 ″ can be made smaller. 3e on the 1-power semiconductor element side and 3f on the 2nd power semiconductor element side of the 1st conductor 3 ″ can be freely deformed. Therefore, the thermal warpage of the laminated structure of the first conductor 3'' and the insulating substrate 50 can be further suppressed, and cracks and peeling of the laminated structure of the first conductor 3'' and the insulating substrate 50 can be prevented. It is possible to provide a highly reliable power semiconductor device. Further, the number of parts is reduced by connecting the first conductor 3'' at at least one place instead of completely dividing it into two by 3e on the first power semiconductor element side and 3f on the second power semiconductor element side. Further, the height adjustment when connecting the first conductor 3'' and the insulating substrate 50 becomes easy.

In the first to third embodiments described above, an example is shown in which the sealing resin includes the heat radiating member 8 and the heat radiating surface 8a is sealed. However, as shown in FIG. 12, the insulating substrates 5 and 50 may have a sealed structure. If the second conductor layers 5c and 50c of the insulating substrates 5 and 50 and the heat radiating member 8 are connected, the same effect can be obtained. Since other configurations are the same as those in FIG. 1, the same parts are designated by the same reference numerals and the description thereof will be omitted.

Further, in the first to third embodiments described above, the case where the heat radiating member 8 is connected to the entire surface of the second conductor layer 5c of the insulating substrates 5 and 50 has been described. However, as shown in FIG. 13, the structure may be such that the heat radiation fins 9 are directly provided on the second conductor layers 5c and 50c. Since other configurations are the same as those in FIG. 1, the same parts are designated by the same reference numerals and the description thereof will be omitted.

According to the embodiment described above, the following effects can be obtained.
(1) The power semiconductor device 100 includes a first power semiconductor element 1a and a second power semiconductor element 1b arranged side by side so as to be separated from each other with a gap region 30 interposed therebetween, and a first power semiconductor element 1a and a second power semiconductor element. Connected to the first conductor 3 and the second conductor 4 connected to 1b and arranged so as to sandwich the first power semiconductor element 1a and the second power semiconductor element 1b, and connected to the first power semiconductor element 1a and the second power semiconductor element 1b. An insulating substrate 5 laminated on a surface opposite to the surface of the first conductor 3 is provided, and the first conductor 3 has a penetrating portion 3a formed in a portion corresponding to the gap region 30. As a result, it is possible to provide a highly reliable power semiconductor device by preventing peeling of the laminated structure portion from the insulating substrate.

The present invention is not limited to the above-described embodiment, and other embodiments considered within the scope of the technical idea of the present invention are also included within the scope of the present invention as long as the features of the present invention are not impaired. .. Further, the configuration may be a combination of the above-described embodiments.

1a ... 1st power semiconductor element 1b ... 2nd power semiconductor element 2a, 2b ... Connecting material 3, 3', 3'' ... 1st conductor 3a ... Penetrating part 3b ... Connecting part 4 ... 2nd conductor 5 ... Insulating substrate 5a ... Insulating member 5b ... First conductor layer 5c ... Second conductor layers 6, 7 ... Connecting material 8 ... Heat dissipation member 8a ... Heat dissipation surface 9 ... Heat dissipation fin 10 ... Sealing resin 11 ... Wiring board 12 ... Wiring 14 ... Terminal 30 ... Gap region 50 ... Insulation substrate 50a ... Insulation member 50b ... First conductor layer 50c ... Second conductor layer

Claims (8)

The first semiconductor element and the second semiconductor element, which are arranged side by side so as to be separated from each other with a gap region,
A first conductor and a second conductor connected to the first semiconductor element and the second semiconductor element and arranged so as to sandwich the first semiconductor element and the second semiconductor element.
The first semiconductor element and the first insulating substrate connected to the second semiconductor element and laminated on the surface opposite to the surface of the first conductor are provided.
The first conductor is a power semiconductor device in which a penetration portion is formed in a portion corresponding to the gap region. In the power semiconductor device according to claim 1,
A power semiconductor device including a second insulating substrate laminated on a surface opposite to the surface of the first semiconductor element and the second conductor connected to the second semiconductor element. In the power semiconductor device according to claim 2,
The first insulating substrate and the second insulating substrate are power semiconductor devices that are substrates containing a ceramic material. In the power semiconductor device according to claim 1,
On the second conductor, a wiring substrate electrically connected to the first semiconductor element and the second semiconductor element is provided in the gap region, and the penetrating portion formed in the first conductor is said. A power semiconductor device installed at a position facing the wiring board. In the power semiconductor device according to claim 4,
A power semiconductor device in which L3 ≧ L4 when the width of the penetrating portion is L3 and the width of the wiring board is L4. The power semiconductor device according to any one of claims 1 to 4.
When the width of the penetrating portion between the first semiconductor element and the second semiconductor element is L3 and the distance between the first semiconductor element and the second semiconductor element is L5, the power semiconductor is L3 ≦ L5. apparatus. The power semiconductor device according to any one of claims 1 to 4.
A power semiconductor device in which L11 ≥ L10, where L10 is the length of the first semiconductor element or the second semiconductor element in the arrangement direction and L11 is the length of the penetration portion in the arrangement direction. The power semiconductor device according to any one of claims 1 to 4.
A power semiconductor device in which a sealing resin is filled in the penetrating portion.

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