JP2020161676A - Power semiconductor device - Google Patents

Abstract

To solve such a problem that thermal warpage occurs in a lamination structure part with an insulation board in the manufacturing process of power semiconductor device, and exfoliation occurs in the lamination structure part to reduce reliability.SOLUTION: A first power semiconductor element 1a is placed in a central part of arrangement of a first conductor 3 and a second conductor 4, and dummy chips 20 are placed on both end sides of the arrangement. When the dummy chips 20 are placed according to the embodiment, each dummy chips 20 is connected with the second conductor 4 via a connection material 2a, and connected with the first conductor 3 via a connection material 2b so as to reduce a length for connecting only a conductor with an insulation board and thereby thermal warpage can be suppressed. With such an arrangement, stress generated in the connection material 2b is reduced, and crack can be prevented. Consequently, exfoliation of a lamination part can be prevented, and a highly reliable power semiconductor device 100 can be realized.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power semiconductor device.

Power semiconductor devices are applied to power conversion devices that control motors for driving vehicles. It is also applied not only to vehicle driving but also to power conversion devices that control motors of railways, elevators, industrial equipment, aircraft, and the like.

For example, in a power conversion device for a hybrid vehicle or an electric vehicle, a power semiconductor device having a high operating voltage is desired for the purpose of shortening the charging time. In a power semiconductor device having a high operating voltage, a ceramic material having a high dielectric strength may be used as an insulating substrate. On the other hand, double-sided direct cooling type power semiconductor devices are known due to the demand for miniaturization and cooling performance. Patent Document 1 discloses a power semiconductor device that cools a plurality of semiconductor elements constituting the upper and lower arms of the power conversion device from both sides.

Japanese Unexamined Patent Publication No. 2012-257369

In the manufacturing process of the power semiconductor device, thermal warpage may occur in the laminated structure portion with the insulating substrate, causing peeling or the like in the laminated structure portion, which may reduce reliability.

The power semiconductor device according to the present invention includes a first conductor, a semiconductor element and a plurality of dummy chips arranged side by side on the same surface of the first conductor and connected to the first conductor, and the semiconductor element and the plurality of dummies. A second conductor arranged so as to face the first conductor with a chip interposed therebetween and connected to the semiconductor element and the plurality of dummy chips, and the first conductor in which the semiconductor element and the plurality of dummy chips are arranged. A first insulating substrate connected to a surface opposite to the surface of the second conductor, and a second insulating substrate connected to a surface opposite to the surface of the second conductor in which the semiconductor element and the plurality of dummy chips are arranged. , And the thickness sandwiched between the first conductor and the second conductor is the same as that of the semiconductor element, and the dummy chip does not function as a semiconductor element.

According to the present invention, it is possible to provide a highly reliable power semiconductor device by preventing peeling of a laminated structure portion from an insulating substrate.

It is sectional drawing of the power semiconductor device which concerns on 1st Embodiment. It is a developed perspective view of the power semiconductor device which concerns on 1st Embodiment. It is an external view of the power semiconductor device which concerns on 1st Embodiment. It is a top view which shows the component on the 2nd conductor which concerns on 1st Embodiment. It is a figure which shows the manufacturing process of a power semiconductor device. It is a figure which shows the manufacturing process of a power semiconductor device. It is a figure which shows the manufacturing process of a power semiconductor device. It is a figure which shows the manufacturing process of a power semiconductor device. It is sectional drawing for comparison with this embodiment. It is sectional drawing of the power semiconductor device which concerns on 2nd Embodiment. It is a top view which shows the component on the 2nd conductor which concerns on 2nd Embodiment. It is sectional drawing of the power semiconductor device which concerns on another form. It is sectional drawing of the power semiconductor device which concerns on another form.

[First Embodiment]
The power semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 1 to 9. FIG. 1 is a cross-sectional view of the power semiconductor device 100. FIG. 2 is a developed perspective view of the power semiconductor device 100. FIG. 3 is an external view of the power semiconductor device 100. Note that FIG. 1 shows a cross-sectional view taken along the line AA'shown in FIGS. 2 and 3.

As shown in FIG. 1, in the power semiconductor device 100 of the present embodiment, three first power semiconductor elements 1a are arranged side by side in the central portion, and the first power semiconductor element 1a is located at positions on both ends away from the central portion. Two dummy chips 20 are arranged side by side with. The plurality of first power semiconductor elements 1a and the dummy chip 20 are sandwiched between the first conductor 3 and the second conductor 4 arranged so as to face each of the electrode surfaces. The dummy chip 20 is a material that does not function as a semiconductor element because the thickness sandwiched between the first conductor 3 and the second conductor 4 is the same as that of the first power semiconductor element 1a. The first power semiconductor element 1a and the dummy chip 20 are joined to the first conductor 3 and the second conductor 4 by connecting materials 2b and 2a, respectively. The dummy chip 20 is connected to the same surface as the surface 4b of the second conductor 4 to which the first power semiconductor element 1a is connected. The first conductor 3 and the second conductor 4 are formed of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like, and the connecting materials 2b and 2a are formed of a solder material, a sintered material, or the like.

The dummy chip 20 may use the same components as the first power semiconductor element 1a. In this case, since the wiring 12 (see FIG. 4) is not connected, no current flows through the dummy chip 20. By using the same components as the first power semiconductor element 1a as the dummy chip 20, there is no increase in the types of components, and an increase in cost can be suppressed. Further, the dummy chip 20 may be a semiconductor material having metal films formed on both surfaces in contact with the first conductor 3 and the second conductor 4. Further, the dummy chip may be an insulating material having metal films formed on both sides in contact with the first conductor 3 and the second conductor 4. If the thickness of the dummy chip 20 is the same as that of the first power semiconductor element 1a, the solder thickness can be easily controlled in the step of connecting with the connecting material 2b.

The second insulating substrate 50 is composed of an insulating member 50a, a first conductor layer 50b, and a second conductor layer 50c. The surface of the first conductor 3 opposite to the surface connecting the power semiconductor element 1a and the dummy chip 20 is connected to the first conductor layer 50b via the connecting material 6. The first conductor layer 50b is arranged on one surface of the insulating member 50a, and the second conductor layer 50c is arranged on the other surface. The second conductor layer 50c is connected to the heat radiating member 8 via the connecting material 7. A heat radiating fin 9 is formed on the surface of the heat radiating member 8.

The first insulating substrate 5 is composed of an insulating member 5a, a first conductor layer 5b, and a second conductor layer 5c. The surface of the second conductor 4 opposite to the surface connecting the first power semiconductor element 1a and the dummy chip 20 is connected to the first conductor layer 5b via the connecting material 6. In the first insulating substrate 5, the first conductor layer 5b is arranged on one surface of the insulating member 5a, and the second conductor layer 5c is arranged on the other surface. The second conductor layer 5c is connected to the heat radiating member 8 via the connecting material 7. Heat dissipation fins 9 are formed on the surface of the heat dissipation member 8.

As shown in FIG. 2, three first power semiconductor elements 1a and three second power semiconductor elements 1b are provided in one row, and two rows are provided in parallel. Dummy chips 20 are arranged at both ends of the row of the first power semiconductor element 1a and the row of the second power semiconductor element 1b. Two first conductors 3, two second conductors 4, and two wiring boards 11 are provided corresponding to the first power semiconductor element 1a and the second power semiconductor element 1b provided in parallel in two rows. The terminal 14 shown in FIG. 2 is connected to the first conductor layer 5b of the first insulating substrate 5 and the first conductor layer 50b of the second insulating substrate 50.

A wiring board 11 is provided on the second conductor 4 between the first power semiconductor element 1a and the second power semiconductor element 1b on the second conductor 4. The wiring board 11 is provided with pattern wiring on, for example, a glass epoxy resin. The pattern wiring of the wiring board 11 is electrically connected to the first power semiconductor element 1a and the second power semiconductor element 1b.

The insulating member 5a of the first insulating substrate 5 and the insulating member 50a of the second insulating substrate 50 conduct the heat generated from the first power semiconductor element 1a and the second power semiconductor element 1b to the heat radiating member 8. Use a ceramic material with high thermal conductivity and high insulation withstand voltage. For example, ceramic materials such as aluminum oxide (alumina), aluminum nitride, and silicon nitride are used. The connecting material 6 and the connecting material 7 are formed of a solder material, a sintered material, or the like. The heat radiating member 8 and the heat radiating fin 9 are members having electrical conductivity, for example, a composite material such as Cu, Cu alloy, Cu-C, Cu-CuO, or a composite material such as Al, Al alloy, AlSiC, Al-C, etc. Is formed from.

FIG. 3 is an external view of the power semiconductor device 100. As shown in FIG. 3, except for the heat radiating surface 8a and the terminal 14 on which the heat radiating fins 9 are formed, the heat radiating surface 8a and the terminal 14 are sealed with the sealing resin 10.

FIG. 4 is a top view showing the second conductor 4 and the parts and the like on the second conductor 4. That is, it is a top view of the second conductor 4 taken out and viewed from the connection surface side with the second insulating substrate 50. As shown in FIG. 4, the first power semiconductor element 1a and the second power semiconductor element 1b are arranged in parallel, and dummy chips 20 are arranged at both ends in the arrangement direction. A wiring board 11 is arranged between the arranged first power semiconductor elements 1a and the second power semiconductor elements 1b. That is, the first power semiconductor element 1a and the second power semiconductor element 1b are arranged so as to sandwich the wiring board 11. The first power semiconductor element 1a and the second power semiconductor element 1b are electrically connected by the wiring pattern of the wiring substrate 11 and the wiring 12. For the wiring 12, for example, an aluminum wire or a copper wire can be used. On the other hand, the dummy chip 20 is not electrically connected to the wiring board 11.

5 to 8 are diagrams showing a manufacturing process of the power semiconductor device 100.
First, as shown in FIG. 5, the first power semiconductor element 1a and the dummy chip 20 are connected to the second conductor 4 via the connecting material 2a. Dummy chips 20 are provided at positions far from the center of the second conductor 4, that is, on both ends as compared with the first power semiconductor element 1a. The first power semiconductor element 1a is electrically connected to the pattern wiring of the wiring board 11 by the wiring 12 (see FIG. 4). On the other hand, the dummy chip 20 is not electrically connected to the pattern wiring of the wiring board 11.

The second conductor 4 is formed of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. The connecting material 2a is formed of a solder material, a sintered material, or the like.

Next, as shown in FIG. 6, the first conductor 3 is connected to the surface opposite to the surface to which the first power semiconductor element 1a and the second conductor 4 of the dummy chip 20 are connected via the connecting material 2b. .. The first conductor 3 is formed of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. The connecting material 2b is formed of a solder material, a sintered material, or the like.

Next, as shown in FIG. 7, the first conductor 3 and the second conductor 4 are connected to the first conductor layer 50b of the second insulating substrate 50 and the first conductor layer of the first insulating substrate 5 via the connecting material 6, respectively. Connected to 5b. In the first insulating substrate 5, the first conductor layer 5b is arranged on one surface of the insulating member 5a, and the second conductor layer 5c is arranged on the other surface. The second insulating substrate 50 and the first insulating substrate 5 may be connected to the first conductor 3 and the second conductor 4 at the same time. By connecting at the same time, symmetry can be maintained and warpage deformation during assembly can be suppressed.

Next, as shown in FIG. 8, the heat radiating member 8 is connected to the second insulating substrate 50 and the first insulating substrate 5 via the connecting material 7. At this time, the heat radiating members 8 on both sides may be connected at the same time. By connecting at the same time, it is possible to suppress warpage deformation during assembly. Heat dissipation fins 9 are formed on the surface of the heat dissipation member 8. Finally, as shown in FIG. 1, the heat-dissipating surface 8a on which the heat-dissipating fins of the heat-dissipating member 8 are formed is sealed with the sealing resin 10.

Although the shape of the heat radiating fin 9 of the heat radiating member 8 is a pin fin, other shapes such as straight fins and corrugated fins may be used. Further, in the present embodiment, an example is shown in which the sealing resin 10 includes the heat radiating member 8 and the heat radiating surface 8a is sealed, but even if the structure up to the first insulating substrate 5 is resin-sealed. Good. In this case, if the second conductor layer 50c of the second insulating substrate 50 and the heat radiating member 8 are connected, and the second conductor layer 5c of the first insulating substrate 5 and the heat radiating member 8 are connected, the same effect can be obtained. can get.

Generally, in the case of a power semiconductor device that drives a plurality of power semiconductor elements having a small chip size in parallel, such as a SiC chip, the connection area of the connecting material 2b that connects the first power semiconductor element 1a and the first conductor 3 becomes small. FIG. 9 is a cross-sectional view taken from the dummy chip 20 shown in FIG. 7 for comparison with the present embodiment. That is, FIG. 9 shows a step of connecting the second insulating substrate 50 and the first insulating substrate 5 to the surface of the first conductor 3 and the second conductor 4 opposite to the surface to which the first power semiconductor element 1a is connected. Is shown. As shown in FIG. 9, there is a concern that the stress of the connecting material 2b having a small connecting area increases and cracks occur. This is a wire of the second insulating substrate 50, the first insulating substrate 5, the first conductor 3 and the second conductor 4 in the process of connecting the second insulating substrate 50 and the first insulating substrate 5 at a high temperature and cooling to room temperature. This is because warpage deformation (heat warpage) occurs due to the difference in expansion coefficient. The stress of the connecting material 2b generated by this thermal warp is the length L3 in which only the first conductor 3 is connected to the second insulating substrate 50 and the length in which only the second conductor 4 is connected to the first insulating substrate 5. The longer L4, the larger it becomes.

However, in the present embodiment, the arrangement of the first power semiconductor element 1a is at the center of the arrangement of the first conductor 3 and the second conductor 4, and the arrangement of the dummy chips 20 is on both ends of the arrangement. When the dummy chip 20 is arranged as in the present embodiment, the dummy chip 20 is connected to the second conductor 4 via the connecting material 2a and is connected to the first conductor 3 via the connecting material 2b. Since the length in which only the conductor is connected to the insulating substrates 5 and 50 is reduced, thermal warpage can be suppressed. As a result, the stress generated in the connecting material 2b and the like is reduced. Therefore, peeling of the laminated portion can be prevented, and a highly reliable power semiconductor device 100 can be realized.

Further, when the power semiconductor device 100 is installed and used in a vehicle or the like, the power semiconductor device 100 repeatedly operates and stops, and as a result, repeatedly generates heat and cools. Since the power semiconductor device 100 repeatedly applies a large strain to the laminated portion of the insulating substrates 5 and 50 and the conductor, there is a concern that the laminated portion may be peeled off. The distortion of the laminated portion becomes large especially at the end portion A (see FIG. 9) of the second conductor 4. In the present embodiment, in order to reduce the strain of the connecting material 4a at the end A of the second conductor 4, the first power semiconductor element 1a that generates heat is arranged so as to be away from the end A of the second conductor 4. That is, the first power semiconductor element 1a is arranged close to the center of the second conductor 4. The temperature at which the first power semiconductor element 1a is repeatedly turned on and off is highest in the portion where the first power semiconductor element 1a is arranged, and becomes lower as the distance from the first power semiconductor element 1a increases. Therefore, the farther the first power semiconductor element 1a is from the end A of the second conductor 4, the lower the temperature of the end A of the second conductor 4, and the temperature change that repeatedly occurs due to the on / off of the first power semiconductor element 1a. It becomes smaller. Therefore, the stress generated repeatedly is reduced, and the fatigue life is improved. As a result, a highly reliable power semiconductor device 100 can be realized.

In the present embodiment, as shown in FIGS. 1 and 2, an example in which three first power semiconductor elements 1a and three second power semiconductor elements 1b are arranged has been described, but the first power semiconductor element 1a has been described. , The number of the second power semiconductor element 1b may be one or more.

[Second Embodiment]
The second embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a cross-sectional view of the power semiconductor device 100 according to the present embodiment. FIG. 11 is a top view showing parts and the like on the second conductor 4 according to the present embodiment. That is, FIG. 11 is a top view of the second conductor 4 taken out and viewed from the connection surface side with the second insulating substrate 50.

As shown in FIG. 10, in the present embodiment, three first power semiconductor elements 1a are arranged, and one dummy chip 20 is arranged between each first power semiconductor element 1a. In other words, the dummy chip 20 is arranged so as to be sandwiched between the first power semiconductor elements 1a. Other configurations are the same as those of the first embodiment, and the same reference numerals are given and the description thereof will be omitted.

As shown in FIG. 11, the first power semiconductor element 1a and the second power semiconductor element 1b are arranged in parallel, and the first power semiconductor element 1a and the dummy chip 20 are arranged along the arrangement direction, and the second power semiconductor is also provided. The elements 1b and the dummy chips 20 are arranged alternately. A wiring board 11 is arranged between the arranged first power semiconductor elements 1a and the second power semiconductor elements 1b. That is, the first power semiconductor element 1a and the second power semiconductor element 1b are arranged so as to sandwich the wiring board 11. The first power semiconductor element 1a and the second power semiconductor element 1b are electrically connected by the wiring pattern of the wiring substrate 11 and the wiring 12. For the wiring 12, for example, an aluminum wire or a copper wire can be used. On the other hand, the dummy chip 20 is not electrically connected to the wiring board 11.

When the first power semiconductor element 1a and the second power semiconductor element 1b are arranged as shown in FIGS. 10 and 11, the distance between the first power semiconductor element 1a and the second power semiconductor element 1b becomes long. Generally, when this embodiment is not applied, in the manufacturing process of the power semiconductor device 100, the first insulation is provided on the surface of the first conductor 3 and the second conductor 4 opposite to the surface to which the first power semiconductor element 1a is connected. In the process of connecting the substrate 5 and the second insulating substrate 50, thermal warpage occurs in the laminated structure of the insulating substrate and the conductor. Therefore, there is a concern that cracks may occur in the connecting material 2b. On the other hand, when the present embodiment is applied, a dummy chip 20 is provided between the first power semiconductor elements 1a, and the first conductor 3 and the second conductor 4 are connected on both sides of the dummy chip 20. , Thermal warpage can be suppressed, and cracks in the bonding material 2b can be prevented. As a result, a highly reliable power semiconductor device 100 can be realized.

Further, when the power semiconductor device 100 is installed and used in a vehicle or the like, the power semiconductor device 100 repeatedly operates and stops, and as a result, repeatedly generates heat and cools. When this embodiment is applied, when the first power semiconductor element 1a is driven to generate heat, the heat interference between adjacent power semiconductor elements is reduced, and the effect of reducing the thermal resistance can be obtained.

In the first to second embodiments described above, an example is shown in which the sealing resin includes the heat radiating member 8 and the heat radiating surface 8a is sealed. However, for example, as shown in FIG. 12, the insulating substrates 5 and 50 may be sealed. If the second conductor layers 5c and 50c of the insulating substrates 5 and 50 and the heat radiating member 8 are connected, the same effects as described in the first to second embodiments described above can be obtained. Since other configurations are the same as those in FIGS. 1 and 10, the same reference numerals are given to the same parts and the description thereof will be omitted.

Further, in the above-described first embodiment to the second embodiment, the case where the heat radiating member 8 is connected to the entire surfaces of the second conductor layers 5c and 50c of the insulating substrates 5 and 50 has been described. However, for example, as shown in FIG. 13, the structure may be such that the heat radiation fins 9 are directly provided on the second conductor layers 5c and 50c. Since other configurations are the same as those in FIGS. 1 and 10, the same reference numerals are given to the same parts and the description thereof will be omitted.

According to the embodiment described above, the following effects can be obtained.
(1) The power semiconductor device 100 is a semiconductor element (first power semiconductor element 1a, second power semiconductor element 1a, second power semiconductor element 1a) arranged side by side on the same surface of the first conductor 3 and the first conductor 3 and connected to the first conductor 3. 2a) and a plurality of dummy chips 20 are arranged so as to face the first conductor 3 with the semiconductor element (first power semiconductor element 1a, second power semiconductor element 2a) and the plurality of dummy chips 20 interposed therebetween. A first power semiconductor element 1a, a second power semiconductor element 2a), a second conductor 4 connected to a plurality of dummy chips 20, a semiconductor element (first power semiconductor element 1a, a second power semiconductor element 2a), and a plurality of A first insulating substrate 5 connected to a surface opposite to the surface of the first conductor 3 on which the dummy chip 20 is arranged, semiconductor elements (first power semiconductor element 1a, second power semiconductor element 2a), and a plurality of dummies. A second insulating substrate 50 connected to a surface opposite to the surface of the second conductor 4 on which the chip 20 is arranged is provided, and the dummy chip 20 is sandwiched between the first conductor 3 and the second conductor 4. The thickness is the same as that of the semiconductor element (first power semiconductor element 1a, second power semiconductor element 2a) and does not function as a semiconductor element. As a result, it is possible to provide a highly reliable power semiconductor device by preventing peeling of the laminated structure portion from the insulating substrate.

(Modification example)
The present invention can be implemented by modifying the first and second embodiments described above as follows.
(1) In the first and second embodiments, an example in which dummy chips are arranged on both ends of an array of semiconductor elements and an example in which dummy chips are arranged sandwiched between semiconductor elements are shown. However, dummy chips may be arranged in a mixed manner in an array of a plurality of semiconductor elements. For example, the dummy chips may be arranged on both ends of the array of semiconductor elements, and the dummy chips may also be arranged between the semiconductor elements arranged in the central portion. Further, the number of semiconductor elements sandwiched between the dummy chips may be a plurality.

The present invention is not limited to the above-described embodiment, and other embodiments considered within the scope of the technical idea of the present invention are also included within the scope of the present invention as long as the features of the present invention are not impaired. .. Further, the configuration may be a combination of the above-described embodiment and a plurality of modified examples.

1a ... 1st power semiconductor element 2a ... 2nd power semiconductor element 2a ... 2b ... Connecting material 3 ... 1st conductor 4 ... 2nd conductor 5 ... 1st insulating substrate 5a ... Insulating member 5b ... 1st conductor layer 5c ... 2nd Conductor layers 6, 7 ... Connecting material 8 ... Heat dissipation member 8a ... Heat dissipation surface 9 ... Heat dissipation fin 10 ... Sealing resin 11 ... Wiring board 12 ... Wiring 14 ... Terminal 20 ... Dummy chip 50 ... Second insulating board 50a ... Insulating member 50b ... 1st conductor layer 50c ... 2nd conductor layer

Claims (7)

With the first conductor
A semiconductor element and a plurality of dummy chips arranged side by side on the same surface of the first conductor and connected to the first conductor.
A second conductor arranged so as to face the first conductor with the semiconductor element and the plurality of dummy chips interposed therebetween and connected to the semiconductor element and the plurality of dummy chips.
A first insulating substrate connected to a surface opposite to the surface of the first conductor in which the semiconductor element and the plurality of dummy chips are arranged, and a first insulating substrate.
A second insulating substrate connected to a surface opposite to the surface of the second conductor on which the semiconductor element and the plurality of dummy chips are arranged is provided.
The dummy chip is a power semiconductor device in which the thickness sandwiched between the first conductor and the second conductor is the same as that of the semiconductor element and does not function as a semiconductor element. The power semiconductor device according to claim 1.
The first insulating substrate and the second insulating substrate are power semiconductor devices that are substrates containing a ceramic material. The power semiconductor device according to claim 1 or 2.
A power semiconductor device in which a plurality of the semiconductor elements and the plurality of dummy chips are mixedly arranged on the same surface of the first conductor. The power semiconductor device according to claim 3.
A power semiconductor device in which the semiconductor elements arranged side by side on the same surface of the first conductor are arranged in the central portion of the array, and the dummy chips are arranged on both ends of the array. The power semiconductor device according to claim 3.
The dummy chips arranged side by side on the same surface of the first conductor are power semiconductor devices sandwiched between the semiconductor elements. The power semiconductor device according to claim 1 or 2.
The dummy chip is a power semiconductor device that is the same member as the semiconductor element and is not electrically connected. The power semiconductor device according to claim 1 or 2.
The dummy chip is a semiconductor material or an insulating material, and is a power semiconductor device in which a metal film is formed on a surface in contact with the first conductor and the second conductor.

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