JP7193395B2 - power semiconductor equipment - Google Patents

power semiconductor equipment Download PDF

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JP7193395B2
JP7193395B2 JP2019060328A JP2019060328A JP7193395B2 JP 7193395 B2 JP7193395 B2 JP 7193395B2 JP 2019060328 A JP2019060328 A JP 2019060328A JP 2019060328 A JP2019060328 A JP 2019060328A JP 7193395 B2 JP7193395 B2 JP 7193395B2
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power semiconductor
semiconductor element
conductor
semiconductor device
insulating substrate
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JP2020161675A (en
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ひろみ 島津
晃 松下
徹 加藤
英一 井出
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Hitachi Astemo Ltd
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Hitachi Astemo Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、パワー半導体装置に関する。 The present invention relates to power semiconductor devices.

パワー半導体装置は、車両駆動用のモータを制御する電力変換装置に適用されている。また、車両駆動用のみならず、鉄道、エレベータ、産業機器、航空機等のモータを制御する電力変換装置にも適用されている。 A power semiconductor device is applied to a power conversion device that controls a motor for driving a vehicle. Moreover, it is applied not only to vehicles, but also to electric power converters for controlling motors of railways, elevators, industrial equipment, aircraft, and the like.

例えば、ハイブリッド自動車や電気自動車向けの電力変換装置では、充電時間を短縮する目的で動作電圧の高いパワー半導体装置が望まれている。動作電圧の高いパワー半導体装置では絶縁基板として絶縁耐圧の高いセラミック材料を使用する場合がある。一方で、小型化や、冷却性能の要求により両面直接冷却方式のパワー半導体装置が知られている。特許文献1には、電力変換装置の上下アームを構成する複数の半導体素子を両面から冷却するパワー半導体装置が開示されている。 For example, in power converters for hybrid vehicles and electric vehicles, a power semiconductor device with a high operating voltage is desired for the purpose of shortening the charging time. A power semiconductor device with a high operating voltage may use a ceramic material with a high withstand voltage as an insulating substrate. On the other hand, a double-sided direct cooling type power semiconductor device is known due to the demand for miniaturization and cooling performance. Patent Document 1 discloses a power semiconductor device that cools from both sides a plurality of semiconductor elements forming upper and lower arms of a power conversion device.

特開２０１２－２５７３６９号公報JP 2012-257369 A

パワー半導体装置の製造過程で絶縁基板との積層構造部分に熱反りが発生し、積層構造部分に剥離等が生じて信頼性が低下する虞がある。 During the manufacturing process of the power semiconductor device, thermal warp may occur in the laminated structure portion with the insulating substrate, and peeling or the like may occur in the laminated structure portion, which may reduce the reliability.

本発明によるパワー半導体装置は、互いに間隙領域を介して離間して並べて配置される第１半導体素子及び第２半導体素子と、前記第１半導体素子及び前記第２半導体素子に接続され、前記第１半導体素子及び前記第２半導体素子を挟んで配置される第１導体および第２導体と、前記第１半導体素子及び前記第２半導体素子に接続された前記第１導体の面とは反対の面に積層される第１絶縁基板と、を備え、前記第１導体は、前記間隙領域に対応する部分に貫通部が形成される。 A power semiconductor device according to the present invention includes a first semiconductor element and a second semiconductor element arranged side by side with a gap region therebetween; on the surface opposite to the surface of the first conductor connected to the first conductor and the second conductor sandwiching the semiconductor element and the second semiconductor element, and the first conductor connected to the first semiconductor element and the second semiconductor element and a laminated first insulating substrate, wherein the first conductor has a penetrating portion formed in a portion corresponding to the gap region.

本発明によれば、絶縁基板との積層構造部分の剥離等を防止して信頼性の高いパワー半導体装置を提供できる。 According to the present invention, it is possible to provide a highly reliable power semiconductor device by preventing detachment or the like of the laminated structure portion from the insulating substrate.

第１の実施形態に係るパワー半導体装置の断面図である。1 is a cross-sectional view of a power semiconductor device according to a first embodiment; FIG. 第１の実施形態に係るパワー半導体装置の展開斜視図である。1 is an exploded perspective view of a power semiconductor device according to a first embodiment; FIG. 第１の実施形態に係るパワー半導体装置の外観図である。1 is an external view of a power semiconductor device according to a first embodiment; FIG. 第１の実施形態に係る第１導体を示す上面図である。It is a top view showing the 1st conductor concerning a 1st embodiment. パワー半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of a power semiconductor device. パワー半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of a power semiconductor device. パワー半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of a power semiconductor device. パワー半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of a power semiconductor device. 第１の実施形態に係るパワー半導体装置の断面図であり、幅を表記した図である。FIG. 2 is a cross-sectional view of the power semiconductor device according to the first embodiment, showing the width; 第２の実施形態に係る第１導体を示す上面図である。It is a top view showing the 1st conductor concerning a 2nd embodiment. 第３の実施形態に係る第１導体を示す上面図である。It is a top view showing the 1st conductor concerning a 3rd embodiment. 他の実施形態に係るパワー半導体装置の断面図である。It is a cross-sectional view of a power semiconductor device according to another embodiment. 他の実施形態に係るパワー半導体装置の断面図である。It is a cross-sectional view of a power semiconductor device according to another embodiment.

［第１の実施形態]
本実施形態に係るパワー半導体装置１００について、図１～図９を参照して説明する。図１は、パワー半導体装置１００の断面図である。図２は、パワー半導体装置１００の展開斜視図である。図３は、パワー半導体装置１００の外観図である。なお、図１は、図２中のＡ－Ａ’における断面図を示している。 [First embodiment]
A power semiconductor device 100 according to this embodiment will be described with reference to FIGS. 1 to 9. FIG. FIG. 1 is a cross-sectional view of a power semiconductor device 100. FIG. FIG. 2 is an exploded perspective view of the power semiconductor device 100. FIG. FIG. 3 is an external view of the power semiconductor device 100. FIG. 1 shows a cross-sectional view taken along the line AA' in FIG.

図１に示すように、パワー半導体装置１００は、パワー半導体素子１ａおよびパワー半導体素子１ｂが並べて配置される。すなわち、パワー半導体素子１ａおよびパワー半導体素子１ｂは、互いに間隙領域３０を介して離間して並べて配置される。パワー半導体素子１ａおよびパワー半導体素子１ｂの各電極は、それぞれの電極面に対向して配置される第１導体３と第２導体４とによって挟まれる。第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂは、第１導体３及び第２導体４とそれぞれ接続材２ａ、２ｂによって接合される。第１導体３、第２導体４は、例えば、銅、銅合金、あるいはアルミニウム、アルミニウム合金などにより形成されている。接続材２ａ、２ｂは、はんだ材、焼結材などにより形成されている。 As shown in FIG. 1, in the power semiconductor device 100, a power semiconductor element 1a and a power semiconductor element 1b are arranged side by side. That is, the power semiconductor element 1a and the power semiconductor element 1b are arranged side by side with the gap region 30 interposed therebetween. Each electrode of the power semiconductor element 1a and the power semiconductor element 1b is sandwiched between a first conductor 3 and a second conductor 4 arranged to face the respective electrode surfaces. The first power semiconductor element 1a and the second power semiconductor element 1b are joined to the first conductor 3 and the second conductor 4 by connecting materials 2a and 2b, respectively. The first conductor 3 and the second conductor 4 are made of, for example, copper, copper alloy, aluminum, aluminum alloy, or the like. The connecting members 2a and 2b are made of solder material, sintered material, or the like.

第１導体３には、間隙領域３０に対応する部分に貫通部３ａが形成されている。また、第２導体４上の第１パワー半導体素子１ａと第２パワー半導体素子１ｂとの間、すなわち間隙領域３０には、配線基板１１が設けられている。配線基板１１は、例えばガラスエポキシ樹脂上に銅電極が設けられたパターン配線を有しており、第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂと配線１２で電気的に接続されている。配線１２は例えばアルミワイヤや銅ワイヤなどを用いることができる。 A through portion 3 a is formed in the first conductor 3 at a portion corresponding to the gap region 30 . A wiring board 11 is provided between the first power semiconductor element 1 a and the second power semiconductor element 1 b on the second conductor 4 , that is, in the gap region 30 . The wiring board 11 has a pattern wiring in which a copper electrode is provided on, for example, a glass epoxy resin, and is electrically connected to the first power semiconductor element 1a and the second power semiconductor element 1b by wiring 12 . For the wiring 12, for example, an aluminum wire, a copper wire, or the like can be used.

第１導体３には、第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂに接続された第１導体３の面とは反対の面に絶縁基板５０が積層される。絶縁基板５０は、絶縁部材５０ａ、第１導体層５０ｂ及び第２導体層５０ｃから構成され、絶縁部材５０ａの一面に第１導体層５０ｂが配置され、他面に第２導体層５０ｃが配置される。第１導体３の第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂと接続する面と反対の面は、接続材６を介して第１導体層５０ｂと接続される。第２導体層５０ｃは、接続材７を介して放熱部材８と接続される。放熱部材８の表面には放熱フィン９が形成される。 An insulating substrate 50 is laminated on the surface of the first conductor 3 opposite to the surface of the first conductor 3 connected to the first power semiconductor element 1a and the second power semiconductor element 1b. The insulating substrate 50 is composed of an insulating member 50a, a first conductor layer 50b and a second conductor layer 50c. The first conductor layer 50b is arranged on one surface of the insulating member 50a, and the second conductor layer 50c is arranged on the other surface. be. The surface of the first conductor 3 opposite to the surface connected to the first power semiconductor element 1a and the second power semiconductor element 1b is connected to the first conductor layer 50b via the connection material 6 . The second conductor layer 50c is connected to the heat dissipation member 8 via the connection material 7. As shown in FIG. A heat radiating fin 9 is formed on the surface of the heat radiating member 8 .

第２導体４には絶縁基板５が積層される。絶縁基板５は、絶縁部材５ａ、第１導体層５ｂ及び第２導体層５ｃから構成され、絶縁部材５ａの一面に第１導体層５ｂが配置され、他面に第２導体層５ｃが配置される。第２導体４の第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂと接続する面と反対の面は、接続材６を介して第１導体層５ｂと接続される。第２導体層５ｃは、接続材７を介して放熱部材８と接続される。放熱部材８の表面には放熱フィン９が形成される。 An insulating substrate 5 is laminated on the second conductor 4 . The insulating substrate 5 is composed of an insulating member 5a, a first conductor layer 5b, and a second conductor layer 5c. The first conductor layer 5b is arranged on one surface of the insulating member 5a, and the second conductor layer 5c is arranged on the other surface. be. A surface of the second conductor 4 opposite to the surface connected to the first power semiconductor element 1a and the second power semiconductor element 1b is connected to the first conductor layer 5b via the connection material 6 . The second conductor layer 5c is connected to the heat radiating member 8 via the connecting material 7. As shown in FIG. A heat radiating fin 9 is formed on the surface of the heat radiating member 8 .

絶縁部材５ａおよび絶縁部材５０ａは、第１パワー半導体素子１ａと第２パワー半導体素子１ｂから発生する熱を放熱部材８に熱伝導するものであり、熱伝導率が高く、かつ、絶縁耐圧が大きい材料であるセラミック材料を用いる。例えば、酸化アルミニウム（アルミナ）、窒化アルミニウム、窒化ケイ素等のセラミック材料を用いる。接続材６および接続材７は、はんだ材や焼結材などから形成されている。放熱部材８および放熱フィン９は、電気伝導性を有する部材、例えばＣｕ、Ｃｕ合金、Ｃｕ－Ｃ、Ｃｕ－ＣｕＯなどの複合材、あるいはＡｌ、Ａｌ合金、ＡｌＳｉＣ、Ａｌ－Ｃなどの複合材などから形成されている。 The insulating member 5a and the insulating member 50a conduct heat generated from the first power semiconductor element 1a and the second power semiconductor element 1b to the heat radiating member 8, and have high thermal conductivity and high withstand voltage. A ceramic material is used as the material. For example, ceramic materials such as aluminum oxide (alumina), aluminum nitride, and silicon nitride are used. The connection material 6 and the connection material 7 are made of a solder material, a sintered material, or the like. The heat dissipating member 8 and the heat dissipating fins 9 are electrically conductive members, for example, composite materials such as Cu, Cu alloys, Cu—C, and Cu—CuO, or composite materials such as Al, Al alloys, AlSiC, and Al—C. is formed from

図２に示すように、第１パワー半導体素子１ａと第２パワー半導体素子１ｂは、それぞれ１列に５個設けられ、さらに２列並列に設けられている。２列並列に設けられた第１パワー半導体素子１ａと第２パワー半導体素子１ｂに対応して、第１導体３、第２導体４、配線基板１１がそれぞれ２個設けられる。そして、図２中のＡ－Ａ’で示す第１パワー半導体素子１ａと第２パワー半導体素子１ｂとの間の間隙領域に対応して、第１導体３には貫通部３ａが設けられている。図２に示す端子１４は、絶縁基板５の第１導体層５ｂ、および絶縁基板５０の第１導体層５０ｂに接続される。 As shown in FIG. 2, five first power semiconductor elements 1a and five second power semiconductor elements 1b are provided in one row, and two rows are provided in parallel. Two first conductors 3, two second conductors 4, and two wiring substrates 11 are provided corresponding to the first power semiconductor elements 1a and the second power semiconductor elements 1b provided in two rows in parallel. A through portion 3a is provided in the first conductor 3 corresponding to a gap region between the first power semiconductor element 1a and the second power semiconductor element 1b indicated by AA' in FIG. . The terminal 14 shown in FIG. 2 is connected to the first conductor layer 5 b of the insulating substrate 5 and the first conductor layer 50 b of the insulating substrate 50 .

図３は、パワー半導体装置１００の外観図である。図３に示すように、放熱フィン９が形成されている放熱面８ａ及び端子１４以外は、封止樹脂１０で封止されている。 FIG. 3 is an external view of the power semiconductor device 100. FIG. As shown in FIG. 3, the parts other than the heat dissipation surface 8a on which the heat dissipation fins 9 are formed and the terminals 14 are sealed with a sealing resin 10. As shown in FIG.

図４は、第１導体３を示す上面図である。すなわち、第１導体３のみを取り出し、絶縁基板５０との接続面側からみた上面図である。図４に示すように、第１導体３には貫通部３ａが設けられている。貫通部３ａは、第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂの配列方向に沿って細長く設けられている。貫通部３ａの位置は、第１パワー半導体素子１ａと第２パワー半導体素子１ｂの間の間隙領域３０に対応して、すなわち第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂの間の配線基板１１に対向する位置に設けられている。このように第１導体３に貫通部３ａを設けることにより、絶縁基板５と第１導体３との接合面積を小さくすることができる。ここで、第１パワー半導体素子１ａと第２パワー半導体素子１ｂの配列方向の長さをＬ１０、貫通部３ａの長さをＬ１１とした場合、Ｌ１１≧Ｌ１０とすることが望ましい。 FIG. 4 is a top view showing the first conductor 3. FIG. That is, it is a top view of only the first conductor 3 taken out and viewed from the connecting surface side with the insulating substrate 50 . As shown in FIG. 4, the first conductor 3 is provided with a through portion 3a. The penetrating portion 3a is elongated along the arrangement direction of the first power semiconductor element 1a and the second power semiconductor element 1b. The position of the penetrating portion 3a corresponds to the gap region 30 between the first power semiconductor element 1a and the second power semiconductor element 1b, that is, the wiring substrate between the first power semiconductor element 1a and the second power semiconductor element 1b. 11. By providing the through portion 3a in the first conductor 3 in this way, the bonding area between the insulating substrate 5 and the first conductor 3 can be reduced. Here, when the length in the arrangement direction of the first power semiconductor element 1a and the second power semiconductor element 1b is L10, and the length of the penetrating portion 3a is L11, it is desirable that L11≧L10.

図５～図８は、パワー半導体装置１００の製造工程を示す図である。
まず、図５に示すように、第１パワー半導体素子１ａと第２パワー半導体素子１ｂが第２導体４に接続材２ａを介して接続される。第２導体４には配線基板１１が設けられており、この配線基板１１を挟むように第１パワー半導体素子１ａと第２パワー半導体素子１ｂが配置されている。第１パワー半導体素子１ａと第２パワー半導体素子１ｂはそれぞれ配線１２で配線基板１１上のパターン配線に接続される。第２導体４は、例えば、銅、銅合金、あるいはアルミニウム、アルミニウム合金などにより形成される。接続材２ａは、はんだ材または焼結材などにより形成されている。 5 to 8 are diagrams showing the manufacturing process of the power semiconductor device 100. FIG.
First, as shown in FIG. 5, the first power semiconductor element 1a and the second power semiconductor element 1b are connected to the second conductor 4 via the connecting material 2a. A wiring substrate 11 is provided on the second conductor 4, and a first power semiconductor element 1a and a second power semiconductor element 1b are arranged so as to sandwich the wiring substrate 11 therebetween. The first power semiconductor element 1a and the second power semiconductor element 1b are connected to pattern wiring on a wiring substrate 11 by wirings 12, respectively. The second conductor 4 is made of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. The connection material 2a is made of a solder material, a sintered material, or the like.

次に、図６に示すように、第１パワー半導体素子１ａと第２パワー半導体素子１ｂの第２導体４が接続されている面と反対の面に、接続材２ｂを介して第１導体３を接続する。第１導体３は、例えば、銅、銅合金、あるいはアルミニウム、アルミニウム合金などにより形成される。接続材２ｂは、はんだ材または焼結材などにより形成される。 Next, as shown in FIG. 6, the first conductor 3 is attached to the surface opposite to the surface to which the second conductor 4 of the first power semiconductor element 1a and the second power semiconductor element 1b is connected via the connection material 2b. to connect. The first conductor 3 is made of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. The connection material 2b is formed of a solder material, a sintered material, or the like.

次に、図７に示すように、第１導体３及び第２導体４が、接続材６を介してそれぞれ絶縁基板５０の第１導体層５０ｂ、絶縁基板５の第１導体層５ｂに接続される。絶縁基板５は、絶縁部材５ａの一面に第１導体層５ｂが配置され、他面に第２導体層５ｃが配置される。なお、絶縁基板５０と絶縁基板５を同時に、第１導体３および第２導体４に接続してもよい。同時に接続することで、対称性を保つことができ、組立時の反り変形を抑制することができる。 Next, as shown in FIG. 7, the first conductor 3 and the second conductor 4 are connected to the first conductor layer 50b of the insulating substrate 50 and the first conductor layer 5b of the insulating substrate 5 through the connecting material 6, respectively. be. In the insulating substrate 5, the first conductor layer 5b is arranged on one surface of the insulating member 5a, and the second conductor layer 5c is arranged on the other surface. Note that the insulating substrate 50 and the insulating substrate 5 may be connected to the first conductor 3 and the second conductor 4 at the same time. By connecting them at the same time, symmetry can be maintained, and warp deformation during assembly can be suppressed.

次に、図８に示すように、放熱部材８は、絶縁基板５０および絶縁基板５に接続材７を介して、接続される。このとき、両面の放熱部材８を同時に接続してもよい。同時に接続することにより、組立時の反り変形を抑制することができる。放熱部材８の表面には放熱フィン９が形成されている。そして最後に、放熱部材８の放熱フィン９が形成されている放熱面８ａ以外は、封止樹脂１０で封止される。 Next, as shown in FIG. 8, the heat radiating member 8 is connected to the insulating substrate 50 and the insulating substrate 5 via the connecting material 7 . At this time, the heat radiating members 8 on both sides may be connected at the same time. By connecting them at the same time, warp deformation during assembly can be suppressed. Radiation fins 9 are formed on the surface of the radiation member 8 . Finally, the heat dissipation surface 8a of the heat dissipation member 8 other than the heat dissipation surface 8a on which the heat dissipation fins 9 are formed is sealed with a sealing resin 10. As shown in FIG.

一般に、ＳｉＣチップを使用したパワー半導体素子を複数並列駆動させるパワー半導体装置の場合、パワー半導体素子のゲート配線を接続するための配線基板を設ける必要がある。具体的には、第１パワー半導体素子１ａと第２パワー半導体素子１ｂの間に配線基板１１が設けられる。これにより、第１パワー半導体素子１ａと第２パワー半導体素子１ｂの間の距離が長くなる。第１導体３に貫通部３ａを設けない場合、パワー半導体装置１００の製造工程において高温で接続し室温まで冷却する過程で、絶縁基板と導体との線膨張係数差により、絶縁基板と導体の積層構造の反り変形が大きくなる。これにより、接合面積の小さい第１パワー半導体素子１ａと第２導体界面の接続材２ｂや、第２パワー半導体素子１ｂと第２導体界面の接続材２ｂに応力が発生し、クラックが発生しやすくなる。特にパワー半導体素子の両面に第１導体３および第２導体４を接続し、さらにその外側に絶縁基板を接続する両面冷却構造のパワー半導体装置では、第１導体３および第２導体４と絶縁基板の積層構造の熱反りによって、積層構造部分に剥離が生じて信頼性が低下する虞がある。 Generally, in the case of a power semiconductor device that drives a plurality of power semiconductor elements using SiC chips in parallel, it is necessary to provide a wiring substrate for connecting the gate wiring of the power semiconductor elements. Specifically, a wiring board 11 is provided between the first power semiconductor element 1a and the second power semiconductor element 1b. This increases the distance between the first power semiconductor element 1a and the second power semiconductor element 1b. If the first conductor 3 is not provided with the penetrating portion 3a, in the process of connecting at a high temperature and cooling to room temperature in the manufacturing process of the power semiconductor device 100, the lamination of the insulating substrate and the conductor may occur due to the difference in linear expansion coefficient between the insulating substrate and the conductor. The warp deformation of the structure increases. As a result, stress is generated in the connection material 2b at the interface between the first power semiconductor element 1a and the second conductor, which has a small bonding area, and in the connection material 2b at the interface between the second power semiconductor element 1b and the second conductor, and cracks are likely to occur. Become. In particular, in a power semiconductor device having a double-sided cooling structure in which a first conductor 3 and a second conductor 4 are connected to both sides of a power semiconductor element, and an insulating substrate is connected to the outside thereof, the first conductor 3 and the second conductor 4 and the insulating substrate Due to the thermal warping of the laminated structure, there is a possibility that the laminated structure portion may be peeled off and the reliability may be lowered.

しかし、本実施形態のように、第１導体３の第１パワー半導体素子１ａと第２パワー半導体素子１ｂの間の配線基板１１に対向する位置に、貫通部３ａを設けることにより、第１パワー半導体素子１ａと第２パワー半導体素子１ｂの間において、絶縁基板である絶縁基板５０に第１導体３のみが接続される長さL１、L２（図９参照）を短くすることができる。これにより、絶縁基板５０に第１導体３のみが接続される領域が減少するため、熱反りを抑制することができ、第１パワー半導体素子１ａと第２導体界面の接続材２ｂや、第２パワー半導体素子１ｂと第２導体界面の接続材２ｂに発生する応力も低減される。したがって、第１導体３と絶縁基板５０との積層構造のクラックやはく離を防止することができ、信頼性の高いパワー半導体装置を提供できる。 However, as in the present embodiment, by providing the through portion 3a at a position facing the wiring board 11 between the first power semiconductor element 1a and the second power semiconductor element 1b of the first conductor 3, the first power Between the semiconductor element 1a and the second power semiconductor element 1b, lengths L1 and L2 (see FIG. 9) where only the first conductor 3 is connected to the insulating substrate 50, which is an insulating substrate, can be shortened. As a result, since the area where only the first conductor 3 is connected to the insulating substrate 50 is reduced, thermal warping can be suppressed, and the connecting material 2b at the interface between the first power semiconductor element 1a and the second conductor and the second The stress generated in the connecting material 2b at the interface between the power semiconductor element 1b and the second conductor is also reduced. Therefore, it is possible to prevent cracks and delamination of the laminated structure of the first conductor 3 and the insulating substrate 50, and to provide a highly reliable power semiconductor device.

さらに、パワー半導体装置１００を車両等に設置して使用した場合、パワー半導体装置１００は、動作、停止を繰り返し、その結果、発熱と冷却を繰り返す。パワー半導体装置１００は、絶縁基板と導体の積層部に繰り返し大きな歪み加わるため、積層部のはく離等が懸念される。本実施形態では、第１導体３の第１パワー半導体素子１ａと第２パワー半導体素子１ｂの間の配線基板１１に対向する位置に、貫通部３ａを設ける。これにより、繰り返し発生する応力が減少し、疲労寿命が向上する。これにより信頼性の高いパワー半導体装置１００が実現できる。 Furthermore, when the power semiconductor device 100 is installed in a vehicle or the like and used, the power semiconductor device 100 repeats operation and stoppage, resulting in repeated heat generation and cooling. In the power semiconductor device 100, since a large strain is repeatedly applied to the laminated portion of the insulating substrate and the conductor, peeling of the laminated portion is a concern. In this embodiment, a through portion 3a is provided at a position facing the wiring substrate 11 between the first power semiconductor element 1a and the second power semiconductor element 1b of the first conductor 3 . This reduces repetitive stress and improves fatigue life. Thereby, a highly reliable power semiconductor device 100 can be realized.

なお、放熱部材８の放熱フィン９の形状をピンフィンの例で説明したが、他の形状、例えばストレートフィンやコルゲートフィンであっても良い。また、本説明では、封止樹脂１０が放熱部材８を含み、放熱面８ａ以外が封止された例を示したが、絶縁基板５までが樹脂封止された構造であってもよい。この場合、絶縁基板５０の第２導体層５０ｃと放熱部材８とが接続され、絶縁基板５の第２導体層５ｃと放熱部材８とが接続されていれば、同様の効果が得られる。 Although the shape of the heat radiation fins 9 of the heat radiation member 8 has been described as a pin fin, other shapes such as straight fins and corrugated fins may be used. Also, in this description, an example is shown in which the sealing resin 10 includes the heat dissipation member 8 and the areas other than the heat dissipation surface 8a are sealed. In this case, if the second conductor layer 50c of the insulating substrate 50 and the heat radiating member 8 are connected, and the second conductor layer 5c of the insulating substrate 5 and the heat radiating member 8 are connected, the same effect can be obtained.

図９は、図１と同様のパワー半導体装置１００の断面図であるが、貫通部３ａ他の幅を表記した図である。
図９に示すように、貫通部の幅をＬ３、配線基板１１の幅をＬ４とした場合、Ｌ３≧Ｌ４とすることが望ましい。さらに第１パワー半導体素子１ａと第２パワー半導体素子１ｂ間の距離をＬ５とする。すなわち、第１パワー半導体素子１ａの配線基板１１側の側面を１ｃとし、第２パワー半導体素子１ｂの配線基板側の側面を１ｄとした場合に、側面１ｃと側面１ｄとの距離をＬ５とすると、Ｌ３≦Ｌ５とすることが望ましい。 FIG. 9 is a cross-sectional view of the power semiconductor device 100 similar to that of FIG. 1, but shows widths of the through portion 3a and others.
As shown in FIG. 9, when the width of the through portion is L3 and the width of the wiring substrate 11 is L4, it is desirable that L3≧L4. Furthermore, the distance between the first power semiconductor element 1a and the second power semiconductor element 1b is defined as L5. That is, when the side surface of the first power semiconductor element 1a on the wiring board 11 side is 1c and the side surface of the second power semiconductor element 1b on the wiring board side is 1d, the distance between the side surface 1c and the side surface 1d is L5. , L3≦L5.

本実施形態においては、図２に示したように第１パワー半導体素子１ａを５個、第２パワー半導体素子１ｂを５個備えた例を示したが、第１パワー半導体素子１ａ、第２パワー半導体素子１ｂがそれぞれ１つ以上あればよい。そして、貫通部３ａは少なくとも第１パワー半導体素子１ａと第２パワー半導体素子１ｂの間に設けられていればよい。これにより同様の効果が得られる。 In this embodiment, as shown in FIG. 2, an example is shown in which five first power semiconductor elements 1a and five second power semiconductor elements 1b are provided. It suffices if there are one or more semiconductor elements 1b. Penetrating portion 3a may be provided at least between first power semiconductor element 1a and second power semiconductor element 1b. Similar effects can be obtained in this way.

［第２の実施形態]
第２の実施形態について、図１０を参照して説明する。図１０は、第１導体３’を示す上面図である。なお、第１導体３’を含む図１０中のＡ－Ａ’におけるパワー半導体装置１００の断面図は図１と同様であり、第１導体３’を含むパワー半導体装置１００の展開斜視図は図２と同様である。 [Second embodiment]
A second embodiment will be described with reference to FIG. FIG. 10 is a top view showing the first conductor 3'. The cross-sectional view of the power semiconductor device 100 taken along line AA' in FIG. 10 including the first conductor 3' is the same as FIG. 2.

本実施形態における第１導体３’は、図１０に示すように、第１パワー半導体素子１ａと第２パワー半導体素子１ｂとの間には貫通部３ａ’が設けられている。貫通部３ａ’は、第１パワー半導体素子１ａおよび第２パワー半導体素子１ｂの配列方向に複数個設けられている。第１導体３’における第１パワー半導体素子側と第２パワー半導体素子側の間をつなぐ接続部３ｂ’が各第１パワー半導体素子１ａおよび各第２パワー半導体素子１ｂの間隔毎に設けられている。 As shown in FIG. 10, the first conductor 3' in this embodiment is provided with a penetrating portion 3a' between the first power semiconductor element 1a and the second power semiconductor element 1b. A plurality of through portions 3a' are provided in the arrangement direction of the first power semiconductor element 1a and the second power semiconductor element 1b. A connecting portion 3b' connecting between the first power semiconductor element side and the second power semiconductor element side of the first conductor 3' is provided at intervals between the first power semiconductor elements 1a and the second power semiconductor elements 1b. there is

ここで、第１パワー半導体素子１ａと第２パワー半導体素子１ｂの配列方向における長さをＬ１０’、貫通部３ａの長さをＬ１１’とした場合、Ｌ１１’≧Ｌ１０’とすることが望ましい。
本実施形態によれば、第１の実施形態で述べた効果を有する他に、第１導体３’における電気抵抗を低減できる効果が得られる。 Here, when the length in the arrangement direction of the first power semiconductor element 1a and the second power semiconductor element 1b is L10' and the length of the penetrating portion 3a is L11', it is desirable that L11'≧L10'.
According to this embodiment, in addition to the effects described in the first embodiment, the effect of reducing the electrical resistance of the first conductor 3' can be obtained.

［第３の実施形態]
第３の実施形態について、図１１を参照して説明する。図１１は、第１導体３’’を示す上面図である。なお、第１導体３’’を含む図１１中のＡ－Ａ’におけるパワー半導体装置１００の断面図は図１と同様であり、第１導体３’’を含むパワー半導体装置１００の展開斜視図は図２と同様である。 [Third embodiment]
A third embodiment will be described with reference to FIG. FIG. 11 is a top view showing the first conductor 3''. The cross-sectional view of the power semiconductor device 100 taken along line AA' in FIG. 11 including the first conductor 3'' is the same as FIG. is the same as in FIG.

本実施形態における第１導体３’’は、図１１に示すように、第１パワー半導体素子側と第２パワー半導体素子側の間をつなぐ接続部３ｂ’’が１か所にだけ設けられている。そして、接続部３ｂ’’を除く第１パワー半導体素子１ａと第２パワー半導体素子１ｂとの間は貫通部３ａ’’が形成されている。 As shown in FIG. 11, the first conductor 3'' in this embodiment is provided with a connecting portion 3b'' connecting between the first power semiconductor element side and the second power semiconductor element side only at one location. there is A through portion 3a'' is formed between the first power semiconductor element 1a and the second power semiconductor element 1b except for the connecting portion 3b''.

本実施形態によれば、第１の実施形態で述べた効果を有する他に、絶縁基板５０に接続される第１導体３’’の接合面積が小さくでき、かつ第１導体３’’の第１パワー半導体素子側の３eと第１導体３’’の第２パワー半導体素子側３fが自由に変形できる。このため、第１導体３’’と絶縁基板５０の積層構造の熱反りをさらに抑制することができ、第１導体３’’と絶縁基板５０との積層構造のクラックやはく離を防止することができ、信頼性の高いパワー半導体装置を提供できる。また、第１導体３’’を第1パワー半導体素子側の３eと第２パワー半導体素子側３fで完全に２分割するのではなく、少なくとも一か所で接続することにより、部品点数を少なくすることができ、さらに、第１導体３’’と絶縁基板５０を接続する際の高さ調整が容易になる。 According to this embodiment, in addition to the effects described in the first embodiment, the bonding area of the first conductor 3'' connected to the insulating substrate 50 can be reduced, and the first conductor 3'' The first power semiconductor element side 3e and the second power semiconductor element side 3f of the first conductor 3'' can be freely deformed. Therefore, thermal warping of the laminated structure of the first conductor 3'' and the insulating substrate 50 can be further suppressed, and cracking and separation of the laminated structure of the first conductor 3'' and the insulating substrate 50 can be prevented. A highly reliable power semiconductor device can be provided. Also, the number of parts can be reduced by connecting the first conductor 3'' at least at one point instead of completely dividing the first conductor 3'' into 3e on the side of the first power semiconductor element and 3f on the side of the second power semiconductor element. Further, the height adjustment when connecting the first conductor 3'' and the insulating substrate 50 is facilitated.

上述した第１の実施形態～第３の実施形態では、封止樹脂が放熱部材８を含み、放熱面８ａ以外が封止された例を示した。しかし、図１２に示すように、絶縁基板５、５０までが封止された構造であってもよい。絶縁基板５、５０の第２の導体層５ｃ、５０ｃと放熱部材８とが接続されていれば、同様の効果が得られる。その他の構成は、図１と同様であるので、同一箇所には同一の符号を付してその説明を省略する。 In the above-described first to third embodiments, examples were shown in which the sealing resin contained the heat radiating member 8 and the areas other than the heat radiating surface 8a were sealed. However, as shown in FIG. 12, the structure up to the insulating substrates 5 and 50 may be sealed. Similar effects can be obtained if the second conductor layers 5c, 50c of the insulating substrates 5, 50 and the heat dissipation member 8 are connected. Since other configurations are the same as those in FIG. 1, the same reference numerals are assigned to the same portions, and the description thereof will be omitted.

また、上述した第１の実施形態～第３の実施形態では、絶縁基板５、５０の第２の導体層５ｃ全面に放熱部材８を接続した場合について説明した。しかし、図１３に示すように、第２の導体層５ｃ、５０ｃに放熱フィン９を直接設けた構造であってもよい。その他の構成は、図１と同様であるので、同一箇所には同一の符号を付してその説明を省略する。 Further, in the first to third embodiments described above, the case where the heat dissipation member 8 is connected to the entire surface of the second conductor layer 5c of the insulating substrates 5 and 50 has been described. However, as shown in FIG. 13, a structure in which the heat radiation fins 9 are directly provided on the second conductor layers 5c and 50c may also be used. Since other configurations are the same as those in FIG. 1, the same reference numerals are assigned to the same portions, and the description thereof will be omitted.

以上説明した実施形態によれば、次の作用効果が得られる。
（１）パワー半導体装置１００は、互いに間隙領域３０を介して離間して並べて配置される第１パワー半導体素子１ａ及び第２パワー半導体素子１ｂと、第１パワー半導体素子１ａ及び第２パワー半導体素子１ｂに接続され、第１パワー半導体素子１ａ及び第２パワー半導体素子１ｂを挟んで配置される第１導体３および第２導体４と、第１パワー半導体素子１ａ及び第２パワー半導体素子１ｂに接続された第１導体３の面とは反対の面に積層される絶縁基板５と、を備え、第１導体３は、間隙領域３０に対応する部分に貫通部３ａが形成される。これにより、絶縁基板との積層構造部分の剥離等を防止して信頼性の高いパワー半導体装置を提供できる。 According to the embodiment described above, the following effects are obtained.
(1) The power semiconductor device 100 includes a first power semiconductor element 1a and a second power semiconductor element 1b arranged side by side with a gap region 30 interposed therebetween, and a first power semiconductor element 1a and a second power semiconductor element. A first conductor 3 and a second conductor 4 connected to the first power semiconductor element 1b and arranged to sandwich the first power semiconductor element 1a and the second power semiconductor element 1b, and connected to the first power semiconductor element 1a and the second power semiconductor element 1b. and an insulating substrate 5 laminated on a surface opposite to the surface of the first conductors 3 formed on the first conductor 3 . As a result, it is possible to provide a highly reliable power semiconductor device by preventing detachment or the like of the laminated structure portion from the insulating substrate.

本発明は、上記の実施形態に限定されるものではなく、本発明の特徴を損なわない限り、本発明の技術思想の範囲内で考えられるその他の形態についても、本発明の範囲内に含まれる。また、上述の実施形態を組み合わせた構成としてもよい。 The present invention is not limited to the above embodiments, and other forms conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention as long as the features of the present invention are not impaired. . Moreover, it is good also as a structure which combined the above-mentioned embodiment.

１ａ…第１パワー半導体素子
１ｂ…第２パワー半導体素子
２ａ、２ｂ…接続材
３、３’、３’’…第１導体
３ａ…貫通部
３ｂ…接続部
４…第２導体
５…絶縁基板
５ａ…絶縁部材
５ｂ…第１導体層
５ｃ…第２導体層
６、７…接続材
８…放熱部材
８ａ…放熱面
９…放熱フィン
１０…封止樹脂
１１…配線基板
１２…配線
１４…端子
３０…間隙領域
５０…絶縁基板
５０ａ…絶縁部材
５０ｂ…第１導体層
５０ｃ…第２導体層 1a... First power semiconductor element 1b... Second power semiconductor elements 2a, 2b... Connecting members 3, 3', 3''... First conductor 3a... Penetrating part 3b... Connecting part 4... Second conductor 5... Insulating substrate 5a Insulating member 5b First conductor layer 5c Second conductor layer 6, 7 Connection material 8 Heat dissipation member 8a Heat dissipation surface 9 Heat dissipation fin 10 Sealing resin 11 Wiring board 12 Wiring 14 Terminal 30 Gap region 50... Insulating substrate 50a... Insulating member 50b... First conductor layer 50c... Second conductor layer

Claims (8)

互いに間隙領域を介して離間して並べて配置される第１半導体素子及び第２半導体素子と、
前記第１半導体素子及び前記第２半導体素子に接続され、前記第１半導体素子及び前記第２半導体素子を挟んで配置される第１導体および第２導体と、
前記第１半導体素子及び前記第２半導体素子に接続された前記第１導体の面とは反対の面に積層される第１絶縁基板と、を備え、
前記第１導体は、前記間隙領域に対応する部分に貫通部が形成されるパワー半導体装置。 a first semiconductor element and a second semiconductor element arranged side by side with a gap interposed therebetween;
a first conductor and a second conductor connected to the first semiconductor element and the second semiconductor element and arranged to sandwich the first semiconductor element and the second semiconductor element;
a first insulating substrate laminated on a surface opposite to the surface of the first conductor connected to the first semiconductor element and the second semiconductor element;
A power semiconductor device in which the first conductor has a through portion formed in a portion corresponding to the gap region. 請求項１に記載のパワー半導体装置において、
前記第１半導体素子及び第２半導体素子に接続された前記第２導体の面とは反対の面に積層される第２絶縁基板を備えるパワー半導体装置。 In the power semiconductor device according to claim 1,
A power semiconductor device comprising a second insulating substrate laminated on a surface opposite to a surface of the second conductor connected to the first semiconductor element and the second semiconductor element. 請求項２に記載のパワー半導体装置において、
前記第１絶縁基板および前記第２絶縁基板はセラミック材料を含む基板であるパワー半導体装置。 In the power semiconductor device according to claim 2,
The power semiconductor device, wherein the first insulating substrate and the second insulating substrate are substrates containing a ceramic material. 請求項１に記載のパワー半導体装置において、
前記第２導体上であって、前記間隙領域に、前記第１半導体素子および第２半導体素子と電気的に接続される配線基板が設けられ、前記第１導体に形成される前記貫通部は前記配線基板と対向する位置に設けられるパワー半導体装置。 In the power semiconductor device according to claim 1,
A wiring board electrically connected to the first semiconductor element and the second semiconductor element is provided on the second conductor and in the gap region, and the penetrating portion formed in the first conductor is the A power semiconductor device provided at a position facing a wiring board. 請求項４に記載のパワー半導体装置において、
前記貫通部の幅をＬ３、前記配線基板の幅をＬ４とした場合、Ｌ３≧Ｌ４であるパワー半導体装置。 In the power semiconductor device according to claim 4,
The power semiconductor device satisfies L3≧L4, where L3 is the width of the through portion and L4 is the width of the wiring board. 請求項１から請求項４までのいずれか一項に記載のパワー半導体装置において、
前記第１半導体素子と前記第２半導体素子の間の前記貫通部の幅をＬ３、前記第１半導体素子と前記第２半導体素子の間の距離をＬ５とした場合、Ｌ３≦Ｌ５であるパワー半導体装置。 In the power semiconductor device according to any one of claims 1 to 4,
A power semiconductor satisfying L3≦L5, where L3 is the width of the through portion between the first semiconductor element and the second semiconductor element, and L5 is the distance between the first semiconductor element and the second semiconductor element. Device. 請求項１から請求項４までのいずれか一項に記載のパワー半導体装置において、
前記第１半導体素子もしくは第２半導体素子の配列方向の長さをＬ１０、前記配列方向における前記貫通部の長さをＬ１１とした場合、Ｌ１１≧Ｌ１０であるパワー半導体装置。 In the power semiconductor device according to any one of claims 1 to 4,
A power semiconductor device wherein L11≧L10, where L10 is the length in the arrangement direction of the first semiconductor element or the second semiconductor element, and L11 is the length of the through portion in the arrangement direction. 請求項１から請求項４までのいずれか一項に記載のパワー半導体装置において、
前記貫通部に封止樹脂が充填されているパワー半導体装置。 In the power semiconductor device according to any one of claims 1 to 4,
A power semiconductor device in which the through portion is filled with a sealing resin.
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Publication number Priority date Publication date Assignee Title
WO2016021341A1 (en) 2014-08-07 2016-02-11 日立オートモティブシステムズ株式会社 Power module
JP2017073483A (en) 2015-10-08 2017-04-13 三菱マテリアル株式会社 Heat sink-attached power module substrate and power module

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016021341A1 (en) 2014-08-07 2016-02-11 日立オートモティブシステムズ株式会社 Power module
JP2017073483A (en) 2015-10-08 2017-04-13 三菱マテリアル株式会社 Heat sink-attached power module substrate and power module

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