JP2020129600A - Semiconductor device and power conversion device - Google Patents

Abstract

To relax stress at a junction of a semiconductor device without increasing the manufacturing cost.SOLUTION: A semiconductor device 1 according to the present invention includes: a semiconductor element 3 having an insulating bonding surface; a first metal plate 5, one surface of which is metal-bonded to the bonding surface of the semiconductor element 3; and a second metal plate 7 metal-bonded to the other surface of the first metal plate 5. The linear expansion coefficient of the first metal plate 5 is larger than the linear expansion coefficient of the semiconductor element 3 and smaller than the linear expansion coefficient of the second metal plate 7, and the thermal conductivity of the first metal plate 5 is larger than the thermal conductivity of the second metal plate 7.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device in which a semiconductor element is bonded to a metal plate and a power conversion device including the semiconductor device.

While the output of the semiconductor device and the power conversion device is increasing, the heat dissipation performance is required to be improved as the device is downsized. To solve such a problem, a power module in which a cooler is bonded to a semiconductor via an insulating substrate has been conventionally proposed, but stress is generated due to a difference in linear expansion coefficient between the semiconductor element and the cooler. As a result, cracks occurred in the joint member between the semiconductor element and the cooler, and sufficient heat dissipation performance could not be maintained during the required life period.

Therefore, in the conventional semiconductor device disclosed in Patent Document 1, when a thin semiconductor element having a thickness of 0.05 mm or more and 0.1 mm or less is used, it is caused by a difference in linear expansion coefficient between the semiconductor element and the cooler. The stress generated is absorbed in the semiconductor element.

International publication WO2017/183222

However, in the above-described conventional semiconductor device, since the semiconductor element is made thin to absorb the stress, there is a problem that the manufacturing cost increases.

Therefore, the present invention has been proposed in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a power conversion device capable of relieving stress in a joint portion of a semiconductor element without increasing manufacturing cost. To do.

In order to solve the above-described problems, a semiconductor device according to one aspect of the present invention has a semiconductor element metal-bonded to one surface of a first metal plate and a second metal plate to the other surface of the first metal plate. The metal plates are metal-bonded. The linear expansion coefficient of the first metal plate is larger than the linear expansion coefficient of the semiconductor element and smaller than the linear expansion coefficient of the second metal plate, and the thermal conductivity of the first metal plate is equal to that of the second metal plate. It is characterized by being larger than the conductivity.

According to the present invention, it is possible to relieve the stress in the joint portion of the semiconductor element without increasing the manufacturing cost.

FIG. 1 is a sectional view showing the structure of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a perspective view showing the structure of a semiconductor element that constitutes the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. FIG. 5 is a plan view showing the structure of the semiconductor device according to the second embodiment of the present invention. FIG. 6 is a sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention. FIG. 7 is a plan view showing the structure of the semiconductor device according to the third embodiment of the present invention. FIG. 8 is a sectional view showing the structure of the semiconductor device according to the fourth exemplary embodiment of the present invention. FIG. 9 is a plan view showing the structure of the semiconductor device according to the fourth embodiment of the present invention. FIG. 10: is sectional drawing which shows the structure of the power converter device which concerns on 5th Embodiment of this invention. FIG. 11: is a top view which shows the structure of the power converter device which concerns on 5th Embodiment of this invention.

[First Embodiment]
Hereinafter, a first embodiment to which the present invention is applied will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to this embodiment, and FIG. 2 is a plan view. As shown in FIGS. 1 and 2, the semiconductor device 1 according to the present embodiment includes a semiconductor element 3, a first metal plate 5, and a second metal plate 7.

The semiconductor element 3 is made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or the like, and the bonding surface bonded to the first metal plate 5 has an insulating property. For example, the semiconductor element 3 is composed of a metal oxide semiconductor field effect transistor (MOSFET) as shown in FIG. The semiconductor device 3 shown in FIG. 3 includes a well region 32, a source region 33, a drift region 34, a drain region 35, a gate insulating film 36, a gate electrode 37, a source electrode 38, and a substrate 31 on a substrate 31. A drain electrode 39 is formed.

Here, the substrate 31 is a flat plate made of an insulator, and silicon carbide (SiC) can be used as a material, for example. The substrate 31 has an insulating property because the sheet resistance is increased by making the impurity concentration extremely low. Insulation may be provided by interposing an insulator in the substrate 31.

Therefore, by providing the structure as shown in FIG. 3, in the semiconductor element 3, the bonding surface to be bonded to the first metal plate 5 has the insulating property without providing the insulating layer.

One surface of the first metal plate 5 is metal-bonded to the bonding surface of the semiconductor element 3, and the second metal plate 7 is metal-bonded to the other surface. In the present embodiment, the semiconductor element 3 is bonded to the upper surface of the first metal plate 5, and the second metal plate 7 is bonded to the lower surface. The joining method between the semiconductor element 3 and the first metal plate 5 is metal joining such as pressure welding or soldering, and the joining method between the first metal plate 5 and the second metal sheet 7 is also pressure joining. Metal joining such as soldering and soldering.

Further, as shown in FIG. 2, the area of the plane of the first metal plate 5 is larger than the area of the plane of the semiconductor element 3. The first metal plate 5 is formed of copper (Cu), but may be formed of gold (Au) or silver (Ag) instead of copper. Further, the thickness of the first metal plate 5 is preferably 1 mm or more.

The second metal plate 7 is metal-bonded to the other surface of the first metal plate 5, and functions as a cooler for releasing the heat of the semiconductor element 3 to cool it. As shown in FIGS. 1 and 2, the area of the plane of the second metal plate 7 is the same as that of the first metal plate 5, and is larger than the area of the plane of the semiconductor element 3. The second metal plate 7 is made of aluminum (Al).

In the semiconductor device 1 having the structure shown in FIGS. 1 and 2, in the present embodiment, the linear expansion coefficient of the first metal plate 5 is larger than the linear expansion coefficient of the semiconductor element 3, and the linear expansion coefficient of the second metal plate 7 is larger. It is smaller than the coefficient. Thus, by sandwiching the first metal plate 5 having a linear expansion coefficient between the semiconductor element 3 and the second metal plate 7 between the semiconductor element 3 and the second metal plate 7, the semiconductor It is possible to relieve the stress at the joint where the element 3 is joined. Therefore, in the present embodiment, it is not necessary to thin the semiconductor element in order to absorb the stress, so that the stress at the joint portion of the semiconductor element can be relaxed without increasing the manufacturing cost.

Further, in the conventional semiconductor device, since the semiconductor element is made thin in order to absorb the stress, there is a problem that the semiconductor element and the insulating substrate are close to each other and the thermal resistance is deteriorated. However, in the semiconductor device 1 according to this embodiment, it is not necessary to make the semiconductor element 3 thin, so that the thermal resistance can be reduced.

Further, in the semiconductor device 1 according to the present embodiment, the thermal conductivity of the first metal plate 5 is made higher than that of the second metal plate 7. As described above, by sandwiching the first metal plate 5 having a higher thermal conductivity than the second metal plate 7 between the semiconductor device 3 and the second metal plate 7, heat from the semiconductor device 3 is absorbed. The heat radiation performance for radiating heat can be improved.

In the semiconductor device 1 according to the present embodiment, the linear expansion coefficient of the first metal plate 5 is larger than the linear expansion coefficient of the semiconductor element 3 and smaller than the linear expansion coefficient of the second metal plate 7, Moreover, the thermal conductivity of the first metal plate 5 is set to be higher than that of the second metal plate 7. Therefore, the effects described above can be realized at the same time.

Further, in the semiconductor device 1 according to this embodiment, the bonding surface of the semiconductor element 3 bonded to the first metal plate 5 has an insulating property. Thereby, the semiconductor element 3 is bonded to the first metal plate 5 without providing an insulating layer or an insulating substrate, so that the thermal resistance can be further reduced.

Further, in the semiconductor device 1 according to this embodiment, the first metal plate 5 is made of copper and the second metal plate 7 is made of aluminum. Thereby, the linear expansion coefficient of the first metal plate 5 can be made larger than the linear expansion coefficient of the semiconductor element 3 and smaller than the linear expansion coefficient of the second metal plate 7. In addition, since the first metal plate 5 is made of copper and the second metal plate 7 is made of aluminum, the thermal conductivity of the first metal plate 5 is made equal to that of the second metal plate 7. Can be greater than.

Therefore, in the semiconductor device 1 according to the present embodiment, it is possible to simultaneously satisfy the above-mentioned conditions of the linear expansion coefficient and the conditions of the thermal conductivity. That is, by sandwiching the copper metal plate between the semiconductor element and the aluminum cooler, it is possible to simultaneously satisfy the conditions of the coefficient of linear expansion and the conditions of the thermal conductivity described above. As a result, the stress in the joint portion can be relaxed without increasing the manufacturing cost, and the heat radiation performance for radiating the heat from the semiconductor element 3 can be improved and the thermal resistance can be reduced. That is, it is possible to realize a semiconductor device that can exert all of these effects at the same time.

Further, in the semiconductor device 1 according to the present embodiment, the thickness of the first metal plate 5 is 1 mm or more. As the semiconductor device 1 becomes smaller, the area of the semiconductor element 3 becomes smaller. However, if the area of the semiconductor element 3 becomes smaller, the thickness of the first metal plate 5 needs to be increased. At this time, if the thickness of the first metal plate 5 is set to 1 mm or more, even if there is a difference between the coefficient of linear expansion of the semiconductor element 3 and the coefficient of linear expansion of the second metal plate 7, the influence thereof. Can be reduced by the first metal plate 5. Therefore, by setting the thickness of the first metal plate 5 to 1 mm or more, the stress at the joint portion of the semiconductor element 3 can be relaxed.

[Second Embodiment]
Hereinafter, a second embodiment to which the present invention is applied will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

FIG. 4 is a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIG. 5 is a plan view. As shown in FIGS. 4 and 5, the semiconductor device 1 according to the present embodiment differs from the first embodiment in that a water cooling structure is provided on the second metal plate 7. In FIG. 4, a water channel 72 is provided in the second metal plate 7 as a water cooling/cooling structure.

The water channel 72 shown in FIG. 4 may be a water channel having a multi-hole tube or a corrugated fin structure, and may have a comb leaf structure or a pin fin structure in addition to this. Further, an air cooling structure may be used instead of the water cooling structure.

As described above, in the semiconductor device 1 according to the present embodiment, the second metal plate 7 has the water-cooled cooling structure, so that the heat radiation performance for radiating the heat from the semiconductor element 3 can be further improved. Moreover, since the volume of the metal portion of the second metal plate 7 is reduced due to the provision of the water channel, the stress at the joint portion of the semiconductor element 3 can be further reduced.

[Third Embodiment]
Hereinafter, a third embodiment to which the present invention is applied will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

FIG. 6 is a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIG. 7 is a plan view. As shown in FIGS. 6 and 7, the semiconductor device 1 according to the present embodiment differs from the second embodiment in that a plurality of semiconductor elements 3 are provided. In FIGS. 6 and 7, two semiconductor elements 3A and 3B are arranged adjacent to each other on the upper surface of the first metal plate 5. However, the number of semiconductor elements 3 need not be two, and may be three or more. Although FIGS. 6 and 7 exemplify a case where the semiconductor device 1 of the second embodiment shown in FIGS. 4 and 5 is provided with a plurality of semiconductor elements 3A and 3B, the first embodiment shown in FIGS. The semiconductor device 1 of the embodiment may be provided with a plurality of semiconductor elements.

As described above, since the semiconductor device 1 according to the present embodiment includes the plurality of semiconductor elements 3, it is possible to further reduce the stress in the joint portion that joins the semiconductor elements 3.

[Fourth Embodiment]
Hereinafter, a fourth embodiment to which the present invention is applied will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

FIG. 8 is a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIG. 9 is a plan view. As shown in FIGS. 8 and 9, the semiconductor device 1 according to the present embodiment differs from the third embodiment in that the insulating substrate 9 is metal-bonded to the upper surface of the first metal plate 5. The insulating substrate 9 is arranged adjacent to the plurality of semiconductor elements 3A and 3B, and occupies a larger area on the upper surface of the first metal plate 5 than the semiconductor elements 3A and 3B. However, the number of the insulating substrate 9 need not be one and may be two or more. 8 and 9 illustrate the case where the insulating substrate 9 is provided in the semiconductor device 1 of the third embodiment shown in FIGS. 6 and 7, but the semiconductor device 1 of the first and second embodiments is insulated. The substrate 9 may be provided.

The insulating substrate 9 is a substrate made of an insulator, and may be made of the same material as the semiconductor element 3. For example, the insulating substrate 9 is a flat plate made of an insulator, like the substrate 31 of the semiconductor element 3 shown in FIG. 3, and uses, for example, silicon carbide (SiC) as a material.

As described above, in the semiconductor device 1 according to the present embodiment, the insulating substrate 9 is metal-bonded to the upper surface of the first metal plate 5, so that the stress at the bonding portions of the semiconductor elements 3A and 3B can be further relieved.

[Fifth Embodiment]
Hereinafter, a fifth embodiment to which the present invention is applied will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

FIG. 10 is a cross-sectional view showing the structure of the power conversion device according to this embodiment, and FIG. 11 is a plan view. The power conversion device 100 according to the present embodiment is a device such as an inverter, and includes two semiconductor devices 1A and 1B as shown in FIGS. 10 and 11, and shares the second metal plate 7. The semiconductor devices 1A and 1B are arranged side by side in the long side direction of the second metal plate 7. However, the number of semiconductor devices 1A and 1B does not have to be two, and may be three or more. 10 and 11 exemplify a case where a plurality of semiconductor devices 1 of the fourth embodiment shown in FIGS. 8 and 9 are provided, but a plurality of semiconductor devices of the first to third embodiments may be provided. Good.

The power conversion device 100 has a structure in which a plurality of first metal plates 5A and 5B are metal-bonded to the upper surface of one second metal plate 7. Further, the plurality of semiconductor elements 3C and 3D are metal-bonded to the upper surface of the first metal plate 5A, and the plurality of semiconductor elements 3E and 3F are metal-bonded to the upper surface of the first metal plate 5B. Therefore, the power conversion device 100 includes a plurality of semiconductor devices 1A and 1B sharing the second metal plate 7.

As described above, since the power conversion device 100 according to the present embodiment includes the semiconductor devices of the first to fourth embodiments, it is possible to relieve the stress in the joint portion of the semiconductor element without increasing the manufacturing cost and to dissipate the heat. The performance can be improved and the thermal resistance can be reduced.

In particular, the power conversion device 100 according to the present embodiment has a structure in which the plurality of first metal plates 5A and 5B are metal-bonded to the upper surface of one second metal plate 7, so that the second metal The plate 7 can be shared, and the number of parts can be reduced.

The above-mentioned embodiment is an example of the present invention. For this reason, the present invention is not limited to the above-described embodiment, and even in a form other than this embodiment, as long as it does not deviate from the technical idea of the present invention, depending on the design etc. Of course, various modifications are possible.

1 Semiconductor Device 3, 3A, 3B, 3C, 3D, 3E, 3F Semiconductor Element 5, 5A, 5B First Metal Plate 7 Second Metal Plate 9, 9A, 9B Insulating Substrate 31 Substrate 32 Well Region 33 Source Region 34 Drift region 35 Drain region 36 Gate insulating film 37 Gate electrode 38 Source electrode 39 Drain electrode 72 Water channel 100 Power converter

Claims (7)

A semiconductor element having an insulating joint surface;
A first metal plate having one surface metal-bonded to the bonding surface of the semiconductor element;
A second metal plate metal-bonded to the other surface of the first metal plate,
The linear expansion coefficient of the first metal plate is larger than the linear expansion coefficient of the semiconductor element and smaller than the linear expansion coefficient of the second metal plate,
The semiconductor device according to claim 1, wherein a thermal conductivity of the first metal plate is higher than a thermal conductivity of the second metal plate. The semiconductor device according to claim 1, wherein the second metal plate has a water cooling structure. The semiconductor device according to claim 1, further comprising a plurality of the semiconductor elements. The semiconductor device according to claim 1, wherein an insulating substrate is metal-bonded to one surface of the first metal plate. The semiconductor device according to claim 1, wherein the first metal plate is formed of copper, and the second metal plate is formed of aluminum. The thickness of the said 1st metal plate is 1 mm or more, The semiconductor device of any one of Claims 1-5 characterized by the above-mentioned. A power conversion device, wherein a plurality of the first metal plates are metal-bonded to one of the second metal plates of the semiconductor device according to any one of claims 1 to 6.

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