JP2008244394A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability and high cooling performance. <P>SOLUTION: The semiconductor device A is provided with: semiconductor chips 11a, 11b each having a semiconductor element formed thereon; a heat dissipation substrate 21; metal plates 23a, 23b and 23c; a plurality of fin-like members 22 separated from each other; a sealing member 15 for sealing the semiconductor chips 11a (11b); a rear surface side metallized layer 24 interposed between the heat dissipating plate 21 and the fin-like members 22; and a main surface side metallized layer 26 interposed between the heat dissipating substrate 21 and the metal plates 23a, 23b and 23c. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device on which a semiconductor chip is mounted, and more particularly to a heat dissipation measure.

  FIG. 7 is a cross-sectional view showing the structure of a semiconductor device on which a conventional IGBT chip is mounted. As shown in the figure, on the main surface side of the heat radiating substrate 101 made of ceramic or the like, an Al plate 104 fixed to the heat radiating substrate 101 with a solder layer 102 and an Al brazing on the main surface of the Al plate 104 A fixed AlN plate 106, an Al wiring 108 fixed to the main surface of the AlN plate 106 with Al solder, and a semiconductor chip 120 fixed on the Al wiring 108 with solder 109 are provided. Further, a heat sink 113 with fins is attached to the rear surface side of the heat dissipation substrate 101 with the grease 112 interposed therebetween. In general, the heat dissipation substrate 101 is made of Cu—Mo or the like, and the heat sink 113 is made of an Al alloy.

  The grease 112 interposed between the heat dissipation substrate 101 and the heat sink 113 includes a heat sink 113 made of an Al alloy having a thermal expansion coefficient α of about 23 (ppm / K), and a thermal expansion coefficient α of about 9 (ppm / K). This is to relieve stress caused by the difference in thermal expansion coefficient between the heat dissipation substrates 101 made of Cu-Mo.

  As described above, for example, Japanese Patent Application Laid-Open No. 2003-27080 discloses a thermally conductive grease between a finned heat dissipator and an electronic component that is a heat generator. A semiconductor device in which is interposed is disclosed.

Japanese Patent Laid-Open No. 2003-27080

  In the structure disclosed in FIG. 7 and the above publication, although the thermal stress due to the difference in thermal expansion coefficient can be relieved by the grease, the grease has a lower thermal conductivity than that of metal or ceramic, There is a difficulty in deteriorating the reliability of the part. In other words, since the grease displaces the members on both sides, the members on both sides are not fixed by the grease. In addition, voids are likely to occur in the grease. If voids are generated, the expected effect cannot be obtained even if the thermal conductivity of the grease is improved as described in the above publication.

  An object of the present invention is to provide a semiconductor device having a high heat dissipation function while maintaining the reliability of a connection portion.

  The semiconductor device of the present invention includes a mounting member group for mounting a semiconductor chip. The mounting member group includes a heat dissipation substrate made of an inorganic insulating material, a metal plate mounted on the main surface side thereof, and And a plurality of fin-like members fixed to the back surface side apart from each other.

  Accordingly, since the plurality of fin-like members are separated from each other on the back surface side of the heat dissipation board, the difference in thermal expansion coefficient between the heat dissipation board and the metal plate and the difference in thermal expansion coefficient between the heat dissipation board and the fin-like member are large. However, the reliability of the connection portion between the fin-like member and the heat dissipation substrate resulting from that is maintained. That is, even if thermal stress is generated between the fin-like member and the heat dissipation board, the thermal stress is dispersed (absorbed) in the open part of the heat dissipation board, so that the possibility of the connection part being peeled off is avoided. is there. Therefore, it is not necessary to interpose the grease between the fin-like member and the heat dissipation substrate, and the fin-like member can be fixed to the heat dissipation substrate by brazing, bonding, fitting, or the like with the metallized layer. Therefore, the reliability of the connection part between the fin-like member which is a heat sink and the heat dissipation substrate is improved.

  By forming the main surface side metallization layer on the main surface of the heat dissipation board and brazing the metal plate to the main surface side metallization layer, the connection state between the heat dissipation substrate and the metal plate becomes stronger and more reliable Improves. Brazing includes low-temperature brazing such as solder and high-temperature brazing such as brass brazing, and any of them may be used.

  By forming a backside metallization layer on the backside of the heat dissipation board and brazing the fin-like member to the backside metallization layer, the connection state between the heat dissipation board and the fin-like member becomes stronger and more reliable. Will improve.

  Since the metal plate is made of a metal material having a thermal expansion coefficient greater than 0 (ppm / K) and not more than 10 (ppm / K), the difference in thermal expansion coefficient from the semiconductor chip is reduced. The stress can be made as small as possible.

  When the metal plate is made of Cu—Mo or Cu—W, the amount of heat transferred from the semiconductor chip side to the heat dissipation substrate is increased, and the heat dissipation function is improved.

    Since the heat dissipation substrate is made of an inorganic insulating material having a thermal expansion coefficient larger than 0 (ppm / K) and 10 (ppm / K) or less, the difference in thermal expansion coefficient from the metal plate is reduced. The thermal stress can be made as small as possible.

The heat dissipation substrate is made of a material selected from AlN, silicon nitride, SiC, and a composite material containing at least one of them as a main component, so that the heat expansion coefficient of the heat dissipation substrate is the coefficient of thermal expansion of the semiconductor chip. Therefore, the thermal stress can be made as small as possible. Silicon nitride includes not only stoichiometric Si ₃ N ₄ but also non-stoichiometric ones deviating from stoichiometric composition.

  When the thermal expansion coefficient difference between the heat dissipation substrate and the metal plate is 7 (ppm / K) or less, the thermal stress due to the thermal expansion coefficient difference can be made as small as possible.

  Since the fin-like member is made of a metal material having a thermal expansion coefficient greater than 0 (ppm / K) and not more than 10 (ppm / K), the difference in thermal expansion coefficient between the fin-like member and the heat dissipation substrate can be reduced. The resulting thermal stress can be made as small as possible.

  Since the fin-like member is made of Cu-Mo or Cu-W, the heat transfer amount from the fin-like member serving as a heat sink to the heat medium is maintained while minimizing the thermal stress and maintaining the reliability of the joining. And the heat dissipation function is improved. Since the fin-like member is made of Cu or Cu alloy having a high thermal conductivity, the heat dissipation function is particularly improved.

  Because the semiconductor element is a power device using a wide band gap semiconductor, even when the chip temperature reaches a relatively high temperature, the thermal stress is kept as low as possible to maintain the reliability of the connection part, and the high heat resistance. , Can continue operation.

  According to the semiconductor device of the present invention, it is possible to provide a semiconductor device having a high heat dissipation function while maintaining the reliability of the connecting portion by suppressing thermal stress.

  FIG. 1 is a longitudinal sectional view showing a structure of a semiconductor device A in the embodiment. As shown in the figure, the semiconductor device A of the present embodiment has, as main members, semiconductor chips 11a and 11b on which semiconductor elements such as switching transistors are formed, and heat generated in the semiconductor chips 11a and 11b. The metal plate 23a, 23b, 23c made of Cu-Mo or Cu-W, which is connected to the heat dissipation substrate 21 and the back electrode 14 of the semiconductor chip 11a (11b) and extends to the main surface side of the heat dissipation substrate 21. And a ribbon member 17 that connects the main surface electrode 16 of the semiconductor chip 11a (11b) and the metal plate 23, and the semiconductor chip 11a (11b), the metal plate 23b (23c), the ribbon member 17 and the like It is made of a sealing member 15 that is sealed on the surface side, and Cu, Cu alloy, Cu—Mo, or Cu—W that are fixed to the back surface of the heat dissipation substrate 21 so as to be separated from each other. And a plurality of fin-shaped member 22.

  The heat dissipation substrate 21 is made of an inorganic insulating material (in this embodiment, ceramics) such as AlN, Al—SiC, or Si—SiC. On the back surface of the heat dissipation substrate 21, a back surface side metallized layer 24 is formed over almost the entire surface, and the fin-like member 22 made of Cu, Cu alloy, Cu—Mo or Cu—W is brazed (silver brazing, The back metallization layer 24 is joined by a copper braze or the like. The main surface side metallized layer 26 is formed on the main surface of the heat dissipation substrate 21 only at the connection portions with the metal plates 23a, 23b, and 23c, and the metal plates 23a, 23b, and the like made of Cu-Mo, Cu-W, or the like. 23c is joined to the main surface side metallization layer 26 by brazing (low temperature brazing such as solder). The back surface side metallized layer 24 and the main surface side metallized layer 26 are formed by reacting, for example, a metal film such as Mo alloy, W alloy, Mo—Mn alloy and AlN in a hydrogen atmosphere. It is plated.

  The material of the heat dissipation substrate 21 is not limited to AlN, silicon nitride, SiC, or a composite material containing at least one of them as a main component, but is preferably limited. The thermal expansion coefficient α of AlN is about 4.5 (ppm / K), the thermal conductivity is about 200 (W / m · K), and the thermal expansion coefficient α of silicon nitride is about 2 to 3 (ppm / K). The thermal conductivity is about 80 (W / m · K) at the maximum, the thermal expansion coefficient α of SiC is about 4 (ppm / K), and the thermal conductivity is about 200 to 500 (W / m · K). . Therefore, these heat-dissipating materials are much larger than the thermal conductivity of general-purpose ceramics such as alumina, and have a thermal conductivity close to that of aluminum (thermal conductivity of about 240 (W / m · K), while being thermally expanded. The coefficient α is much smaller than aluminum (α≈23 (ppm / K)) and is close to the thermal expansion coefficient α of the semiconductor chip (about 3 (ppm / K) for Si and about 4 (ppm / K) for SiC). Therefore, by configuring the heat dissipation substrate 21 with AlN, silicon nitride, SiC, or a composite material containing at least one of them as a main component, it is possible to minimize the thermal stress while maintaining a large heat transfer amount. it can.

  The material of the metal plates 23a, 23b, and 23c is not limited to Cu—Mo or Cu—W. However, the thermal expansion coefficient α of Cu—Mo is about 6.5 to 8 (ppm / K), the thermal conductivity is about 200 (W / m · K), and the thermal expansion coefficient α of Cu—W is about 6 .5-7 (ppm / K), and thermal conductivity is 180-200 (W / m · K). The thermal conductivity of these composite materials is much lower than that of Cu (about 400 (W / m · K)), but is close to that of aluminum (Al), while the thermal expansion coefficient α is , Much smaller than the thermal expansion coefficient α (≈17) of Cu and close to the thermal expansion coefficient α of the semiconductor chip (about 3 (ppm / K) for Si and about 4 (ppm / K) for SiC). Therefore, by configuring the metal plate 23 from Cu—Mo or Cu—W, it is possible to minimize the thermal stress while maintaining a large heat transfer amount.

  The material of the fin-like member 22 is not limited to Cu, Cu alloy, Cu—Mo, or Cu—W. However, similarly to the metal plates 23a, 23b, and 23c, by configuring the fin-like member 22 from Cu—Mo or Cu—W, it is possible to minimize the thermal stress while maintaining a large heat transfer amount. . Further, by configuring the fin-like member 22 from Cu or Cu alloy, the heat radiation function can be further enhanced by using the fin-like member 22 having high thermal conductivity.

  The back surface of the heat dissipation substrate 21 and the fin-like member 22 are exposed to a coolant (cooling medium) flowing in a direction perpendicular to the paper surface, and the fin-like member 22 is configured to increase the heat exchange efficiency with the coolant. ing. Instead of the coolant, a gas such as helium, argon, nitrogen, or air may be used.

  The sealing member 15 is made of epoxy resin, urethane resin, silicone resin, or the like, and is formed by potting. In general, after the semiconductor device A is incorporated in a module and necessary wiring is completed, the upper portion is filled with a gelatinous protective film, so that a sealing member is not always necessary. In consideration of reliability and various changes in environment during use, it is preferable to provide the sealing member 15.

  Next, the structure of the semiconductor chip 11a (11b) will be described. FIG. 2 is a longitudinal sectional view of the semiconductor chip 11a (11b) in the present embodiment. As shown in the figure, the semiconductor chip 11a (11b) has a resistivity of 0.02 Ωcm, a thickness of 400 μm, and a (0 0 0 1) plane that is turned off by about 8 ° in the [1 1-2 0] direction. An n-type 4H—SiC substrate 30 as a main surface and an n-type epitaxial growth layer 31 having a thickness of about 10 μm grown on the 4H—SiC substrate 30 by a CVD epitaxial growth method with in-situ doping. Yes.

The vertical MOSFET 1 in the semiconductor chip 11a (11b) includes a p-well region 32 formed in a part of the surface portion of the epitaxial growth layer 31, and an n-type formed in each part of the surface portion of the p-well region 32. Type source region 33 and p ⁺ contact region 35, gate insulating film 38 made of a silicon oxide film formed on epitaxially grown layer 31, and Ni film (or Ni) formed on the back surface of 4H-SiC substrate 30 A rear electrode 40 made of an alloy film) and a Ni film (or Ni alloy film) formed on the gate insulating film 38 on a region where the portions located above the source region 33 and the p ⁺ contact region 35 are opened. A gate electrode made of an Al film (or an Al alloy film) formed on the gate insulating film 40 at a position apart from the source electrode 41 and the source electrode 41. And a 42.

  Although not shown in FIG. 2, a number of transistor cells are gathered to form one vertical MOSFET. In each transistor cell of the vertical MOSFET, when supplied, electrons supplied from the back electrode 40 flow in the vertical direction from the 4H-SiC substrate 30 to the uppermost portion of the epitaxial growth layer 31, and then the uppermost portion of the p-well region 32. The source region 33 is reached through the channel region.

  On the other hand, the Schottky diode 2 in the semiconductor chip 11 a (11 b) is formed on the p guard ring region 45 formed on a part of the surface portion of the epitaxial growth layer 31 and the epitaxial growth layer 31 including the p guard ring region 45. Schottky comprising a silicon oxide film 43 formed and a Ni film (or Ni alloy film) formed on a region of the silicon oxide film 43 that is located above the portion extending over the p guard ring region 45. An electrode 46 and a back electrode 40 common to the vertical MOSFET 1 are provided.

  Here, the source electrode 41 of the vertical MOSFET 1 and the Schottky electrode 46 of the Schottky diode 2 extend to the protective insulating film and form the upper surface electrode 16 (see FIG. 3) which is a common pad. Further, the gate electrode of the vertical MOSFET 1 extends onto the protective insulating film in a cross section different from that of FIG. 2 and serves as a gate pad 18 (see FIG. 3).

  FIG. 4 is an electric circuit diagram of a module including the semiconductor device according to the embodiment. As shown in the figure, in the module, three sets of semiconductor chips 11a and 11b connected in series are connected in parallel between the power supply terminal VDD and the ground terminal VSS. In each semiconductor chip 11a (11b), a vertical MOSFET 1 and a Schottky diode 2 are arranged in parallel with each other. Each electrical wiring 13a is connected to the ground terminal VSS, the electrical wiring 13c is connected to the power supply terminal VDD, and three-phase power signals U, V, and W are taken out from each intermediate electrical wiring 13b. That is, an inverter circuit that converts a DC power signal applied between the power supply terminal VDD and the ground terminal VSS into a three-phase power signal is configured. The inverter circuit according to the present embodiment converts direct-current power such as a fuel cell or a hydrogen battery into three-phase power for driving an automobile engine.

  FIG. 3 is a top view of the semiconductor device A according to the embodiment. In the semiconductor device A, three sets of a pair of semiconductor chips 11a and 11b arranged in series are arranged between the power supply terminal VDD and the ground terminal VSS shown in FIG. That is, a total of six semiconductor chips 11a or 11b are arranged. Further, the metal plate 23 functioning as electric wiring extends not only to the back surface side of the semiconductor chip 11a (11b) but also to a region that becomes a pad for electrical connection with the outside. The metal plate 23a connected to the ground terminal VSS and the upper surface electrode 16 of the semiconductor chip 11a are connected by the ribbon member 17, and the metal plate 23a and the ribbon member 17 function as the electrical wiring 13a. The metal plate 23b and the upper surface electrode 16 of the semiconductor chip 11b are connected by a ribbon member 17, and the metal plate 23b and the ribbon member 17 function as the electrical wiring 13b. The end of the metal plate 23c is a pad connected to the power supply terminal VDD, and the metal plate 23c functions as a part of the electric wiring 13c. That is, in the state assembled as a module, the two semiconductor chips 11a and 11b are connected in series by the electric wirings 13a, 13b, and 13c.

  On the other hand, the gate pad 18 of the semiconductor chip 11a and the metal plate 23d as a control signal input unit are electrically connected by a bonding wire 19. Further, the gate pad 18 of the semiconductor chip 11b and the metal plate 23e which is a control signal input unit are electrically connected by a bonding wire 19. The sealing member 15 also seals part of the gate pad 18, the bonding wire 19 and the metal plate 23d (23e).

  And in the state assembled as a module, the signal wiring for control signals is connected to the metal plates 23d and 23e, and the power wiring from the ground terminal VSS (see FIG. 4) is connected to the pad of the metal plate 23a. The power wiring from the power supply terminal VDD (see FIG. 4) is connected to the pad of the metal plate 23c, and the power wiring for outputting the three-phase power signals U, V, W is connected to the pad of the metal plate 23. The

  According to the semiconductor device A of the present embodiment, the plurality of fin-like members 22 that are separated from each other are provided on the back surface side of the heat dissipation substrate 21, so that thermal stress is generated between the fin-like member 22 and the heat dissipation substrate 21. Even if it occurs, it is absorbed by the open portion of the heat dissipation substrate 21 and the reliability of the connecting portion is maintained. Therefore, even if the fin-like member 22 is made of a metal material having a high thermal conductivity such as Cu or Cu alloy, the heat radiation function can be enhanced while maintaining the reliability of the connecting portion. Further, since the fin-like member 22 is made of Cu-Mo or Cu-W, the difference in thermal expansion coefficient between the heat dissipation substrate 21 made of an inorganic insulating material and the fin-like member 22 can be reduced, so that the connecting portion Reliability is further improved.

(Other embodiments)
The structure of the embodiment of the present invention disclosed above is merely an example, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  FIG. 5 is a partial cross-sectional view showing a first modification of the embodiment. As shown in the figure, the same number of grooves as the fin-like member 22 are formed on the back surface of the heat dissipation substrate 21, and the base end portion 22 a of the fin-like member 22 is fitted in the groove. The back surface side metallized layer 24 is formed on the wall surface of the groove, and the fin-like member 22 is joined to the back surface side metallized layer 24 by brazing. According to this modification, the bonding area between the fin-like member 22 and the back-side metallized layer 24 is increased as compared with the embodiment, so that the connection reliability is improved and the fin-like member 22 and the heat dissipation board 21 are connected. Since the area of the heat path is expanded, the heat dissipation function is also improved.

  FIG. 6 is a partial cross-sectional view showing a second modification of the embodiment. As shown in the figure, a groove formed after the back surface side metallization layer 24 is formed is formed on the back surface of the heat dissipation substrate 21. Further, the base end portion 22 b of the fin-like member 22 is thinner and stepped than the other portions, and the base end portion 22 b is fitted in the groove of the heat dissipation substrate 21. And the edge part of the step part of the fin-shaped member 22 and the back surface side metallization layer 24 are joined by brazing. According to this modification, since the fin-like member 22 is fitted in the groove of the heat dissipation board 21 at the base end portion 22b, the holding function of the fin-like member 22 by the heat dissipation board 21 is increased compared to the embodiment. , The reliability of the connecting portion is improved. Furthermore, since the base end portion 22b of the fin-like member 22 and the heat dissipation substrate 21 are in direct contact with each other at the wall surface of the groove, the heat transfer coefficient between the heat dissipation substrate 21 and the fin-like member 22 is higher than that in the first modification. Increases heat dissipation function. At the time of assembly, since the base end portion 22b of the fin-like member 22 is fitted into the groove of the heat dissipation board 21 at room temperature, the thermal expansion coefficient α of the fin-like member 22 must be larger than the thermal expansion coefficient α of the heat dissipation board 21. For example, even if the temperature rises, the fitting between the base end portion 22b of the fin member 22 and the groove of the heat dissipation board 21 does not loosen.

  In the first modification and the second modification, the heat radiating substrate 21 and the fin-like member 22 may be connected by an adhesive without forming the back-side metallized layer 24. This is because the base end portion 22b of the fin-like member 22 and the groove of the heat dissipation substrate 21 are fitted, so that the reliability of the connection portion does not deteriorate. This has the advantage that the manufacturing cost can be reduced. In particular, in the second modification, the base end portion 22a and the wall surface of the groove are in direct contact with each other, so that the heat transfer coefficient is also maintained high.

  In the embodiment and the modification described above, the fin-like member 22 has a plate shape. However, the fin-like member 22 may have a plate shape or a notch therebetween, or may have a rod shape or a needle shape. Shall.

  By applying the semiconductor device of the present invention to a device having a power device using a wide band gap semiconductor (SiC, GaN, Diamond, etc.), the switching operation is performed at a temperature higher than the operating temperature of the Si device, and the chip temperature is increased. Even when the temperature reaches 150 ° C. or higher, the operation can be maintained with high heat resistance while reducing the thermal stress as much as possible to maintain the reliability of the connecting portion, and a remarkable effect can be obtained.

  In the above embodiment, the vertical MOSFET 1 and the Schottky diode 2 are formed on the semiconductor chip 11a (11b). However, the vertical MOSFET and the Schottky diode may be formed on individual semiconductor chips. The semiconductor chip 11a (11b) may be provided with a vertical MISFET whose gate insulating film is not a silicon oxide film but a nitride film or an oxynitride film instead of the vertical MOSFET 1.

  In the above embodiment, the vertical MOSFET is formed in the semiconductor chip 11a (11b). However, the semiconductor chip of the present invention may be one in which a semiconductor element such as a lateral MOSFET is formed. In this case, since the drain electrode is formed on the main surface side of the semiconductor chip instead of the back surface electrode 40, the metal plate may ensure a back bias. 21 may be in contact with substantially the entire surface. Further, the metal plate may be a die pad that has only a function of simply supporting the chip, and in that case, it may be provided only under the chip.

  Further, the semiconductor device of the present invention is not limited to the one having a semiconductor chip on which a MOSFET or a Schottky diode is formed, and may be a semiconductor device having an IGBT, JFET or the like. Even in that case, as long as the heat dissipation substrate 21, the metal plates 23a to 23e, and the fin-like member 22 exist, regardless of the type of semiconductor element in the semiconductor chip mounted above the metal plates 23a to 23e, It is possible to improve the heat dissipation function while maintaining the reliability of the connection portion against thermal stress.

  The semiconductor device of the present invention can be used for various devices equipped with MOSFETs, IGBTs, diodes, JFETs, etc., and in particular, can be used as an element of a semiconductor module.

It is a longitudinal cross-sectional view which shows the structure of the semiconductor device in embodiment. It is a longitudinal cross-sectional view of the semiconductor chip in embodiment. It is a top view of a semiconductor device in an embodiment. It is an electric circuit diagram of a module including a semiconductor device in an embodiment. It is sectional drawing which shows the 1st modification of embodiment. It is sectional drawing which shows the 2nd modification of embodiment. It is sectional drawing which shows the structure of the semiconductor device which mounts the conventional IGBT chip | tip.

Explanation of symbols

A Semiconductor device 1 Vertical MOSFET
2 Schottky diode 11a Semiconductor chip 11b Semiconductor chip 13a-13c Electrical wiring 14 Back surface electrode 15 Sealing member 16 Upper surface electrode 17 Ribbon member 18 Gate pad 19 Bonding wire 21 Heat radiation substrate 22 Fin-shaped member 22a Base end portion 22b Base end portion 23a -23e Metal plate 24 Back surface side metallization layer 26 Main surface side metallization layer 30 4H-SiC substrate 31 n type epitaxial growth layer 32 p well region 33 n type source region 35 p ⁺ contact region 38 gate insulating film 40 back surface electrode 41 source electrode 42 Gate electrode 43 Silicon oxide film 45 p-type guard ring region 46 Schottky electrode

Claims (11)

A semiconductor device comprising a semiconductor chip on which a semiconductor element is formed, and a mounting member group for mounting the semiconductor chip on the main surface side,
The mounting member group includes:
A heat dissipation substrate made of an inorganic insulating material;
A metal plate mounted on the main surface side of the heat dissipation substrate;
A semiconductor device having a plurality of fin-like members spaced apart and fixed to the back side of the heat dissipation substrate. The semiconductor device according to claim 1,
The mounting member group further includes a main surface side metallization layer formed on the main surface of the heat dissipation substrate,
The semiconductor device, wherein the metal plate is brazed to the main surface side metallization layer. The semiconductor device according to claim 1 or 2,
The mounting member group further includes a back side metallized layer formed on the back side of the heat dissipation substrate,
The semiconductor device, wherein the fin-like member is brazed to the back metallization layer. The semiconductor device according to claim 1,
The said metal plate is a semiconductor device comprised with the metal material whose thermal expansion coefficient is larger than 0 (ppm / K) and below 10 (ppm / K). In the semiconductor device according to claim 1,
The said metal plate is a semiconductor device comprised by Cu-Mo or Cu-W. In the semiconductor device according to claim 1,
The said heat dissipation board | substrate is a semiconductor device comprised with the inorganic insulating material whose thermal expansion coefficient is larger than 0 (ppm / K) and below 10 (ppm / K). In the semiconductor device according to claim 1,
The semiconductor substrate is made of a material selected from AlN, silicon nitride, SiC, and a composite material containing at least one of them as a main component. In the semiconductor device according to claim 1,
The difference in thermal expansion coefficient between the heat dissipation substrate and the metal plate is 7 (ppm / K) or less. The semiconductor device according to claim 1,
The fin-like member is a semiconductor device made of a metal material having a thermal expansion coefficient larger than 0 (ppm / K) and not larger than 10 (ppm / K). The semiconductor device according to claim 1,
The said fin-shaped member is a semiconductor device comprised with the material chosen from Cu, Cu alloy, Cu-Mo, and Cu-W. The semiconductor device according to claim 1,
The semiconductor device is a power device using a wide band gap semiconductor.

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