JP2007184366A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007184366A
JP2007184366A JP2006000744A JP2006000744A JP2007184366A JP 2007184366 A JP2007184366 A JP 2007184366A JP 2006000744 A JP2006000744 A JP 2006000744A JP 2006000744 A JP2006000744 A JP 2006000744A JP 2007184366 A JP2007184366 A JP 2007184366A
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semiconductor device
heat sink
sink member
dimensional network
semiconductor
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Hideyuki Okamoto
秀之 岡本
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability and high cooling capability. <P>SOLUTION: The semiconductor device A comprises semiconductor chips 11a and 11b, whereon semiconductor elements are formed, heat dissipation substrate 21, wiring boards 23a, 23b, and 23c, sealing members 15 for sealing the semiconductor chips 11a and 11b, respectively, and heat sink member 22 arranged on the rear face side of the heat dissipation substrate 21. The heat sink member 22 consists of a flat support 22a and a solid mesh 22b formed of a solid mesh-like material. According to to this structure, the surface area of the heat sink member 22 as a whole is increased, so the space dominated by the heat sink member 22 is used effectively, which improves the heat exchange function of the device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体チップを実装してなる半導体装置に係り、特に、放熱対策に関する。   The present invention relates to a semiconductor device on which a semiconductor chip is mounted, and more particularly to a heat dissipation measure.

従来より、たとえば特許文献１に開示されるように、発熱体である電子部品を実装した半導体装置の構造として、フィン付きのヒートシンク部材を備え、フィンによって冷却効果を高めつつ、ヒートシンク部材と水や空気などの冷却媒体との熱交換を行わせるようにしたものは公知の技術である。   Conventionally, as disclosed in, for example, Patent Document 1, as a structure of a semiconductor device in which an electronic component that is a heating element is mounted, a heat sink member with fins is provided, and the cooling effect is enhanced by the fins. A technique that allows heat exchange with a cooling medium such as air is a known technique.

特開２００３−２７０８０号公報Japanese Patent Laid-Open No. 2003-27080

上記公報の構造により、フィンを利用して比較的高い熱交換効率を実現することができる。しかし、放熱のために利用しうるヒートシンク部材の表面積には限界があるために、必ずしもヒートシンク部材が占めるスペースの有効利用が図られていない。   With the structure of the above publication, relatively high heat exchange efficiency can be realized using fins. However, since there is a limit to the surface area of the heat sink member that can be used for heat dissipation, effective use of the space occupied by the heat sink member is not necessarily achieved.

本発明の目的は、ヒートシンク部材が占めるスペースの有効利用を図ることにより、効率のよい放熱機能を有する半導体装置を提供することにある。   An object of the present invention is to provide a semiconductor device having an efficient heat dissipation function by effectively utilizing a space occupied by a heat sink member.

本発明の半導体装置は、半導体チップを冷却するためのヒートシンク部材を備えており、ヒートシンク部材は、熱交換媒体の通過が可能な立体網状部を有している。   The semiconductor device of the present invention includes a heat sink member for cooling the semiconductor chip, and the heat sink member has a three-dimensional network portion capable of passing a heat exchange medium.

これにより、立体網状部の壁面もヒートシンク部材の表面となるので、ヒートシンク部材と熱交換媒体との熱交換が行われる表面の面積が飛躍的に増大する。したがって、ヒートシンク部材が占めるスペースを効率よく利用した，高い放熱機能を有する半導体装置が得られる。   As a result, the wall surface of the three-dimensional mesh portion also becomes the surface of the heat sink member, so that the area of the surface where heat exchange between the heat sink member and the heat exchange medium is dramatically increased. Therefore, a semiconductor device having a high heat dissipation function that efficiently utilizes the space occupied by the heat sink member can be obtained.

本発明の半導体装置は、ヒートシンク部材が、平板状の支持部を有していて、立体網状部が平板状の支持部の裏面に取り付けられている構造を採ることができる。   The semiconductor device of the present invention can adopt a structure in which the heat sink member has a flat plate-like support portion, and the three-dimensional network portion is attached to the back surface of the flat plate-like support portion.

立体網状部が金属材料によって構成されていることにより、立体網状部が高い熱伝導率を有することになり、さらに放熱機能が向上する。その場合、平板状の支持部が無機絶縁性材料によって構成されている場合には、平板状の支持部の裏面にメタライズ層を設けて、ヒートシンク部材をメタライズ層にろう付けする構造を採ることにより、有機接着剤が不要となるので、ヒートシンク部材の熱伝達率が向上する。   When the three-dimensional network part is made of a metal material, the three-dimensional network part has a high thermal conductivity, and the heat dissipation function is further improved. In that case, by adopting a structure in which a metallized layer is provided on the back surface of the plate-like support part and the heat sink member is brazed to the metallized layer when the plate-like support part is made of an inorganic insulating material. Since the organic adhesive becomes unnecessary, the heat transfer coefficient of the heat sink member is improved.

立体網状部が、フィン状、柱状などの形状であることにより、ヒートシンク部材の熱交換効率がより高くなる。ただし、立体網状部が平板状であってもよい。   When the three-dimensional network portion has a fin shape, a column shape, or the like, the heat exchange efficiency of the heat sink member is further increased. However, the three-dimensional network part may be flat.

立体網状部が、ヒートシンク部材全体を占めている構造を採ることにより、ヒートシンク部材の占めるスペースをできるだけ有効的に利用することができる。   By adopting a structure in which the three-dimensional network portion occupies the entire heat sink member, the space occupied by the heat sink member can be used as effectively as possible.

この場合にも、ヒートシンク部材が金属材料によって構成されていることにより、ヒートシンク部材が高い熱伝導率を有することになり、さらに放熱機能が向上する。   Also in this case, since the heat sink member is made of a metal material, the heat sink member has high thermal conductivity, and the heat dissipation function is further improved.

立体網状部が、連続気孔を有する材料によって構成されていることにより、発泡金属などを利用して、比較的高効率の熱交換を行うことができる。   Since the three-dimensional network portion is made of a material having continuous pores, heat exchange with relatively high efficiency can be performed using foam metal or the like.

立体網状部が、熱交換媒体の通路の断面全体に亘って設けられていることにより、最大限、高効率の熱交換を行うことが可能になる。   By providing the three-dimensional network part over the entire cross section of the passage of the heat exchange medium, it becomes possible to perform heat exchange with high efficiency to the maximum.

本発明の半導体装置によると、ヒートシンク部材に立体網状部を設けたので、ヒートシンク部材の占めるスペースを有効利用して、高い放熱機能を有する半導体装置を提供することができる。   According to the semiconductor device of the present invention, since the three-dimensional mesh portion is provided on the heat sink member, a semiconductor device having a high heat dissipation function can be provided by effectively using the space occupied by the heat sink member.

（実施の形態１）
図１は、実施の形態１における半導体装置Ａの構造を示す縦断面図である。同図に示すように、本実施の形態の半導体装置Ａは、主要部材として、スイッチングトランジスタなどの半導体素子が形成された半導体チップ１１ａ，１１ｂと、半導体チップ１１ａ，１１ｂで発生した熱を外方に放出するための，無機絶縁性材料からなる放熱基板２１と、Ｃｕ，Ｃｕ合金，Ａｌ，Ａｌ合金などからなり、半導体チップ１１ａ（１１ｂ）の裏面電極１４等に接続され放熱基板２１の主面側に延びる配線板２３ａ，２３ｂ，２３ｃと、半導体チップ１１ａ（１１ｂ）の主面電極１６と配線板２３とを接続するリボン部材１７と、半導体チップ１１ａ（１１ｂ），配線板２３ｂ（２３ｃ），リボン部材１７等を放熱基板２１の主面側で封止する封止部材１５と、放熱基板２１の裏面に設けられたヒートシンク部材２２とを備えている。同図に示すように、ヒートシンク部材２２は、ＣｕまたはＣｕ合金からなる平板状の支持部２２ａと、連続気孔を有する材料によって構成された立体網状部２２ｂとを有している。 (Embodiment 1)
FIG. 1 is a longitudinal sectional view showing the structure of the semiconductor device A according to the first embodiment. As shown in the figure, the semiconductor device A of the present embodiment has, as main members, semiconductor chips 11a and 11b on which semiconductor elements such as switching transistors are formed, and heat generated in the semiconductor chips 11a and 11b. The heat dissipation substrate 21 made of an inorganic insulating material and the main surface of the heat dissipation substrate 21 connected to the back electrode 14 of the semiconductor chip 11a (11b), etc. Wiring board 23a, 23b, 23c extending to the side, ribbon member 17 connecting main surface electrode 16 of semiconductor chip 11a (11b) and wiring board 23, semiconductor chip 11a (11b), wiring board 23b (23c), A sealing member 15 that seals the ribbon member 17 and the like on the main surface side of the heat dissipation substrate 21 and a heat sink member 22 provided on the back surface of the heat dissipation substrate 21 are provided. That. As shown in the figure, the heat sink member 22 has a flat plate-like support portion 22a made of Cu or Cu alloy, and a three-dimensional network portion 22b made of a material having continuous pores.

放熱基板２１は、ＡｌＮ，Ａｌ−ＳｉＣ，Ｓｉ−ＳｉＣ等の無機絶縁性材料（本実施の形態では、セラミックス）によって構成されている。ただし、アルミナなどの汎用セラミックスによって構成されていてもよい。放熱基板２１の裏面には、ほぼ全面に亘って裏面側メタライズ層２４が形成されており、ヒートシンク部材２２の支持部２２ａは、ろう付け（銀ろう，銅ろうなど）によって裏面側メタライズ層２４に接合されている。放熱基板２１の主面には、配線板２３ａ，２３ｂ，２３ｃとの接続部のみに主面側メタライズ層２６が形成されており、配線板２３ａ，２３ｂ，２３ｃは、ろう付け（はんだなどの低温ろう）によって主面側メタライズ層２６に接合されている。裏面側メタライズ層２４および主面側メタライズ層２６は、たとえばＭｏ合金，Ｗ合金，Ｍｏ−Ｍｎ合金などの金属膜とＡｌＮ等とを水素雰囲気中で反応させることにより形成され、その後、表面にＮｉメッキが施されている。ただし、メタライズ層を形成することなく、有機接着剤などにより、放熱基板２１と、配線板２３およびヒートシンク部材２２の支持部２２ａとの間をそれぞれ接着してもよい。   The heat dissipation substrate 21 is made of an inorganic insulating material (in this embodiment, ceramics) such as AlN, Al—SiC, or Si—SiC. However, you may be comprised with general purpose ceramics, such as an alumina. A rear surface side metallized layer 24 is formed almost entirely on the rear surface of the heat dissipation substrate 21, and the support 22 a of the heat sink member 22 is formed on the rear surface side metallized layer 24 by brazing (silver brazing, copper brazing, etc.). It is joined. The main surface side metallized layer 26 is formed on the main surface of the heat dissipation board 21 only at the connection portions with the wiring boards 23a, 23b, and 23c. The wiring boards 23a, 23b, and 23c are brazed (low temperature such as solder). The main surface side metallized layer 26 is joined by brazing. The back surface side metallized layer 24 and the main surface side metallized layer 26 are formed by reacting, for example, a metal film such as Mo alloy, W alloy, Mo—Mn alloy and AlN in a hydrogen atmosphere. It is plated. However, you may adhere | attach between the heat sink 21 and the support part 22a of the wiring board 23 and the heat sink member 22 with an organic adhesive etc., without forming a metallization layer, respectively.

本実施の形態では、立体網状部２２ｂは、Ｃｕ，Ｎｉ，ＳＵＳ（ステンレス），Ｎｉ合金，Ａｌ，Ａｌ合金などの金属を発泡させた連続気孔を有するものであって、具体的な材料としては、たとえば三菱マテリアル株式会社製の発泡金属がある。発泡金属には、気孔率が８０〜９０％，９４〜９６％、９５〜９７％のものがあるので、冷却媒体や、半導体素子の適正温度などに応じて、適宜気孔率を選択することができる。金属だけでなく、セラミックス，ガラスなどの連続気孔を有する材料を用いてもよい。また、連続気孔を有するものでなくても、たとえば、金属ワイヤを立体的に丸めた金たわし状のものや、平板状のメッシュを立体的に組み合わせたもの、などによっても、立体網状構造を実現することができる。すなわち、本発明における「立体網状」とは、多孔質体、交差して孔を形成する線状または帯状のものの集合体、などを含む概念である。   In the present embodiment, the three-dimensional network portion 22b has continuous pores obtained by foaming a metal such as Cu, Ni, SUS (stainless steel), Ni alloy, Al, Al alloy, etc. For example, there is a foam metal manufactured by Mitsubishi Materials Corporation. Since foam metal has a porosity of 80 to 90%, 94 to 96%, and 95 to 97%, the porosity can be appropriately selected according to the cooling medium, the appropriate temperature of the semiconductor element, and the like. it can. You may use the material which has not only a metal but continuous pores, such as ceramics and glass. Even if it does not have continuous pores, a three-dimensional network structure can be realized, for example, by using a metal wire with three-dimensionally rolled metal wires or a three-dimensional combination of flat meshes. can do. That is, the “three-dimensional network” in the present invention is a concept including a porous body, an aggregate of linear or belt-like objects that intersect to form pores, and the like.

なお、本実施の形態では、立体網状部２２ｂは、ろう付けによって支持部２２ａに接合されているが、有機接着剤によって接着されていてもよい。特に、立体網状部２２ｂが、セラミックスによって構成されている場合には、立体網状部２２ｂの上面にメタライズ層を形成しておいて、このメタライズ層と支持部２２ａとをろう付けする構造を採ることもできる。   In the present embodiment, the three-dimensional network portion 22b is bonded to the support portion 22a by brazing, but may be bonded by an organic adhesive. In particular, when the three-dimensional network portion 22b is made of ceramics, a metallized layer is formed on the upper surface of the three-dimensional network portion 22b, and the metallized layer and the support portion 22a are brazed. You can also.

配線板２３ａ，２３ｂ，２３ｃの材料は、ＣｕまたはＣｕ合金に代えて、Ｃｕ−ＭｏやＣｕ−Ｗなどの複合材料を選択することもできる。Ｃｕ−Ｍｏの熱膨張係数αは約６．５〜８であり，Ｃｕの熱膨張係数α（≒１７）よりもはるかに小さく半導体チップ１１ａ（１１ｂ）の熱膨張係数α（Ｓｉで約３、ＳｉＣで約４）や放熱基板２１の熱膨張係数αに近い。したがって、配線板２３ａ，２３ｂ，２３ｃを、Ｃｕ−ＭｏまたはＣｕ−Ｗより構成することによって、半導体チップ１１ａ（１１ｂ）との間における熱応力をできるだけ小さくすることができる。   As the material of the wiring boards 23a, 23b, and 23c, a composite material such as Cu—Mo or Cu—W can be selected instead of Cu or a Cu alloy. The thermal expansion coefficient α of Cu—Mo is about 6.5 to 8, which is much smaller than the thermal expansion coefficient α (≈17) of Cu, and the thermal expansion coefficient α of the semiconductor chip 11a (11b) (about 3 for Si, It is close to the thermal expansion coefficient α of about 4) and the heat dissipation substrate 21 with SiC. Therefore, by configuring the wiring boards 23a, 23b, and 23c from Cu—Mo or Cu—W, the thermal stress between the semiconductor chip 11a (11b) can be made as small as possible.

ヒートシンク部材２２の立体網状部２２ｂの表面は、冷却液（冷却媒体）にさらされている。立体網状部２２ｂの表面積は一般的なフィンに比べて大幅に大きいので、立体網状部２２ｂにより、冷却液との熱交換効率を高めるように構成されている。冷却媒体としては、液体に代えて、ヘリウム，アルゴン，窒素，空気などの気体であってもよい。   The surface of the three-dimensional network portion 22b of the heat sink member 22 is exposed to a cooling liquid (cooling medium). Since the surface area of the three-dimensional network portion 22b is significantly larger than that of a general fin, the three-dimensional network portion 22b is configured to increase the efficiency of heat exchange with the coolant. The cooling medium may be a gas such as helium, argon, nitrogen, air instead of the liquid.

封止部材１５は、エポキシ樹脂，ウレタン樹脂，シリコーン樹脂などからなり、ポッティングによって形成されたものである。一般に、組み立て工程における信頼性や、使用時には環境が多彩に変化することを考慮すると、封止部材１５を設けることが好ましい。   The sealing member 15 is made of epoxy resin, urethane resin, silicone resin, or the like, and is formed by potting. In general, it is preferable to provide the sealing member 15 in consideration of reliability in the assembly process and various changes in environment during use.

次に、半導体チップ１１ａ（１１ｂ）の構造について説明する。図２は、本実施の形態における半導体チップ１１ａ（１１ｂ）の縦断面図である。同図に示すように、半導体チップ１１ａ（１１ｂ）は、抵抗率が０．０２Ωｃｍ、厚みが４００μｍで、［ 1 1-2 0 ］方向に約８°オフさせた（ 0 0 0 1 ）面を主面とするｎ型の４Ｈ−ＳｉＣ基板３０と、in-situドープを伴うＣＶＤエピタキシャル成長法により、４Ｈ−ＳｉＣ基板３０の上に成長された，厚みが約１０μｍのｎ型エピタキシャル成長層３１と備えている。   Next, the structure of the semiconductor chip 11a (11b) will be described. FIG. 2 is a longitudinal sectional view of the semiconductor chip 11a (11b) in the present embodiment. As shown in the figure, the semiconductor chip 11a (11b) has a resistivity of 0.02 Ωcm, a thickness of 400 μm, and a (0 0 0 1) plane that is turned off by about 8 ° in the [1 1-2 0] direction. An n-type 4H—SiC substrate 30 as a main surface, and an n-type epitaxial growth layer 31 having a thickness of about 10 μm grown on the 4H—SiC substrate 30 by a CVD epitaxial growth method with in-situ doping. Yes.

そして、半導体チップ１１ａ（１１ｂ）内の縦型ＭＯＳＦＥＴ１は、エピタキシャル成長層３１の表面部の一部に形成されたｐウェル領域３２と、ｐウェル領域３２の表面部の各一部に形成されたｎ型ソース領域３３およびｐ＋コンタクト領域３５と、エピタキシャル成長層３１の上に形成されたシリコン酸化膜からなるゲート絶縁膜３８と、４Ｈ−ＳｉＣ基板３０の裏面上に形成された、Ｎｉ膜（又はＮｉ合金膜）からなる裏面電極４０と、ゲート絶縁膜３８のうちソース領域３３及びｐ＋コンタクト領域３５の上方に位置する部分を開口した領域の上に形成されたＮｉ膜（又はＮｉ合金膜）からなるソース電極４１と、ゲート絶縁膜４０の上にソース電極４１とは離間した位置に形成されたＡｌ膜（又はＡｌ合金膜）からなるゲート電極４２とを備えている。 The vertical MOSFET 1 in the semiconductor chip 11a (11b) includes a p-well region 32 formed in a part of the surface portion of the epitaxial growth layer 31, and an n-type formed in each part of the surface portion of the p-well region 32. Type source region 33 and p + contact region 35, gate insulating film 38 made of a silicon oxide film formed on epitaxial growth layer 31, and Ni film (or Ni film) formed on the back surface of 4H—SiC substrate 30 A rear electrode 40 made of an alloy film) and a Ni film (or Ni alloy film) formed on the gate insulating film 38 on a region where the portions located above the source region 33 and the p + contact region 35 are opened. A gate electrode made of an Al film (or an Al alloy film) formed on the gate insulating film 40 at a position apart from the source electrode 41 and the source electrode 41. And a 42.

図２には表示されていないが、多数のトランジスタセルが集合して１つの縦型ＭＯＳＦＥＴが構成されている。この縦型ＭＯＳＦＥＴの各トランジスタセルにおいて、オン時には、裏面電極４０から供給される電子が、４Ｈ−ＳｉＣ基板３０からエピタキシャル成長層３１の最上部まで縦方向に流れた後、ｐウェル領域３２の最上部のチャネル領域を経て、ソース領域３３に達することになる。   Although not shown in FIG. 2, a number of transistor cells are gathered to form one vertical MOSFET. In each transistor cell of the vertical MOSFET, when supplied, electrons supplied from the back electrode 40 flow in the vertical direction from the 4H-SiC substrate 30 to the uppermost portion of the epitaxial growth layer 31, and then the uppermost portion of the p-well region 32. The source region 33 is reached through the channel region.

一方、半導体チップ１１ａ（１１ｂ）内のショットキーダイオード２は、エピタキシャル成長層３１の表面部の一部に形成されたｐガードリング領域４５と、ｐガードリング領域４５を含むエピタキシャル成長層３１の上に形成されたシリコン酸化膜４３と、シリコン酸化膜４３のうちｐガードリング領域４５に跨る部分の上方に位置する部分を開口した領域の上に形成されたＮｉ膜（又はＮｉ合金膜）からなるショットキー電極４６と、縦型ＭＯＳＦＥＴ１と共通の裏面電極４０とを備えている。   On the other hand, the Schottky diode 2 in the semiconductor chip 11 a (11 b) is formed on the p guard ring region 45 formed on a part of the surface portion of the epitaxial growth layer 31 and the epitaxial growth layer 31 including the p guard ring region 45. Schottky comprising a silicon oxide film 43 formed and a Ni film (or Ni alloy film) formed on a region of the silicon oxide film 43 that is located above the portion extending over the p guard ring region 45. An electrode 46 and a back electrode 40 common to the vertical MOSFET 1 are provided.

ここで、縦型ＭＯＳＦＥＴ１のソース電極４１と、ショットキーダイオード２のショットキー電極４６とは、保護用絶縁膜まで延びて共通のパッドである上面電極１６（図２参照）となっている。また、縦型ＭＯＳＦＥＴ１のゲート電極は、図２とは異なる断面において保護用絶縁膜上まで延びてゲートパッド１８（図３参照）となっている。   Here, the source electrode 41 of the vertical MOSFET 1 and the Schottky electrode 46 of the Schottky diode 2 extend to the protective insulating film and form the upper surface electrode 16 (see FIG. 2) which is a common pad. Further, the gate electrode of the vertical MOSFET 1 extends onto the protective insulating film in a cross section different from that of FIG. 2 and serves as a gate pad 18 (see FIG. 3).

図４は、実施の形態における半導体装置を含むモジュールの電気回路図である。同図に示すように、モジュール内において、電源端子ＶＤＤと接地端子ＶＳＳとの間には、直列に接続された３組の半導体チップ１１ａ，１１ｂが、互いに並列に接続されている。各半導体チップ１１ａ（１１ｂ）には、縦型ＭＯＳＦＥＴ１とショットキーダイオード２とが互いに並列に配置されている。各電気配線１３ａは接地端子ＶＳＳに接続され、各電気配線１３ｃは電源端子ＶＤＤに接続され、中間の各電気配線１３ｂから三相の電力信号Ｕ，Ｖ，Ｗが取り出される。すなわち、電源端子ＶＤＤおよび接地端子ＶＳＳ間に印加される直流電力信号を３相の電力信号に変換するインバータ回路が構成されている。本実施の形態のインバータ回路は、燃料電池や水素電池などの直流電力を自動車のエンジンを駆動するための三相の電力に変換するものである。   FIG. 4 is an electric circuit diagram of a module including the semiconductor device according to the embodiment. As shown in the figure, in the module, three sets of semiconductor chips 11a and 11b connected in series are connected in parallel between the power supply terminal VDD and the ground terminal VSS. In each semiconductor chip 11a (11b), a vertical MOSFET 1 and a Schottky diode 2 are arranged in parallel with each other. Each electric wiring 13a is connected to the ground terminal VSS, each electric wiring 13c is connected to the power supply terminal VDD, and three-phase power signals U, V, and W are taken out from each intermediate electric wiring 13b. That is, an inverter circuit that converts a DC power signal applied between the power supply terminal VDD and the ground terminal VSS into a three-phase power signal is configured. The inverter circuit according to the present embodiment converts direct-current power such as a fuel cell or a hydrogen battery into three-phase power for driving an automobile engine.

図３は、実施の形態における半導体装置Ａの上面図である。半導体装置Ａには、図４に示す電源端子ＶＤＤと接地端子ＶＳＳとの間に、直列に配置された１対の半導体チップ１１ａ，１１ｂの３組が配置されている。つまり、合計６個の半導体チップ１１ａまたは１１ｂが配置されている。また、電気配線として機能する配線板２３は、半導体チップ１１ａ（１１ｂ）の裏面側だけでなく、外部との電気的接続を行うためのパッドとなる領域まで延びている。そして、接地端子ＶＳＳに接続される配線板２３ａと、半導体チップ１１ａの上面電極１６とは、リボン部材１７により接続され、配線板２３ａおよびリボン部材１７が電気配線１３ａとして機能する。配線板２３ｂと半導体チップ１１ｂの上面電極１６とは、リボン部材１７によって接続されており、配線板２３ｂおよびリボン部材１７が電気配線１３ｂとして機能する。配線板２３ｃの端部は、電源端子ＶＤＤに接続されるパッドになっていて、配線板２３ｃが電気配線１３ｃの一部として機能する。すなわち、モジュールとして組立てられた状態では、各２つの半導体チップ１１ａ，１１ｂが電気配線１３ａ，１３ｂ，１３ｃにより直列に接続されている。   FIG. 3 is a top view of the semiconductor device A according to the embodiment. In the semiconductor device A, three sets of a pair of semiconductor chips 11a and 11b arranged in series are arranged between the power supply terminal VDD and the ground terminal VSS shown in FIG. That is, a total of six semiconductor chips 11a or 11b are arranged. Further, the wiring board 23 functioning as an electrical wiring extends not only to the back surface side of the semiconductor chip 11a (11b) but also to a region serving as a pad for electrical connection with the outside. The wiring board 23a connected to the ground terminal VSS and the upper surface electrode 16 of the semiconductor chip 11a are connected by the ribbon member 17, and the wiring board 23a and the ribbon member 17 function as the electric wiring 13a. The wiring board 23b and the upper surface electrode 16 of the semiconductor chip 11b are connected by a ribbon member 17, and the wiring board 23b and the ribbon member 17 function as the electric wiring 13b. The end of the wiring board 23c is a pad connected to the power supply terminal VDD, and the wiring board 23c functions as a part of the electrical wiring 13c. That is, in the state assembled as a module, the two semiconductor chips 11a and 11b are connected in series by the electric wirings 13a, 13b, and 13c.

一方、半導体チップ１１ａのゲートパッド１８と、制御信号入力部である配線板２３ｄとは、ボンディングワイヤ１９によって電気的に接続されている。また、半導体チップ１１ｂのゲートパッド１８と、制御信号入力部である配線板２３ｅとは、ボンディングワイヤ１９によって、電気的に接続されている。そして、封止部材１５は、ゲートパッド１８，ボンディングワイヤ１９および配線板２３ｄ（２３ｅ）の一部をも封止している。   On the other hand, the gate pad 18 of the semiconductor chip 11a and the wiring board 23d as a control signal input unit are electrically connected by a bonding wire 19. Further, the gate pad 18 of the semiconductor chip 11 b and the wiring board 23 e as a control signal input unit are electrically connected by a bonding wire 19. The sealing member 15 also seals part of the gate pad 18, the bonding wire 19 and the wiring board 23d (23e).

そして、モジュールとして組み立てられた状態では、配線板２３ｄ，２３ｅには制御信号用の信号配線が接続され、配線板２３ａのパッドには接地端子ＶＳＳ（図４参照）からの電力配線が接続され、配線板２３ｃのパッドには電源端子ＶＤＤ（図４参照）からの電力配線が接続され、配線板２３のパッドには三相の電力信号Ｕ，Ｖ，Ｗを出力するための電力配線が接続される。   In a state assembled as a module, signal wiring for control signals is connected to the wiring boards 23d and 23e, and power wiring from the ground terminal VSS (see FIG. 4) is connected to the pads of the wiring board 23a. The power wiring from the power supply terminal VDD (see FIG. 4) is connected to the pad of the wiring board 23c, and the power wiring for outputting the three-phase power signals U, V, W is connected to the pad of the wiring board 23. The

本実施の形態の半導体装置Ａによると、ヒートシンク部材２２に立体網状部２２ｂを設けたので、従来の単なるフィン付きのヒートシンクを備えたものに比べ、熱交換媒体との熱交換が行われるヒートシンクの表面の面積を大幅に拡大することができる。よって、ヒートシンク部材２２が占めるスペースを有効に利用して、高効率の熱交換を行わせることができる。   According to the semiconductor device A of the present embodiment, since the three-dimensional mesh portion 22b is provided in the heat sink member 22, the heat sink that performs heat exchange with the heat exchange medium is performed as compared with a conventional heat sink with fins. The surface area can be greatly enlarged. Therefore, the space occupied by the heat sink member 22 can be effectively used to perform highly efficient heat exchange.

立体網状部２２ｂを連続気孔を有する材料によって構成する場合、一般的には、気孔率が高いほどヒートシンク部材２全体の表面積が大きくなる。ただし、半導体素子の種類によっては、たとえば１５０°Ｃ前後の高温に維持されることが好ましい場合もあるので、適度な冷却機能が望まれることがある。また、壁自体の熱パスがあまりに小さいと、立体網状部２２ｂの冷却がもっぱら支持部２２ａの裏面付近だけで行われることになり、冷却効率が悪化する。したがって、熱交換媒体、半導体素子の種類、などを考慮して、立体網状部２２ｂの気孔率を適正な範囲に設定することが好ましい。   When the three-dimensional network portion 22b is made of a material having continuous pores, generally, the surface area of the heat sink member 2 as a whole increases as the porosity increases. However, depending on the type of semiconductor element, it may be preferable to maintain a high temperature of, for example, around 150 ° C., and thus an appropriate cooling function may be desired. On the other hand, when the heat path of the wall itself is too small, the cooling of the three-dimensional mesh portion 22b is performed only near the back surface of the support portion 22a, and the cooling efficiency is deteriorated. Therefore, it is preferable to set the porosity of the three-dimensional network portion 22b within an appropriate range in consideration of the heat exchange medium, the type of semiconductor element, and the like.

（実施の形態２）
図５は、実施の形態２に係る半導体装置の一部を示す部分断面図である。図５においては、放熱基板２１の主面側に配置されている部材の図示は省略し、かつ、図１に示す断面の一部のみを抜き出して示されているが、ヒートシンク部材２２の立体網状部２２ｂ以外の部材の構造は、実施形態１で説明したとおりである。図５に示すように、本実施の形態では、支持部２２ａの裏面には、フィン状の立体網状部２２ｂがろう付けされている。 (Embodiment 2)
FIG. 5 is a partial cross-sectional view showing a part of the semiconductor device according to the second embodiment. In FIG. 5, illustration of members arranged on the main surface side of the heat dissipation substrate 21 is omitted, and only a part of the cross section shown in FIG. The structure of members other than the part 22b is as described in the first embodiment. As shown in FIG. 5, in the present embodiment, a fin-shaped three-dimensional network portion 22b is brazed to the back surface of the support portion 22a.

本実施の形態により、実施の形態１に比べ、冷却液の流れがスムーズになるという利点がある。   According to the present embodiment, there is an advantage that the flow of the coolant is smoother than that of the first embodiment.

（実施の形態３）
図６は、実施の形態３に係る半導体装置の一部を示す部分断面図である。図６においては、放熱基板２１の主面側に配置されている部材の図示は省略し、かつ、図１に示す断面の一部のみを抜き出して示されているが、ヒートシンク部材２２以外の部材の構造は、実施形態１で説明したとおりである。図６に示すように、本実施の形態では、ヒートシンク部材全体が立体網状の材料、たとえば連続気孔を有する材料（発泡金属など）によって構成されている。言い換えると、立体網状部がヒートシンク全体を占めていることになる。ヒートシンク部材２２は、裏面側メタライズ層２４にろう付けされている。 (Embodiment 3)
FIG. 6 is a partial cross-sectional view showing a part of the semiconductor device according to the third embodiment. In FIG. 6, illustration of members disposed on the main surface side of the heat dissipation substrate 21 is omitted, and only a part of the cross section shown in FIG. 1 is extracted, but members other than the heat sink member 22 are shown. The structure is as described in the first embodiment. As shown in FIG. 6, in the present embodiment, the entire heat sink member is made of a three-dimensional net-like material, for example, a material having continuous pores (foam metal or the like). In other words, the solid network portion occupies the entire heat sink. The heat sink member 22 is brazed to the back metallization layer 24.

本実施の形態により、ヒートシンク部材２２の表面積が増大するので、実施の形態２に比べ、冷却機能は向上する。   According to the present embodiment, the surface area of the heat sink member 22 is increased, so that the cooling function is improved as compared with the second embodiment.

（実施の形態４）
図７は、実施の形態４に係る半導体装置の一部を示す部分断面図である。図７においては、放熱基板２１の主面側に配置されている部材の図示は省略し、かつ、図１に示す断面の一部のみを抜き出して示されているが、ヒートシンク部材２２以外の部材の構造は、実施形態１で説明したとおりである。図７に示すように、本実施の形態では、実施の形態３と同様に、ヒートシンク部材全体が立体網状の材料、たとえば連続気孔を有する材料（発泡金属など）によって構成されている。加えて、ヒートシンク部材２２の裏面が、半導体装置を収納するケースの底面にまで達している。 (Embodiment 4)
FIG. 7 is a partial cross-sectional view showing a part of the semiconductor device according to the fourth embodiment. In FIG. 7, the members arranged on the main surface side of the heat dissipation substrate 21 are not shown, and only a part of the cross section shown in FIG. 1 is extracted, but members other than the heat sink member 22 are shown. The structure is as described in the first embodiment. As shown in FIG. 7, in the present embodiment, as in the third embodiment, the entire heat sink member is made of a three-dimensional network material, for example, a material having continuous pores (foam metal or the like). In addition, the back surface of the heat sink member 22 reaches the bottom surface of the case that houses the semiconductor device.

本実施の形態により、冷却液の流れが均一になるとともに、ヒートシンク部材２２の表面積が最大になるので、実施の形態３に比べ、さらに冷却機能が向上する。   According to the present embodiment, the flow of the cooling liquid becomes uniform, and the surface area of the heat sink member 22 is maximized, so that the cooling function is further improved as compared with the third embodiment.

（他の実施の形態）
上記開示された本発明の実施の形態の構造は、あくまで例示であって、本発明の範囲はこれらの記載の範囲に限定されるものではない。本発明の範囲は、特許請求の範囲の記載によって示され、さらに特許請求の範囲の記載と均等の意味及び範囲内でのすべての変更を含むものである。 (Other embodiments)
The structure of the embodiment of the present invention disclosed above is merely an example, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

実施の形態２においては、フィン状の立体網状部２２ｂは、縦方向に延びる平板状であるが、板状であってもその間に切り込みを入れることができ、あるいは、棒状もしくは針状であってもよいものとする。   In the second embodiment, the fin-shaped three-dimensional network portion 22b has a flat plate shape extending in the vertical direction. However, even if it is a plate shape, a notch can be provided therebetween, or a rod shape or a needle shape. It shall be good.

本発明の半導体装置は、ワイドバンドギャップ半導体（ＳｉＣ，ＧａＮ，Diamondなど）を用いたパワーデバイスを有するものに適用することにより、高負荷状態では発熱量が急激に増大するような半導体装置においても、熱応力をできるだけ小さくして接続部の信頼性を維持しつつ、高い放熱機能により、パワーデバイスの過剰な温度上昇を防止することができ、著効を奏することができる。   The semiconductor device of the present invention can be applied to a semiconductor device having a power device using a wide bandgap semiconductor (SiC, GaN, Diamond, etc.), so that the amount of heat generated suddenly increases in a high load state. In addition, while maintaining the reliability of the connection part by reducing the thermal stress as much as possible, an excessive temperature rise of the power device can be prevented by a high heat dissipation function, and a remarkable effect can be obtained.

上記各実施の形態では、半導体チップ１１ａ（１１ｂ）に、縦型ＭＯＳＦＥＴ１とショットキーダイオード２とが形成されているが、縦型ＭＯＳＦＥＴとショットキーダイオードが個別の半導体チップに形成されていてもよい。なお、半導体チップ１１ａ（１１ｂ）には、縦型ＭＯＳＦＥＴ１に代えて、ゲート絶縁膜がシリコン酸化膜でなく窒化膜や酸窒化膜である縦型ＭＩＳＦＥＴを設けてもよい。   In each of the above embodiments, the vertical MOSFET 1 and the Schottky diode 2 are formed on the semiconductor chip 11a (11b). However, the vertical MOSFET and the Schottky diode may be formed on individual semiconductor chips. . The semiconductor chip 11a (11b) may be provided with a vertical MISFET whose gate insulating film is not a silicon oxide film but a nitride film or an oxynitride film instead of the vertical MOSFET 1.

上記各実施の形態では、半導体チップ１１ａ（１１ｂ）に、縦型ＭＯＳＦＥＴが形成されているが、本発明の半導体チップは、横型ＭＯＳＦＥＴなどの半導体素子が形成されているものであってもよい。その場合には、裏面電極４０に代えて、半導体チップの主面側にドレイン電極が形成されることになるので、配線板２３は、バックバイアスを確保するものでよく、放熱基板２１とほぼ全面に亘って接触していてもよい。   In each of the above embodiments, the vertical MOSFET is formed in the semiconductor chip 11a (11b). However, the semiconductor chip of the present invention may be one in which a semiconductor element such as a lateral MOSFET is formed. In this case, since the drain electrode is formed on the main surface side of the semiconductor chip instead of the back surface electrode 40, the wiring board 23 may ensure a back bias and is almost the entire surface of the heat dissipation substrate 21. May be in contact with each other.

また、本発明の半導体装置は、ＭＯＳＦＥＴやショットキーダイオードが形成された半導体チップを搭載したものに限定されるものではなく，ＩＧＢＴ，ＪＦＥＴ等を搭載した半導体装置であってもよい。その場合にも、ヒートシンク部材２２の少なくとも一部が、立体網状材料により構成されていれば、ヒートシンク部材２２の上方に搭載される半導体チップ内の半導体素子の種類を問わず、熱応力に対する接続部の信頼性を維持しつつ、放熱機能の向上を図ることができる。   Further, the semiconductor device of the present invention is not limited to the one having a semiconductor chip on which a MOSFET or a Schottky diode is formed, and may be a semiconductor device having an IGBT, JFET or the like. Even in such a case, if at least a part of the heat sink member 22 is made of a three-dimensional net-like material, the connection portion against the thermal stress regardless of the type of the semiconductor element in the semiconductor chip mounted above the heat sink member 22. It is possible to improve the heat dissipation function while maintaining the reliability.

本発明の半導体装置は、ＭＯＳＦＥＴ，ＩＧＢＴ，ダイオード，ＪＦＥＴ等を搭載した各種機器に利用することができ、特に半導体モジュールの要素として利用することができる。   The semiconductor device of the present invention can be used for various devices equipped with MOSFETs, IGBTs, diodes, JFETs, etc., and in particular, can be used as an element of a semiconductor module.

実施の形態１における半導体装置の構造を示す縦断面図である。1 is a longitudinal sectional view showing a structure of a semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体チップの縦断面図である。1 is a longitudinal sectional view of a semiconductor chip in a first embodiment. 実施の形態１における半導体装置の上面図である。4 is a top view of the semiconductor device in the first embodiment. FIG. 実施の形態１における半導体装置を含むモジュールの電気回路図である。3 is an electric circuit diagram of a module including the semiconductor device in the first embodiment. FIG. 実施の形態２における半導体装置の構造を示す部分断面図である。FIG. 6 is a partial cross-sectional view showing a structure of a semiconductor device in a second embodiment. 実施の形態３における半導体装置の構造を示す部分断面図である。FIG. 10 is a partial cross-sectional view illustrating a structure of a semiconductor device in a third embodiment. 実施の形態４における半導体装置の構造を示す部分断面図である。FIG. 10 is a partial cross-sectional view showing a structure of a semiconductor device in a fourth embodiment.

符号の説明Explanation of symbols

Ａ 半導体装置
１ 縦型ＭＯＳＦＥＴ
２ ショットキーダイオード
１１ａ 半導体チップ
１１ｂ 半導体チップ
１３ａ〜１３ｃ 電気配線
１４ 裏面電極
１５ 封止部材
１６ 上面電極
１７ リボン部材
１８ ゲートパッド
１９ ボンディングワイヤ
２１ 放熱基板
２２ ヒートシンク部材
２２ａ 支持部
２２ｂ 立体網状部
２３ａ〜２３ｅ 配線板
２４ 裏面側メタライズ層
２６ 主面側メタライズ層
３０ ４Ｈ−ＳｉＣ基板
３１ ｎ型エピタキシャル成長層
３２ ｐウェル領域
３３ ｎ型ソース領域
３５ ｐ＋コンタクト領域
３８ ゲート絶縁膜
４０ 裏面電極
４１ ソース電極
４２ ゲート電極
４３ シリコン酸化膜
４５ ｐ型ガードリング領域
４６ ショットキー電極 A Semiconductor device 1 Vertical MOSFET
2 Schottky diode 11a Semiconductor chip 11b Semiconductor chip 13a-13c Electric wiring 14 Back surface electrode 15 Sealing member 16 Upper surface electrode 17 Ribbon member 18 Gate pad 19 Bonding wire 21 Heat radiation board 22 Heat sink member 22a Support part 22b Three-dimensional network part 23a-23e Wiring board 24 Back surface side metallized layer 26 Main surface side metallized layer 30 4H-SiC substrate 31 n type epitaxial growth layer 32 p well region 33 n type source region 35 p + contact region 38 gate insulating film 40 back surface electrode 41 source electrode 42 gate electrode 43 Silicon oxide film 45 p-type guard ring region 46 Schottky electrode

Claims (8)

半導体素子が形成された半導体チップと、
前記半導体チップを冷却するためのヒートシンク部材と
を備えた半導体装置であって、
前記ヒートシンク部材は、少なくとも一部に、熱交換媒体の通過が可能な立体網状部を有している、半導体装置。 A semiconductor chip on which a semiconductor element is formed;
A semiconductor device comprising a heat sink member for cooling the semiconductor chip,
The heat sink member is a semiconductor device having at least a part of a three-dimensional network part through which a heat exchange medium can pass. 請求項１記載の半導体装置において、
前記ヒートシンク部材は、平板状の支持部を有しており、
前記立体網状部は、前記平板状の支持部の裏面に取り付けられている、半導体装置。 The semiconductor device according to claim 1,
The heat sink member has a flat plate-like support part,
The three-dimensional network part is a semiconductor device attached to the back surface of the flat support part. 請求項２記載の半導体装置において、
前記立体網状部は、金属材料によって構成されている、半導体装置。 The semiconductor device according to claim 2,
The three-dimensional network portion is a semiconductor device made of a metal material. 請求項３記載の半導体装置において、
前記平板状の支持部は、無機絶縁性材料によって構成されており、
前記平板状の支持部の裏面に形成されたメタライズ層をさらに備え、
前記ヒートシンク部材は、前記メタライズ層にろう付けされている、半導体装置。 The semiconductor device according to claim 3.
The plate-like support portion is made of an inorganic insulating material,
Further comprising a metallized layer formed on the back surface of the flat plate-like support part,
The semiconductor device, wherein the heat sink member is brazed to the metallized layer. 請求項２〜４のいずれかに記載の半導体装置において、
前記ヒートシンク部材の前記立体網状部の外形は、フィン状，柱状，または平板状のいずれかである、半導体装置。 The semiconductor device according to claim 2,
The external shape of the three-dimensional net-like portion of the heat sink member is a semiconductor device having any one of a fin shape, a column shape, and a flat plate shape. 請求項１記載の半導体装置において、
前記立体網状部は、ヒートシンク部材の全体を占めている、半導体装置。 The semiconductor device according to claim 1,
The three-dimensional network portion occupies the entire heat sink member. 請求項６記載の半導体装置において、
前記ヒートシンク部材は、金属材料によって構成されている、半導体装置。 The semiconductor device according to claim 6.
The heat sink member is a semiconductor device made of a metal material. 請求項１〜７のいずれかに記載の半導体装置において、
前記立体網状部は、熱交換媒体の通路の断面全体に亘って設けられている、半導体装置。 In the semiconductor device according to claim 1,
The three-dimensional network unit is a semiconductor device provided over the entire cross section of the passage of the heat exchange medium.
JP2006000744A 2006-01-05 2006-01-05 Semiconductor device Pending JP2007184366A (en)

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012165045A1 (en) * 2011-06-01 2012-12-06 住友電気工業株式会社 Semiconductor device and wiring substrate
WO2019026952A1 (en) 2017-08-02 2019-02-07 三菱マテリアル株式会社 Heatsink

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012165045A1 (en) * 2011-06-01 2012-12-06 住友電気工業株式会社 Semiconductor device and wiring substrate
JP2012253125A (en) * 2011-06-01 2012-12-20 Sumitomo Electric Ind Ltd Semiconductor device and wiring board
WO2019026952A1 (en) 2017-08-02 2019-02-07 三菱マテリアル株式会社 Heatsink

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