JP2007329164A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of prolonging a high load status of a semiconductor element. <P>SOLUTION: The semiconductor device A includes semiconductor chips 11 each having the semiconductor element formed thereon, heat radiating substrate 21, wiring boards 23, dummy rings 20 provided on the side of the semiconductor chip 11 on the wiring board 23, a sealing member 15 for sealing the semiconductor chips 11, the dummy rings 20 and the like, and a heat sink member 22. When the semiconductor element in each of the semiconductor chips 11 becomes a high load state and a junction temperature rises, heat generated in the semiconductor chip 11 is absorbed by the dummy ring 20 and the temperature of the dummy ring 20 rises. Thus, a time required when the temperature of the semiconductor chip 11 reaches the upper limit is prolonged. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device for suppressing an excessive rise in the temperature of a chip on which a semiconductor element such as a transistor is formed.

  FIG. 5 is a cross-sectional view showing the structure of a semiconductor device on which a conventional IGBT chip is mounted. As shown in the figure, on the main surface side of the heat radiating substrate 101 made of ceramic or the like, an Al plate 104 fixed to the heat radiating substrate 101 with a solder layer 102 and an Al brazing on the main surface of the Al plate 104 A fixed AlN plate 106, an Al wiring 108 fixed to the main surface of the AlN plate 106 with Al solder, and a semiconductor chip 120 fixed on the Al wiring 108 with solder 109 are provided. Further, a heat sink 113 with fins is attached to the rear surface side of the heat dissipation substrate 101 with the grease 112 interposed therebetween. In general, the heat dissipation substrate 101 is made of Cu—Mo or the like, and the heat sink 113 is made of an Al alloy.

  The grease 112 interposed between the heat dissipation substrate 101 and the heat sink 113 includes a heat sink 113 made of an Al alloy having a thermal expansion coefficient α of about 23 (ppm / K), and a thermal expansion coefficient α of about 9 (ppm / K). This is to relieve stress caused by the difference in thermal expansion coefficient between the heat dissipation substrates 101 made of Cu-Mo.

  As described above, for example, Japanese Patent Application Laid-Open No. 2003-27080 discloses a thermally conductive grease between a finned heat dissipator and an electronic component that is a heat generator. A semiconductor device in which is interposed is disclosed.

Japanese Patent Laid-Open No. 2003-27080

  By the way, in the structure disclosed in FIG. 5 and the above publication, when the chip generates heat due to an increase in the current of the semiconductor element or the like, an attempt to avoid the chip temperature (junction temperature) from instantaneously reaching the upper limit is as follows. There was a problem. In general, in a semiconductor device equipped with a power device used for an inverter such as a hybrid vehicle, when a state where the chip temperature is equal to or higher than an upper limit temperature has passed for an allowable time or longer, it is applied to the semiconductor element to prevent the breakdown of the junction. The voltage or current is turned off. In particular, when grease is present, the heat transfer coefficient in the grease is poor, so that the time for reaching an excessive rise in the chip temperature is shortened.

  In order to avoid such a problem, it is conceivable to increase the heat capacity by increasing the thickness of the heat dissipation substrate. However, the size of the module in which the semiconductor device is incorporated is limited, and the thickness of the entire semiconductor device cannot be increased unnecessarily.

  An object of the present invention is to provide a semiconductor device capable of suppressing an increase in chip temperature while suppressing an increase in thickness of the semiconductor device.

  In the semiconductor device of the present invention, a heat absorbing member for absorbing heat generated by the chip is disposed on the side of the chip on the supporting member of the chip.

  As a result, a structure in which a member having a large heat capacity including the support member and the heat absorbing member is present at a position where heat transfer from the chip is quickly performed is obtained. Therefore, when the chip temperature rises, the temperature of the heat absorbing member also rises promptly, and as a result, the rise of the chip temperature is suppressed, even if the chip temperature does not reach the upper limit of the allowable temperature, The time until then is extended. For example, when the semiconductor device is mounted on a hybrid vehicle, the time during which the engine of the hybrid vehicle can be accelerated is lengthened, and driving comfort is increased.

  Since the height position of the heat absorbing member is not more than the chip, and the thickness of the heat absorbing member is not more than the total thickness of the chip and the joining member, without increasing the thickness of the entire semiconductor device, It becomes possible to increase the heat capacity around the chip.

  When the difference in thermal expansion coefficient between the heat absorbing member and the chip is (15 ppm / K) or less, and because the difference in thermal expansion coefficient between the heat absorbing member and the support member is (15 ppm / K) or less, The thermal stress resulting from the difference in expansion coefficient can be made as small as possible. Of course, it is preferable that these numerical values are smaller in that acceleration is possible for a long time. In particular, the thermal expansion coefficient of the heat absorbing member is preferably a value between the thermal expansion coefficient of the chip and the thermal expansion coefficient of the support member.

  Since the heat absorbing member surrounds the chip in an annular shape, the heat capacity of the heat absorbing member can be increased as much as possible without changing the thickness of the semiconductor device.

  By further including a sealing member that seals the chip and the heat absorption member on the upper surface side of the support member, it is possible to reliably prevent entry of foreign matter, moisture, moisture, etc. into the chip, and reliability of the semiconductor device Will improve.

  The semiconductor device of the present invention can suppress an increase in chip temperature while suppressing an increase in the thickness of the entire semiconductor device.

  FIG. 1 is a longitudinal sectional view showing a structure of a semiconductor device A in the embodiment. As shown in the figure, the semiconductor device A of the present embodiment includes a semiconductor chip 11 having a semiconductor element such as a switching transistor as a main member and having a thickness of, for example, about 0.2 mm, and the semiconductor chip 11. The heat dissipation substrate 21 for releasing the heat generated in the outside, the wiring board 23 joined to the back electrode 14 of the semiconductor chip 11 by solder or the like and extending to the main surface side of the heat dissipation substrate 21, and the main of the semiconductor chip 11 Ribbon member 17 that connects surface electrode 16 and wiring board 23, dummy ring 20 that is a rectangular annular heat absorbing member that is joined to wiring board 23 by solder or the like and surrounds semiconductor chip 11, semiconductor chip 11, A sealing member 15 that seals the dummy ring 20, the wiring board 23, the ribbon member 17, and the like on the main surface side of the heat radiating substrate 21, and a flange fixed to the back surface of the heat radiating substrate 21. It has with down of a heat sink member 22. Here, the heat dissipation substrate 21 and the wiring board 23 constitute a support member that supports the semiconductor chip 11.

  The wiring board 23 is made of Cu, Cu alloy, Al, Al alloy, Cu—Mo, Cu—W or the like having a thickness of about 0.3 mm. The dummy ring 20 is made of Cu, Cu alloy, Al, Al alloy, Cu—Mo, Cu—W or the like having a thickness of about 0.4 mm. The thermal expansion coefficient α of Cu—Mo is about 6.5 to 8 (ppm / K), the thermal conductivity is about 200 (W / m · K), the specific heat is 0.28 to 0.35, and the specific gravity is 9.3. ~ 10.01. The thermal expansion coefficient α of Cu—W is about 6.5 to 7 (ppm / K), the thermal conductivity is 180 to 200 (W / m · K), the specific heat is 0.16 to 0.18, and the specific gravity is 15. 5-17. The thermal expansion coefficient α of Cu is about 17 (ppm / K), the thermal conductivity is about 400 (W / m · K), the specific heat is 0.038, and the specific gravity is 8.96. The thermal expansion coefficient α of Al is about 23 (ppm / K), the thermal conductivity is about 238 (W / m · K), the specific heat is 0.27, and the specific gravity is 2.7. The thermal expansion coefficient α of Si is about 3 to 4.5 (ppm / K), and the thermal conductivity is about 150 (W / m · K). The thermal expansion coefficient α of SiC is about 3 (ppm / K), the thermal conductivity is about 210 (W / m · K), the specific heat is 0.73, and the specific gravity is 3.2.

  The heat dissipation substrate 21 is made of an inorganic insulating material (in this embodiment, ceramics) such as AlN, Al—SiC, or Si—SiC having a thickness of about 0.5 mm, for example. A rear surface side metallized layer 24 is formed almost entirely on the rear surface of the heat dissipation substrate 21, and the heat sink member 22 made of Cu or Cu alloy is bonded to the rear surface side metallized layer by brazing (silver brazing, copper brazing, etc.). 24. A main surface side metallized layer 26 is formed on the main surface of the heat dissipation substrate 21 only at the connection portion with the wiring board 23, and the wiring board 23 is brazed (low temperature brazing such as solder). 26 is joined. The back surface side metallized layer 24 and the main surface side metallized layer 26 are formed by reacting, for example, a metal film such as Mo alloy, W alloy, Mo—Mn alloy and AlN in a hydrogen atmosphere. It is plated.

  The thermal expansion coefficient α of AlN is about 4.5 (ppm / K) and the thermal conductivity is about 200 (W / m · K). The thermal expansion coefficient α of Al—SiC is about 8 (ppm / K), and the thermal conductivity is 180 to 200 (W / m · K). The thermal expansion coefficient α of Si—SiC is about 2.3 to 3 (ppm / K), and the thermal conductivity is about 200 (W / m · K). Therefore, these heat-dissipating materials are much larger than the thermal conductivity of general-purpose ceramics such as alumina, and have a thermal conductivity close to that of aluminum (thermal conductivity of about 240 (W / m · K), while being thermally expanded. The coefficient α is much smaller than aluminum (α≈23 (ppm / K)) and is close to the thermal expansion coefficient α of the semiconductor chip (about 3 (ppm / K) for Si and about 4 (ppm / K) for SiC).

  The back surface of the heat dissipation substrate 21 and the heat sink member 22 are exposed to a coolant (cooling medium) that flows in a direction perpendicular to the paper surface, and the heat sink member 22 is configured to increase the efficiency of heat exchange with the coolant. . Instead of the coolant, a gas such as helium, argon, nitrogen, or air may be used.

  The sealing member 15 is made of epoxy resin, urethane resin, silicone resin, or the like, and is formed by potting. In general, after the semiconductor device A is incorporated in a module and necessary wiring is completed, the upper portion is filled with a gelatinous protective film, so that a sealing member is not always necessary. In consideration of reliability and various changes in environment during use, it is preferable to provide the sealing member 15.

  In the semiconductor device A of the present embodiment, since the dummy ring 20 is provided in the vicinity of the semiconductor chip 11 on the heat dissipation substrate 21 and the wiring board 23 which are supporting members, the following effects are obtained. That is, when the temperature of the semiconductor chip 11 rises, the temperature of not only the heat dissipation board 21 and the wiring board 23 but also the dummy ring 20 rises quickly before heat is released to the heat sink member 22 through the heat dissipation board 21. Therefore, it is avoided that the temperature of the semiconductor chip 11 exceeds the upper limit of the allowable temperature, or the time until it is exceeded is extended.

  Hereinafter, taking the case where the dummy ring 20 is made of Cu as an example, specific effects are calculated. The specific heat of Cu is 0.38 (kJ / kg · K), and the specific gravity is 8.96. It is assumed that the dummy ring 20 is a square ring having an outer side length of 20 × 20 mm, an inner side length of 12 × 12 mm, and a thickness of 0.4 mm. At this time. The heat capacity of the dummy ring 20 is (20 × 20−12 × 12) × 0.4 × 8.96 × 0.38 = 0.35 (J / K). The upper limit of the allowable temperature of the semiconductor element is generally 150 ° C. Assuming that the current flowing through the junction of the semiconductor element increases and the chip temperature (junction temperature) reaches 50 ° C. to 150 ° C., 150−50 = 100 (K), so the dummy ring is 100 W The exotherm will be absorbed for 0.35 seconds. Usually, even when the chip temperature reaches 150 ° C., an allowable time of about 2 seconds is recognized, so that an extension effect of about 18% can be obtained. For example, when the semiconductor device A is mounted on a hybrid vehicle, the time during which the engine of the hybrid vehicle can be accelerated becomes longer, and the driving comfort is increased.

  Moreover, since the heat released from the heat sink member 22 through the heat dissipation substrate 21 increases during this extended time, an extension effect of 18% or more is actually obtained. It is also easy to adjust the shapes and materials of the heat dissipation substrate 21 and the heat sink member 22 so that the chip temperature does not exceed the allowable time and reach the temperature exceeding the upper limit of the allowable temperature.

  In the present embodiment, the dummy ring 20 (heat absorbing member) surrounds the periphery of the semiconductor chip 11 in a closed ring shape, but the heat absorbing member of the present invention does not necessarily surround the periphery of the semiconductor chip 11 in an annular shape. It does not have to be. That is, even if it is disposed on the side of the semiconductor chip 11, heat transfer from the wiring board 23, which is a support member, is rapidly received, so that the heat absorption function can be exhibited. However, it is preferable that the heat absorption member is close to the semiconductor chip 11 and directly receives heat transfer from the side surface of the semiconductor chip 11. Further, the heat absorption member may be annular or not closed but may be open.

  In the present embodiment, the height position of the front end surface of the dummy ring 20 is the height position of the front end surface of the semiconductor chip 11 including the main surface electrode 16 and the back surface electrode 14 (that is, the front end surface of the main surface electrode 16). It is as follows. Further, the thickness of the dummy ring 20 (0.4 mm in the present embodiment) is the sum of the thickness of the semiconductor chip 11 including the main surface electrode 16 and the back surface electrode 14 and the thickness of the brazing layer that is a bonding member. It is less than the thickness (in this embodiment, about 0.5 mm). With this setting, the heat capacity can be increased while the thickness of the entire semiconductor device is kept thin due to the dummy ring 20. However, even if the height of the front end surface of the dummy ring 20 is located above the front end surface of the semiconductor chip 11, the dimensions of the semiconductor device A hardly change or change does not cause a large disadvantage. Shall not be a problem. Similarly, a part of the dummy ring 20 may be located immediately above the semiconductor chip 11.

  Further, the dummy ring (heat absorbing member) 20 is made of Cu-Mo (thermal expansion coefficient 6.5 to 8 (ppm / K), specific heat) or Cu-W (thermal expansion coefficient 7.5 to 8 (ppm / K)). In this case, the difference in thermal expansion coefficient from the semiconductor chip 11 made of SiC (thermal expansion coefficient 3 (ppm / K)) is 3.5 to 5 (ppm / K). In this way, by setting the difference between the thermal expansion coefficient of the dummy ring 20 and the thermal expansion coefficient of the semiconductor chip 11 to 15 (ppm / K) or less, the heat dissipation board 21 and the wiring board 23 that are the support members are both formed. Since the thermal stress generated between them is relatively uniform, deformation such as distortion of the entire heat dissipation substrate 21 can be reduced.

  When the dummy ring 20 and the wiring board 21 are made of Cu-Mo or Cu-W and the heat dissipation board 21 is made of AlN (thermal expansion coefficient 4.5 (ppm / K)), The difference in coefficient of thermal expansion from the support member is a maximum of 3.5 (ppm / K). In this way, by setting the difference in thermal expansion coefficient between the dummy ring 20 and the support member to 15 (ppm / K) or less, the dummy ring 20 and the heat dissipation substrate 21 and the wiring board 23b (23c) as the support members are disposed. It is possible to minimize the thermal stress generated between the thermal stress generated in the above.

  The dummy ring 20 is made of Cu-W (thermal expansion coefficient 6.5-7 (ppm / K)), and the wiring boards 21a, 21b, 21c are made of Cu (thermal expansion coefficient 17 (ppm / K)). When the heat dissipation substrate 21 is made of Al-SiC (thermal expansion coefficient of about 8 (ppm / K)) and the semiconductor chip 11 is made of SiC (thermal expansion coefficient 3 (ppm / K)), the dummy ring 20 Is an intermediate value between the thermal expansion coefficient of the semiconductor chip 11 and the average thermal expansion coefficient of the heat dissipation board 21 and the wiring board 21 as the support members. By making the expansion coefficient an intermediate value between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the support member, the thermal stress around the semiconductor chip can be reduced, so deformation such as warpage can be prevented. It is possible to win.

  Here, the material of the wiring board 23 is required to have a thermal expansion coefficient close to that of the semiconductor chip 11a (11b) and a low specific resistance, rather than having a large specific heat × specific gravity contributing to the heat capacity. In that respect, Cu or Cu alloy is preferable. On the other hand, in a composite material such as Cu—Mo or Cu—W, whether the specific resistance, specific heat, and specific gravity are close to Cu or close to Mo or W is determined by the ratio of Cu, Mo, and W. Therefore, when Cu—Mo or Cu—W is used as the material of the wiring board 23, it is assumed that the thermal expansion coefficient is as close to the semiconductor chip 11 as possible (the difference in thermal expansion coefficient is 15 (ppm / K) or less). It is preferable to use one having a small specific resistance (one having a high Cu composition ratio).

  On the other hand, the material of the dummy ring 20 is not limited even if the specific resistance is large, and it is important that the heat capacity is large and that the thermal expansion coefficient is close to that of the semiconductor chip or the support member. Therefore, when Cu-Mo or Cu-W is used as the material of the dummy ring 20, it is assumed that the thermal expansion coefficient is as close to the semiconductor chip 11 as possible (the difference in thermal expansion coefficient is 15 (ppm / K) or less). It is preferable to use a material having a large heat capacity (a material having a low Cu composition ratio).

  Next, the structure of the semiconductor chip 11 will be described. FIG. 2 is a vertical cross-sectional view of the semiconductor chip 11 in the present embodiment. As shown in the figure, the semiconductor chip 11 has a resistivity of 0.02 Ωcm, a thickness of 400 μm, and a (0 0 0 1) plane that is turned off about 8 ° in the [1 1-2 0] direction as a main surface. And an n-type epitaxial growth layer 31 having a thickness of about 10 μm grown on the 4H-SiC substrate 30 by CVD epitaxial growth with in-situ doping.

The vertical MOSFET 1 in the semiconductor chip 11 includes a p-well region 32 formed in a part of the surface portion of the epitaxial growth layer 31 and an n-type source region formed in each part of the surface portion of the p-well region 32. 33 and p ⁺ contact region 35, gate insulating film 38 made of a silicon oxide film formed on epitaxial growth layer 31, and Ni film (or Ni alloy film) formed on the back surface of 4H-SiC substrate 30 And a source electrode made of a Ni film (or a Ni alloy film) formed on a region of the gate insulating film 38 that is open above the source region 33 and the p ⁺ contact region 35. 41 and a gate electrode 42 made of an Al film (or an Al alloy film) formed on the gate insulating film 40 at a position separated from the source electrode 41. To have.

  Although not shown in FIG. 2, a number of transistor cells are gathered to form one vertical MOSFET. In each transistor cell of the vertical MOSFET, when supplied, electrons supplied from the back electrode 40 flow in the vertical direction from the 4H-SiC substrate 30 to the uppermost portion of the epitaxial growth layer 31, and then the uppermost portion of the p-well region 32. The source region 33 is reached through the channel region.

  On the other hand, the Schottky diode 2 in the semiconductor chip 11 includes a p guard ring region 45 formed in a part of the surface portion of the epitaxial growth layer 31 and a silicon formed on the epitaxial growth layer 31 including the p guard ring region 45. An oxide film 43, and a Schottky electrode 46 made of a Ni film (or a Ni alloy film) formed on a region in which a portion of the silicon oxide film 43 located above the portion extending over the p guard ring region 45 is opened. The vertical MOSFET 1 and the common back electrode 40 are provided.

  Here, the source electrode 41 of the vertical MOSFET 1 and the Schottky electrode 46 of the Schottky diode 2 extend to the protective insulating film and form a top surface electrode which is a common pad. Further, the gate electrode of the vertical MOSFET 1 extends to the protective insulating film in a cross section different from that of FIG.

  FIGS. 3A and 3B are a plan view illustrating an example of the semiconductor module 50 and a plan view in which a part thereof is enlarged, in order. In the figure, the wiring structure is not shown. As shown in FIG. 3A, the semiconductor device module is configured by arranging various semiconductor chips 51 in a frame 50 made of copper or copper alloy. When a three-phase inverter is assumed as a module, the semiconductor chip 51 is divided into three regions 52a, 52b, and 52c corresponding to the U-phase, V-phase, and W-phase, respectively. In each region 52a, 52b, 52c, two sets of high-side and low-side semiconductor chips 51 are arranged. As shown in FIG. 3B, each semiconductor chip includes a vertical MOSFET, And a Schottky diode are provided. A cooling pipe through which cooling water flows is provided below the frame body 50.

(Other embodiments)
The structure of the embodiment of the present invention disclosed above is merely an example, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  FIG. 4 is a partial cross-sectional view showing a modification of the embodiment. As shown in the figure, in this modification, the dummy ring 20 is in direct contact with the semiconductor chip 11 and has a structure for receiving heat directly from the semiconductor chip 11. The dummy ring 20 is made of ceramics (for example, alumina, SiC sintered body, etc.) that is an insulator. Unlike the embodiment, the dummy ring 20 is not a closed ring but an open ring with a cut in part. . Further, the dummy ring 20 does not necessarily have to be connected to the wiring board 23 by bonding or adhesion, and may simply be installed on the wiring board 23. In addition, the dummy ring 20 and the semiconductor chip 11 may be partially bonded by brazing or the like, or may be bonded by an adhesive.

  According to the present modification, it is possible to maintain the contact state between the semiconductor chips 11 while suppressing the thermal stress caused by the difference in thermal expansion coefficient with the semiconductor chip 11. It becomes possible to absorb heat generation. That is, if the semiconductor chip 11 uses a Si substrate or a SiC substrate and the dummy ring is SiC, there is almost no difference in thermal expansion coefficient. Therefore, if the dummy ring 20 is not joined to the wiring board 23, the thermal stress is also reduced. Small enough to be ignored. On the other hand, even when the thermal expansion coefficient of the dummy ring 20 (for example, alumina) is larger than the thermal expansion coefficient of the semiconductor chip 11, the contact state between the two can be maintained even in a high temperature state by being strongly fitted in the assembled state. . The dummy ring 20 and the semiconductor chip 11 do not need to be in contact with each other on both sides. This is because the necessary heat transfer can be obtained even with a structure in which only two opposite sides or only the portions other than the corners of each side are in contact with each other. On the other hand, since dummy ring 20 is composed of a SiC sintered body, it does not cause a significant increase in cost as in the case of increasing the size of the single crystal SiC substrate.

  The semiconductor device of the present invention can be applied to a semiconductor device having a power device using a wide bandgap semiconductor (SiC, GaN, Diamond, etc.), so that the amount of heat generated suddenly increases in a high load state. In addition, while maintaining the reliability of the connection part by reducing the thermal stress as much as possible, an excessive temperature rise of the power device can be prevented by a high heat dissipation function, and a remarkable effect can be obtained.

  In the above embodiment, the vertical MOSFET 1 and the Schottky diode 2 are formed on the semiconductor chip 11, but the vertical MOSFET and the Schottky diode may be formed on separate semiconductor chips. The semiconductor chip 11 may be provided with a vertical MISFET whose gate insulating film is not a silicon oxide film but a nitride film or an oxynitride film instead of the vertical MOSFET 1. Further, a PN diode or a PiN diode may be provided in place of the Schottky diode.

  In the above embodiment, the vertical MOSFET is formed on the semiconductor chip 11, but the semiconductor chip of the present invention may be one in which a semiconductor element such as a lateral MOSFET is formed. In that case, since the drain electrode is formed on the main surface side of the semiconductor chip instead of the back surface electrode 40, the wiring board may ensure a back bias. 21 may be in contact with substantially the entire surface. Further, the wiring board may be a die pad having only a function of simply supporting the chip. In that case, the wiring board may be provided only below the chip.

  Further, the semiconductor device of the present invention is not limited to the one having a semiconductor chip on which a MOSFET or a Schottky diode is formed, and may be a semiconductor device having an IGBT, JFET or the like. Even in this case, if the semiconductor chip 11, the wiring board 23, the heat dissipation substrate 21, and the dummy ring 20 exist, the semiconductor in the semiconductor chip can be used regardless of the structure of the heat sink member 22 provided below the heat dissipation substrate 21. The high load state of the element can be maintained for as long as possible.

  The semiconductor device of the present invention can be used for various devices equipped with MOSFETs, IGBTs, diodes, JFETs, etc., and in particular, can be used as an element of a semiconductor module.

It is a longitudinal cross-sectional view which shows the structure of the semiconductor device in embodiment. It is a longitudinal cross-sectional view of the semiconductor chip in embodiment. It is a top view of the semiconductor module in an embodiment. It is sectional drawing which shows the modification of embodiment. It is sectional drawing which shows the structure of the semiconductor device which mounts the conventional IGBT chip | tip.

Explanation of symbols

A Semiconductor device 1 Vertical MOSFET
2 Schottky diode 11 Semiconductor chip 13 Electrical wiring 14 Back surface electrode 15 Sealing member 16 Top surface electrode 17 Ribbon member 18 Gate pad 19 Bonding wire 20 Dummy ring (heat absorption member)
DESCRIPTION OF SYMBOLS 21 Heat sink 22 Heat sink member 22a Base end part 22b Base end part 23 Wiring board 24 Back surface side metallization layer 26 Main surface side metallization layer 30 4H-SiC substrate 31 n-type epitaxial growth layer 32 p well region 33 n type source region 35 p ⁺ Contact region 38 Gate insulating film 40 Back electrode 41 Source electrode 42 Gate electrode 43 Silicon oxide film 45 p-type guard ring region 46 Schottky electrode 50 Semiconductor module 51 Semiconductor chips 52a to 52c region

Claims (8)

A chip on which a semiconductor element is formed;
A support member for supporting the chip on the main surface side;
A semiconductor device, comprising: a heat absorption member disposed on a side of the chip on the main surface of the support member and configured to absorb heat generated by the chip. The semiconductor device according to claim 1,
The height position of the front end surface of the heat absorption member is a semiconductor device which is below the front end surface of the chip. The semiconductor device according to claim 1 or 2,
A bonding member for bonding the chip and the support member;
The thickness of the said heat absorption member is a semiconductor device which is below the total thickness of the said chip | tip and the said joining member. The semiconductor device according to claim 1,
A difference in thermal expansion coefficient between the heat absorbing member and the chip is (15 ppm / K) or less. In the semiconductor device according to claim 1,
The difference in thermal expansion coefficient between the heat absorbing member and the support member is (15 ppm / K) or less. In the semiconductor device according to claim 1,
The semiconductor device, wherein a thermal expansion coefficient of the heat absorbing member is a value between a thermal expansion coefficient of the chip and a thermal expansion coefficient of the support member. In the semiconductor device according to claim 1,
The semiconductor device, wherein the heat absorbing member surrounds the chip in an annular shape. In the semiconductor device according to claim 1,
The semiconductor device further provided with the sealing member which seals the said chip | tip and a heat absorption member on the upper surface side of the said supporting member.

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