JP2020123127A - Electronic control device - Google Patents

Abstract

To assure simultaneity of data while preventing processing loads from increasing.SOLUTION: A microcomputer 109 comprises a core A1 and a core A2. The core A1 comprises a current command section 105. The core A2 comprises a current detection section 103, a current control section 104, and a three-phase voltage conversion section 106. The current command section 105 comprises an inclusive section B1. The current control section 104 comprises a splitting section B2. The inclusive section B1 includes a plurality of data whose simultaneity has to be assured in processing of the microcomputer 109 into one piece of data that can be settled by the microcomputer 109 as a group, a total data size for the plurality of data whose simultaneity has to be assured in the processing of the microcomputer 109 is equal to or less than a data size that can be settled by the microcomputer 109 as a group, and the splitting section B2 splits the one piece of data post inclusion by the inclusive section B1 into the original plurality of data.SELECTED DRAWING: Figure 2

Description

The present invention relates to an electronic control device equipped with a microcomputer (hereinafter referred to as a microcomputer).

In the motor control, a plurality of data such as three-phase current values Iu, Iv, Iw or current command values Id*, Iq* that must be guaranteed to be synchronized may be used. In the motor control using the multi-core microcomputer, in order to distribute the processing load, the core and the task having different control cycles may update and refer to the same data group. In that case, depending on the timing of referring to the data group, one data is updated with the current value and the other data is updated with the previous value. There were things that weren't done.

If interrupt inhibition is used to guarantee the simultaneity of a plurality of data, a task with a fast control cycle may increase the processing load and may cause a task failure. Therefore, it is necessary to guarantee the simultaneity of the data group used for motor control without using interrupt inhibition. Patent Documents 1 and 2 disclose a method of guaranteeing simultaneity of data groups without using interrupt inhibition.

JP, 2017-130140, A JP, 2009-24509, A

However, in the method disclosed in Patent Document 1, if the second processor core is interrupted while the reference memory is being referred to and the processing of the second processor core is stopped, the update memory is executed. The data simultaneity cannot be guaranteed. Therefore, there is a possibility that the referrer may refer to data whose concurrency is not guaranteed.

In the method disclosed in Patent Document 2, since the arbitration unit manages the update/reference, the reference of data for which the simultaneity that is generated in the method disclosed in Patent Document 1 is not guaranteed does not occur. However, the method disclosed in Patent Document 2 has a problem that the processing load is larger than that of the method disclosed in Patent Document 1.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic control device capable of guaranteeing data simultaneity while suppressing an increase in processing load.

In order to achieve the above object, an electronic control device according to a first aspect includes a microcomputer, and a plurality of data referred to by the same task in the microcomputer can be handled at one time by the microcomputer. Include in the data.

According to the present invention, it is possible to guarantee data simultaneity while suppressing an increase in processing load.

FIG. 1 is a block diagram showing the configuration of the electronic control device according to the first embodiment. FIG. 2 is a block diagram showing an application example of the multi-core of the microcomputer of FIG. FIG. 3 is a timing chart showing an example of the relationship between update and reference when the current command values Id* and Iq* of FIG. 2 are not included. FIG. 4 is a diagram showing an example of data including the current command values Id* and Iq* of FIG. FIG. 5 is a timing chart showing an example of the relationship between update and reference when the current command values Id* and Iq* of FIG. 2 are included. FIG. 6 is a flowchart showing a method of including the current command values Id* and Iq* in FIG. FIG. 7 is a flowchart showing a method of referring to the current command values Id* and Iq* of FIG. FIG. 8 is a block diagram showing the configuration of the electronic control device according to the second embodiment. FIG. 9 is a timing chart showing an example of the relationship between update and reference when the simultaneity of the three-phase current values Iu, Iv, and Iw is not guaranteed. FIG. 10 is a block diagram showing a data transfer method between the update side of the detected values of the three-phase current values Iu, Iv, and Iw and the reference side according to the second embodiment. FIG. 11 is a timing chart showing an example of the relationship between update and reference when the three buffers of FIG. 10 are used. FIG. 12 is a flowchart showing a method of updating the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 10 are used. FIG. 13 is a flowchart showing a method of referring to the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 10 are used. FIG. 14 is a block diagram showing a method of passing data between the update side and the reference side of the three-phase current values Iu, Iv, Iw of the electronic control device according to the third embodiment. FIG. 15 is a timing chart showing an example of the relationship between update and reference when the three buffers of FIG. 14 are used. FIG. 16 is a flowchart showing a method of updating the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 14 are used. FIG. 17 is a flowchart showing a method of referring to the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 14 are used. FIG. 18 is a flowchart showing a method of selectively using the method of guaranteeing the simultaneity of a plurality of data.

Embodiments will be described with reference to the drawings. It should be noted that the embodiments described below do not limit the invention according to the claims, and all of the elements and combinations described in the embodiments are essential to the solution means of the invention. Not necessarily.

FIG. 1 is a block diagram showing the configuration of the electronic control device according to the first embodiment.
In FIG. 1, the motor device includes a motor 101, an inverter circuit 102, a microcomputer 109, a battery 110, a resolver 111, and current sensors Su, Sv, Sw. The motor device can be used, for example, as a drive device for a vehicle, a robot, an elevator, or a crane. The microcomputer 109 can be used as, for example, an electronic control device mounted on a vehicle.

The motor 101 is, for example, a three-phase induction motor. The battery 110 supplies the DC voltage Edc to the inverter circuit 102. The microcomputer 109 controls the inverter circuit 102 by PWM (Pulse Width Modulation). The inverter circuit 102 converts the DC voltage Edc into three-phase voltages Vu, Vv, Vw based on PWM control by the microcomputer 109, and drives the motor 101. The resolver 111 detects the angle of the rotating shaft attached to the motor 101 and outputs it to the microcomputer 109. The current sensors Su, Sv, Sw detect the three-phase current values Iu, Iv, Iw of the current flowing through the motor 101, and output them to the microcomputer 109.

The microcomputer 109 includes an AD (Analog to Digital) converter 112, a PWM control unit 113, an RDC (resolver to digital converter) 114, and a motor current control unit 108. The motor current control unit 108 includes a current detection unit 103, a current control unit 104, a current command unit 105, a three-phase voltage conversion unit 106, and a rotational position detection unit 107.

The AD converter 112 AD-converts the three-phase current values Iu, Iv, Iw detected by the current sensors Su, Sv, Sw, and outputs them to the current detection unit 103. The PWM control unit 113 PWM-controls the inverter circuit 102. The RDC 114 digitizes the rotation angle detected by the resolver 111 and outputs it to the rotation position detection unit 107.

The rotational position detection unit 107 detects the rotation angle θe of the motor 101 and outputs it to the current detection unit 103 and the three-phase voltage conversion unit 106. The current command unit 105 outputs the current command values Id* and Iq* to the current control unit 104. The current detection unit 103 dq-converts the detected current values Id^, Iq based on the three-phase current values Iu, Iv, Iw digitized by the AD converter 112 and the rotation angle θe detected by the rotation position detection unit 107. Generate ^ and output to the current control unit 104

The current control unit 104 sets the voltage command value Vd so that the current detection values Id^ and Iq^ output from the current detection unit 103 and the current command values Id* and Iq* output from the current command unit 105 match. *, Vq* are generated and output to the three-phase voltage conversion unit 106. The three-phase voltage conversion unit 106 once converts the voltage command values Vd*, Vq* and the rotation angle θe into three-phase voltages Vu, Vv, Vw, and then uses a pulse-width modulated (PWM) drive signal to output the inverter circuit 113. The output voltage is adjusted by controlling ON/OFF of the semiconductor switch element.

Since the microcomputer 109 distributes these processes used for motor control, a multi-core can be adopted. At this time, the microcomputer 109 includes a plurality of data referred to by the same task in the microcomputer 109 into one data that can be handled by the microcomputer 109 at one time. A task is an execution unit of a program executed by the microcomputer 109. The plurality of pieces of data referred to by the same task in the microcomputer 109 are the plurality of pieces of data whose simultaneity should be guaranteed in the processing of the microcomputer 109. If a part of the data of the plurality of data for which the simultaneity is to be guaranteed is the data before this update, the other data is also the data before this update. In addition, among a plurality of data for which simultaneity should be guaranteed, when some of the data are data after this update, other data are also data after this update. For example, when the microcomputer 109 updates a plurality of pieces of data referred to by the same task at different timings, the plurality of pieces of updated values are included in one piece of data that the microcomputer 109 can handle at one time. A plurality of data whose simultaneity should be guaranteed can be designated by a program for operating the microcomputer 109, for example. The plurality of data for which the simultaneity should be guaranteed is, for example, a three-phase current value used for motor control or a current command value of dq coordinates.

FIG. 2 is a block diagram showing an application example of the multi-core of the microcomputer of FIG.
In FIG. 2, the microcomputer 109 includes cores A1 and A2. The core A1 includes a current command unit 105. The core A2 includes a current detector 103, a current controller 104, and a three-phase voltage converter 106. The control cycle of the cores A1 and A2 does not necessarily have to be the same cycle.

The current control unit 104 refers to the current command values Id* and Iq* output from the current command unit 105 in order to generate the voltage command values Vd* and Vq*. At this time, the current command values Id* and Iq* output from the current command unit 105 to the current control unit 104 are data on the assumption that simultaneity is guaranteed.

However, the current command unit 105 is provided in the core A1 and the current control unit 104 is provided in the core A2. Therefore, the update and reference of the voltage command values Vd* and Vq* are independently executed in the different cores A1 and A2, and the simultaneity of the current command values Id* and Iq* referred to by the current control unit 104 is not guaranteed. There is. That is, depending on the timing at which the current control unit 104 refers to the current command values Id*, Iq*, the updated current value is adopted as the data Id* of one of the current command values Id*, Iq*, and the other data is adopted. The previous value that has not been updated may be used as the data Iq* of.

FIG. 3 is a timing chart showing an example of the relationship between update and reference when the current command values Id* and Iq* of FIG. 2 are not included.
In FIG. 3, the current command unit 105 in FIG. 2 executes the update 301 of the data Id* of one of the current command values Id* and Iq* for which simultaneity should be guaranteed at time t1, and the other data Iq. It is assumed that the update 302 of * is executed at time 4. At this time, the current control unit 104 and the current command unit 105 use a shared RAM (Random Access Memory), the current command unit 105 outputs the current command values Id*, Iq*, and the current control unit 104 outputs the current command value. The values Id* and Iq* are referred to.

Here, one data Id* of the current command values Id* and Iq* and the other data Iq* are not output at the same timing. At this time, the current control unit 104 executes the reference 305 of the data Id* at the time t2 between the time t1 of the update 301 of the data Id* and the time 4 of the update 302 of the data Iq*, and at the time t3. It is assumed that the reference 306 of Iq* has been executed. In this case, the reference value 303 of one data Id* of the current command values Id* and Iq* has been updated, but the reference value 304 of the other data Iq* of the current command values Id* and Iq* has not been updated. Of the current command value Id* and Iq* referred to by the current control unit 104 is not guaranteed.

In FIG. 2, in order to guarantee the simultaneity of the current command values Id* and Iq* referred to by the current control unit 104, the current command unit 105 includes the enclosing unit B1, and the current control unit 104 includes the dividing unit B2. Prepare The inclusion unit B1 includes a plurality of data whose simultaneity should be guaranteed in the processing of the microcomputer 109 into one data that can be handled by the microcomputer 109 at one time. At this time, the sum of the data sizes of the plurality of data for which the simultaneity should be guaranteed in the processing of the microcomputer 109 is less than or equal to the data size that the microcomputer 109 can handle at one time. For example, the data size that can be handled at one time by the microcomputer 109 is 32 bits, the data size of one of the current command values Id* and Iq* is 16 bits, and the data size of the other data Iq* is also 16 bits. In this case, the inclusion unit B1 can include these two data Id* and Iq* in one data.

The dividing unit B2 divides one piece of data that has been covered by the covering unit B1 into a plurality of original data. For example, the dividing unit B2 divides one piece of data that has been covered by the covering unit B1 into two pieces of data Id* and Iq*.

FIG. 4 is a diagram showing an example of data including the current command values Id* and Iq* of FIG.
In FIG. 4, it is assumed that the data 401 and 402 of the current command values Id* and Iq* updated by the current command unit 105 of FIG. 2 are managed by a 16-bit RAM. At this time, a 32-bit shared RAM 404 capable of including the two data 401 and 402 of the current command values Id* and Iq* as one data 403 is prepared.

Then, the current command unit 105 stores the data 401 in the upper 16 bits and the data 402 in the lower 16 bits of the shared RAM 404 after both the data 401 and 402 of the current command values Id* and Iq* are updated, It manages as one data 403.

The current control unit 104 accesses the shared RAM 404 in which one data 403 is stored as the current command values Id* and Iq*, and refers to the current command values Id* and Iq* as one data 403. Then, the current control unit 104 extracts two pieces of data 401 and 402 from one piece of 32-bit data 403 every 16 bits. As a result, the current control unit 104 refers to the current command values Id* and Iq* whose simultaneity is guaranteed even when the data 401 and 402 of the current command values Id* and Iq* are not updated at the same timing. be able to.

At this time, the updating process of the current command values Id* and Iq* in the current command unit 105 and the reference process of the current command values Id* and Iq* in the current control unit 104 are performed by the current command unit 105 and the current control unit 104. And can be run asynchronously and independently. Therefore, the reference timing of the current command values Id* and Iq* in the current command unit 105 is managed according to the update timing of the current command values Id* and Iq* in the current command unit 105, and the current command unit 105 manages the reference timing. It is not necessary to manage the update timing of the current command values Id* and Iq* in the current command unit 105 according to the reference timings of the current command values Id* and Iq* of FIG. it can.

FIG. 5 is a timing chart showing an example of the relationship between update and reference when the current command values Id* and Iq* of FIG. 2 are included.
In FIG. 5, the current command unit 105 of FIG. 2 executes the update 501 of 16-bit data Id* of the current command values Id* and Iq* for which simultaneity should be guaranteed at time t11, and the other 16 It is assumed that the update 502 of the bit data Iq* is executed at time 12.

Next, the current command unit 105 includes the current command values Id* and Iq* whose simultaneity should be guaranteed in one data, and stores the included 32-bit current command values Id* and Iq* in the shared RAM. By doing so, the update 503 of the current command values Id* and Iq* of the shared RAM is executed at time 13.

Next, the current control unit 104 executes reference 507 of the 32-bit current command values Id* and Iq* stored as one data in the shared RAM at time 14. Next, the current control unit 104 executes the division 508 of the 32-bit current command values Id* and Iq* referred to as one data at time 15 to obtain the 16-bit current command value Id* and the 16-bit current command. Get the value Iq*.

At this time, even when the 16-bit data Id* is updated at time t11 and the 16-bit data Iq* is updated at time t12, the current control unit 104 includes these two data as one data. The 32-bit current command values Id* and Iq* can be referenced at time t14. Here, since the reference value 504 of the 32-bit current command value Id*, Iq* is updated, the 16-bit current command value Id* of the 32-bit current command value Id*, Iq* is divided. Both the reference value 505 and the reference value 505 of the 16-bit current command value Iq* are updated values, and the simultaneity of the current command values Id* and Iq* referenced by the current control unit 104 can be guaranteed. ..

Further, the updates 501, 502, and 503 in the current command unit 105 and the reference 507 and the division 508 in the current control unit 104 can be independently executed asynchronously in the current command unit 105 and the flow control unit 104. It is possible to suppress an increase in processing load on the current command unit 105 and the current control unit 104.

FIG. 6 is a flowchart showing a method of including the current command values Id* and Iq* in FIG.
In FIG. 6, the current command unit 105 of FIG. 2 calculates one data Id* of the current command values Id* and Iq* (S11). Next, the current command unit 105 calculates the other data Iq* of the current command values Id* and Iq* (S12).

Next, the current command unit 105 stores the data Id* in the upper 16 bits of the shared RAM in which data is stored in units of 32 bits (S13), stores the data Iq* in the lower 16 bits, and outputs the current command value Id. *, Iq* are managed as 32-bit data.

FIG. 7 is a flowchart showing a method of referring to the current command values Id* and Iq* of FIG.
In FIG. 7, the current control unit 104 of FIG. 2 refers to the 32-bit current command values Id* and Iq* included in the current command unit 105 (S21). Next, the current control unit 104 acquires the upper 16-bit data Id* from the 32-bit current command values Id* and Iq* included in one data. Next, the current control unit 104 acquires the lower 16-bit data Iq* from the 32-bit current command values Id* and Iq* included in one data.

In the above-described first embodiment, the current command values Id* and Iq* updated on the update side are included in one data, thereby guaranteeing the simultaneity of the current command values Id* and Iq* used on the reference side. I explained how to do it. However, in the method of guaranteeing data simultaneity by including data, the total data size of a plurality of data for which simultaneity is to be guaranteed must be equal to or smaller than the data size that the microcomputer 109 can handle at one time.

Hereinafter, a method of guaranteeing the simultaneity of a plurality of data when the total data size of the plurality of data for which the simultaneity is to be guaranteed is larger than the data size that the microcomputer 109 can handle at once will be described.

FIG. 8 is a block diagram showing the configuration of the electronic control device according to the second embodiment.
In FIG. 8, this electronic control unit includes a microcomputer 109A instead of the microcomputer 109 of FIG. In the following description, it is assumed that the microcomputer 109A is a 32-bit multicore microcomputer. The microcomputer 109A includes a motor temperature estimation unit 115 in addition to the configuration of the microcomputer 109 of FIG. The motor temperature estimation unit 115 estimates the temperature of the motor 101 in FIG. 1 based on the three-phase current values Iu, Iv, Iw digitized by the AD converter 112.

The microcomputer 109A includes cores A11 to A13. The core A11 includes an AD converter 112. The core A12 includes a current detection unit 103, a current control unit 104, a current command unit 105, a three-phase voltage conversion unit 106, and a rotational position detection unit 107. The core A13 includes a motor temperature estimation unit 115. The control cycle of the cores A11 to A13 does not necessarily have to be the same cycle.

The motor temperature estimation unit 115 refers to the three-phase current values Iu, Iv, Iw output from the AD converter 112 in order to estimate the temperature of the motor 101. In the following description, the three-phase current values Iu, Iv, and Iw are each 16-bit data. At this time, the three-phase current values Iu, Iv, and Iw output from the AD converter 112 to the motor temperature estimation unit 115 are data on the assumption that simultaneity is guaranteed.

However, the AD converter 112 is provided in the core A11, and the motor temperature estimation unit 115 is provided in the core A3. Therefore, the three core current values Iu, Iv, and Iw are independently updated and referred to by the different cores A11 and A13, and the simultaneity of the three phase current values Iu, Iv, and Iw referred to by the motor temperature estimation unit 115 is determined. May not be guaranteed. That is, depending on the timing when the motor temperature estimation unit 115 refers to the three-phase current values Iu, Iv, and Iw, some of the three-phase current values Iu, Iv, and Iw have the updated current values, For the remaining data, the previous value that has not been updated may be adopted.

FIG. 9 is a timing chart showing an example of the relationship between update and reference when the simultaneity of the three-phase current values Iu, Iv, and Iw is not guaranteed.
In FIG. 9, the AD converter 112 of FIG. 8 executes the update 601 of the data Iu of the three-phase current values Iu, Iv, Iw for which the simultaneity should be guaranteed at time t21, and the update 602 of the data Iv at time 22. The update 603 of the data Iw is executed at time 26.

On the other hand, the motor temperature estimation unit 115 executes the reference 607 of the data Iu at the time t23 between the time t22 of the update 602 of the data Iv and the time 26 of the update 603 of the data Iw, and refers to the data Iv at the time t24. It is assumed that 608 is executed and the reference 609 of the data Iw is executed at time t25. In this case, the reference values 604, 605 of the data Iu, Iv of the three-phase current values Iu, Iv, Iw are updated, but the reference value 606 of the data Iw of the three-phase current values Iu, Iv, Iw is This is the previous value before updating, and the simultaneity of the three-phase current values Iu, Iv, Iw referred to by the motor temperature estimating unit 115 is not guaranteed.

In the second embodiment, the total data size of the three-phase current values Iu, Iv, Iw is 48 bits, whereas the data size that can be handled at one time by the microcomputer 109A is 32 bits. Therefore, the sum of the data sizes of the three-phase current values Iu, Iv, and Iw for which simultaneity should be guaranteed in the processing of the microcomputer 109A is larger than the data size that the microcomputer 109A can handle at one time, and the three-phase current value Iu, Iv and Iw cannot be included in one data that can be handled at one time by the microcomputer 109A.

In the following embodiments, when the total data size of a plurality of data for which the simultaneity is to be guaranteed is larger than the data size that can be handled at one time by the microcomputer 109A, an intermediate buffer (triple buffer) of the same size on three sides is prepared. A method of guaranteeing the simultaneity of the three-phase current values Iu, Iv, Iw by updating and referring to the three-phase current values Iu, Iv, Iw for the triple buffer will be described.

The second embodiment is premised on the case where the control cycle on the update side of the three-phase current values Iu, Iv, and Iw for which the simultaneity is to be guaranteed is faster than the control cycle on the reference side. It is premised that the control cycle on the reference side of the three-phase current values Iu, Iv, and Iw that should be guaranteed is faster than the control cycle on the update side.

FIG. 10 is a block diagram showing a data transfer method between the update side of the detected values of the three-phase current values Iu, Iv, and Iw and the reference side according to the second embodiment.
10, the microcomputer 109A in FIG. 8 includes three buffers 701 to 703 as triple buffers. The data size of each of the buffers 701 to 703 can be 48 bits. At this time, the buffers 701 to 703 can hold the 48-bit three-phase current values Iu, Iv, and Iw.

The microcomputer 109A of FIG. 8 includes an AD converter 112A as the AD converter 112 and a motor temperature estimation unit 115A as the motor temperature estimation unit 115. The AD converter 112A is assigned to the core A11, and the motor temperature estimation unit 115A is assigned to the core A13. The AD converter 112A operates as an update side of the three-phase current values Iu, Iv, Iw, and the motor temperature estimation unit 115A operates as a reference side of the three-phase current values Iu, Iv, Iw. Each of the update side and the reference side of the three-phase current values Iu, Iv, and Iw can asynchronously access any of the buffers arbitrarily selected from the three buffers 701 to 703.

Here, the three buffers 701 to 703 can be used for passing the three-phase current values Iu, Iv, and Iw from the update side to the reference side. At this time, when the reference side refers to any buffer arbitrarily selected from the three buffers 701 to 703, the updating side does not update any of the three buffers 701 to 703.

For example, it is assumed that the AD converter 112A stores the data of the three-phase current values Iu, Iv, and Iw in one of the buffers arbitrarily selected from the three buffers 701 to 703. Further, it is assumed that the latest data is stored in the buffer 703 of the three buffers 701 to 703, and the motor temperature estimation unit 115A is performing the reference process.

In this case, which of the three buffers 701 to 703 is to be the data storage target by the AD converter 112A will be described.

The AD converter 112A sets a buffer 703 storing the latest data and a buffer 701 other than the reference target buffer 702 as data storage targets. That is, the AD converter 112A determines the storage destination of the data of the three-phase current values Iu, Iv, and Iw in the buffer 701.

When the buffer 701 that stores the latest data and the buffer 701 other than the buffer 702 that is the reference target are the data storage targets, the AD converter 112A knows that the reference target of the motor temperature estimation unit 115A is the buffer 702. There must be. Therefore, the motor temperature estimation unit 115A notifies the AD converter 112A of the data reference destination as shared RAM data between the different cores A11 and A13 (705).

Further, at the timing of storing the three-phase current values Iu, Iv, Iw in the buffer 701 determined as the storage target by the AD converter 112A, the previous storage destination is currently the three-phase current values Iu, Iv, Iw. Since it is the buffer that stores the latest data, the buffer 703 that is the previous storage destination of the three-phase current values Iu, Iv, and Iw is stored.

In this way, the AD converter 112A sets the buffer 701 other than the reference target buffer 702 and the buffer 703 of the storage destination of the previous three-phase current values Iu, Iv, and Iw to the next of the three-phase current values Iu, Iv, and Iw. It can be determined as the storage destination.

On the other hand, the motor temperature estimation unit 115A acquires the latest data of the three-phase current values Iu, Iv, Iw stored in the AD converter 112A, so that the latest data of the three-phase current values Iu, Iv, Iw can be referred to at all times. To Therefore, the motor temperature estimation unit 115A has the AD converter 112A notify which buffer stores the latest data of the three-phase current values Iu, Iv, and Iw. At this time, the AD converter 112A notifies the motor temperature estimation unit 115A of the data storage destination as shared RAM data between the different cores A11 and A13 (704).

However, even if an attempt is made to guarantee the simultaneity of the three-phase current values Iu, Iv, and Iw by the above method, if a processing delay occurs due to an interrupt, the motor temperature estimation unit 115A stores the same buffer as the one being referred to. On the other hand, there is a possibility that the AD converter 112A stores data and the simultaneity of the three-phase current values Iu, Iv, and Iw cannot be guaranteed. Therefore, while the motor temperature estimation unit 115A is referring to the triple buffer, the AD converter 112A is restricted so as not to store data in the triple buffer.

To limit the storage in the triple buffer by the AD converter 112A in this way, the AD converter 112A must know whether the motor temperature estimation unit 115A is referring to the triple buffer. Therefore, the motor temperature estimation unit 115A notifies the AD converter 112A of the reference flag as shared RAM data between the different cores A11 and A13 (706). The AD converter 112A refers to the reference flag and prevents the triple buffer from storing data when the reference flag is ON, so that the three-phase current values Iu, Iv, and It is possible to guarantee the simultaneity of Iw.

FIG. 11 is a timing chart showing an example of the relationship between update and reference when the three buffers of FIG. 10 are used.
11, the AD converter 112A of FIG. 10 executes the update 801 of the 16-bit data Iu of the three-phase current values Iu, Iv, and Iw for which the simultaneity should be guaranteed at time t31, and the 16-bit data Iv. 802 is executed at time t32, and the update 803 of 16-bit data Iw is executed at time t33.

Next, the AD converter 112A determines a buffer to be stored among the triple buffers, and stores 804 the 48-bit data Iu, Iv, and Iw for which the updates 801 to 803 have been executed, at time t34.

Next, the motor temperature estimation unit 115A sets the buffer in which the latest data Iu, Iv, and Iw are stored among the triple buffers as the reference destination, executes the reference 808 of the data Iu at time t35, and refers to the data Iv. 809 is executed at time t36, and reference 810 of the data Iw is executed at time t37.

At this time, after updating the three data Iu, Iv, and Iw, the three data Iu, Iv, and Iw are stored in the buffer. For this reason, the motor temperature estimation unit 115A refers to the three data Iu, Iv, and Iw stored in the buffer to determine the reference value 805 of the data Iu, the reference value 806 of the data Iv, and the reference value 807 of the data Iw. Both can be updated values, and the simultaneity of the three-phase current values Iu, Iv, and Iw referred to by the motor temperature estimation unit 115A can be guaranteed.

FIG. 12 is a flowchart showing a method of updating the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 10 are used.
In FIG. 12, the AD converter 112A in FIG. 10 determines the reference flag set by the motor temperature estimation unit 115A (S31), and ends the process if the reference flag is ON.

On the other hand, when the in-reference flag is OFF, the AD converter 112A is other than the buffer set as the reference destination by the motor temperature estimating unit 115A and the buffer storing the latest data of the three-phase current values Iu, Iv, and Iw. Is determined as the storage destination of the three-phase current values Iu, Iv, and Iw (S32).

Next, the AD converter 112A stores the three-phase current values Iu, Iv, and Iw in the buffer determined as the storage destination of the three-phase current values Iu, Iv, and Iw (S33), and the three-phase current value Iu, The storage destination of the latest data of Iv and Iw is updated (S34).

FIG. 13 is a flowchart showing a method of referring to the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 10 are used.
In FIG. 13, the motor temperature estimation unit 115A of FIG. 10 turns on the reference flag (S41).

Next, the motor temperature estimation unit 115A sets the buffer that stores the latest data of the three-phase current values Iu, Iv, and Iw set by the AD converter 112A as the reference destination (S42).

Next, the motor temperature estimation unit 115A turns off the reference flag (S43), and acquires the latest data of the three-phase current values Iu, Iv, Iw from the reference destination buffer (S44).

Here, by performing the process of setting the reference destination between ON and OFF of the reference flag, the storage process of the AD converter 112A does not always occur while the reference flag is ON. Therefore, the three-phase current values Iu, Iv, and Iw are not stored. After that, the motor temperature estimation unit 115A refers to the latest data of the three-phase current values Iu, Iv, Iw from the buffer set as the reference destination. By the method described above, the motor temperature estimation unit 115A, which is the reference side of the three-phase current values Iu, Iv, and Iw, can refer to the three-phase current values Iu, Iv, and Iw with guaranteed simultaneity.

In the method of guaranteeing the simultaneity by applying the in-reference flag shown in the second embodiment described above, when the update-side control cycle is faster than the reference-side control cycle, the in-reference flag is used to perform the data storage processing. Concurrency is guaranteed by limiting.

However, if the control cycle on the reference side is faster than the control cycle on the update side, the data reference processing must be restricted. In the following third embodiment, a method of guaranteeing data simultaneity when the control cycle on the reference side is faster than the control cycle on the update side will be described.

FIG. 14 is a block diagram showing a method of passing data between the update side and the reference side of the three-phase current values Iu, Iv, Iw of the electronic control device according to the third embodiment.
14, the microcomputer 109A in FIG. 8 includes three buffers 711 to 713. The data size of each buffer 711-713 can be 48 bits. At this time, the buffers 711 to 713 can hold the 48-bit three-phase current values Iu, Iv, and Iw.

The microcomputer 109A in FIG. 8 includes an AD converter 112B as the AD converter 112 and a motor temperature estimation unit 115B as the motor temperature estimation unit 115. The AD converter 112B is assigned to the core A11, and the motor temperature estimation unit 115B is assigned to the core A13. The AD converter 112B operates as an update side of the three-phase current values Iu, Iv, Iw, and the motor temperature estimation unit 115B operates as a reference side of the three-phase current values Iu, Iv, Iw. Each of the update side and the reference side of the three-phase current values Iu, Iv, and Iw can asynchronously access any of the buffers arbitrarily selected from the three buffers 711 to 713.

Here, the three buffers 711 to 713 can be used to transfer the three-phase current values Iu, Iv, and Iw from the update side to the reference side. At this time, when the updating side is updating any one of the three buffers 711 to 703, the reference side does not refer to any of the three buffers 711 to 713.

For example, it is assumed that the AD converter 112B stores the data of the three-phase current values Iu, Iv, and Iw in one of the buffers arbitrarily selected from the three buffers 711 to 713. Further, it is assumed that the latest data is stored in the buffer 713 of the three buffers 711 to 713, and the motor temperature estimation unit 115B is performing the reference process.

This third embodiment can use the same method as the second embodiment except for the control method using the in-reference flag. However, since the control cycle of the motor temperature estimation unit 115B on the reference side is faster than the control cycle of the AD converter 112B on the update side, in order to guarantee the simultaneity of the three-phase current values Iu, Iv, and Iw, the AD converter is required. While the 112B is updating the triple buffer, the motor temperature estimating unit 115B is restricted so as not to refer to the triple buffer.

In order to limit the reference of the triple buffer by the motor temperature estimating unit 115B in this manner, the motor temperature estimating unit 115B must know whether the AD converter 112B is updating the triple buffer. Therefore, the AD converter 112B notifies the motor temperature estimating unit 115B of the updating flag as shared RAM data between the different cores A11 and A13 (716). The motor temperature estimation unit 115B refers to the updating flag, and when the updating flag is ON, the triple buffer does not refer to the data, so that the three-phase current value Iu using the triple buffer, It is possible to guarantee the simultaneity of Iv and Iw.

FIG. 15 is a timing chart showing an example of the relationship between update and reference when the three buffers of FIG. 14 are used.
15, the AD converter 112B of FIG. 14 executes the update 901 of the 16-bit data Iu of the three-phase current values Iu, Iv, and Iw for which the simultaneity should be guaranteed at time t41, and the 16-bit data Iv. 902 is executed at time t42, and update 903 of 16-bit data Iw is executed at time t43.

Next, the AD converter 112B determines a buffer to be stored among the triple buffers, and stores 904 of the 48-bit data Iu, Iv, and Iw for which the updates 901 to 903 have been executed at time t44.

Next, the motor temperature estimation unit 115B sets a buffer in which the latest data Iu, Iv, and Iw are stored among the triple buffers as a reference destination, executes reference 908 of the data Iu at time t45, and refers to the data Iv. 909 is executed at time t46, and reference 910 of the data Iw is executed at time t47.

At this time, after updating the three data Iu, Iv, and Iw, the three data Iu, Iv, and Iw are stored in the buffer. Therefore, the motor temperature estimation unit 115B refers to the three data Iu, Iv, and Iw stored in the buffer to determine the reference value 905 of the data Iu, the reference value 906 of the data Iv, and the reference value 907 of the data Iw. Both can be updated values, and the simultaneity of the three-phase current values Iu, Iv, and Iw referred to by the motor temperature estimation unit 115B can be guaranteed.

FIG. 16 is a flowchart showing a method of updating the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 14 are used.
In FIG. 16, the AD converter 112B of FIG. 14 turns on the updating flag (S51).

Next, the AD converter 112B uses a buffer set by the motor temperature estimation unit 115B as a reference destination and a buffer other than the buffer in which the latest data of the three-phase current values Iu, Iv, and Iw are stored. The storage destinations of Iu, Iv, and Iw are determined (S52).

Next, the AD converter 112B stores the three-phase current values Iu, Iv, Iw in the buffer determined as the storage destination of the three-phase current values Iu, Iv, Iw (S53).

Next, the AD converter 112B updates the storage destination of the latest data of the three-phase current values Iu, Iv, and Iw (S54), and turns off the updating flag (S55).

FIG. 17 is a flowchart showing a method of referring to the three-phase current values Iu, Iv, Iw when the three buffers of FIG. 14 are used.
In FIG. 17, the motor temperature estimation unit 115B of FIG. 14 determines the updating flag set by the AD converter 112B (S61), and ends the processing if the updating flag is ON.

On the other hand, when the updating flag is OFF, the motor temperature estimation unit 115B sets the buffer storing the latest data of the three-phase current values Iu, Iv, and Iw set by the AD converter 112B as the reference destination (S62). ..

Next, the motor temperature estimation unit 115B acquires the latest data of the three-phase current values Iu, Iv, Iw from the reference buffer (S63).

FIG. 18 is a flowchart showing a method of selectively using the method of guaranteeing the simultaneity of a plurality of data.
As shown in FIGS. 6 and 7, in the process of collectively referring to a plurality of data in one data, there is no determination process for determining the branch destination, but in the process using the triple buffer, the process shown in FIGS. 12 and 17 is performed. As described above, there is a determination process for determining the branch destination on the update side or the reference side. Therefore, the process of including a plurality of data in one data is more effective in suppressing the increase of the processing load than the process using the triple buffer.

Therefore, as shown in FIG. 18, when the total data size of a plurality of data for which the simultaneity is to be guaranteed is equal to or smaller than the data size that the microcomputer can handle at one time (YES in S71), the plurality of data are included in one data. The simultaneity of data is assured by applying the processing (S72). For example, when the plurality of data for which the simultaneity is to be guaranteed are the current command values Id* and Iq*, the processing of FIGS. 5 and 6 can be applied.

On the other hand, if the total data size of the plurality of data for which the simultaneity is to be guaranteed is larger than the data size that the microcomputer can handle at one time (NO in S71), the plurality of data for which the simultaneity should be guaranteed cannot be included in one data. , Guarantee the simultaneity of data by applying the process using triple buffer.

In the process using the triple buffer, if the control cycle on the update side is faster than the control cycle on the reference side (YES in S73), the process using the triple buffer that restricts the process on the update side is applied (S74). For example, when the plurality of data for which the simultaneity is to be guaranteed are the three-phase current values Iu, Iv, Iw, the processing of FIGS. 12 and 13 can be applied.

On the other hand, when the control cycle on the reference side is faster than the control cycle on the update side (NO in S73), the processing using the triple buffer that restricts the processing on the reference side is applied (S75). For example, when the plurality of data for which the simultaneity is to be guaranteed are the three-phase current values Iu, Iv, Iw, the processing of FIGS. 16 and 17 can be applied.

In the above embodiment, the motor control using the two cores has been described, but the invention can be applied to guaranteeing the simultaneity of the data group between the tasks of the same core and different control cycles. The present invention can be applied to a multi-core microcomputer having two or more cores as long as it guarantees data simultaneity between the two cores.

101... Motor, 102... Inverter circuit, 103... Current detection part, 104... Current control part, 105... Current command part, 106... Three-phase voltage conversion part, 107... Rotation position detection part, 108... Motor current control part, 109 … Microcomputer

Claims (10)

An electronic control device comprising a microcomputer,
An electronic control device that includes a plurality of data referred to by the same task in the microcomputer into one data that can be handled by the microcomputer at one time. The microcomputer, when executing the first task and the second task,
The first task updates the plurality of data at different timings,
The electronic control device according to claim 1, wherein the second task acquires a plurality of data updated by the first task from one data including a plurality of data updated by the first task. The plurality of data referred to by the same task in the microcomputer is a plurality of data for which simultaneity should be guaranteed in the processing of the microcomputer,
The electronic control device according to claim 1, wherein a total of data sizes of a plurality of data whose simultaneity is to be guaranteed in the processing of the microcomputer is equal to or smaller than a data size which can be handled by the microcomputer at one time. The microcomputer includes a first core and a second core,
When the first core is an update side of a plurality of data for which the concurrency is to be guaranteed and the second core is a reference side of a plurality of data for which the concurrency is to be guaranteed,
The first core includes a plurality of data for which the concurrency should be guaranteed in one data,
The electronic control device according to claim 3, wherein the second core acquires the plurality of pieces of data for which the simultaneity is to be guaranteed from one piece of data including the plurality of pieces of data for which the simultaneity is to be guaranteed. The electronic control device according to claim 4, wherein the plurality of data for which the simultaneity is to be guaranteed is a three-phase current value used for motor control or a current command value of dq coordinates. The first core includes a current command unit that updates the current command value,
The second core includes a current control unit that refers to the current command value updated by the current command unit,
The current command unit includes the current command value of the dq coordinates in one data,
The electronic control device according to claim 5, wherein the current control unit acquires the current command value of the dq coordinates from one data included in the current command unit. An electronic control device comprising three buffers capable of respectively storing a plurality of data referred to by the same task in a microcomputer,
The plurality of data referred to in the same task in the microcomputer is a plurality of data for which simultaneity should be guaranteed,
Each of the update side and the reference side of the plurality of data for which the simultaneity should be guaranteed can asynchronously access any buffer arbitrarily selected from the three buffers,
When the control cycle on the update side of a plurality of data for which the simultaneity should be guaranteed is faster than the control cycle on the reference side, and when the reference side refers to any one of the three buffers arbitrarily selected, An electronic control unit in which the update side does not update any of the three buffers. The microcomputer includes a first core that is the reference side and a second core that is the update side,
8. The electronic control device according to claim 7, wherein the sum of the data sizes of a plurality of data whose simultaneity should be guaranteed in the processing of the microcomputer is larger than the data size that can be handled by the microcomputer at one time. An electronic control device comprising three buffers capable of respectively storing a plurality of data referred to by the same task in a microcomputer,
The plurality of data referred to in the same task in the microcomputer is a plurality of data for which simultaneity should be guaranteed,
Each of the update side and the reference side of the plurality of data for which the simultaneity should be guaranteed can asynchronously access any buffer arbitrarily selected from the three buffers.
When the control cycle of the reference side of the plurality of data for which the simultaneity is to be guaranteed is faster than the control cycle of the update side, when the update side is updating any buffer arbitrarily selected from the three buffers, The reference side is an electronic control device that does not reference any of the three buffers. The microcomputer includes a first core that is the reference side and a second core that is the update side,
10. The electronic control device according to claim 9, wherein the sum of the data sizes of a plurality of data for which the simultaneity should be guaranteed in the processing of the microcomputer is larger than the data size that can be handled by the microcomputer at one time.

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