JPH05143779A - Pattern recognizing device - Google Patents

Abstract

PURPOSE:To provide the pattern recognizing device capable of high-speed recognition processing and reducing the memory consumption amount. CONSTITUTION:The X and Y coordinates of input and reference patterns are divided into high-order and low-order bits to be stored in a recognition memory 1, and the input pattern is stored in a register 7 by separating the X and Y coordinates through an internal register 6. At the same time, the reference pattern is stored in a register 8 separating the X and Y coordinates. The distance between patterns is operated the X coordinates of the registers 7 and 8 are operated by an X coordinate computing element 9 and the Y coordinates by a Y coordinate computing element 10. An adder 11 adding the arithmetic result and a parallel sorter 12 rearranging the addition result in the order of the shorter pattern distance as well as the identification code of the reference pattern corresponding to the distance between pattern during the reference pattern is changed in a specified range and the operation and addition is repeated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a pattern recognition device,
In particular, the present invention relates to a pattern recognition device having a high recognition rate and a short recognition time.

[0002]

2. Description of the Related Art A pointing device such as a digitizer as an input means having an electronic pen, a computer for recognizing an input pattern (character or graphic pattern) handwritten by the electronic pen, and a recognition processing result. An input / output device including a display for displaying a certain suitability standard pattern has been developed and put into practical use. In recent years, in such an input / output device, an input / output device in which a digitizer and a liquid crystal display are superposed on the same surface has attracted attention. The input pattern recognition processing performed by the computer consists of calculating the distance between the representative points in all strokes of the input pattern and the standard pattern, and selecting the standard pattern that minimizes the total sum of the distances.

Conventionally, when performing the above-described pattern recognition processing, the input pattern and the standard pattern were stored in the memory as follows. That is, to store the x and y coordinate data forming the pattern in, for example, a 32-bit width memory, the x coordinate is stored in the upper bit of the 32-bit data and the y coordinate is stored in the lower bit. As shown in FIG. 10, x-coordinates and y-coordinates are separately stored in 32-bit data, and as shown in FIG. 11, x-coordinates and y-coordinates are read out separately, and inter-pattern distance calculation is performed.

[0004]

According to the method of the invention, the memory can be saved and the number of memory read cycles of the CPU can be reduced. However, the read data is separated into an x coordinate and ay coordinate. This requires additional work, which increases the total processing time. According to this method, the time required for the separation work is eliminated, but since there is more invalid data than valid data stored in the memory, the memory is wasted. Moreover, the memory call cycle is doubled as compared with the method, and the processing time is long.

As described above, the biggest problem of the conventional pattern recognition is that the recognition rate is directly proportional to the recognition time. That is, in order to improve the recognition rate, an enormous amount of inter-pattern calculation is required, which results in a slower recognition speed and a deterioration in system responsiveness. On the other hand, when real-time performance is required, practical responsiveness cannot be obtained unless the recognition rate is sacrificed to reduce the recognition time.

Therefore, an object of the present invention is to enable high-speed recognition processing by eliminating the wasted time that has occurred in the software processing by the sequential CPU used in conventional pattern recognition. Another object of the present invention is to provide a pattern recognition device that can reduce recognition time and memory consumption by optimally storing standard patterns. That is, in the present invention, x
By storing the 16-bit coordinate data for each of the coordinates and the y-coordinate in 32-bit data as shown in FIGS. 2 to 4, which will be described later, both reduction of the number of read cycles and effective use of memory are realized. .. This uses a 32-bit read register for memory data of the recognition circuit.
This is because each bit can be used separately for the x and y coordinates.

[0007]

The above-mentioned problems are solved by a hardware circuit provided with a parallel arithmetic unit and a high-speed sorter, that is, a recognition circuit, and a memory in which input patterns and standard patterns are efficiently stored, that is, a recognition memory. It is solved by combining and. That is, the present invention is a pattern recognition device for recognizing a character or graphic pattern handwritten by an input means, wherein the x-coordinate and the y-coordinate of the input pattern and the standard pattern respectively have upper bits and lower bits. The recognition circuit includes a recognition memory and a recognition circuit that are stored separately from each other, and the recognition circuit includes an internal register that stores the input pattern stored in the recognition memory, and an x-coordinate of the input pattern stored in the internal register. And a y-coordinate of the standard pattern stored in the recognition memory, and a first register that stores the y-coordinate separately in the upper bit and the lower bit, respectively.
Between a second register that stores coordinates separately in upper bits and lower bits, and an x-coordinate pattern between the input pattern stored in the first register and the standard pattern stored in the second register An x-coordinate calculator for calculating a distance, and a y-coordinate calculator for calculating a y-coordinate pattern distance between an input pattern stored in the first register and a standard pattern stored in the second register. And an adder for cumulatively adding the calculation results of the x-coordinate arithmetic unit and the y-coordinate arithmetic unit, and identification of the standard pattern corresponding to the inter-pattern distance in ascending order of the inter-pattern distance of the addition result by the adder. A parallel sorter for rearranging along with a code, the first and second registers, the x
And a y-coordinate computing unit, the adder, and a control circuit for controlling the parallel sorter.

A block diagram of the recognition circuit is shown in FIG. 1, a method of storing an input pattern in a recognition memory is shown in FIG. 2, and a method of storing a standard pattern in a recognition memory is shown in FIGS. 3 and 4. FIG. 3 shows a normal storage method, and FIG. 4 shows a storage method when weighting is performed.

A block diagram of the basic configuration of the present invention is shown in FIG. In FIG. 5, the recognition memory 1 is directly connected to the recognition circuit 2 and is not directly connected to the bus 4 of the CPU 3 which controls the entire system. This is CPU3 and recognition circuit 2
This is to eliminate the dead time due to the competition of the buses 4 when and operate in parallel. When the CPU 3 accesses the recognition memory 1, the recognition memory 1 called a window 5 is used as a CP.
This is done via a circuit that is indirectly accessed from U3 bus 4.

A pattern recognition method according to the present invention will be described below with reference to the drawings. (1) A standard pattern is stored in the recognition memory 1 in advance according to the method shown in FIG. 3 or 4. At this time, in the standard pattern, a code specifying the standard pattern is stored in addition to the array of coordinate values. As a result of pattern recognition, this code is treated as a code corresponding to the standard pattern. (2) From the pointing device such as digitizer to CPU3
The coordinate string of the input character pattern obtained via
It is stored in the recognition memory 1 according to the method shown in FIG. (3) The CPU 3 writes the following data in the input register of the recognition circuit 2. How to interpret the input pattern. (The input pattern is regarded as a set of line segments, and the number of line segments and the number of divisions obtained by equally dividing each line segment) A calculation method for calculating the distance between the input pattern and the standard pattern. (The calculation method will be described later) Storage addresses on the recognition memory 1 for the input pattern and the standard pattern. In the case of a standard character pattern, the starting and ending addresses can be given. This is because the distance of an extra pattern is not calculated when the number of strokes and the character type of a character can be specified in the case of character recognition and the figure type in the case of graphic recognition. (4) The CPU 3 sends a recognition processing start signal to the recognition circuit 2.

(5) The recognition circuit 2 stores the input pattern stored in the recognition memory 1 in the internal register 6 provided in the recognition memory 1. (6) The input pattern is read from the internal register 6 to the first register 7 of the recognition circuit 2 and the standard pattern from the recognition memory 1 to the second register 7 of the recognition circuit 2 at the same time. (7) The x-coordinate calculator 9 of the recognition circuit 2 calculates the pattern distance of the x-coordinate between the input pattern and the standard pattern according to the specified calculation formula, and the y-coordinate calculator of the recognition circuit 2 is calculated. Reference numeral 10 calculates the y-coordinate pattern distance between the input pattern and the standard pattern according to the designated calculation formula. These operations are performed simultaneously. (8) The adder 11 of the recognition circuit 2 cumulatively adds the calculation results of the inter-pattern distances of the x coordinate and the y coordinate.

(9) The steps (5) to (8) are repeated until the input pattern is exhausted. (10) The addition result of the adder 11 is sent to the parallel sorter 12 of the recognition circuit 2 described later. The parallel sorter 12 can store up to 10 candidate patterns (10 patterns with the smallest inter-pattern distance). Parallel sorter 12
Compares 10 candidate patterns with the addition result, and makes a 10: 1 comparison to determine whether or not to include them in the candidates. If the addition result is smaller than any of the 10 candidate patterns, the contents of the register storing the candidate pattern larger than the addition result are shifted, and then the addition result is stored in a predetermined location. That is, the patterns are sorted in ascending order of inter-pattern distance.

(11) The steps (5) to (8) are repeated until the standard patterns within the designated range are exhausted. (12) Return the information stored in the parallel sorter 12 to the recognition memory 1. The data structure of the sorter can store not only the distance between patterns to be sorted but also a code representing a standard pattern, and the code of the standard pattern closest to the finally required input pattern is obtained.

Next, the formula for calculating the distance between the input pattern and the standard pattern will be described. There are two distance calculation formulas, one of which is the absolute value distance calculation formula expressed by the following formula (1). d _jk ^p = Σ _{i = 1} ^N ｜ x _i ^k _−p x _i ^j ｜ + Σ _{i = 1} ^N ｜ y _i ^k _−p y _i ^j ｜ --- (1) where d _jk ^{p is} the jth standard stroke and the stroke distance of the k-th input strokes, x _i ^k: x-coordinate value of the i-th stroke representative point of the k-th input stroke, _p x _i ^j: i of the j-th standard stroke X-coordinate value of the th stroke representative point, y _i ^k : y-coordinate value of the i-th stroke representative point of the k-th input stroke, _p y _i ^j : i-th stroke representative point of the j-th standard stroke Y coordinate value, N: number of stroke representative points.

The second is a dispersion distance calculation formula represented by the following formula (2). d _jk ^p = Σ _{i = 1} ^N σ _xi ^j (x _i ^k − _p x _i ^j ) ² + Σ _{i = 1} ^N σ _yi ^j (y _i ^k − _p y _i ^j ) ² --- (2) , D _jk ^p : distance between strokes of the j-th standard stroke and the k-th input stroke, x _i ^k : x-coordinate value of the i-th stroke representative point of the k-th input stroke, _p x _i ^j : X-coordinate value of the i-th stroke representative point of the j-th standard stroke, y _i ^k : y-coordinate value of the i-th stroke representative point of the k-th input stroke, _p y _i ^j : the j-th standard Y coordinate value of i-th stroke representative point of stroke, σ _xi ^j : weighting coefficient of x-coordinate value of i-th stroke representative point of j-th input stroke, σ _yi ^j : i-th stroke of j-th input stroke The y-coordinate weighting coefficient of the th stroke representative point, N: the number of stroke representative points.

The input pattern storage memory will be further described. The distance between patterns is calculated by brute force calculation of the input pattern and each category of the standard pattern. Since the input pattern is referred to many times during the calculation, the access time of the memory that stores it greatly affects the recognition time. The standard pattern is DRAM because of its size.
However, it is not a good idea to store the input pattern in the same memory as the standard pattern because of its nature. Therefore, the recognition circuit 2 is provided with an internal register composed of a high-speed SRAM, and an input pattern is input therein, whereby the recognition time can be greatly shortened.

The parallel calculation of the recognition circuit 2 will be further described. Both the x and y coordinates stored in the recognition memory 1 as 32-bit 1-word data are read in one read cycle. Read data is upper and lower
16-bit separated 32-bit first register 7, second
It is stored in the register 8 at once. The coordinate data stored in the first and second registers 7 and 8 are sent to the arithmetic units 9 and 10 separately for the x and y coordinates, and the x and y coordinates are calculated simultaneously. Thus, in order to execute the operations at the same time, two subtracters and two absolute value units are provided in the case of the above arithmetic expression (1), and two subtracters are provided in the case of the above arithmetic expression (2). And two multipliers are provided.

The parallel sorter 12 will be further described. In the pattern recognition, there is a method of arranging the inter-pattern distances in ascending order and using them as solution candidates in addition to the standard pattern having the minimum inter-pattern distance with respect to the input pattern as one solution. The latter method has a parallel sorter that rearranges the distances between patterns in ascending order and holds 10 candidates. A block diagram of the parallel sorter 12 is shown in FIG.
The parallel sorter 12 consists of 10 barrel shifters 13 and 10 comparators.
14 and shift control circuit 15. A distance between patterns is stored as a key of the barrel shifter 13, and a code corresponding to the pattern is stored as a satellite of the barrel shifter 13.

Sorting is performed according to the following method. The ten barrel shifters 13 in which some numerical values are stored in advance as keys and the inter-pattern distances as the distance calculation result are simultaneously compared by the ten comparators 14. As a result, the comparator 14 paired with the barrel shifter 13 having a key larger than the inter-pattern distance sends a signal to the shift control circuit 15. The shift control circuit 15, in response to the signal, the barrel shifter 13 corresponding to the comparator 14 which has issued the signal,
And, a shift signal is sent to all barrel shifters 13 that store a large inter-pattern distance as a key. As a result, the barrel shifter 13 that has stored a value larger than the given pattern-to-pattern distance sends all the stored values (including satellites) to the barrel shifter 13 in the next stage. Sorting is completed by storing the inter-pattern distance and the code corresponding to the pattern in the barrel shifter 13 corresponding to the comparator 14 that finally issued the signal.

Normalizing the standard pattern, -128 to 127
If the rounding is performed within a range that can be expressed by 8 bits and the weighting coefficient can also be expressed within 8 bits, it is possible to further save memory and speed up the distance calculation. FIG. 7 shows a method of storing the standard pattern memory in this case. FIG. 8 shows a partial block diagram of the recognition circuit 2 that calculates the data stored in this state. By using such a recognition circuit, the standard pattern and the weight coefficient can be read at once, and the calculation of the x and y coordinates and the multiplication of the weight coefficient can be performed in a shorter time.

[0021]

EXAMPLES Next, the pattern recognition apparatus of the present invention will be further described with reference to examples. FIG. 9 is a block diagram showing an embodiment of the pattern recognition device of the present invention. Digitizer 16
The coordinate sequence of the handwritten characters input from and the on / off information from the digitizer 16 are sent to the CPU 3. The CPU 3 separates the received information about the handwritten character from the on / off information from the digitizer 16 into character strokes. The separated strokes are converted into a coordinate sequence that is further time-sequentially divided into N equal parts. In addition, all transformed coordinate sequences are -128 to 12
Normalized to fit in the 7 range.

The coordinate sequence thus normalized is written in the recognition memory 1 as an input pattern, and the stroke decomposition information and the stroke number are sent to the recognition circuit 2. At the same time, the address on the recognition memory 1 in which the standard pattern corresponding to the stroke as the auxiliary information is stored is also sent. When the start signal is sent to the CPU3, the recognition circuit 2 executes a predetermined operation, and the codes corresponding to the maximum 10 candidate characters which are the pattern recognition result are CP-coded.
Return to U3. The code returned here is the JIS column corresponding to the pattern, that is, the character, along with the coordinate sequence of the standard pattern.
Is the character code of. When the CPU3 knows that the processing by the recognition circuit 2 is completed, it reads all the returned JIS character codes. The font corresponding to the pattern having the smallest distance between patterns is displayed on the display 17 such as a liquid crystal display.

If the displayed character matches the input character, the operator who inputs the handwritten character proceeds to the next step. If an incorrect character is displayed, the CPU3 is notified of that fact. The CPU 3 causes the display unit 17 to display the remaining candidate characters. The operator selects a character that matches the input character from among them.

The recognition speed by the pattern recognition device of the present invention was compared with the recognition speed by the conventional pattern recognition device having software having the same function as the recognition circuit in the pattern recognition device of the present invention. The CPU used in the conventional pattern recognition device is a 20MHz version MC
It was 68030. The comparison results are most apparent in the 12 stroke characters that include the most character patterns as standard patterns, and 250 patterns are registered as standard patterns. As a result, the conventional pattern recognition apparatus using software required 2.3 seconds to recognize one character, while the pattern recognition apparatus of the present invention required 0.
It was 083 seconds, and we were able to achieve a speedup of 27 times or more.

[0025]

As described above, according to the present invention, the recognition circuit having the arithmetic units for x and y coordinates and the parallel sorter is combined with the recognition memory in which the input pattern and the standard pattern are efficiently stored. Therefore, the sequential CP used for the conventional pattern recognition
Since the unnecessary time generated in the software processing by U can be eliminated, the recognition processing can be speeded up and the standard pattern can be optimally stored, so that the recognition time and the consumption of memory can be reduced. Such a useful effect is brought about.

[Brief description of drawings]

FIG. 1 is a block diagram showing a recognition circuit in a pattern recognition device of the present invention.

FIG. 2 is a diagram showing a method of storing an input pattern in a recognition memory in the pattern recognition device of the present invention.

FIG. 3 is a diagram showing a method of storing a standard pattern in a recognition memory in the pattern recognition device of the present invention.

FIG. 4 is a diagram showing a method of storing a standard pattern using a weight coefficient in a recognition memory in the pattern recognition device of the present invention.

FIG. 5 is a block diagram showing a basic configuration of a pattern recognition device of the present invention.

FIG. 6 is a block diagram showing a parallel sorter in the pattern recognition apparatus of the present invention.

FIG. 7 is a diagram showing another method of storing a standard pattern using a weighting coefficient in a recognition memory in the pattern recognition device of the present invention.

FIG. 8 is a partial block diagram showing another recognition circuit in the pattern recognition device of the present invention.

FIG. 9 is a block diagram showing an embodiment of the pattern recognition device of the present invention.

FIG. 10 is a diagram showing a conventional method of storing an input pattern in a memory.

FIG. 11 is a diagram showing a conventional calculation sequence of the distance between patterns.

[Explanation of symbols]

 1: recognition memory, 2: recognition circuit, 3: CPU, 4: bus, 5: window, 6: internal register, 7: first register, 8: second register, 9: x coordinate calculator, 10: y Coordinate calculator, 11: Adder, 12: Parallel sorter, 13: Barrel shifter, 14: Comparator, 15: Shift control circuit, 16: Digitizer, 17: Display.

Claims (1)

[Claims] 1. A pattern recognition device for recognizing a character or graphic pattern handwritten by an input means, wherein the x-coordinate and the y-coordinate of an input pattern and a standard pattern respectively correspond to an upper bit and a lower bit. The recognition circuit includes a recognition memory and a recognition circuit that are separately stored, and the recognition circuit includes an internal register that stores the input pattern stored in the recognition memory, an x coordinate of the input pattern stored in the internal register, and A first register for separately storing the y-coordinate into upper bits and lower bits, and an x-coordinate and a y-coordinate of the standard pattern stored in the recognition memory are separately stored into upper bits and lower bits. A second register, an input pattern stored in the first register, and a standard stored in the second register An x-coordinate calculator for calculating the inter-pattern distance of the x-coordinate with the pattern, and a y-coordinate pattern between the input pattern stored in the first register and the standard pattern stored in the second register. An y-coordinate arithmetic unit for calculating an inter-distance, an adder for accumulatively adding arithmetic results by the x-coordinate arithmetic unit and the y-coordinate arithmetic unit, and an addition result by the adder in ascending order of the inter-pattern distance, A parallel sorter for rearranging together with an identification code of a standard pattern corresponding to a distance between patterns, a control circuit for controlling the first and second registers, the arithmetic unit for the x and y coordinates, the adder, and the parallel sorter A pattern recognition device comprising: