JP2017130140A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for suppressing data having different update timings by a first processor core from being referenced by a second processor core by reducing processing loads as much as possible.SOLUTION: A data processor 2 comprises one first processor core 10, one or more second processor cores 2, a memory 30 for updating and a memory 42 for reference. An updating task 12 that the first processor core 10 executes is configured to write data in the memory 30 for updating. The memory 42 for reference is provided in each second processor core 20 so as to be referenced by a reference task 24 that the second processor core 20 executes. A copy task 22 that the second processor core 20 executes with higher priority than the reference task 24 is configured to write the data acquired from the memory 30 for updating in the memory 42 for reference.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a technique in which different processor cores perform update of data and reference of updated data in a plurality of processor cores.

A technique is known in which, in a plurality of processor cores, different processor cores update data and reference updated data.
For example, in the technique described in Patent Document 1, when one CPU core among two CPU cores as a plurality of processor cores generates and updates data by a generation task, the other CPU core is interrupted. One CPU core sets the requested flag.

  When the interrupt request flag is set, an interrupt to the other CPU core is activated, and the fetch task of the other CPU core is activated. The fetching task executed by the other CPU core sets its prohibition flag in the interrupt prohibition register, thereby acquiring the data updated by the generation task of one CPU core and writing it to another memory. Disable other interrupt processing for.

  While the capture task of another CPU core acquires the data updated by the generation task of one CPU core and writes it to another memory, interrupt processing to the other CPU core is prohibited, so the capture task writes The data inside is not referenced by other tasks.

  Since the capture task resets the prohibition flag set in the interrupt prohibition register when writing is completed, CPU core tasks other than the capture task can refer to the data for which the capture task has finished writing. As a result, the technique disclosed in Patent Document 1 tries to prevent other tasks of other CPU cores from referring to data having different write timings by the capture task.

JP 2009-245209 A

  The capture task of another CPU core needs to set the prohibit flag of the interrupt disable register to prohibit interrupt processing to the CPU core during the capture task processing, and reset the prohibit flag when the capture task processing ends. As a result, the processing load increases.

  An object of one aspect of the present disclosure is to provide a technique that reduces processing load as much as possible and suppresses a reference task of a second processor core from referring to data having different update timings by a first processor core.

  One aspect of the present disclosure includes one first processor core (10), one or more second processor cores (20, 50, 70), an update memory (30), and a reference memory (42, 62). , 80).

The update task (12, S400 to S404) executed by the first processor core writes data in the update memory.
A reference memory is provided for each second processor core. The reference tasks (24, 54, 74, 76, S430 to S434, S440 to S444) executed by the second processor core refer to the reference memory, and the second processor core executes and has a higher priority than the reference task. The high copy task (22, 52, 72, S410 to S420, S450 to S460) writes the data acquired from the update memory to the reference memory.

  According to this configuration, since the update memory and the reference memory are separate memories, even if the update task updates the data in the update memory while the reference task is referring to the data in the reference memory, the update memory and the reference memory are updated. The task does not update the reference memory data.

  Further, since the priority of the copy task is set higher than that of the reference task in the second processor core, the data acquired from the update memory by the copy task having a higher priority than the reference task is written to the reference memory. The reference task is not executed while

Therefore, the data in the reference memory referred to by the reference task can be changed to the data updated by the update task at the same timing and written in the reference memory by the copy task.
In addition, since the priority for executing the copy task and the reference task is set in advance, the execution of the reference task is prohibited during the execution of the copy task, and the execution of the reference task is permitted when the execution of the copy task is completed. There is no need to do. Thereby, it is possible to adjust the execution timing of the reference task while reducing the processing load as much as possible.

In this way, it is possible to reduce the processing load as much as possible, and to prevent the reference task of the second processor core from referring to data having different update timings by the first processor core.
Note that the reference numerals in parentheses described in this column and in the claims indicate the correspondence with the specific means described in the embodiment described later as one aspect, and the technical scope of the present invention. It is not limited.

The block diagram which shows the data processor by 1st Embodiment. The flowchart which shows the update process which an update task performs. 10 is a flowchart showing copy processing executed by a copy task. The time chart which shows the copy process which a copy task performs. The flowchart which shows the reference process which a reference task performs. The time chart which shows an update process, a copy process, and a reference process. The block diagram which shows the data processor by 2nd Embodiment. The block diagram which shows the data processor by 3rd Embodiment. The flowchart which shows the reference process which a reference task performs. 10 is a flowchart showing copy processing executed by a copy task. The block diagram which shows the data processor by 4th Embodiment.

Embodiments to which the present invention is applied will be described below with reference to the drawings.
[1. First Embodiment]
[1-1. Constitution]
The data processing apparatus 2 of the first embodiment shown in FIG. 1 includes two processor cores 10 and 20, an update RAM 30, an update start counter 32, an update end counter 34, a temporary storage RAM 40, and a reference A RAM 42, a reference flag 44, a ROM and a flash memory (not shown), and the like are provided. The data processing device 2 is a multi-core processor including two cores 10 and 20. Hereinafter, the processor core is also simply referred to as “core”.

  Each function of the data processing device 2 is realized by the cores 10 and 20 executing programs stored in a non-transitional physical recording medium such as a ROM or a flash memory. By executing this program, a method corresponding to the program is executed. The method of realizing each function of the data processing device 2 is not limited to software, and hardware in which some or all of the elements are combined with a logic circuit, an analog circuit, or the like may be used.

  The core 10 corresponding to the first processor core executes the update task 12 to update the data in the update RAM 30. The update task 12 increments the value of the update start counter 32 by 1 when the update of the data in the update RAM 30 is started, and increments the value of the update end counter 34 by 1 when the update of the data in the update RAM 30 is finished. . The initial values of the update start counter 32 and the update end counter 34 are set to the same value, for example, 0.

  That is, the update start counter 32 and the update end counter 34 have the same value when the update task 12 is not updating the data in the update RAM 30, and are different values while the update task 12 is updating the data in the update RAM 30. It is.

  Instead of incrementing the update start counter 32 and the update end counter 34 by 1, the update task 12 may decrement by 1. That is, the value of the update start counter 32 and the value of the update end counter 34 change in the same direction of increase or decrease. Further, the increase / decrease amount of the update start counter 32 and the update end counter 34 is not limited to 1 as long as they are the same.

The core 10 executes the update task 12 regardless of whether the copy task 22 and the reference task 24 executed by the core 20 are being executed.
The core 20 corresponding to the second processor core executes a copy task 22 and a reference task 24. The priority for executing the copy task 22 is higher than the priority for executing the reference task 24. When the core 10 is not executing the update task, the copy task 22 acquires the data in the update RAM 30 and temporarily stores it in the temporary storage RAM 40.

  When the update task 12 does not update the data in the update RAM 30 while acquiring the data in the update RAM 30 and storing it in the temporary storage RAM 40, the copy task 22 stores the update RAM 30 stored in the temporary storage RAM 40. Data is written into the reference RAM 42.

  The reference task 24 refers to data in the reference RAM 42. The reference task 24 sets the value of the in-reference flag 44 while referring to the data in the reference RAM 42, for example, to 1 as a value indicating the ON state being referred to. When the reference task 24 finishes referring to the data in the reference RAM 42, the reference task 24 sets the value of the reference flag 44 to, for example, 0 as a value indicating an off state that is not being referred to.

  When the reference flag 44 is set to 1, the copy task 22 having a higher priority than the reference task 24 does not execute the copy process of acquiring the data in the update RAM 30 and writing it in the reference RAM 42.

[1-2. processing]
(1) Update Process The update process shown in FIG. 2 is executed by the update task 12 when the update timing for updating the data in the update RAM 30 comes. In S400 of FIG. 2, the update task 12 increments the update start counter 32 by one. In S402, the update task 12 updates the data in the update RAM 30. When the update of the data in the update RAM 30 is completed, the update task 12 increments the value of the update end counter 34 by 1 in S404.

(2) Copy Process The copy process shown in FIG. 3 is executed by the copy task 22 when it is time to acquire data in the update RAM 30 and write it to the reference RAM 42. In S410 of FIG. 3, the copy task 22 determines whether or not the reference flag 44 is on.

  If the determination in S410 is Yes and the reference flag 44 is on, it indicates that the reference task 24 is referring to the reference RAM 42. In this case, the copy task 22 ends this processing in order to prevent the copy task 22 from acquiring the data in the update RAM 30 and writing it to the reference RAM 42 while the reference task 24 is referring to the reference RAM 42.

  If the determination in S410 is No and the reference task 24 is not referring to the reference RAM 42, the copy task 22 determines in S412 whether or not the value of the update start counter 32 matches the value of the update end counter 34. Determine.

  For example, as shown in FIG. 4, when the value of the update start counter 32 and the value of the update end counter 34 are “4” and the determination in S 412 is Yes, the copy task 22 is updated in the update RAM 30. Judge that the data is not being updated. In this case, the copy task 22 shifts the process to S414.

  In FIG. 4, the copy process executed at four types of execution timing is not executed at each timing, but is executed at any one of the four types of execution timing.

  When the value of the update start counter 32 is “5” and the value of the update end counter 34 is “4”, so that the determination in S 412 is No, the copy task 22 has the update task 12 store the data in the update RAM 30. Judge that update is in progress.

  In this case, the copy task 22 waits until the value of the update start counter 32 and the value of the update end counter 34 become “5” and become equal. When the value of the update start counter 32 and the value of the update end counter 34 become “5”, it is determined that the update task 12 has finished updating the data in the update RAM 30, and the copy task 22 proceeds to S414. To do.

In S <b> 414, the copy task 22 saves the value of the update start counter 32 in a temporary storage area such as the temporary storage RAM 40.
In S 416, the copy task 22 stores the data acquired from the update RAM 30 in the temporary storage RAM 40. When the storage of the data in the update RAM 30 to the temporary storage RAM 40 is completed, in S418, the copy task 22 determines the value of the update start counter 32 saved in the temporary storage area in S414 and the current value of the update start counter 32. It is determined whether or not.

  If the determination in S418 is No and the value of the update start counter 32 saved in the temporary storage area is different from the current value of the update start counter 32, the copy task 22 uses the data in the update RAM 30 for temporary storage. During the storage in the RAM 40, it is determined that the update task 12 of the core 10 has updated the data in the update RAM 30.

  In this case, the data in the update RAM 30 stored in the temporary storage RAM 40 by the copy task 22 may include data before and after the update by the update task 12. In this state, the data in the update RAM 30 stored in the temporary storage RAM 40 is mixed with data with different update timings, and data simultaneity cannot be ensured. Therefore, the copy task 22 shifts the process to S412 and restarts the copy process. Run.

  If the determination in S418 is Yes and the value of the update start counter 32 saved in the temporary storage area matches the current value of the update start counter 32, the copy task 22 updates the update stored in the temporary storage RAM 40. It is determined that the data synchronism of the RAM 30 is secured. Therefore, in S420, the copy task 22 writes the data of the update RAM 30 stored in the temporary storage RAM 40 into the reference RAM 42.

(3) Reference Process The reference process shown in FIG. 5 is executed when the reference task 24 refers to the reference RAM 42 and the copy task 22 having a higher priority than the reference task 24 is not being executed. In S430 of FIG. 5, the reference task 24 sets the reference flag 44 to ON. When the reference flag 44 is set to ON, the copy task 22 does not execute the copy process. In S432, the reference task 24 refers to the data in the reference RAM 42.

  Here, as shown in FIG. 6, the copy task 22 acquires the variables A, B, and C from the update RAM 30 and writes them in the variables a, b, and c of the reference RAM 42, and the reference task 24 has the following equation (1): The execution timing of each task will be described using the case where X is calculated from the above as an example. In FIG. 6, the value of X calculated from the equation (1) is rounded off.

X = (a + b + c) / 3 (1)
Initially, the variables A, B, and C of the update RAM 30 are set to 10, 15, and 45, respectively. By executing the copy task 22 at the timing (1) shown in FIG. 6, 10, 15, and 45 are written in the variables a, b, and c of the reference RAM 42, respectively. After the execution of the copy task 22, the reference task 24 refers to the variables a, b, and c in the reference RAM 42 at the timing (2), and calculates X = 23 from the equation (1).

  Even if the copy task 22 is executed at the timing of (3), the values of the variables a, B, and C in the update RAM 30 are not updated, so the values of the variables a, b, and c in the reference RAM 42 do not change.

  Even if the reference task 24 is executed at the timing of (4), the values of the variables a, b, and c in the reference RAM 42 have not changed, so X = 23 remains. Even if the update task 12 is executed at the timing (5) while the reference task 24 is being executed, and the values of the variables A, B, and C in the update RAM 30 are updated to 20, 30, and 29, the copy task 22 Is not executed, the values of the variables a, b, c in the reference RAM 42 do not change.

  The update task 12 is executed at the timing (5), and the copy task 22 is executed at the timing (6), whereby 20, 30, 29 are written in the variables a, b, c of the reference RAM 42.

  Even if the update task 12 is executed at the timing (7) and the reference task 24 is executed at the timing (8) while the update task 12 is being executed, the copy task 22 is not executed. The values of the variables a, b, and c remain 20, 30, and 29. Therefore, the reference task 24 calculates X = 26 from the equation (1).

  After the update task 12 is executed at the timing (7), the copy task 22 is executed at the timing (9), whereby 30, 22, and 8 are written in the variables a, b, and c of the reference RAM 42. .

  Even if the copy task 22 is executed at the timing of (10), since the update task 12 has not been executed before that, the values of the variables a, b, and c in the reference RAM 42 remain 30, 22, and 8. . At the timing of (11), the reference task 24 calculates X = 20 from Expression (1).

  Next, referring to the data in the reference RAM 42 in S432, the reference task 24 sets the reference flag 44 to OFF in S434. As a result, the copy task 22 can be executed.

[1-3. effect]
According to the first embodiment described above, the following effects can be obtained.
(1) The update RAM 30 for updating data by the update task 12 and the reference RAM 42 to which the reference task 24 refers are made different memories. Thereby, even if the update task 12 updates the data in the update RAM 30, the update task 12 does not update the data in the reference RAM 42. The reference task 24 is not executed while the copy task 22 having higher priority than the reference task 24 writes data from the update RAM 30 to the reference RAM 42.

  Therefore, even if the update task 12 and the reference task 24 are executed in duplicate, the reference task 24 can be prevented from referring to the data in the update RAM 30 having different update timings by the update task 12 from the reference RAM 42.

  (2) Since the priority of executing the copy task 22 and the reference task 24 is set in advance, the execution of the reference task 24 is prohibited during the execution of the copy task 22, and when the execution of the copy task 22 ends, the reference task It is not necessary to perform processing for permitting the execution of 24. Thereby, the processing load can be reduced as much as possible, and the execution timing of the reference task 24 can be adjusted.

  (3) If the update task 12 is updating the data in the update RAM 30 by comparing the value of the update start counter 32 with the value of the update end counter 34, the copy task 22 temporarily stores the data in the update RAM 30. The data is not stored in the storage RAM 40.

  Further, when it is determined that the update task 12 has updated the data while the copy task 22 is storing data in the temporary storage RAM 40 based on the change in the value of the update start counter 32, the copy task 22 determines the data in the temporary storage RAM 40. Are not written in the reference RAM 42.

  As described above, the copy task 22 writes the data with different update timings by the update task 12 to the reference RAM 42 while reducing the processing load as much as possible based on the values of the update start counter 32 and the update end counter 34. Can be suppressed.

(4) By setting the reference flag 44, the processing load can be reduced as much as possible, and execution of the copy task 22 can be prohibited while the reference task 24 is being executed.
(5) Refer to the copy task 22 by setting the value of the update start counter 32 and the value of the update end counter 34, the preset priority of the copy task 22 and the reference task 24, and the setting of the reference flag 44. The execution timing with the task 24 is adjusted.

  Compared with the case where adjustment is performed by interrupt processing, the processing load required for adjusting the execution timing of the copy task 22 and the reference task 24 can be reduced as much as possible. Furthermore, a processing unit for adjusting the execution timing of the copy task 22 and the reference task 24 is not necessary.

[2. Second Embodiment]
[2-1. Constitution]
The data processing device 4 according to the second embodiment shown in FIG. 7 further includes a core 50, a temporary storage RAM 60, a reference RAM 62, and a reference flag 64, as compared with the data processing device 2 according to the first embodiment. ing. That is, a reference flag 44 or 64 is provided for each reference task 24 or 54.

In the second embodiment, the same reference numerals as those in the first embodiment indicate the same configuration, and the preceding description will be referred to for details.
The core 50 corresponding to the second processor core executes the copy task 52 and the reference task 54 similarly to the core 20. The copy process executed by the copy task 52 is substantially the same as the copy process executed by the copy task 22. The reference process executed by the reference task 54 is substantially the same as the reference process executed by the reference task 24.

The functions of the temporary storage RAM 40 and the temporary storage RAM 60, the reference RAM 42 and the reference RAM 62, the reference flag 44, and the reference flag 64 are substantially the same.
The core 20 and the core 50 each independently execute a task for each core.

[2-2. effect]
Even if the data processing device 4 includes the two cores 20 and 50 as the second processor cores, the effects (1) to (1) of the first embodiment in relation to the cores 10 and 20 and the cores 10 and 50. The same effect as 5) can be obtained.

[3. Third Embodiment]
[3-1. Constitution]
In the data processing device 6 of the third embodiment shown in FIG. 8, a reference counter 82 is provided instead of the reference flag 44 of the first embodiment, and a core 70 is provided instead of the core 20. The reference RAM 80 corresponds to the reference RAM 42 of the first embodiment.

In the third embodiment, the same reference numerals as those in the first embodiment indicate the same configuration, and the preceding description will be referred to for details.
The core 70 executes a copy task 72 and two reference tasks 74 and 76. The priority of the copy task 72 is higher than the priority of the reference tasks 74 and 76. The priority of the reference task 74 is higher than the priority of the reference task 76. The copy process executed by the copy task 72 is substantially the same as the copy process executed by the copy task 22. The reference processing executed by the reference tasks 74 and 76 differs in the processing content of the referenced data.

[3-2. processing]
(1) Reference Process The reference process shown in FIG. 9 is executed when the reference tasks 74 and 76 refer to the reference RAM 80 and the copy task 72 is not being executed. While the reference task 74 having a higher priority than the reference task 76 is being executed, the reference task 76 is not executed.

In S440 of FIG. 9, the reference tasks 74 and 76 increment the value of the reference counter 82 by one. The initial value of the reference counter 82 is 0, for example.
When the value of the reference counter 82 is not 0, it indicates that one of the reference tasks 74 and 76 is referring to the reference RAM 80. In this case, the copy task 72 does not execute the copy process.

When the reference task 74 having a higher priority than the reference task 76 is activated while the reference task 76 is being executed, the value of the reference counter 82 is incremented by 1 and becomes 2.
In S442, the reference tasks 74 and 76 refer to the data in the reference RAM 80. When the reference of data in the reference RAM 80 is completed, the reference tasks 74 and 76 decrement the reference counter 82 by 1 in S444.

(2) Copy Process The copy process shown in FIG. 10 is executed by the copy task 72 when it is time to copy the data in the update RAM 30 to the reference RAM 80. In S450 of FIG. 10, the copy task 72 determines whether or not the reference counter 82 is zero.

  When the determination in S450 is No and the value of the reference counter 82 is not 0, it indicates that at least one of the reference tasks 74 and 76 is referring to the reference RAM 80. In this case, the copy task 72 ends this processing in order to prevent the copy task 72 from acquiring the data in the update RAM 30 and writing it to the reference RAM 80 while the reference tasks 74 and 76 are referring to the reference RAM 80. .

  When the determination in S450 is Yes and neither of the reference tasks 74 and 76 is referring to the reference RAM 80, the copy task 72 executes the processes of S452 to S460. Since the processes of S452 to S460 are substantially the same as the processes of S412 to S420 of the first embodiment, the description thereof is omitted.

[3-3. effect]
In the third embodiment described above, in addition to the effects obtained by replacing the reference flag 44 with the reference counter 82 in the effects (1) to (5) of the first embodiment, the following effects can be obtained.

  Even if the core 70 executes a plurality of reference tasks 74 and 76 by increasing and decreasing each of the reference tasks 74 and 76 by the value of the reference counter 82, at least one of the reference tasks 74 and 76 is being executed. It can be easily determined.

[4. Fourth Embodiment]
[4-1. Constitution]
The data processing device 8 according to the fourth embodiment shown in FIG. 11 is different from the data processing device 2 according to the first embodiment in that the core 70 described in the third embodiment and the temporary storage RAM 84 correspond to the core 70. A reference RAM 80 and a reference counter 82. The temporary storage RAM 84, the reference RAM 80, and the reference counter 82 correspond to the temporary storage RAM 40, the reference RAM 80, and the reference counter 82 of the third embodiment.

In addition, in 4th Embodiment, the same code | symbol as 1st Embodiment and 3rd Embodiment shows the same structure, Comprising: The previous description shall be referred for the detail.
The core 20 and the core 70 execute tasks for each core independently.

[4-2. effect]
The data processing device 8 includes two cores 20 and 70 as second processor cores, and the core 70 executes two reference tasks 74 and 76 having different priorities. Therefore, it is possible to obtain the combined effect of the second embodiment and the third embodiment.

  In the above-described embodiment, the core 10 corresponds to the first processor core, and the cores 20, 50, and 70 correspond to the second processor core. Further, the update RAM 30 corresponds to the update memory, the temporary storage RAMs 40, 60, and 84 correspond to the temporary storage memory, and the reference RAMs 42, 62, and 80 correspond to the reference memory.

  In the above embodiment, S400 to S404 correspond to processing as the update task 12, S410 to S420 correspond to processing as the copy task 22, S430 to S432 correspond to processing as the reference task 24, and S440. To S444 correspond to the processing as the reference tasks 74 and 76, and S450 to S460 correspond to the processing as the copy task 72.

[5. Other Embodiments]
(1) In the above embodiment, when the data processing apparatus includes a plurality of second processor cores, two second processor cores are exemplified. On the other hand, the number of the second processor cores included in the data processing device may be three or more.

  (2) In the above embodiment, when the copy task updates the data in the update RAM 30 before the copy task stores the data in the update RAM 30 in the temporary storage RAM or while the data is stored in the temporary storage RAM, the copy task Re-executes the copy process.

  On the other hand, when the update task 12 updates the data in the update RAM 30 before the copy task stores the data in the update RAM 30 in the temporary storage RAM or while the data is stored in the temporary storage RAM, the copy task performs the current copy process. May be terminated.

  (3) In the third embodiment, whether or not at least one of the reference tasks 74 and 76 is referring to the reference RAM 42 is expressed by increasing and decreasing the value of the reference counter 82. On the other hand, a reference flag indicating whether or not the reference RAM 42 is being referred to may be provided in each of the reference tasks 74 and 76.

  (4) In the third embodiment, the core 70 corresponding to the second processor core executes the two reference tasks 74 and 76 having different priorities. On the other hand, one second processor core may execute three or more reference tasks having different priorities as a plurality of reference tasks.

  (5) In the third embodiment, one core 70 corresponding to the second processor core executes the two reference tasks 74 and 76 having different priorities. On the other hand, two or more second processor cores may execute a plurality of reference tasks having different priorities. In this case, a reference counter is provided for each second processor that executes a plurality of reference tasks.

  (6) A plurality of functions of one constituent element in the above embodiment may be realized by a plurality of constituent elements, or a single function of one constituent element may be realized by a plurality of constituent elements. Further, a plurality of functions possessed by a plurality of constituent elements may be realized by one constituent element, or a single function possessed by a plurality of constituent elements may be realized by one constituent element. Moreover, you may abbreviate | omit a part of structure of the said embodiment. Further, at least a part of the configuration of the above embodiment may be added to or replaced with the configuration of the other embodiment. In addition, all the aspects included in the technical idea specified only by the wording described in the claims are embodiments of the present invention.

  (7) In addition to the data processing apparatus described above, the present invention is realized in various forms such as a data processing program for causing a computer to function as the data processing apparatus, a recording medium on which the data processing program is recorded, and a data processing method. You can also.

2-8: Data processing device, 10: Core (first processor core), 12: Update task, 20, 50, 70: Core (second processor core), 22, 52, 72: Copy task, 24, 54, 74, 76: Reference task, 30: Update RAM (update memory), 32: Update start counter, 34: Update end counter, 40, 60, 84: Temporary storage RAM (temporary storage memory), 42, 62 80: Reference RAM (reference memory) 44, 64: Referenced flag 82: Referenced counter

Claims (8)

One first processor core (10);
One or more second processor cores (20, 50, 70);
An update memory (30) in which the update task (12, S400 to S404) executed by the first processor core writes data;
At least one reference task (24, 54, 74, 76, S430 to S434, S440 to S444) provided by each second processor core and executed by the second processor core refers to the second processor core. A reference memory (42, 62, 80) for writing data acquired from the update memory by a copy task (22, 52, 72, S410 to S420, S450 to S460) that is executed and has a higher priority than the reference task; ,
A data processing device (2, 4, 6, 8). The data processing apparatus according to claim 1,
When at least one second processor core (20, 50) executes one reference task (24, 54), a reference flag (44) indicating that the reference task is referring to the reference memory 64) for each reference task,
The copy task (S410) obtains data in the update memory and writes to the reference memory when the reference flag indicates that the reference task is referring to the reference memory Do not execute the process,
When at least one second processor core (70) executes a plurality of reference tasks (74, 76), the plurality of reference tasks increases for each second processor core that executes the plurality of reference tasks. And a decrementing reference counter (82),
The plurality of reference tasks (S440, S444) execute one of incrementing or decrementing of the reference counter when starting the reference of the reference memory (80), and ending the reference of the reference memory The other of the incrementing or decrementing of the reference counter
When the reference counter indicates that the reference task is referring to the reference memory, the copy task (72, S450) acquires data in the update memory and stores it in the reference memory. Do not execute the copy process to write,
Data processing device. The data processing apparatus according to claim 1,
A reference flag (44, 64) indicating that at least one reference task (24, 54) executed by the second processor core (20, 50) is referring to the reference memory is set for each reference task. In addition,
The copy task (S410) obtains data in the update memory and writes to the reference memory when the reference flag indicates that the reference task is referring to the reference memory Do not perform processing,
Data processing device. In the data processing device according to any one of claims 1 to 3,
An update start counter (32) that causes the update task to increase or decrease when writing to the update memory is started;
An update end counter (34) that causes the update task to increase or decrease in the same direction as the update start counter when writing to the update memory is terminated;
Further comprising
When the copy task (S412, S452) determines that the update task is writing to the update memory based on the values of the update start counter and the update end counter, the copy task stores the data in the update memory. Re-execute the copy process of acquiring and writing to the reference memory;
Data processing device. The data processing apparatus according to claim 4, wherein
The copy task (S418, S458) determines that the update task has written in the update memory when the value of the update start counter changes during execution of the copy process, and re-executes the copy process.
Data processing device. In the data processing device according to any one of claims 1 to 3,
An update start counter (32) that causes the update task to increase or decrease when writing to the update memory is started;
An update end counter (34) that causes the update task to increase or decrease in the same direction as the update start counter when writing to the update memory is terminated;
Further comprising
When the copy task determines that the update task is writing to the update memory based on the values of the update start counter and the update end counter, the copy task acquires data of the update memory and references the End the copy process to write to the memory
Data processing device. The data processing apparatus according to claim 6, wherein
When the value of the update start counter changes during execution of the copy process, the copy task determines that the update task has written to the update memory and ends the copy process.
Data processing device. In the data processing device according to any one of claims 1 to 7,
A temporary storage memory (40, 60, 84) for temporarily storing data acquired from the update memory by the copy task;
In the copy task (S416, S456), the reference task is not referring to the reference memory, the update task is not updating the update memory, and the copy task is acquired from the update memory. When the update task has not updated the update memory while storing the data to be stored in the temporary storage memory, the data of the update memory stored in the temporary storage memory is written to the reference memory.
Data processing device.

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