JP2020113725A - Manufacturing method of wiring board - Google Patents

Manufacturing method of wiring board Download PDF

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JP2020113725A
JP2020113725A JP2019005648A JP2019005648A JP2020113725A JP 2020113725 A JP2020113725 A JP 2020113725A JP 2019005648 A JP2019005648 A JP 2019005648A JP 2019005648 A JP2019005648 A JP 2019005648A JP 2020113725 A JP2020113725 A JP 2020113725A
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conductor layer
straight line
back surface
surface conductor
plan
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金子 正幸
Masayuki Kaneko
正幸 金子
田中 篤志
Atsushi Tanaka
篤志 田中
渡辺 誠
Makoto Watanabe
誠 渡辺
文孝 西尾
Fumitaka Nishio
文孝 西尾
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Abstract

To provide a manufacturing method of a wiring board making it possible to form a front surface conductor layer and a back surface conductor layer with high positional accuracy for each predetermined position on the front and back surfaces of the board body formed by stacking a plurality of insulating layers.SOLUTION: A manufacturing method of a wiring board 1 includes: a step of preparing a plurality of insulating layers G1 to G3; a first hole step of forming a first positioning hole H1 for each of the insulating layers G1 to G3; a surface conductor layer step of forming a surface conductor layer 5 on a surface of the insulating layer G1 forming a surface 3 among the insulating layers G1 to G3; a stacking step of stacking the insulating layers G1 to G3 and press-bonding to form a board body 2m so that the first positioning holes H1 are overlapped with each other along a stacking direction by making the insulating layer G1 on the surface of which the surface conductor layer 5 is formed to be an outermost layer; a second hole step of forming a plurality of second positioning holes H2 penetrating between the front surface 3 and a back surface 4 of the board body 2m by making the surface conductor layer 5 as a reference; and a back surface conductor layer step of forming a back conductor layer 6 on the back surface 4 of the board body 2m with reference to the plurality of second positioning holes H2.SELECTED DRAWING: Figure 2

Description

本発明は、複数の絶縁層を積層してなり、対向する表面および裏面を有する基板本体の前記表面と裏面との双方における所定の位置ごとに導体層を精度良く配設できる配線基板の製造方法に関する。 The present invention is a method of manufacturing a wiring board, which is formed by laminating a plurality of insulating layers, and in which a conductor layer can be accurately arranged at predetermined positions on both the front surface and the back surface of a substrate body having a front surface and a back surface facing each other. Regarding

例えば、主面の中央部に四角形状の配線基板領域が縦横に隣接して配列形成され、これらの周囲に枠形状のダミー領域が位置している母基板と、該母基板の上記主面に上記配線基板領域同士間の境界および該配線基板領域と上記ダミー領域との境界に沿って形成された複数の溝と、該溝ごとの延長線上に位置するように上記ダミー領域に形成された複数の孔と、を備えた多数個取り配線基板が提案されている(例えば、特許文献1参照)。
上記多数個取り配線基板によれば、前記孔を基準に前記母基板を複数の配線基板に分割できることから、位置合わせマークと実際の境界との間におけるずれの発生を防止できるので、各境界に沿って位置精度良く上記母基板を切断できる。
For example, in a central portion of the main surface, rectangular wiring board regions are vertically and horizontally adjacently arranged in an array, and a mother substrate in which frame-shaped dummy regions are located around them is formed on the main surface of the mother substrate. A plurality of grooves formed along the boundaries between the wiring board areas and the boundaries between the wiring board areas and the dummy areas, and a plurality of grooves formed in the dummy areas so as to be located on extension lines of the grooves. Has been proposed (for example, see Patent Document 1).
According to the multi-cavity wiring board, since the mother board can be divided into a plurality of wiring boards based on the holes, it is possible to prevent the occurrence of a deviation between the alignment mark and the actual boundary, and therefore, at each boundary. The mother substrate can be cut along with high positional accuracy.

しかし、前記のような多数個取り配線基板では、一方の表面(主面)における配線基板領域ごとの切断位置や配線導体の位置は、精度良く決めることができる反面、前記配線基板領域ごとで対向する表面と裏面とにおける所定のごとに対して、導体層を個別に精度良く形成することは、困難となる場合がある。
例えば、複数の絶縁層を積層して前記母基板を形成する場合、個々の絶縁層における表面(または裏面)ごとに導体層が位置精度良く形成されていても、これらの絶縁層を積層する際に積層ずれが生じた場合、得られた母基板を配線基板ごとに切断して分割した際に、対向する表面と裏面とに個別に形成された2つの導体層の位置が、相互にずれてしまう、というおそれがあった。
However, in the above-described multi-cavity wiring board, the cutting position for each wiring board area and the position of the wiring conductor on one surface (main surface) can be accurately determined, while facing each other wiring board area. It may be difficult to individually and accurately form the conductor layer for each predetermined amount on the front surface and the back surface.
For example, when a plurality of insulating layers are laminated to form the mother substrate, even if a conductor layer is formed with high positional accuracy on each surface (or back surface) of each insulating layer, when these insulating layers are laminated. When a stacking deviation occurs in the wiring board, when the obtained mother board is cut and divided into wiring boards, the positions of the two conductor layers individually formed on the front surface and the back surface facing each other are shifted from each other. There was a risk that it would end up.

特開2006−128298号公報(第1〜8頁、図1)JP-A-2006-128298 (pages 1 to 8, FIG. 1)

本発明は、背景技術で説明した問題点を解決し、複数の絶縁層を積層してなる基板本体の表面と裏面とにおける所定の位置ごとに表面導体層および裏面導体層を、位置精度良く形成できる配線基板の製造方法を提供する、ことを課題とする。 The present invention solves the problems described in the background art and forms a front surface conductor layer and a back surface conductor layer with high position accuracy at predetermined positions on the front surface and the back surface of a substrate body formed by laminating a plurality of insulating layers. An object of the present invention is to provide a method of manufacturing a wiring board that can be performed.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、予め第1の位置決め穴が個別に形成された複数の絶縁層のうち、追って基板本体の表面となる第1の絶縁層の該表面における所定の位置に表面導体層を形成し、前記絶縁層と他の絶縁層とを積層して得られた基板本体の表面と裏面との間に第2の位置決め孔を貫通して形成した後、該第2の位置決め孔を基準として、上記基板本体の裏面に裏面導体層を形成する、ことに着想して成されたものである。
即ち、本発明による配線基板の製造方法(請求項1)は、複数の絶縁層を積層してなり、且つ対向する表面および裏面を有する基板本体と、該基板本体の前記表面に形成された表面導体層と前記裏面に形成された裏面導体層とが平面視で互いに所定の位置ごとに形成されている配線基板の製造方法であって、上記複数の絶縁層を準備する準備工程と、該複数の絶縁層ごとに第1の位置決め穴を形成する第1穴形成工程と、前記複数の絶縁層のうち、少なくとも上記表面を構成する絶縁層の表面に上記表面導体層を形成する表面導体層形成工程と、該表面導体層が表面に形成された上記絶縁層を最表層とし、且つ上記第1の位置決め穴同士が積層方向に沿って重なるように、上記複数の絶縁層を積層し且つ圧着して基板本体を形成する積層工程と、該基板本体の表面と裏面との間を貫通する複数の第2の位置決め穴を、上記表面導体層を基準にして形成する第2穴形成工程と、上記基板本体の裏面に、上記複数の第2の位置決め穴を基準として裏面導体層を形成する裏面導体層形成工程と、を含む、ことを特徴とする。
In order to solve the above-mentioned problems, the present invention provides a plurality of insulating layers in which first positioning holes are individually formed in advance, at a predetermined position on the surface of the first insulating layer which will be the surface of the substrate body later. After forming a surface conductor layer and forming a second positioning hole between the front surface and the back surface of the substrate body obtained by laminating the insulating layer and another insulating layer, the second positioning hole is formed. It is made in view of forming a back surface conductor layer on the back surface of the substrate body with reference to the positioning hole.
That is, a method of manufacturing a wiring board according to the present invention (claim 1) is a board body having a plurality of insulating layers laminated and having a front surface and a back surface facing each other, and a surface formed on the surface of the board body. A method for manufacturing a wiring board, wherein a conductor layer and a back surface conductor layer formed on the back surface are formed at predetermined positions with respect to each other in a plan view, comprising: a preparatory step of preparing the plurality of insulating layers; First hole forming step of forming a first positioning hole for each insulating layer, and forming a surface conductor layer on the surface of at least the insulating layer constituting the surface of the plurality of insulating layers Step, and stacking and crimping the plurality of insulating layers so that the insulating layer having the surface conductor layer formed on the surface is the outermost layer and the first positioning holes overlap each other along the stacking direction. And a second hole forming step of forming a plurality of second positioning holes penetrating between the front surface and the back surface of the substrate body with reference to the surface conductor layer, And a back surface conductor layer forming step of forming a back surface conductor layer on the back surface of the substrate body with the plurality of second positioning holes as a reference.

前記配線基板の製造方法によれば、以下の効果(1)乃至(3)が得られる。
(1)前記積層工程において、前記複数の絶縁層を積層し且つ圧着した際に、事前にこれらに個別に形成した第1の位置決め穴の中心軸が互いにずれていても、上記積層工程の後で上記複数の絶縁層が一体に積層された基板本体の表面と裏面との間を貫通し、前記表面導体層を基準として前記第2の位置決め穴を形成し、該第2の位置決め穴を基準として上記基板本体の裏面に裏面導体層が形成される。従って、前記基板本体の表面に予め形成された上記表面導体層と上記裏面導体層との位置関係が明確であり、該表面導体層と該裏面導体層とを平面視における所要の位置ごと配設した配線基板を確実に製造することができる。
(2)上記効果(1)に伴って、後述するように、上記表面導体層と裏面導体層とを電気的に接続することによって、例えば、本発明により得られる配線基板における前記表面導体層の上方に追って実装される電子部品と、前記裏面導体を介して上記配線基板が追って搭載されるプリント基板などのマザーボードとの間における電気的な接続を、確実に且つ安定したものとすることが可能となる。
(3)前記配線基板を多数個取り用の基板として形成する際に、前記表面導体層と前記裏面導体層との位置関係が明確であるので、該表面導体層を基準にして、個々の配線基板(基板領域)を切断して固化した場合でも、該裏面導体層が不用意に切断される事態や、配線基板の外周縁から上記裏面導体層までの間の距離が不十分になる事態を防止することができる。
According to the method for manufacturing the wiring board, the following effects (1) to (3) can be obtained.
(1) In the laminating step, when the plurality of insulating layers are laminated and pressure-bonded, even if the central axes of the first positioning holes individually formed in advance are misaligned with each other, after the laminating step, And the plurality of insulating layers are integrally laminated to penetrate between the front surface and the back surface of the substrate body, the second positioning hole is formed with the surface conductor layer as a reference, and the second positioning hole is used as a reference. A back conductor layer is formed on the back surface of the substrate body. Therefore, the positional relationship between the front surface conductor layer and the back surface conductor layer formed in advance on the surface of the substrate body is clear, and the front surface conductor layer and the back surface conductor layer are arranged at required positions in a plan view. The printed wiring board can be reliably manufactured.
(2) With the effect (1), as described later, by electrically connecting the front surface conductor layer and the back surface conductor layer, for example, the surface conductor layer of the wiring board obtained by the present invention It is possible to ensure reliable and stable electrical connection between an electronic component that is mounted upwardly and a motherboard such as a printed circuit board on which the wiring board is mounted via the back surface conductor. Becomes
(3) Since the positional relationship between the front surface conductor layer and the back surface conductor layer is clear when the wiring board is formed as a substrate for taking a large number of wiring boards, individual wirings are made with reference to the front surface conductor layer. Even when the substrate (substrate region) is cut and solidified, the situation where the back surface conductor layer is inadvertently cut or the distance from the outer peripheral edge of the wiring board to the above-mentioned back surface conductor layer becomes insufficient. Can be prevented.

尚、前記絶縁層は、セラミック(例えば、アルミナ)または樹脂(例えば、エポキシ系樹脂)からなる。
また、前記表面と裏面とは、相対的な呼称であり、前記基板本体において対向する一対の表面である一方を表面と称した際に、他方を裏面と称したものである。
更に、前記表面導体層と裏面導体層、および後述する内層配線やビア導体は、前記絶縁層がアルミナなどの高温同時焼成セラミックの場合には、タングステン(以下、単にWと略記する)、あるいはモリブデン(以下、単にMoと略記する)からなり、ガラス−セラミックなどの低温同時焼成セラミックや前記樹脂の場合には、銅(Cu)または銀(Ag)からなる。
また、前記第1および第2の位置決め穴の平面視における外形の形状は、円形状、長円形状、あるいは四角形以上の正多角形状または変形多角形(例えば、長方形)状である。
更に、前記第1および第2の位置決め穴は、打ち抜き加工のほか、レーザー加工によって形成され、これらの穴は、少なくも2つ以上(複数)が穿孔される。
また、前記第2穴形成工程において前記表面導体層を基準とし、前記裏面導体形成工程において前記第2の位置決め穴を基準とする際には、前記表面導体層における一部分、あるいは第2の位置決め穴の中心を基準として撮像する画像処理手段により撮影された画像を認識することによって、上記各工程が行われる。
加えて、前記各工程は、多数個取りの形態によって行う方法が推奨される。
The insulating layer is made of ceramic (for example, alumina) or resin (for example, epoxy resin).
Further, the front surface and the back surface are relative names, and when one of a pair of surfaces of the substrate body facing each other is called a front surface, the other is called a back surface.
Further, when the insulating layer is a high temperature co-fired ceramic such as alumina, the front surface conductor layer and the back surface conductor layer, and inner layer wirings and via conductors described later are made of tungsten (hereinafter simply referred to as W) or molybdenum. (Hereinafter, simply abbreviated as Mo), and in the case of a low temperature co-fired ceramic such as glass-ceramic or the above resin, it is made of copper (Cu) or silver (Ag).
The shape of the outer shape of the first and second positioning holes in a plan view is a circular shape, an oval shape, or a regular polygonal shape of a quadrangle or more or a deformed polygonal shape (for example, a rectangular shape).
Further, the first and second positioning holes are formed by laser processing as well as punching, and at least two or more (plural) of these holes are punched.
In addition, when the front surface conductor layer is used as a reference in the second hole forming step and the second positioning hole is used as a reference in the back surface conductor forming step, a part of the front surface conductor layer or a second positioning hole is used. The above steps are performed by recognizing the image taken by the image processing means for taking an image with the center of the image as a reference.
In addition, it is recommended that each of the steps be carried out in a multi-cavity form.

また、本発明には、前記複数の絶縁層は、平面視で中央側に位置する矩形状の製品領域と、該製品領域の周囲を囲む矩形枠状の耳部とからなり、前記第1の位置決め穴および第2の位置決め穴は、前記耳部において異なる辺ごとに個別に形成されている、配線基板の製造方法(請求項2)も含まれる。
これによれば、上記第1の位置決め穴および第2の位置決め穴が、上記耳部において異なる辺ごとに個別に形成されているので、例えば、上記製品領域を構成する配線基板の基板本体に貫通穴や側面導体を有していない形態であっても、前記基板本体の表面と裏面とにおける所定の位置に前記表面導体層および裏面導体を配設した配線基板を、容易に製造することができる。従って、前記効果(1)、(3)が容易に得られる。
尚、前記製品領域は、平面視で前記配線基板を縦横に隣接して複数個が併設される形態のほか、追って1個の配線基板となる形態であっても良い。
Further, in the present invention, the plurality of insulating layers include a rectangular product region located on the center side in a plan view and a rectangular frame-shaped ear portion surrounding the periphery of the product region. The positioning hole and the second positioning hole also include a method of manufacturing a wiring board (claim 2), which is individually formed for each different side in the ear portion.
According to this, since the first positioning hole and the second positioning hole are individually formed for each different side in the ear portion, for example, the first positioning hole and the second positioning hole are penetrated into the board body of the wiring board that constitutes the product area. A wiring board having the front surface conductor layer and the back surface conductor arranged at predetermined positions on the front surface and the back surface of the board body can be easily manufactured even if it has no holes or side surface conductors. .. Therefore, the effects (1) and (3) can be easily obtained.
The product area may have a configuration in which a plurality of the wiring boards are juxtaposed vertically and horizontally adjacent to each other in plan view, or may be a single wiring board later.

更に、本発明には、前記複数の絶縁層は、平面視で中央側に位置する矩形状の製品領域と、該製品領域の周囲を囲む矩形枠状の耳部とからなり、前記第1の位置決め穴は、前記耳部おいて異なる辺ごとに個別に形成されており、前記第2の位置決め穴は、上記製品領域に形成されている、配線基板の製造方法(請求項3)も含まれる。
これによれば、前記第1の位置決め穴は、前記耳部おいて異なる辺ごとに個別に形成され、前記第2の位置決め穴は、前記製品領域に形成されているので、例えば、該製品領域を構成する何れかの配線基板の基板本体における表面と裏面との間を貫通する貫通穴を、上記第2の位置決め穴として前記第2穴形成工程で形成して兼用させることができる。従って、加工工数を低減しつつ、前記効果(1)、(3)を得ることが可能となる。
Further, in the present invention, the plurality of insulating layers include a rectangular product region located on the center side in a plan view and a rectangular frame-shaped ear portion surrounding the periphery of the product region. The wiring board manufacturing method (claim 3) is also included, in which the positioning holes are individually formed for different sides in the ear portion, and the second positioning holes are formed in the product region. ..
According to this, the first positioning hole is individually formed for each different side in the ear portion, and the second positioning hole is formed in the product region. A through hole penetrating between the front surface and the back surface of the substrate body of any of the wiring boards constituting the above can be formed and used as the second positioning hole in the second hole forming step. Therefore, the effects (1) and (3) can be obtained while reducing the number of processing steps.

また、本発明には、前記複数の絶縁層は、平面視で中央側に位置する矩形状の製品領域と、該製品領域の周囲を囲む矩形枠状の耳部とからなり、前記第1の位置決め穴は、前記耳部おいて異なる辺ごとに個別に形成されており、前記第2の位置決め穴は、上記製品領域と上記耳部との境界に跨がっており、且つ平面視で前記耳部で異なる辺側に形成されている、配線基板の製造方法(請求項4)も含まれる。
これによれば、前記第1の位置決め穴は、前記耳部おいて異なる辺ごとに個別に形成されており、前記第2の位置決め穴は、前記製品領域と上記耳部との境界に跨がり、且つ平面視で前記耳部で異なる辺側に形成されている。そのため、例えば、上記製品領域における外側に位置する配線基板の基板領域において、上記耳部に隣接する側面に側面導体を形成するための凹部を形成する場合、該配線基板と耳部とに跨がって形成した第2の位置決め穴の一部を上記凹部にて兼用することにより、加工工数を低減しつつ、前記効果(1)、(3)を得ることが可能となる。
Further, in the present invention, the plurality of insulating layers include a rectangular product region located on the center side in a plan view and a rectangular frame-shaped ear portion surrounding the periphery of the product region. The positioning hole is individually formed for each different side in the ear portion, and the second positioning hole straddles the boundary between the product region and the ear portion, and is in plan view. Also included is a method of manufacturing a wiring board (claim 4), which is formed on different sides of the ears.
According to this, the first positioning hole is individually formed for each different side in the ear portion, and the second positioning hole extends over the boundary between the product region and the ear portion. In addition, the ears are formed on different sides in plan view. Therefore, for example, in the substrate area of the wiring board located outside the product area, when forming a recess for forming a side surface conductor on the side surface adjacent to the ear portion, the wiring board and the ear portion are straddled. By using part of the second positioning hole formed in this way as the concave portion, it is possible to obtain the effects (1) and (3) while reducing the number of processing steps.

更に、本発明には、前記第2の位置決め穴は、前記製品領域の四隅を含む4つの角領域のうち、平面視で対角位置にある2つの角領域を通過する対角仮想直線上に2つ以上が形成されているか、または、平面視で前記製品領域の辺と平行に向かい合う2つの角領域を通過する平行仮想直線上に2つ以上が形成され、且つ上記対角仮想直線上に1つ以上が形成されているか、または、平面視で上記平行仮想直線が通過する2つの角領域と対向する別の2つの角領域を通過する対向仮想直線上であり、上記製品領域の中点に形成され、且つ上記平行仮想直線上に2つ以上が形成されているか、あるいは、平面視で前記平行仮想直線上に2つ以上が形成され、且つ上記対向仮想直線上に2つ以上が形成されている、配線基板の製造方法(請求項5)も含まれる。
これによれば、前記第2の位置決め穴は、前記製品領域における角領域内ごと、該角領域内に位置する前記耳部、あるいは、前記製品領域の一辺における中央(中点)付近、またはこれに近接する耳部の中点に形成される。そのため、上記複数の第2の位置決め穴を形成すべき位置を互いに離間させて容易に設定できる。従って、前記表面導体層と裏面導体層との位置決め精度を高くし且つ安定させられるため、前記効果(1)、(3)を一層確実に得ることが可能となる。
尚、前記角領域とは、前記製品領域における1つの角部付近とこれに隣接する耳部とを併有し、例えば、平面視が30mm×30mm程度である矩形の領域である。
Furthermore, in the present invention, the second positioning hole is on a diagonal virtual straight line that passes through two corner regions diagonally located in a plan view among four corner regions including four corners of the product region. Two or more are formed, or two or more are formed on a parallel virtual straight line that passes through two corner regions that face each other in parallel with the sides of the product region in a plan view, and on the diagonal virtual straight line. One or more are formed, or on an opposing virtual straight line passing through another two corner regions opposite to the two corner regions passing through the parallel virtual straight line in plan view, and the midpoint of the product region Or two or more are formed on the parallel virtual straight line, or two or more are formed on the parallel virtual straight line in plan view and two or more are formed on the opposing virtual straight line. Also included is a method for manufacturing a wiring board (claim 5).
According to this, the second positioning hole is provided in each corner area of the product area, the ear portion located in the corner area, or near the center (middle point) of one side of the product area, or Is formed at the midpoint of the ear near the. Therefore, the positions where the plurality of second positioning holes are to be formed can be easily set apart from each other. Therefore, since the positioning accuracy of the front surface conductor layer and the back surface conductor layer can be increased and stabilized, the effects (1) and (3) can be more reliably obtained.
The corner area is a rectangular area that has both one corner and the adjacent ear in the product area, and has a plan view of about 30 mm×30 mm, for example.

加えて、本発明には、前記複数の絶縁層同士の層間には、内層配線が形成されており、該内層配線は、上記絶縁層を貫通するビア導体を介して、前記表面導体層および裏面導体層と個別に導通可能とされている、配線基板の製造方法(請求項6)も含まれる。
これによれば、上記表面導体層および裏面導体層が、上記内層配線およびビア導体を介して電気的に接続されているので、前記効果(2)を確実に得ることができる。
In addition, according to the present invention, an inner layer wiring is formed between the plurality of insulating layers, and the inner layer wiring includes the front surface conductor layer and the back surface via a via conductor penetrating the insulating layer. Also included is a method of manufacturing a wiring board (claim 6), which is individually electrically conductive with the conductor layer.
According to this, since the front surface conductor layer and the back surface conductor layer are electrically connected to each other through the inner layer wiring and the via conductor, the effect (2) can be reliably obtained.

(A)は、本発明に用いる絶縁層を示す平面図、(B1)は、その垂直断面図、(B2)は、(B1)の拡大断面図、(C)は、本発明の第1穴形成工程および表面導体層形成工程を示す概略図、(D)は、本発明の積層工程を示す概略図、(d)は、(D)中における一点鎖線部分の拡大図。(A) is a plan view showing an insulating layer used in the present invention, (B1) is a vertical sectional view thereof, (B2) is an enlarged sectional view of (B1), and (C) is a first hole of the present invention. Schematic diagrams showing the forming step and the surface conductor layer forming step, (D) is a schematic diagram showing the laminating step of the present invention, and (d) is an enlarged view of a one-dot chain line portion in (D). (A1)、(A2)は、本発明の第2穴形成工程を示す平面図と拡大垂直断面図、(B)は、本発明の裏面導体層形成工程を示す概略断面図、(C)は、焼成工程を示す概略断面図、(D)は、分割工程で得られた複数の配線基板を示す概略断面図。(A1) and (A2) are a plan view and an enlarged vertical sectional view showing the second hole forming step of the present invention, (B) is a schematic sectional view showing the back surface conductor layer forming step of the present invention, and (C) is , A schematic sectional view showing a firing step, and (D) is a schematic sectional view showing a plurality of wiring boards obtained in the dividing step. (A)は、本発明に用いる絶縁層において、角領域、対角仮想直線、平行仮想直線、および、対向仮想直線を示す平面図、(B)は、製品領域に第2の位置決め穴を有す形態における第1穴形成工程および表面導体層形成工程を示す平面図。(A) is a plan view showing a corner region, a diagonal virtual straight line, a parallel virtual straight line, and an opposing virtual straight line in the insulating layer used in the present invention, and (B) has a second positioning hole in the product region. FIG. 6 is a plan view showing a first hole forming step and a surface conductor layer forming step in the embodiment. (A)は、図3(B)に引き続く第2穴形成工程を示す平面図、(B)は、製品領域と耳部との境界に跨がって第2の位置決め穴を形成した形態を示す平面図。FIG. 3A is a plan view showing a second hole forming step following FIG. 3B, and FIG. 3B shows a form in which a second positioning hole is formed across the boundary between the product region and the ear. FIG. (A)、(B)は、前記絶縁層において、更に異なる位置に第2の位置決め穴を形成した形態を示す平面図。(A), (B) is a top view which shows the form which formed the 2nd positioning hole in a different position in the said insulating layer. (A)、(B)は、前記絶縁層において、更に別なる位置に第2の位置決め穴を形成した形態を示す平面図。(A), (B) is a top view which shows the form which formed the 2nd positioning hole in the insulating layer in another position further.

以下において、本発明を実施するための形態について説明する。
予め、アルミナ粉、バインダ樹脂、溶剤、および可塑剤などを適量ずつ配合してセラミックスラリーを作成し、該セラミックスラリーをドクターブレード法によってシート状に成形して、図1(A),(B1),(B2)に示すように、多数個取り用で、且つ対向する一対の表面を有するセラミックグリーンシート(絶縁層、以下、単にグリーンシートと称する)Gnを3層作製した(準備工程)。
上記グリーンシートGnは、何れも平面視で中央側に位置し、複数の基板領域2aを縦横に隣接して併有する矩形状の製品領域Paと、該製品領域Paの周囲を囲む矩形枠状の耳部Faとからなる。これら製品領域Paと耳部Faとの境界は、図1(A)中の破線で示す仮想の切断予定面9によって区画されている。
尚、図1および後述する図2中においては、作図上の都合により、垂直方向を実際の大きさよりも過大に表現している。
Hereinafter, modes for carrying out the present invention will be described.
Alumina powder, a binder resin, a solvent, a plasticizer, and the like are mixed in advance in appropriate amounts to prepare a ceramic slurry, and the ceramic slurry is formed into a sheet by the doctor blade method, as shown in FIGS. 1(A) and 1(B1). , (B2), three layers of ceramic green sheets (insulating layers, hereinafter simply referred to as green sheets) Gn for preparing a large number and having a pair of opposing surfaces were prepared (preparation step).
Each of the green sheets Gn is located on the center side in a plan view, and has a rectangular product area Pa having a plurality of substrate areas 2a adjacent to each other vertically and horizontally, and a rectangular frame shape surrounding the periphery of the product area Pa. It consists of the ears Fa. The boundary between the product area Pa and the ear portion Fa is partitioned by an imaginary planned cutting surface 9 indicated by a broken line in FIG.
Note that, in FIG. 1 and FIG. 2 described later, the vertical direction is represented as being larger than the actual size for convenience of drawing.

先ず、図1(C)に示す3層のグリーンシートG1〜G3の左右に示すように、前記耳部Faにおける異なる辺ごとに3つ(複数)の第1の位置決め穴H1を個別に形成した(第1穴形成工程)。引き続いて、同図中の左側に示すように、前記製品領域Pa内の基板領域2aごとにおける所定の位置に複数のビアホール10を穿孔した。これらは、断面が円形状で、公知の打ち抜き加工により行った。
また、図1(C)中の中央付近に示すように、上記ビアホール10内ごとに、W粉またはMo粉を含む導電性ペーストを、スキージ(図示せず)および負圧を利用して充填して、未焼成のビア導体8を個別に形成した後、同図中の右側に示すように、グリーンシートG1〜G3における上側の表面ごとに、上記同様の導電性ペーストをスクリーン印刷して、未焼成の表面導体層5を形成した(表面導体層形成工程)。該表面導体層5は、上記ビア導体8と個別に接続されていた。
First, as shown on the left and right of the three-layer green sheets G1 to G3 shown in FIG. 1C, three (plural) first positioning holes H1 are individually formed on different sides of the ear portion Fa. (First hole forming step). Subsequently, as shown on the left side of the figure, a plurality of via holes 10 were drilled at predetermined positions in each substrate region 2a within the product region Pa. These have a circular cross section and are formed by a known punching process.
Further, as shown in the vicinity of the center in FIG. 1(C), a conductive paste containing W powder or Mo powder is filled in each of the via holes 10 by using a squeegee (not shown) and a negative pressure. Then, after individually forming the unfired via conductors 8, as shown on the right side of the figure, a conductive paste similar to the above is screen-printed on each of the upper surfaces of the green sheets G1 to G3, and The baked surface conductor layer 5 was formed (surface conductor layer forming step). The surface conductor layer 5 was individually connected to the via conductor 8.

次いで、前記表面導体層5およびビア導体8が形成された前記グリーンシートG1〜G3を、追って後述する基板本体2の表面3を構成するグリーンシートG1を最表層とし、且つこれらにおける前記第1の位置決め穴H1が積層(軸)方向に沿って重なるように、積層し且つ圧着した(積層工程)。
その結果、図1(D)に示すように、上記グリーンシートG1〜G3が積層され、且つ対向する表面3および裏面4を有する多数個取り用の基板本体2mが形成された。この際、図1(d)の拡大図に示すように、前記第1の位置決め穴H1同士は、上記グリーンシートG1〜G3相互間の積層時における誤差によって、互いの中心軸がずれている場合があった。
Next, the green sheets G1 to G3 on which the surface conductor layer 5 and the via conductors 8 are formed are the outermost layers of the green sheet G1 which forms the surface 3 of the substrate body 2 described later, and the first of these The layers were laminated and pressure-bonded so that the positioning holes H1 were overlapped along the lamination (axial) direction (lamination step).
As a result, as shown in FIG. 1D, the above-mentioned green sheets G1 to G3 were laminated, and a substrate body 2m for multi-cavity formation having a front surface 3 and a back surface 4 facing each other was formed. At this time, as shown in the enlarged view of FIG. 1D, when the first positioning holes H1 are deviated from each other in center axis due to an error in stacking the green sheets G1 to G3. was there.

次に、図2(A1)の平面図と図2(A2)の垂直断面図とで示すように、前記表面導体層5の一部を基準として、前記基板本体2mの耳部Faに合計3つ(複数)の第2の位置決め穴H2を、打ち抜き加工によって形成した(第2穴形成工程)。かかる第2の位置決め穴H2は、上記耳部Faにおける図2(A1)で左辺に1つと、右辺(異なる辺)に2つとが形成されていた。
また、上記基板本体2mの裏面4における製品領域Pa内の基板領域2aごとに対し、少なくとも2つ(複数)以上の上記第2の位置決め穴H2を基準として、前記同様の導電性ペーストをスクリーン印刷を施した。尚、断面が円形の前記第2の位置決め穴H2を基準とするため、例えば、図示しないCCDカメラによって、第2の位置決め穴H2ごとの中心を撮像し、これらの中心の位置を基準として、上記スクリーン印刷を行った。
その結果、図2(B)に示すように、上記裏面4における製品領域Pa内の基板領域2a内ごとに、所定パターンを有する複数の裏面導体層6が形成された(裏面導体層形成工程)。かかる裏面導体層6は、最下層の前記グリーンシートG3を貫通する前記ビア導体8と個別に接続されていた。
Next, as shown in the plan view of FIG. 2(A1) and the vertical cross-sectional view of FIG. 2(A2), a total of 3 ears are provided on the ears Fa of the substrate body 2m with reference to a part of the surface conductor layer 5. One (plurality) second positioning holes H2 were formed by punching (second hole forming step). In the ear portion Fa, one second positioning hole H2 is formed on the left side and two second positioning holes H2 are formed on the right side (different sides).
Further, for each substrate area 2a in the product area Pa on the back surface 4 of the substrate body 2m, the same conductive paste as described above is screen-printed on the basis of at least two (plural) or more second positioning holes H2. Was applied. Since the second positioning hole H2 having a circular cross section is used as a reference, the center of each second positioning hole H2 is imaged by, for example, a CCD camera (not shown), and the positions of these centers are used as references. Screen printing was performed.
As a result, as shown in FIG. 2B, a plurality of back surface conductor layers 6 having a predetermined pattern were formed in each substrate area 2a in the product area Pa on the back surface 4 (back surface conductor layer forming step). .. The back surface conductor layer 6 was individually connected to the via conductor 8 penetrating the lowermost green sheet G3.

更に、前記表面・裏面導体層5,6などの導体が形成された前記基板本体2mを焼成する(焼成工程)によって、図2(C)に示すように、前記グリーンシートG1〜G3がセラミック層(絶縁層)C1〜C3になると共に、上記表面・裏面導体層5,6などの導体も同時に焼成された。
引き続いて、焼成された上記基板本体2mを、電解ニッケルメッキ浴中および電解金メッキ浴中に順次浸漬して、外部に露出している前記表面・裏面導体層5,6の表面に対し、ニッケル層と金層とを順次被覆するメッキ工程を行った。
そして、メッキされた前記基板本体2mを、前記切断予定面9に沿って、例えば、高速回転する円盤状のカッターを走査することよって、個々の基板領域2aごとに切断すると共に、前記耳部Faを切除した(分割工程)。その結果、図2(D)に示すように、セラミック層C1〜C3からなり、対向する表面3および裏面4を有する基板本体2と、前記表面3および裏面4ごとにおける所定の位置に形成された表面導体層5および裏面導体層6と、これらの間を電気的に接続する内層配線7およびビア導体8とを備えた複数の配線基板1を得ることができた。
Further, as shown in FIG. 2C, the green sheets G1 to G3 are ceramic layers by firing the substrate body 2m on which conductors such as the front and back surface conductor layers 5 and 6 are formed (firing step). (Insulating layers) C1 to C3, and at the same time, the conductors such as the front and back surface conductor layers 5 and 6 were also fired.
Subsequently, the fired substrate body 2m is sequentially dipped in an electrolytic nickel plating bath and an electrolytic gold plating bath to form a nickel layer on the surfaces of the front and back surface conductor layers 5 and 6 exposed to the outside. Then, a plating process of sequentially coating the metal layer and the gold layer was performed.
Then, the plated substrate body 2m is cut along the planned cutting surface 9 by, for example, a disk-shaped cutter that rotates at a high speed to cut each of the substrate regions 2a, and the ears Fa Was excised (division process). As a result, as shown in FIG. 2D, the substrate body 2 made of the ceramic layers C1 to C3 and having the front surface 3 and the back surface 4 facing each other, and the front surface 3 and the back surface 4 were formed at predetermined positions. It was possible to obtain a plurality of wiring boards 1 each including the front surface conductor layer 5 and the back surface conductor layer 6, and the inner layer wiring 7 and the via conductor 8 that electrically connect these.

以上のような配線基板1の製造方法では、複数ずつの前記第1および第2の位置決め穴H1,H2が前記基板本体2mの耳部Faに形成され、前記積層工程において、前記グリーンシートG1〜G3を積層し且つ圧着した際に、これらの第1の位置決め穴H1の中心軸が互いにずれていても、該積層工程の後で上記グリーンシートG1〜G3が一体に積層された基板本体2mの表面3と裏面4との間を貫通しており、且つ前記表面導体層5を基準にして形成された前記第2の位置決め穴H2を基準として、上記基板本体2mの裏面4に裏面導体層6が形成される。従って、前記基板本体2の表面3に予め形成された上記表面導体層5と上記裏面導体層6との位置関係が明確であり、該表面導体層5と該裏面導体層6とを平面視で所要の位置ごとに配設した配線基板1を確実に製造することができた。 In the method of manufacturing the wiring board 1 as described above, a plurality of the first and second positioning holes H1 and H2 are formed in the ears Fa of the board body 2m, and the green sheets G1 to G1 are formed in the laminating step. Even when the central axes of these first positioning holes H1 are deviated from each other when G3 is laminated and pressure-bonded, the green sheet G1 to G3 of the substrate body 2m integrally laminated after the laminating step is performed. The back surface conductor layer 6 is formed on the back surface 4 of the substrate body 2m with reference to the second positioning hole H2 which penetrates between the front surface 3 and the back surface 4 and is formed with the front surface conductor layer 5 as a reference. Is formed. Therefore, the positional relationship between the front surface conductor layer 5 and the rear surface conductor layer 6 which are formed in advance on the front surface 3 of the substrate body 2 is clear, and the front surface conductor layer 5 and the rear surface conductor layer 6 are seen in a plan view. It was possible to reliably manufacture the wiring substrate 1 arranged at each required position.

また、前記表面導体層5と裏面導体層6とが電気的に接続されているので、例えば、得られた配線基板1における前記表面導体層5の上方に追って実装される半導体素子などの電子部品と、前記裏面導体層6を介して上記配線基板1が追って搭載されるプリント基板(マザーボード)などとの間における電気的な接続を確実に且つ安定したものにできる。
更に、前記配線基板1を多数個取り用の形態として形成しており、前記表面導体層5と前記裏面導体層6との位置関係が明確であるため、該表面導体層5を基準にして、個々の配線基板1を切断して個片化した際にも、上記裏面導体層6が不用意に切断される事態や、配線基板1の外周縁から前記裏面導体層6までの間の距離が不十分になる事態を防止することができた。
従って、前記配線基板1の製造方法によれば、前記効果(1)乃至(3)を得られることが容易に理解される。
Further, since the front surface conductor layer 5 and the back surface conductor layer 6 are electrically connected to each other, for example, an electronic component such as a semiconductor element mounted above the front surface conductor layer 5 in the obtained wiring board 1 is mounted. The electrical connection between the wiring board 1 and a printed board (motherboard) on which the wiring board 1 is subsequently mounted via the back surface conductor layer 6 can be surely and stable.
Further, since the wiring board 1 is formed in a form for taking a large number of pieces and the positional relationship between the front surface conductor layer 5 and the back surface conductor layer 6 is clear, the front surface conductor layer 5 is used as a reference, Even when the individual wiring boards 1 are cut into individual pieces, the situation in which the back conductor layer 6 is inadvertently cut and the distance from the outer peripheral edge of the wiring board 1 to the back conductor layer 6 is It was possible to prevent the situation of becoming insufficient.
Therefore, it is easily understood that the effects (1) to (3) can be obtained by the method for manufacturing the wiring board 1.

図3(A)は、本発明に用いる前記基板本体2mにおいて、前述の角領域Ca、対角仮想直線L1、平行仮想直線L2、および、対向仮想直線L3を示すための平面図である。
図示のように、平面視で上記前記基板本体2mの中央側に位置する製品領域Paにおける四隅付近ごとには、平面視が正方形(矩形)状を呈し且つ仮想である4つの角領域Caが個別に設定されている。かかる4つの角領域Caのうち、図3(A)中の一点鎖線で示すように、対角位置にある2つの角領域Caを通過する直線を対角仮想直線L1と称し、上記製品領域Paの同じ辺と平行に向き合う2つの角領域Caを通過する直線を平行仮想直線L2と称し、該平行仮想直線L2が通過する2つの角領域Caと対向する別の2つの角領域Ca通過する直線を対向仮想直線L3と称するものとしている。
尚、上記平行仮想直線L2と対向仮想直線L3とは、互いに対向する直線であり、図3(A)において、下側の直線を平行仮想直線L2とし、且つ同図で上側の直線を対向仮想直線L3としたが、両者は相対的であり、図示で上側の直線を平行仮想直線L2とし、且つ下側の直線を対向仮想直線L3としても構わない。
FIG. 3A is a plan view showing the corner area Ca, the diagonal virtual straight line L1, the parallel virtual straight line L2, and the facing virtual straight line L3 in the substrate body 2m used in the present invention.
As shown in the drawing, four corner areas Ca each having a square (rectangular) shape in plan view and being virtual are individually provided near the four corners of the product area Pa located on the center side of the substrate body 2m in plan view. Is set to. Of the four corner areas Ca, a straight line passing through the two corner areas Ca at diagonal positions is referred to as a diagonal virtual straight line L1 as indicated by a dashed line in FIG. A straight line passing through two corner regions Ca facing in parallel to the same side is called a parallel virtual straight line L2, and another straight line passing through another two corner regions Ca facing the two corner regions Ca passing through the parallel virtual straight line L2. Is referred to as a facing virtual straight line L3.
The parallel virtual straight line L2 and the facing virtual straight line L3 are straight lines that face each other. In FIG. 3A, the lower straight line is the parallel virtual straight line L2, and the upper straight line is the opposite virtual straight line in FIG. Although the straight line L3 is used, the two are relative, and in the figure, the upper straight line may be the parallel virtual straight line L2 and the lower straight line may be the opposing virtual straight line L3.

図3(B)は、前記製品領域Pa内の基板領域2aごとの中央側に、平面視が矩形状の貫通穴10を有する形態において、前記第1穴形成工程および表面導体層形成工程の後における基板本体2mを示す平面図である。
即ち、図示のように、上記基板本体2mにおける耳部Faには、前記第1穴形成工程で形成されていた4つの第1の位置決め穴H1が互いに離れて位置し、製品領域Pa内の基板領域2aには、前記表面導体層形成工程で形成されていた所定パターンの表面導体層5が形成されている。
FIG. 3B shows a state in which the through hole 10 having a rectangular shape in plan view is provided on the center side of each substrate area 2a in the product area Pa after the first hole forming step and the surface conductor layer forming step. FIG. 3 is a plan view showing a substrate body 2m in FIG.
That is, as shown in the drawing, in the ear portion Fa of the substrate body 2m, the four first positioning holes H1 formed in the first hole forming step are located apart from each other, and the substrate in the product area Pa is located. The surface conductor layer 5 having a predetermined pattern formed in the surface conductor layer forming step is formed in the region 2a.

前記のような基板本体2mにおいて、前記製品領域Paに位置する基板領域2aごとの平面視で中央側に対し、貫通穴10を形成するためのポンチとダイ(図示せず)とによる打ち抜き加工によって、第2穴形成工程を行った。その結果、図4(A)に示すように、上記製品領域Paの基板領域2aごとの中央側には、上記基板本体2mの表面3と裏面4との間を貫通し、前記貫通穴10を兼ねる第2の位置決め穴H2が形成された。
これらの貫通穴10において、四隅の基板領域2aごとの中央側に位置し、且つ個々の貫通穴10を兼用する4つの第2の位置決め穴H2のうち、図4(A)中で右上隅側に位置する第2の位置決め穴H2と、左下隅側に位置する第2の位置決め穴H2とは、前記対角仮想直線L1が、それらの中心部を通過している。
尚、図4(A)中で左上隅側に位置する第2の位置決め穴H2と、右下隅側に位置する第2の位置決め穴H2も、上記と同様に対角仮想直線L1の設定が可能である。
In the substrate body 2m as described above, by punching with a punch and a die (not shown) for forming the through hole 10 with respect to the center side of each substrate region 2a located in the product region Pa in plan view. The second hole forming step was performed. As a result, as shown in FIG. 4A, the center side of each substrate region 2a of the product region Pa penetrates between the front surface 3 and the back surface 4 of the substrate body 2m, and the through hole 10 is formed. The second positioning hole H2, which also serves as the double positioning hole, was formed.
In these through holes 10, among the four second positioning holes H2 located on the center side of each of the four corners of the substrate region 2a and also serving as the individual through holes 10, the upper right corner side in FIG. 4(A). With respect to the second positioning hole H2 located at and the second positioning hole H2 located at the lower left corner side, the diagonal virtual straight line L1 passes through the central portions thereof.
In addition, as for the 2nd positioning hole H2 located in the upper left corner side in FIG. 4(A) and the 2nd positioning hole H2 located in the lower right corner side, the diagonal virtual straight line L1 can be set similarly to the above. Is.

一方、前記4つの第2の位置決め穴H2のうち、図4(A)中で前記製品領域Paの左下隅側に位置する第2の位置決め穴H2と、右下隅側に位置する第2の位置決め穴H2とは、前記平行仮想直線L2が、それらの中心部を通過している。尚、図4(A)中で左上隅側に位置する第2の位置決め穴H2と、右上隅側に位置する第2の位置決め穴H2も、上記同様に平行仮想直線L2の設定が可能である。
以上のように、複数の第2の位置決め穴H2を、前記対角仮想直線L1、あるいは前記平行仮想直線L2が通過する2つの角領域Ca内に設定することによって、前記のように、配線基板1の貫通穴10を兼ねる複数の第2の位置決め穴H2を、前記基板本体2mの平面視において互いに離間した位置ごとに容易に設定でき、且つ前記表面・裏面導体層5,6の位置決め精度を高めることができる。
On the other hand, among the four second positioning holes H2, a second positioning hole H2 located on the lower left corner side of the product area Pa and a second positioning hole located on the lower right corner side in FIG. 4(A). The parallel virtual straight line L2 passes through the center of the hole H2. In addition, in the second positioning hole H2 located on the upper left corner side and the second positioning hole H2 located on the upper right corner side in FIG. 4A, the parallel virtual straight line L2 can be set similarly to the above. ..
As described above, by setting the plurality of second positioning holes H2 in the two corner areas Ca through which the diagonal virtual straight line L1 or the parallel virtual straight line L2 passes, as described above, The plurality of second positioning holes H2 also serving as the one through hole 10 can be easily set at positions separated from each other in the plan view of the substrate body 2m, and the positioning accuracy of the front surface/back surface conductor layers 5, 6 can be improved. Can be increased.

図4(B)は、前記第2穴形成工程後における異なる形態の基板本体2mを示す平面図である。
即ち、図4(B)に示すように、上記基板本体2mにおける耳部Faには、前記第1穴形成工程で形成されていた3つの第1の位置決め穴H1が異なる辺ごとに互いに離れて位置し、製品領域Pa内の基板領域2aごとの表面3には、前記表面導体層形成工程で形成された所定パターンの表面導体層5が位置している。更に、隣接する基板領域2a同士を区画する切断予定面9と、外周側に位置する基板領域2aと耳部Faとの間を区画する切断予定面9とに跨がって、平面視が長方形状の貫通穴12をポンチとダイ(図示せず)とによる打ち抜き加工によって、基板本体2mに対して形成した(第2穴形成工程)。該貫通穴12は、個々の基板領域2aごとに追って分割した際に、得られる基板本体2における四辺の側面に、平面視で外側に開口する凹部を形成するためのものである。
FIG. 4B is a plan view showing a different form of the substrate body 2m after the second hole forming step.
That is, as shown in FIG. 4B, in the ear portion Fa of the substrate body 2m, the three first positioning holes H1 formed in the first hole forming step are separated from each other on different sides. The surface conductor layer 5 having a predetermined pattern formed in the surface conductor layer forming step is located on the surface 3 of each substrate area 2a in the product area Pa. Furthermore, the plan view is rectangular across the planned cutting surface 9 that partitions the adjacent substrate areas 2a and the planned cutting surface 9 that partitions the board area 2a located on the outer peripheral side and the ear Fa. -Shaped through holes 12 were formed in the substrate body 2m by punching using a punch and a die (not shown) (second hole forming step). The through holes 12 are for forming recesses that open outward in a plan view on the side surfaces of the four sides of the obtained substrate body 2 when divided into individual substrate regions 2a.

図4(B)に示すように、前記製品領域Paの右上隅に位置する基板領域2aの右辺に位置する貫通穴12と、左下隅に位置する基板領域2aの下辺に位置する貫通穴12とは、何れも第2の位置決め穴H2を兼ねている。図示のように、かかる2つの第2の位置決め穴H2には、対角仮想直線L1が通過している。
また、上記製品領域Paの右上隅に位置する基板領域2aの右辺に位置する貫通穴12と、左上隅に位置する基板領域2aの左辺に位置する貫通穴12も、第2の位置決め穴H2を兼ねている。図示のように、かかる2つの第2の位置決め穴H2には、平行仮想直線L2が通過している。
As shown in FIG. 4B, a through hole 12 located on the right side of the substrate area 2a located in the upper right corner of the product area Pa and a through hole 12 located on the lower side of the board area 2a located in the lower left corner. Both also serve as the second positioning hole H2. As illustrated, the diagonal virtual straight line L1 passes through the two second positioning holes H2.
Further, the through hole 12 located on the right side of the board region 2a located at the upper right corner of the product area Pa and the through hole 12 located on the left side of the board region 2a located at the upper left corner also have the second positioning hole H2. Also serves as. As illustrated, the parallel virtual straight line L2 passes through the two second positioning holes H2.

更に、上記製品領域Paの右上隅に位置する基板領域2aの上辺に位置する貫通穴12と、右下隅に位置する基板領域2aの下辺に位置する貫通穴12も、第2の位置決め穴H2を兼ねている。図示のように、これら2つの位置決め穴H2にも、平行仮想直線L2が通過している。
以上の場合においても、複数の第2の位置決め穴H2を、前記対角仮想直線L1、あるいは前記平行仮想直線L2が通過する角領域Caごと内に設定することによって、前記のように、基板本体2mの貫通穴12を兼ねる複数の第2の位置決め穴H2を、平面視において互いに離間した位置ごとに容易に設定でき、且つ前記表面・裏面導体層5,6の位置決め精度を高めることが可能となる。
Further, the through hole 12 located on the upper side of the substrate area 2a located in the upper right corner of the product area Pa and the through hole 12 located on the lower side of the board area 2a located in the lower right corner also have the second positioning hole H2. Also serves as. As illustrated, the parallel virtual straight line L2 also passes through these two positioning holes H2.
Also in the above case, by setting a plurality of second positioning holes H2 within each corner area Ca through which the diagonal virtual straight line L1 or the parallel virtual straight line L2 passes, as described above, the substrate body It is possible to easily set the plurality of second positioning holes H2 also serving as the 2 m through holes 12 at respective positions separated from each other in plan view, and to improve the positioning accuracy of the front surface/back surface conductor layers 5, 6. Become.

図5(A)は、前記第2穴形成工程において、複数の第2位置決め穴H2の前記とは異なる設定方法を示す前記基板本体2mの平面図である。但し、製品領域Pa内に位置する基板領域2aごとの表面3の表面導体層5は、省略してある。
図5(A)に示すように、上記基板本体2mの平面視において、上記製品領域Paの左上隅および右上隅の角部を含む左右一対で且つ上側の2つの角領域Caと、前記製品領域Paの左下隅および右下隅の角部を含む左右一対で且つ下側の2つの角領域Caとからなる4つ角領域Caとが、予め設定されている。
図5(A)中において、下側に位置する2つの角領域Caには、上記製品領域Paの下辺に沿って平行で、且つ耳部Faを通過する平行仮想直線L2が通過し、該平行仮想直線L2上で且つ上記2つの角領域2a内ごとには、第2の位置決め穴H2が個別に形成されている。
FIG. 5A is a plan view of the substrate main body 2m showing a method of setting the plurality of second positioning holes H2 different from the above in the second hole forming step. However, the surface conductor layer 5 on the surface 3 of each substrate region 2a located in the product region Pa is omitted.
As shown in FIG. 5(A), in a plan view of the substrate body 2m, a pair of left and right upper two corner regions Ca including the upper left corner and the upper right corner of the product region Pa, and the product region. Four corner areas Ca, which are a pair of left and right corner areas Ca and a lower two corner areas Ca including corners at the lower left corner and the lower right corner of Pa, are set in advance.
In FIG. 5A, a parallel virtual straight line L2 that is parallel to the lower side of the product area Pa and passes through the ear portion Fa passes through the two corner areas Ca located on the lower side, and The second positioning hole H2 is individually formed on the virtual straight line L2 and in each of the two corner regions 2a.

一方、図5(A)で前記下側に位置する2つの角領域Caと対向する別の2つの角領域Caである上側の角領域Caごとには、前記製品領域Paの上辺に沿って平行で、且つ耳部Faを通過する別の対向仮想直線L3が通過し、該対向仮想直線L3上の中間(中点)に第2の位置決め穴H2が1つ形成されている。即ち、合計3つの第2の位置決め穴H2が前記平行仮想直線L2上および対向仮想直線L3上に形成されている。
また、図5(B)に示すように、前記対向仮想直線L3にも、前記下側の平行仮想直線L2と同様に、前記対向仮想直線L3が通過する2つの角領域2a内ごとに2つの第2の位置決め穴H2を上下対称に形成して、合計4つの第2の位置決め穴H2を有する形態としても良い。
前記図5(A),(B)で示した第2の位置決め穴H2の設定位置を採用した前記各工程による配線基板1の製造方法によっても、前記効果(1)乃至(3)を得ることが可能である。
On the other hand, for each upper corner area Ca, which is another two corner areas Ca facing the two corner areas Ca located on the lower side in FIG. 5(A), parallel to the upper side of the product area Pa. Further, another facing virtual straight line L3 that passes through the ear portion Fa also passes, and one second positioning hole H2 is formed in the middle (midpoint) on the facing virtual straight line L3. That is, a total of three second positioning holes H2 are formed on the parallel virtual straight line L2 and the opposing virtual straight line L3.
In addition, as shown in FIG. 5B, in the opposite virtual straight line L3 as well as in the lower parallel virtual straight line L2, two in each of the two corner regions 2a through which the opposite virtual straight line L3 passes. The second positioning holes H2 may be vertically symmetrically formed to have a total of four second positioning holes H2.
The effects (1) to (3) can also be obtained by the manufacturing method of the wiring board 1 according to each of the steps that employs the setting position of the second positioning hole H2 shown in FIGS. 5A and 5B. Is possible.

図6(A)は、前記第2穴形成工程において、複数の第2位置決め穴H2の更に異なる設定方法を示す前記基板本体2mの平面図である。但し、前記同様に、表面導体層5は、省略してある。
図6(A)に示すように、前記基板本体2mの平面視において、前記製品領域Paの四隅付近には、前記同様に、4つの角領域Caが設定されている。
また、前記製品領域Paの左下隅と右下隅との角部に位置する左右一対の角領域Caを通過する図示で下側の平行仮想直線L2と、該平行仮想直線L2が通過する2つの角領域Caと対向する別の2つの角領域Caである上記製品領域Paの左上隅と右上隅との角部に位置する左右一対の角領域Caを通過する図示で上側の対向仮想直線L3と、が設定されている。図示のように、下側の平行仮想直線L2が通過する左右一対の角領域Ca内であり、左下隅と右下隅とに位置する基板領域2a内ごとには、上記平行仮想直線L2上に第2の位置決め穴H2が2つ個別に形成されている。
FIG. 6A is a plan view of the substrate main body 2m showing a different setting method of the plurality of second positioning holes H2 in the second hole forming step. However, similarly to the above, the surface conductor layer 5 is omitted.
As shown in FIG. 6(A), in the plan view of the substrate body 2m, four corner regions Ca are set near the four corners of the product region Pa, similarly to the above.
Further, the lower virtual imaginary straight line L2 shown in the drawing passing through the pair of left and right corner regions Ca located at the corners of the lower left corner and the lower right corner of the product region Pa, and the two corners through which the virtual imaginary straight line L2 passes. An opposing virtual straight line L3 on the upper side in the drawing that passes through a pair of left and right corner regions Ca located at the corners of the upper left corner and the upper right corner of the product region Pa that is another two corner regions Ca facing the region Ca, Is set. As shown in the figure, it is within a pair of left and right corner regions Ca through which the lower parallel imaginary straight line L2 passes, and each of the substrate regions 2a located at the lower left corner and the lower right corner has a second position on the parallel imaginary straight line L2. Two positioning holes H2 are individually formed.

一方、図6(A)中で上側である対向仮想直線L3上の中間(中点)には、第2の位置決め穴H2が1つ形成されている。かかる第2の位置決め穴H2は、製品領域Pa内で隣接する2つの基板領域2a同士間の切断予定面9に跨がっており、追ってこれらを分割した際に得られる基板本体2の側面における凹部の一部を形成するものでもある。
以上のような形態でも、合計3つの第2の位置決め穴H2が、前記上下の平行仮想直線L2上および対向仮想直線L3上に形成されている。
また、図6(B)に示すように、上側の対向仮想直線L3上に形成される第2の位置決め穴H2は、前記下側の平行仮想直線L2と同様に、製品領域Paの左上隅と右上隅に位置する基板領域2a内であり、上記対向仮想直線L3上に、2つの第2の位置決め穴H2を個別に形成し、上記平行仮想直線L2上に形成した2つの位置決め穴H2と併せて、合計4つの第2の位置決め穴H2を有する形態としても良い。
前記図6(A),(B)で示した第2の位置決め穴H2の設定位置を採用した前記各工程による配線基板1の製造方法によっても、前記効果(1)乃至(3)を得ることが可能である。
On the other hand, one second positioning hole H2 is formed in the middle (midpoint) on the opposing virtual straight line L3 which is the upper side in FIG. 6(A). The second positioning hole H2 extends over the planned cutting surface 9 between the two adjacent substrate regions 2a in the product region Pa, and is formed on the side surface of the substrate body 2 obtained when these are divided later. It also forms part of the recess.
Also in the above-mentioned form, a total of three second positioning holes H2 are formed on the upper and lower parallel virtual straight lines L2 and the opposing virtual straight line L3.
Further, as shown in FIG. 6(B), the second positioning hole H2 formed on the upper facing virtual straight line L3 is located at the upper left corner of the product area Pa similarly to the lower parallel virtual straight line L2. In the substrate area 2a located in the upper right corner, two second positioning holes H2 are individually formed on the opposing virtual straight line L3, and combined with the two positioning holes H2 formed on the parallel virtual straight line L2. As a result, a configuration having a total of four second positioning holes H2 may be adopted.
The effects (1) to (3) can also be obtained by the manufacturing method of the wiring board 1 according to the above-described steps, which adopts the setting position of the second positioning hole H2 shown in FIGS. 6(A) and 6(B). Is possible.

本発明は、以上において説明した各形態に限定されるものではない。
例えば、前記絶縁層を構成する絶縁材には、前記アルミナ以外のセラミック(例えば、ムライト、窒化アルミニウム、ガラス−セラミック)や、エポキシ系などの樹脂を適用としても良い。前記ガラス−セラミックや樹脂とした場合、前記表面・裏面導体層5,6などの導体には、銅または銀が適用される。
また、前記複数の絶縁層は、セラミックからなる絶縁層と、樹脂からなる絶縁層とを積層した複合形態のものとしても良い。
更に、前記第1穴形成工程および第2穴形成工程は、適宜のレーザー光を照射するレーザー加工により行っても良い。
The present invention is not limited to the forms described above.
For example, a ceramic other than alumina (for example, mullite, aluminum nitride, glass-ceramic) or a resin such as an epoxy resin may be applied to the insulating material forming the insulating layer. When the glass-ceramic or resin is used, copper or silver is applied to the conductors such as the front and back conductor layers 5 and 6.
Further, the plurality of insulating layers may have a composite form in which an insulating layer made of ceramic and an insulating layer made of resin are laminated.
Furthermore, the first hole forming step and the second hole forming step may be performed by laser processing in which appropriate laser light is irradiated.

また、前記絶縁層の絶縁材が前記エポキシ系などの樹脂からなる場合、前記積層工程は、接着あるいはキュア(加熱)処理を伴って行っても良い。
更に、前記絶縁層の絶縁材が前記樹脂からなる場合、前記表面・裏面導体層5,6、内層配線7、およびビア導体8は、各種のフォトリソグラフィ技術によって形成される。
加えて、前記配線基板1の製造方法は、追って1つの配線基板1となる基板領域2a兼製品領域Paと、その周囲を囲む矩形枠状の耳部Faとからなる単数個取り用の基板本体を用いて行うことも可能である。
Further, when the insulating material of the insulating layer is made of the resin such as the epoxy resin, the laminating step may be performed along with adhesion or curing (heating) treatment.
Furthermore, when the insulating material of the insulating layer is made of the resin, the front and back surface conductor layers 5, 6, the inner layer wiring 7, and the via conductor 8 are formed by various photolithography techniques.
In addition, in the method for manufacturing the wiring board 1, the board body for single-piece production is composed of the board area 2a/product area Pa that will become one wiring board 1 later and the rectangular frame-shaped ear portion Fa that surrounds the area. It is also possible to use.

本発明によれば、複数の絶縁層を積層してなる基板本体の表面と裏面とにおける所定の位置ごとに表面導体層および裏面導体層を、位置精度良く形成できる配線基板の製造方法を提供できる。 ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the wiring board which can form a surface conductor layer and a back surface conductor layer with sufficient positional accuracy can be provided for every predetermined position in the surface and the back surface of the board|substrate main body which laminates|stacks several insulating layers. ..

1……………配線基板
2,2m……基板本体
3……………表面
4……………裏面
5……………表面導体層
6……………裏面導体層
7……………内層配線
8……………ビア導体
C1〜C3…セラミック層(絶縁層)
G1〜G3…グリーンシート(絶縁層)
H1…………第1の位置決め穴
H2…………第2の位置決め穴
Fa…………耳部
Pa…………製品領域
Ca…………角領域
L1…………対角仮想直線
L2…………平行仮想直線
L3…………対向仮想直線
1……………… Wiring board 2, 2m……Board body 3………………Front surface 4………………Back surface 5……………… Front conductor layer 6………………Back conductor layer 7…… …………Inner layer wiring ………………Via conductors C1 to C3... Ceramic layer (insulating layer)
G1 to G3... Green sheet (insulating layer)
H1…………First positioning hole H2…………Second positioning hole Fa…………Ear Pa…………Product area Ca…………Corner area L1…………Diagonal virtual straight line L2…………Parallel virtual straight line L3…………Opposed virtual straight line

Claims (6)

複数の絶縁層を積層してなり、且つ対向する表面および裏面を有する基板本体と、該基板本体の前記表面に形成された表面導体層と前記裏面に形成された裏面導体層とが平面視で互いに所定の位置ごとに形成されている配線基板の製造方法であって、
上記複数の絶縁層を準備する準備工程と、
上記複数の絶縁層ごとに第1の位置決め穴を形成する第1穴形成工程と、
上記複数の絶縁層のうち、少なくとも上記表面を構成する絶縁層の表面に上記表面導体層を形成する表面導体層形成工程と、
上記表面導体層が表面に形成された上記絶縁層を最表層とし、且つ上記第1の位置決め穴同士が積層方向に沿って重なるように、上記複数の絶縁層を積層し且つ圧着して基板本体を形成する積層工程と、
上記基板本体の表面と裏面との間を貫通する複数の第2の位置決め穴を、上記表面導体層を基準にして形成する第2穴形成工程と、
上記基板本体の裏面に、上記複数の第2の位置決め穴を基準として裏面導体層を形成する裏面導体層形成工程と、を含む、
ことを特徴とする配線基板の製造方法。
A substrate main body formed by stacking a plurality of insulating layers and having a front surface and a back surface facing each other, a front surface conductor layer formed on the front surface of the substrate main body, and a back surface conductor layer formed on the back surface are seen in a plan view. A method of manufacturing a wiring board formed at predetermined positions with each other,
A preparatory step of preparing the plurality of insulating layers,
A first hole forming step of forming a first positioning hole for each of the plurality of insulating layers;
Of the plurality of insulating layers, at least a surface conductor layer forming step of forming the surface conductor layer on the surface of the insulating layer constituting the surface,
The insulating layer having the surface conductor layer formed on the surface is used as the outermost layer, and the plurality of insulating layers are stacked and pressure-bonded so that the first positioning holes are overlapped with each other along the stacking direction. A stacking step for forming
A second hole forming step of forming a plurality of second positioning holes penetrating between the front surface and the back surface of the substrate body with reference to the surface conductor layer;
A back surface conductor layer forming step of forming a back surface conductor layer on the back surface of the substrate body with the plurality of second positioning holes as a reference.
A method of manufacturing a wiring board, comprising:
前記複数の絶縁層は、平面視で中央側に位置する矩形状の製品領域と、該製品領域の周囲を囲む矩形枠状の耳部とからなり、前記第1の位置決め穴および第2の位置決め穴は、前記耳部において異なる辺ごとに個別に形成されている、
ことを特徴とする請求項1に記載の配線基板の製造方法。
The plurality of insulating layers include a rectangular product region located on the center side in a plan view and rectangular frame-shaped ears surrounding the product region, and the first positioning hole and the second positioning The holes are individually formed for each different side in the ear portion,
The method of manufacturing a wiring board according to claim 1, wherein.
前記複数の絶縁層は、平面視で中央側に位置する矩形状の製品領域と、該製品領域の周囲を囲む矩形枠状の耳部とからなり、前記第1の位置決め穴は、前記耳部おいて異なる辺ごとに個別に形成されており、前記第2の位置決め穴は、上記製品領域に形成されている、
ことを特徴とする請求項1に記載の配線基板の製造方法。
The plurality of insulating layers includes a rectangular product region located on the center side in a plan view and a rectangular frame-shaped ear portion surrounding the periphery of the product region, and the first positioning hole includes the ear portion. And the second positioning hole is formed in the product area.
The method of manufacturing a wiring board according to claim 1, wherein.
前記複数の絶縁層は、平面視で中央側に位置する矩形状の製品領域と、該製品領域の周囲を囲む矩形枠状の耳部とからなり、前記第1の位置決め穴は、前記耳部おいて異なる辺ごとに個別に形成されており、前記第2の位置決め穴は、上記製品領域と上記耳部との境界に跨がっており、且つ平面視で前記耳部で異なる辺側に形成されている、
ことを特徴とする請求項1に記載の配線基板の製造方法。
The plurality of insulating layers includes a rectangular product region located on the center side in a plan view and a rectangular frame-shaped ear portion surrounding the periphery of the product region, and the first positioning hole includes the ear portion. Is formed separately for each side, the second positioning hole extends over the boundary between the product region and the ear portion, and is located on a different side of the ear portion in plan view. Is formed,
The method of manufacturing a wiring board according to claim 1, wherein.
前記第2の位置決め穴は、前記製品領域の四隅を含む4つの角領域のうち、平面視で対角位置にある2つの角領域を通過する対角仮想直線上に2つ以上が形成されているか、または、平面視で前記製品領域の辺と平行に向かい合う2つの角領域を通過する平行仮想直線上に2つ以上が形成され、且つ上記対角仮想直線上に1つ以上が形成されているか、または、平面視で上記平行仮想直線が通過する2つの角領域と対向する別の2つの角領域を通過する対向仮想直線上であり、上記製品領域の中点に形成され、且つ上記平行仮想直線上に2つ以上が形成されているか、あるいは、平面視で前記平行仮想直線上に2つ以上が形成され、且つ上記対向仮想直線上に2つ以上が形成されている、
ことを特徴とする請求項1乃至4の何れか一項に記載の配線基板の製造方法。
Of the four corner areas including the four corners of the product area, two or more of the second positioning holes are formed on a diagonal virtual straight line that passes through two corner areas diagonally located in a plan view. Or two or more are formed on a parallel virtual straight line that passes through two corner regions that face each other in parallel in a plan view, and one or more are formed on the diagonal virtual straight line. Or on an opposing virtual straight line that passes through another two corner regions that the two parallel virtual straight lines pass through in plan view, and that is formed at the midpoint of the product region and Two or more are formed on the virtual straight line, or two or more are formed on the parallel virtual straight line in plan view and two or more are formed on the opposing virtual straight line,
5. The method for manufacturing a wiring board according to claim 1, wherein
前記複数の絶縁層同士の層間には、内層配線が形成されており、該内層配線は、上記絶縁層を貫通するビア導体を介して、前記表面導体層および裏面導体層と個別に導通可能とされている、
ことを特徴とする請求項1乃至5の何れか一項に記載の配線基板の製造方法。
Inner layer wiring is formed between layers of the plurality of insulating layers, and the inner layer wiring can be individually conducted to the front surface conductor layer and the back surface conductor layer via a via conductor penetrating the insulating layer. Has been
The method for manufacturing a wiring board according to claim 1, wherein
JP2019005648A 2019-01-17 2019-01-17 Manufacturing method of wiring board Pending JP2020113725A (en)

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