JP2020088260A - Thin film capacitor and manufacturing method thereof - Google Patents

Abstract

To provide a thin film capacitor in which a lower layer dielectric layer is less likely to be damaged via voids, while preventing exfoliation of an electrode layer and the dielectric layer.SOLUTION: A thin film capacitor 1 is formed by laminating electrode layers 12, 14 and dielectric layers 11, 13 alternately. The electrode layer 12 has a first region 12a having double sides covered with the dielectric layers 11, 13, and a second region 12b having one surface exposed from the dielectric layer 13, and the other surface covered with the dielectric layer 11. Formation density of voids V contained in the second region 12b is lower than the formation density of voids V contained in the first region 12a. With such an arrangement, adhesion of the electrode layer and the dielectric layer is increased, because stress is released in the first region 12a, and the lower layer dielectric layer is less likely to be damaged via the voids in the second region 12b. With such an arrangement, reliability of the thin film capacitor can be increased.SELECTED DRAWING: Figure 2

Description

The present invention relates to a thin film capacitor and a method of manufacturing the same, and more particularly to a thin film capacitor that can be embedded in a circuit board for use and a method of manufacturing the same.

On a circuit board on which an IC is mounted, a decoupling capacitor is usually mounted in order to stabilize the potential of the power supply supplied to the IC. As the decoupling capacitor, a monolithic ceramic chip capacitor is generally used, and a large number of monolithic ceramic chip capacitors are mounted on the surface of a circuit board to secure a necessary decoupling capacitance.

However, in recent years, the space on the circuit board for mounting a large number of multilayer ceramic chip capacitors may become insufficient. Therefore, a thin film capacitor that can be embedded in a circuit board may be used instead of the multilayer ceramic chip capacitor (see Patent Documents 1 and 2).

In Patent Document 1, a plurality of electrode layers and a plurality of dielectric layers are alternately formed by using a sputtering method or the like, an opening for exposing a part of the electrode layers is formed in the dielectric layer, and then firing is performed. A method of making a thin film capacitor is described. Further, Patent Document 2 describes that platinum (Pt) is used as a material of the electrode layer.

JP, 2018-63989, A International Publication No. 2017/057422 Pamphlet

As described in Patent Document 1, when the dielectric layer is fired, the metal material forming the electrode layer may be aggregated and a void may be generated in the electrode layer. The voids generated in the electrode layer do not adversely affect the reliability of the product in the area sandwiched between the two dielectric layers, but rather the stress is released, so that the adhesion between the electrode layer and the dielectric layer is improved. Bring about the effect of increasing. However, if a void is formed in the opening, the underlying dielectric layer may be damaged through the void when the passivation film is patterned.

On the other hand, when platinum (Pt) is used as the material of the electrode layer as in the example described in Patent Document 2, almost no void is generated in the electrode layer even if firing is performed. In this case, since the internal stress of the electrode layer is not sufficiently released, the electrode layer may be peeled off from the dielectric layer.

Therefore, an object of the present invention is to provide a thin film capacitor which prevents the dielectric layer below from being damaged by a void while preventing the electrode layer and the dielectric layer from being separated from each other, and a manufacturing method thereof.

A thin film capacitor according to the present invention is a thin film capacitor in which a plurality of electrode layers including at least a first electrode layer and a plurality of dielectric layers including at least first and second dielectric layers are alternately laminated. , The first electrode layer has one surface covered with the first dielectric layer and the other surface covered with the second dielectric layer, and one surface having the first dielectric layer. The second region is exposed from the body layer and the other surface is covered with the second dielectric layer, and the formation density of the voids included in the second region is smaller than that of the voids included in the first region. It is characterized by being lower than the formation density.

The thin-film capacitor having the above structure has a plurality of electrode layers and a plurality of dielectric layers that are alternately formed into a first step, and an opening is provided in at least one of the plurality of dielectric layers to form a plurality of dielectric layers. A method of manufacturing a thin film capacitor, comprising a second step of exposing a part of a predetermined electrode layer included in an electrode layer, and a third step of firing a plurality of dielectric layers after performing the second step. In the above, it can be manufactured by forming a plurality of electrode layers and a plurality of dielectric layers while maintaining the first step at 300° C. or higher and 900° C. or lower.

According to the present invention, in the first region of the first electrode layer where both surfaces are covered with the dielectric layer, the void formation density is relatively high, and in the second region where one surface is exposed. Since the void formation density is relatively low, the stress is released in the first region, so that the adhesion between the electrode layer and the dielectric layer is enhanced, and in the second region, the lower layer is formed through the voids. The dielectric layer is less susceptible to damage. This makes it possible to increase the reliability of the thin film capacitor.

In the present invention, it is preferable that the second region does not include a void penetrating the first electrode layer. According to this, since the lower dielectric layer is not damaged through the void, it is possible to further improve the reliability.

In the present invention, the plurality of electrode layers contain nickel (Ni) as a main component, and platinum (Pt), ruthenium (Ru), rhenium (Re), palladium (Pd), iridium (Ir), tungsten (W), chromium. At least one element selected from the group consisting of (Cr), tantalum (Ta) and silver (Ag) may be added. According to this, it becomes possible to promote the generation of voids in the first region while suppressing the generation of voids in the second region. In this case, the plurality of electrode layers may contain nickel (Ni) as a main component, and 10 at% or more and 25 at% or less of platinum (Pt) may be added. According to this, it becomes possible to prevent the generation of voids penetrating the first electrode layer in the second region.

As described above, according to the present invention, it is possible to provide a thin film capacitor and a method for manufacturing the same in which the lower dielectric layer is less likely to be damaged by a void while preventing peeling of the electrode layer and the dielectric layer. Become.

FIG. 1 is a schematic sectional view showing the structure of a thin film capacitor 1 according to a preferred embodiment of the present invention. FIG. 2 is a plan view and a cross-sectional view showing an enlarged part of the electrode layer 12. FIG. 3 is a schematic cross-sectional view for explaining the definition of the void V. FIG. 4 is a process chart showing the method of manufacturing the thin film capacitor 1. FIG. 5 is a process chart showing the method of manufacturing the thin film capacitor 1. FIG. 6 is a process chart showing the method of manufacturing the thin film capacitor 1. FIG. 7 is a process chart showing the method of manufacturing the thin film capacitor 1. FIG. 8 is a process chart showing the method of manufacturing the thin film capacitor 1. FIG. 9 is a process chart showing the method of manufacturing the thin film capacitor 1. FIG. 10 is a process chart showing the method of manufacturing the thin film capacitor 1. FIG. 11 is a graph showing conditions under which the void V is formed in the first region 12a and conditions under which the void V is not formed in the second region 12b.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic sectional view showing the structure of a thin film capacitor 1 according to a preferred embodiment of the present invention.

As shown in FIG. 1, the thin film capacitor 1 according to the present embodiment has a capacitive structure including a conductive substrate 10 and a dielectric layer 11, an electrode layer 12, a dielectric layer 13 and an electrode layer 14 which are stacked on the surface of the conductive substrate 10 in this order. It includes a body 2, a rewiring structure 3 covering the capacitive structure 2, and terminals 51 to 53 provided on the surface of the rewiring structure 3.

The conductive substrate 10 is made of a refractory metal such as nickel (Ni) and functions as a support for ensuring the mechanical strength of the thin film capacitor 1 according to the present embodiment, and also as a part of the electrode layer of the capacitor. Function.

The dielectric layers 11 and 13 are made of, for example, a perovskite-based dielectric material. Perovskite-based dielectric materials include BaTiO ₃ (barium titanate), (Ba _1-X Sr _X )TiO ₃ (barium strontium titanate), (Ba _1-X Ca _X )TiO ₃ , PbTiO ₃ , Pb( (Ferroelectric) dielectric material having a perovskite structure such as Zr _X Ti _1-X )O ₃ or a composite perovskite relaxor type ferroelectric material typified by Pb(Mg _1/3 Nb _2/3 )O _{3. and, Bi 4 Ti 3 O 12,} SrBi 2 Ta 2 O bismuth layer compound typified by _{9, (Sr 1-X Ba} X) Nb 2 O 6, PbNb tungsten bronze type ferroelectric typified like ₂ O ₆ Examples include dielectric materials. Here, in the perovskite structure, the perovskite relaxor type ferroelectric material, the bismuth layered compound, and the tungsten bronze type ferroelectric material, the A site and B site ratio are usually integer ratios. You may deviate from the integer ratio. In order to control the characteristics of the dielectric layers 11 and 13, the dielectric layers 11 and 13 may appropriately contain an additive substance as a subcomponent. The dielectric layers 11 and 13 have been fired, and their relative permittivity (ε _r ) is, for example, 100 or more. The higher the relative permittivity of the dielectric layers 11 and 13, the better, and the upper limit thereof is not particularly limited. The thickness of each of the dielectric layers 11 and 13 is, for example, about 10 nm to 1000 nm.

The electrode layers 12 and 14 have nickel (Ni) as a main component, and platinum (Pt), ruthenium (Ru), rhenium (Re), palladium (Pd), iridium (Ir), tungsten (W), chromium (Cr). , A tantalum (Ta), and a silver (Ag) metal material to which at least one element selected from the group consisting of is added. Although the details will be described later, the addition of an element such as platinum (Pt) to nickel (Ni), which is the main component, is due to the fact that both sides of the electrode layer 12 are sandwiched between the dielectric layers 11 and 13. This is to promote the formation of voids in the first region and suppress the formation of voids in the second region where the upper surface side is exposed without being covered with the dielectric layer 13. Here, when platinum (Pt) is selected as an element to be added to nickel (Ni), the voids in the first region are set by adjusting the amount of platinum (Pt) added to 10 at% or more and 25 at% or less of the whole. It is possible to effectively suppress the formation of voids in the second region while effectively promoting the formation of the voids. The thickness of each of the electrode layers 12 and 14 is, for example, about 10 nm to 1000 nm.

As shown in FIG. 1, the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14 are provided with openings A1 that expose the surface of the conductive substrate 10. Further, the dielectric layer 13 and the electrode layer 14 are provided with an opening A2 that exposes the surface of the electrode layer 12.

The rewiring structure 3 includes a passivation layer 20, a first insulating layer 21, a second insulating layer 22, first wiring layers 31 to 33, and second wiring layers 41 to 43. The passivation layer 20 is made of, for example, an inorganic insulating material such as silicon oxide (SiO ₂ ), and is formed on the entire surface of the capacitive structure 2 except the openings B1 to B3. The first insulating layer 21 and the second insulating layer 22 are made of an organic insulating material such as resin. First wiring layers 31 to 33 are formed on the surface of the first insulating layer 21, and second wiring layers 41 to 43 are formed on the surface of the second insulating layer 22.

Here, the first wiring layers 31 to 33 are connected to the conductive substrate 10, the electrode layer 12, and the electrode layer 14 via the openings B1 to B3, respectively. The second wiring layers 41 to 43 are connected to the first wiring layers 31 to 33 via the openings C1 to C3, respectively. Then, the second wiring layers 41 to 43 are connected to the terminals 51 to 53, respectively. As a result, the terminal 51 is connected to the conductive substrate 10, the terminal 52 is connected to the electrode layer 12, and the terminal 53 is connected to the electrode layer 14. Therefore, the thin film capacitor 1 according to the present embodiment can use the terminals 51 and 53 as one electrode and the terminal 52 as the other electrode.

As a material forming the terminals 51 to 53, it is preferable to use a metal material containing nickel (Ni), copper (Cu), gold (Au), platinum (Pt) or an alloy containing these metals as a main component. In particular, it is preferable to use copper (Cu). When copper (Cu) is used as the material of the terminals 51 to 53, the higher the purity, the more preferable, and the purity of 99.99% by mass or more is preferable. When copper (Cu) is used as the material of the terminals 51 to 53, as impurities, iron (Fe), titanium (Ti), nickel (Ni), aluminum (Al), magnesium (Mg), manganese (Mn), silicon ( Si) or chromium (Cr), vanadium (V), zinc (Zn), niobium (Nb), tantalum (Ta) yttrium (Y), lanthanum (La), cesium (Ce) and other transition metal elements or rare earth elements, etc. , Chlorine (Cl), sulfur (S), phosphorus (P), etc. may be contained.

FIG. 2 is a plan view and a cross-sectional view showing an enlarged part of the electrode layer 12.

As shown in FIG. 2, the electrode layer 12 has a first region 12a whose both surfaces are covered with the dielectric layers 11 and 13, and an upper surface which is not covered with the dielectric layer 11 and whose lower surface is covered with the dielectric layer 13. The exposed second region 12b is included. The second region 12b is a region exposed from the dielectric layer 13 through the opening A2. The present embodiment is characterized in that the formation density of voids V included in the second region 12b is lower than the formation density of voids V included in the first region 12a. The void V refers to a space formed as a result of being separated from the dielectric layers 11 and 13 when the surface of the electrode layer 12 is recessed. A typical void V penetrates the electrode layer 12.

However, all the depressions on the surface of the electrode layer 12 do not correspond to the void V, and a slight depression does not correspond to the void V defined by the present invention. Specifically, as shown in FIG. 3A, the void V1 penetrating the electrode layer 12 corresponds to the void V defined in the present invention. As shown in FIG. 3B, a void V2 that does not penetrate the electrode layer 12 but has a depth D1 of 30% or more of the thickness T of the electrode layer 12 also corresponds to the void V defined by the present invention. To do. On the other hand, as shown in FIG. 3C, the slight depression V3 having the depth D2 of less than 30% of the thickness T of the electrode layer 12 does not correspond to the void V defined by the present invention.

The present embodiment is characterized in that the formation density of the void V (V1 or V2) thus defined is lower in the second region 12b than in the first region 12a. In particular, it is preferable that the second region 12b does not include the void V1 penetrating the electrode layer 12. Thereby, in the first region 12a sandwiched between the dielectric layers 11 and 13, the stress is released by the void V, so that the adhesion between the electrode layer 12 and the dielectric layers 11 and 13 is enhanced, As a result, peeling between the electrode layer 12 and the dielectric layers 11 and 13 is less likely to occur. On the other hand, in the second region 12b exposed from the dielectric layer 13, the formation density of the voids V is low, and preferably the voids V1 penetrating the electrode layer 12 are not included. Therefore, the passivation layer 20 and the first insulating layer When the layer 21 is patterned, the lower dielectric layer 11 is less likely to be damaged via the void V. As a result, the thin film capacitor 1 according to the present embodiment can ensure high reliability.

Next, the method of manufacturing the thin film capacitor 1 according to the present embodiment will be explained.

4 to 10 are process diagrams showing the method of manufacturing the thin film capacitor 1 according to the present embodiment.

First, as shown in FIG. 4, a dielectric layer 11, an electrode layer 12, a dielectric layer 13 and an electrode layer 14 are formed in this order on the surface of a conductive substrate 10 made of nickel (Ni) or the like. Examples of the method for forming the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14 include DC sputtering. In this case, a first sputtering chamber targeting a perovskite-type dielectric material and a second sputtering chamber targeting a metal material containing nickel (Ni) as a main component are prepared, and the first and second sputtering chambers are prepared. By alternately using the sputtering chambers, the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14 can be formed in this order. At that time, the dielectric layer 11, the electrode layer 12, the dielectric layer 13 and the dielectric layer 11, the electrode layer 12, and the second sputtering chamber are alternately used while maintaining the temperature of the conductive substrate 10 at 300° C. or higher and 900° C. or lower. It is preferable to form the electrode layer 14.

Generally, the film-forming temperature required for sputtering a perovskite-based dielectric material is about 400° C., whereas the film-forming temperature for sputtering a metal material containing nickel (Ni) as a main component is From room temperature to a hundred and several tens of degrees Celsius is sufficient. Therefore, according to a general manufacturing method, when the dielectric layers 11 and 13 are formed, the temperature of the conductive substrate 10 is heated to about 400° C., and the electrode layers 12 and 14 are formed. The temperature of the conductive substrate 10 is cooled to room temperature to about a hundred and several tens of degrees Celsius, but in the present embodiment, the temperature of the conductive substrate 10 is set to 300° C. or higher and 900° C. or lower, typically about 400° C. The dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14 are sequentially formed in the state of being maintained. By forming the film under such a temperature condition, the formation of voids in the first region 12a is promoted and the formation of voids in the second region 12b is suppressed in the firing step described later.

Next, as shown in FIG. 5, the openings A1 and A2 are formed by patterning the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14. Of these, the opening A1 is a portion where the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14 are removed, and the surface of the conductive substrate 10 is exposed in the opening A1. On the other hand, the opening A2 is a portion where the dielectric layer 13 and the electrode layer 14 are removed, and the surface of the electrode layer 12, that is, the second region 12b is exposed in the opening A2.

After forming the openings A1 and A2, firing is performed to sinter the dielectric layers 11 and 13. The firing temperature is preferably a temperature at which the dielectric material forming the dielectric layers 11 and 13 is sintered (crystallized), and is about 800 to 1000° C. when a perovskite-based dielectric material is used. Preferably. Further, the firing time can be about 5 minutes to 2 hours. The atmosphere at the time of firing is not particularly limited and may be any of an oxidizing atmosphere, a reducing atmosphere and a neutral atmosphere, but it is preferable to fire at least under an oxygen partial pressure at which the electrode layers 12 and 14 are not oxidized.

In the firing step, the metal material forming the electrode layers 12 and 14 is aggregated. As a result, a large number of voids V are generated in the first region 12a of the electrode layer 12, both surfaces of which are covered with the dielectric layers 11 and 13, thereby releasing the internal stress in the first region 12a. .. On the other hand, in the second region 12b of the electrode layer 12 exposed from the opening A2, almost no void V is generated. On the other hand, with respect to the uppermost electrode layer 14, since the entire upper surface thereof is exposed, almost no void V is generated as in the second region 12b.

As described above, the selective formation of such a void V is mainly composed of nickel (Ni) as a material of the electrode layers 12 and 14, and platinum (Pt), ruthenium (Ru), rhenium (Re), palladium ( Pd), iridium (Ir), tungsten (W), chromium (Cr), tantalum (Ta), and at least one element selected from the group consisting of silver (Ag) are added, and the conductive substrate 10 is added to 300 It is realized by forming the dielectric layer 11, the electrode layer 12, the dielectric layer 13 and the electrode layer 14 in a state of being maintained at not lower than 900° C. and not higher than 900° C., typically about 400° C.

Through the above steps, the capacitive structure 2 is completed.

Next, as shown in FIG. 6, a passivation layer 20 is formed on the entire surface of the capacitive structure 2. When silicon oxide (SiO ₂ ) is used as the material of the passivation layer 20, it can be formed by a sputtering method.

Next, as shown in FIG. 7, after removing the passivation layer 20 in the portions corresponding to the openings A1 and A2 by patterning, a first insulating layer 21 is formed on the entire surface, and the opening portions are further formed in the first insulating layer 21. B1 to B3 are formed. The openings B1 and B2 are provided at positions corresponding to the openings A1 and A2, respectively, and the opening B3 is provided at a position where the electrode layer 14 is exposed. As a result, the conductive substrate 10 is exposed through the opening B1, the electrode layer 12 is exposed through the opening B2, and the electrode layer 14 is exposed through the opening B3. Here, when the passivation layer 20 is patterned or the first insulating layer 21 is patterned, the conductive substrate 10 and the electrode layers 12 and 14 function as stoppers, but voids V are formed in the exposed portions of the electrode layers 12 and 14. Especially, if there is a void V1 penetrating the electrode layers 12 and 14, the lower dielectric layers 11 and 13 are damaged during patterning. However, in this embodiment, since almost no voids are present in the exposed portions of the electrode layers 12 and 14, it is possible to suppress damage to the dielectric layers 11 and 13.

It is desirable that voids V do not exist at all in the exposed portions of the electrode layers 12 and 14, but at least if the formation density of the voids V in the first region 12a of the electrode layer 12 is lower than the dielectric layers 11 and 13. It is possible to reduce the damage of. Further, since the void V2 shown in FIG. 3B does not penetrate the electrode layer 12, it does not damage the dielectric layer 11 at the initial stage of patterning, but when the electrode layer 12 is damaged by overetching, The non-penetrating void V2 may progress to the penetrating void V1. Considering this point, it is preferable that not only the through void V1 but also the non-through void V2 do not exist in the exposed portions of the electrode layers 12 and 14.

Next, as shown in FIG. 8, first wiring layers 31 to 33 are formed. Specifically, a metal material made of copper (Cu) or the like is formed on the entire surface and then patterned to separate the first wiring layers 31 to 33 into three first wiring layers. The first wiring layer 31 is connected to the conductive substrate 10 via the opening B1, the first wiring layer 32 is connected to the electrode layer 12 via the opening B2, and the first wiring layer 33 is connected via the opening B3. Connected to the electrode layer 14.

Next, as shown in FIG. 9, after forming the second insulating layer 22, the openings C1 to C3 are formed in the second material layer 22. The openings C1 to C3 are provided at positions exposing the first wiring layers 31 to 33, respectively.

Next, as shown in FIG. 10, second wiring layers 41 to 43 are formed. Specifically, a metal material made of copper (Cu) or the like is formed on the entire surface, and then the metal material is patterned to separate the two second wiring layers 41 to 43. The second wiring layers 41 to 43 are connected to the first wiring layers 31 to 33 via the openings C1 to C3, respectively.

Then, by forming the terminals 51 to 53 on the second wiring layers 41 to 43, respectively, the thin film capacitor 1 shown in FIG. 1 is completed.

As described above, in the method for manufacturing the thin-film capacitor 1 according to the present embodiment, after forming the openings A1 and A2 in the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14, the dielectric layer is formed. Since 11 and 13 are fired, the electrode layer 12 has a first region 12a covered with the dielectric layer 13 and a second region 12b exposed from the dielectric layer 13 under different environments. Is heated in. Then, in the present embodiment, nickel (Ni) is a main component as a material of the electrode layers 12 and 14, and platinum (Pt), ruthenium (Ru), rhenium (Re), palladium (Pd), iridium (Ir), At least one element selected from the group consisting of tungsten (W), chromium (Cr), tantalum (Ta), and silver (Ag) is added, and the conductive substrate 10 is typically 300° C. or higher and 900° C. or lower, typically Specifically, since the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14 are formed while being maintained at about 400° C., voids in the first region 12a are formed in the firing step. The formation can be promoted and the formation of voids in the second region 12b can be suppressed.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention. It goes without saying that it is included in the range.

For example, the thin-film capacitor 1 according to the above embodiment has a structure in which the two dielectric layers 11 and 13 and the two electrode layers 12 and 14 are alternately laminated. The number of layers is not limited to this. Further, it is not essential that the substrate is made of a conductive material.

By actually performing the steps shown in FIGS. 4 and 5, the presence and number of voids V generated in the electrode layer 12 were evaluated. The composition of the metal material forming the electrode layer 12 and the film thickness of the electrode layer 12 were set to different combinations for each sample. The film formation of the dielectric layer 11, the electrode layer 12, the dielectric layer 13, and the electrode layer 14 was performed by the sputtering method while maintaining the temperature at about 400° C. in all the samples.

The results are shown in Table 1. Regarding the first region 12a, the case where two or more voids V exist is evaluated as ◯, the case where one void V exists is evaluated as Δ, and the case where no void V exists is evaluated as x. On the other hand, regarding the second region 12b, the case where the void V does not exist was evaluated as ◯, the case where one void V existed was evaluated as Δ, and the case where two or more voids V existed was evaluated as x.

As shown in Table 1, in Samples 1 to 14 in which the amount of platinum (Pt) added was 25 at% or less, two or more voids V were generated in the first region 12a, and the stress was sufficiently released. However, in Sample 15 in which the amount of platinum (Pt) added is 30 at %, the number of voids V generated in the first region 12 a is one, and the amount of platinum (Pt) added is 35 at %. In sample 16, no void V was generated in the first region 12a.

On the other hand, in Samples 7 to 16 in which the amount of platinum (Pt) added was 12 at% or more, no void V was generated in the second region 12b. Further, in Sample 6 in which the amount of platinum (Pt) added was 10 at% and the film thickness was 500 nm, no void V was generated in the second region 12b. On the other hand, in Samples 1 to 4 in which the amount of platinum (Pt) added is 5 at% or less, and in Sample 5 in which the amount of platinum (Pt) added is 10 at% and the film thickness is 200 nm, One or more voids V were generated in the second region 12b.

Thus, in order to sufficiently generate the void V in the first region 12a, it is necessary to suppress the amount of platinum (Pt) added to nickel (Ni), while the void V in the second region 12b is reduced. It can be understood that it is necessary to increase the amount of platinum (Pt) added to nickel (Ni) in order to prevent the generation. Specifically, by setting the addition amount of platinum (Pt) to 10 at% or more and 25 at% or less, the void V is sufficiently generated in the first region 12a, while the void V is generated in the second region 12b. Can be prevented.

Here, when the amount of platinum (Pt) added is 10 at %, the presence or absence of the void V in the second region 12 b depends on the film thickness of the electrode layer 12. That is, in the present embodiment, when the amount of platinum (Pt) added is 10 at %, the void V is not formed in the second region 12 b when the film thickness of the electrode layer 12 is 500 nm, and the film of the electrode layer 12 is not formed. The result is that one void V is formed in the second region 12b when the thickness is 20 nm.

FIG. 11 is a graph showing a condition that the void V is formed in the first region 12a and a condition that the void V is not formed in the second region 12b, and the horizontal axis represents platinum (Pt) added to nickel (Ni). And the vertical axis represents the film thickness of the electrode layer 12. The plot points indicated by (3) indicate the upper limit value at which the void V is formed in the first area 12a, and the plot points indicated by (♦) indicate the lower limit value at which the void V is not formed in the second area 12b. .. The curve H is an approximate curve of the plot points indicated by ▪, and the curve L is an approximate curve of the plot points indicated by ◆. Therefore, the void V is not formed in the first region 12a under the condition of exceeding the curve H, while the void V is generated in the second region 12b under the condition of exceeding the curve L. Therefore, in order to prevent the formation of the void V in the first region 12a and the formation of the void V in the second region 12b, the amount of platinum (Pt) added to nickel (Ni) and the electrode layer It is understood that it is necessary to set the film thickness of 12 within the range of the condition M shown in FIG.

1 Thin Film Capacitor 2 Capacitance Structure 3 Rewiring Structure 10 Conductive Substrates 11, 13 Dielectric Layers 12, 14 Electrode Layer 12a First Region 12b Second Region 20 Passivation Layer 21 First Insulating Layer 22 Second Insulating Layer 31-33 1st wiring layers 41-43 2nd wiring layers 51-53 Terminals A1, A2, B1-B3, C1-C3 Openings V, V1, V2 Void V3 Recess

Claims (5)

A thin film capacitor comprising a plurality of electrode layers including at least a first electrode layer and a plurality of dielectric layers including at least first and second dielectric layers,
The first electrode layer has a first region in which one surface is covered with the first dielectric layer and the other surface is covered with the second dielectric layer, and one surface is the first region. A second region exposed from one dielectric layer and the other surface covered with the second dielectric layer;
The thin film capacitor, wherein the void formation density included in the second region is lower than the void formation density included in the first region. The thin film capacitor according to claim 1, wherein the second region does not include a void penetrating the first electrode layer. The plurality of electrode layers contain nickel (Ni) as a main component, and platinum (Pt), ruthenium (Ru), rhenium (Re), palladium (Pd), iridium (Ir), tungsten (W), chromium (Cr). 3. The thin film capacitor according to claim 1, wherein at least one element selected from the group consisting of, tantalum (Ta), and silver (Ag) is added. 4. The thin film capacitor according to claim 3, wherein the plurality of electrode layers contain nickel (Ni) as a main component, and platinum (Pt) of 10 at% or more and 25 at% or less is added. A first step of alternately depositing a plurality of electrode layers and a plurality of dielectric layers;
A second step of exposing a part of a predetermined electrode layer included in the plurality of electrode layers by providing an opening in at least one of the plurality of dielectric layers;
A third step of firing the plurality of dielectric layers after performing the second step,
The first step is a method of manufacturing a thin film capacitor, wherein the plurality of electrode layers and the plurality of dielectric layers are formed while being maintained at 300° C. or higher and 900° C. or lower.

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