JP2020068331A - Semiconductor device - Google Patents

Abstract

To suppress the formation of voids inside a solder layer that joins a semiconductor device and a conductor member.SOLUTION: A semiconductor device disclosed in the present specification includes a semiconductor substrate and a solder electrode arranged on the semiconductor substrate. The surface of the solder electrode has a first range in which a first metal material is exposed and a second range in which a second metal material is exposed, and the first metal material has higher solder wettability than the second metal material. The ratio of the area of the first range to the area of the second range decreases from the center of the surface toward the outer peripheral edge of the surface.SELECTED DRAWING: Figure 2

Description

  The technology disclosed in this specification relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device. The semiconductor device includes a semiconductor substrate and a solder electrode arranged on the semiconductor substrate.

JP, 2007-189214, A

  The above semiconductor device is used in a semiconductor module. At that time, the soldering electrodes of the semiconductor device and other constituent parts (for example, a conductor member or the like) constituting the semiconductor module are joined by soldering. In this soldering, formation of voids inside the solder has been a problem. This is because gas (for example, hydrogen or argon) is generated or air is introduced from the solder electrode or the conductor member while the solder is melted. In particular, the melting of the solder located between the semiconductor device and the conductor member proceeds from the peripheral edge of the solder where the temperature easily rises toward the center. Therefore, soldering (that is, formation of an intermetallic compound) also progresses from the peripheral edge of the solder electrode toward the center, so that voids are likely to occur inside the solder on the center side of the solder electrode. Hard to be released to the outside. As a result, relatively large voids may be formed inside the solidified solder. The present specification provides a technique for suppressing the formation of voids inside a solder layer that joins a semiconductor device and a conductor member.

  A semiconductor device disclosed in the present specification includes a semiconductor substrate and a solder electrode arranged on the semiconductor substrate. The surface of the solder electrode has a first range in which the first metal material is exposed and a second range in which the second metal material is exposed, and the first metal material is more than the second metal material. High solder wettability. The ratio of the area of the first range to the area of the second range decreases from the center of the surface toward the outer peripheral edge of the surface.

  In the above semiconductor device, the surface of the solder electrode has a first range in which the first metal material is exposed and a second range in which the second metal material is exposed. The first metal material has higher solder wettability than the second metal material, and the ratio of the area of the first range to the area of the second range is from the center of the surface of the solder electrode to the outside of the surface of the solder electrode. It decreases as it goes to the periphery. As a result, the substantial solder wettability on the surface of the solder electrode is high on the center side where the area ratio of the first range is large, and decreases toward the peripheral edge. Therefore, when the solder is melted between the soldering electrode and the conductor member, the wetting and spreading of the solder with respect to the soldering electrode progresses first on the center side and then expands toward the peripheral edge. As a result, even if voids are generated in the molten solder, the voids gradually move from the center side to the peripheral edge and are easily released to the outside of the solder. As a result, formation of voids is suppressed inside the solder layer that joins the semiconductor device and the conductor member.

Sectional drawing which shows the internal structure of the semiconductor module 50 of an Example. The bottom view of semiconductor device 10 showing the composition of the surface of bottom electrode 10b. The schematic diagram of the semiconductor module 50 which shows the structure of the lower surface electrode 10b. The process of heating the laminated body 40 and melting the solder 36 is shown. The process of heating the laminated body 40 and melting the solder 36 is shown. The process of heating the laminated body 40 and melting the solder 36 is shown. The state where the stacked body 40 is removed of heat and the solder 36 is solidified is shown. The bottom view of semiconductor device 10 showing the modification of composition of the surface of bottom electrode 10b.

  A semiconductor device 10 of an embodiment and a semiconductor module 50 using the same will be described with reference to the drawings. The semiconductor module 50 is mounted in an electronic control circuit mounted in, for example, an electric vehicle, a hybrid vehicle, a fuel cell vehicle, or the like. As shown in FIG. 1, the semiconductor module 50 includes a semiconductor device 10, a conductor spacer 22, an upper heat dissipation plate 24, a lower heat dissipation plate 26, and a sealing body 28. The semiconductor device 10, the conductor spacer 22, the upper heat dissipation plate 24, and the lower heat dissipation plate 26 are integrally sealed by a sealing body 28. The sealing body 28 is made of, for example, a thermosetting resin material such as an epoxy resin. The semiconductor module 50 also includes a plurality of external connection terminals (not shown) extending from the inside of the sealing body 28 to the outside. The semiconductor device 10 is electrically connected to a plurality of external connection terminals inside the sealing body 28.

  The semiconductor device 10 includes a semiconductor substrate 12, an upper surface electrode 10a, and a lower surface electrode 10b. The upper surface electrode 10 a is located on the upper surface of the semiconductor substrate 12, and the lower surface electrode 10 b is located on the lower surface of the semiconductor substrate 12. The semiconductor substrate 12 can be configured using various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). As a material forming the upper surface electrode 10a and the lower surface electrode 10b, for example, nickel (Ni) -based material or another metal can be adopted. The nickel-based metal here indicates pure nickel or an alloy containing nickel as a main component. The characteristic structure of the lower surface electrode 10b will be described later. The semiconductor device 10 is a power semiconductor device and is, for example, an IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor device 10 is not limited to the IGBT, and another power semiconductor device such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a diode may be adopted. Further, the semiconductor device 10 is not limited to the configuration of a single power semiconductor device, and may be configured by combining different types of power semiconductor devices such as an RC-IGBT (Reverse Conducting IGBT) including an IGBT and a diode therein. .

  The conductor spacer 22 is located above the semiconductor device 10. The conductor spacer 22 is a conductor member having a generally plate shape or a block shape, and is made of, for example, copper (Cu) or another metal. The conductor spacer 22 has an upper surface and a lower surface opposite to the upper surface. The upper surface of the conductor spacer 22 is joined to the lower surface of an upper heat dissipation plate 24 described later via a solder layer 32. The lower surface of the conductor spacer 22 is bonded to the upper surface electrode 10 a of the semiconductor device 10 via the solder layer 34. That is, the conductor spacer 22 is electrically and thermally connected to the semiconductor device 10.

  The upper heat dissipation plate 24 is located above the conductor spacer 22. The upper heat dissipation plate 24 is a conductor member having a plate shape or a rectangular parallelepiped shape, and is made of, for example, copper or another metal. The upper heat dissipation plate 24 has an upper surface and a lower surface opposite to the upper surface. The lower surface of the upper heat dissipation plate 24 is joined to the upper surface of the conductor spacer 22 via the solder layer 32. That is, the upper heat dissipation plate 24 is electrically and thermally connected to the semiconductor device 10 via the conductor spacer 22. The upper surface of the upper heat dissipation plate 24 is exposed to the outside on the upper surface of the sealing body 28.

  The lower heat dissipation plate 26 is located below the semiconductor device 10. The lower heat dissipation plate 26 is a conductor member having a plate shape or a rectangular parallelepiped shape, and is made of, for example, copper or another metal. The lower heat dissipation plate 26 has an upper surface and a lower surface opposite to the upper surface. As an example, the upper surface of the lower heat dissipation plate 26 has a nickel-based metal layer 38. The upper surface of the lower heat dissipation plate 26 is bonded to the lower surface electrode 10b of the semiconductor device 10 via the solder layer 36. That is, the lower heat dissipation plate 26 is electrically and thermally connected to the semiconductor device 10. The lower surface of the lower heat dissipation plate 26 is exposed to the outside on the lower surface of the sealing body 28. Therefore, the upper heat dissipation plate 24 and the lower heat dissipation plate 26 also function as heat dissipation plates that radiate the heat generated in the semiconductor device 10 to the outside.

  The structure of the lower surface electrode 10b will be described with reference to FIGS. The lower surface electrode 10b includes a first metal layer 20, a second metal layer 18, a third metal layer 16 and a fourth metal layer 14. These metal layers 14, 16, 18, 20 are laminated on the semiconductor substrate 12 in the order of the fourth metal layer 14, the third metal layer 16, the second metal layer 18, and the first metal layer 20. The first metal layer 20 is made of a metal having a high solder wettability, such as gold (Au). The second metal layer 18 is made of, for example, nickel, which is a metal having excellent bondability with solder.

  The third metal layer 16 is made of, for example, titanium (Ti) or another metal. The fourth metal layer 14 is made of, for example, an aluminum (Al) -based or other metal material. The aluminum-based metal here refers to pure aluminum or an alloy containing aluminum as a main component (for example, an aluminum-silicon (Al-Si) -based alloy). As an example, the thickness dimensions of the first metal layer 20, the second metal layer 18, the third metal layer 16 and the fourth metal layer 14 are about 0.05 μm, about 1 μm, about 0.2 μm and about 0. It may be about 8 μm.

  The first metal layer 20 covers not the entire surface of the second metal layer 18 but a part of the second metal layer 18. As a result, the surface of the lower surface electrode 10b has a first range R1 in which the first metal layer 20 is exposed and a second range R2 in which the second metal layer 18 is exposed. As described above, the first metal layer 20 is made of a metal material having excellent solder wettability and has a higher solder wettability than the second metal layer 18. The solder wettability as used herein refers to the affinity for solder. For example, when the solder wettability is high, the affinity for the solder is high, and the solder is likely to wet and spread on the surface in contact with the solder (in this case, the surface of the lower surface electrode 10b).

  As shown in FIG. 2, the first metal layer 20 is radially patterned on the second metal layer 18. That is, the first range R1 extends radially toward the peripheral edge with the center of the surface of the lower surface electrode 10b as a base point. The second range R2 where the second metal layer 18 is exposed is a range other than the first range R1 on the surface of the lower surface electrode 10b. Thereby, on the surface of the lower surface electrode 10b, the ratio of the area of the first range R1 to the area of the second range R2 decreases from the center of the surface toward the outer peripheral edge.

  With such a configuration, the substantial solder wettability on the surface of the lower surface electrode 10b is high on the center side where the area ratio of the first range R1 is large, and becomes lower toward the peripheral edge. Therefore, when the solder is melted between the lower surface electrode 10b and the lower heat dissipation plate 26, the wetting and spreading of the solder with respect to the lower surface electrode 10b proceeds first on the center side and then expands toward the peripheral edge. . As a result, even if voids are generated in the molten solder, the voids gradually move from the center side to the peripheral edge as the solder spreads and spreads from the center side to the peripheral edge. Easily released to the outside. As a result, formation of voids is suppressed inside the solder layer 36 that joins the semiconductor device 10 and the lower heat dissipation plate 26.

  Here, the lower surface electrode 10b is an example of the "solder electrode" in the technique disclosed in this specification. The material forming the first metal layer 20 and the material forming the second metal layer 18 are examples of the “first metal material” and the “second metal material” in the technology disclosed in this specification. . The specific configuration described above is an example, and can be variously modified. For example, the first metal layer 20 is not limited to gold, and may be made of another metal material. The second metal layer 18 is not limited to nickel and may be made of a nickel-based or other metal material. The combination of the metal materials that form the first metal layer 20 and the second metal layer 18 is not limited to gold and nickel, and the metal material that forms the first metal layer 20 is better than the metal material that forms the second metal layer 18. However, it is sufficient if the solder wettability is high. As an example, the combination of metal materials forming the first metal layer 20 and the second metal layer 18 may be a combination of metal materials such as silver (Ag) and copper, respectively.

  A method of manufacturing the semiconductor module 50 will be described with reference to FIGS. Here, in particular, soldering between the semiconductor device 10 and the lower heat dissipation plate 26 will be described. Regarding the step of forming the other constituent elements, various known methods can be appropriately used, and description thereof will be omitted here.

  First, as shown in FIG. 3, the semiconductor device 10 and the lower heat dissipation plate 26 are prepared, and the stacked body 40 in which the solder 36 is arranged is formed between them. As the solder 36 arranged between the semiconductor device 10 and the lower heat dissipation plate 26, for example, a sheet-shaped solder material can be adopted. Here, since the solder 36 constitutes the above-mentioned solder layer 36, the same reference numerals are given and described.

  Next, as shown in FIGS. 4 to 7, a reflow process of soldering between the semiconductor device 10 and the lower heat dissipation plate 26 is performed. In this step, the stacked body 40 is placed in, for example, a reflow furnace, the stacked body 40 is heated to melt the solder 36, and then the stacked body 40 is deheated to solidify the solder 36. At this time, the intermetallic compound K is formed at the interface between the lower surface electrode 10b and the lower heat dissipation plate 26 that are in contact with the molten solder 36, so that the semiconductor device 10 and the lower heat dissipation plate 26 are joined. In this reflow step, the laminated body 40 may be heated under reduced pressure, for example, by reducing the pressure inside the reflow furnace.

  When the stacked body 40 is heated to melt the solder 36, the wetting and spreading of the solder 36 with respect to the lower surface electrode 10b proceeds first on the center side where the first range R1 is relatively exposed, and then toward the peripheral edge. To expand. Therefore, the void X generated when the solder 36 melts gradually moves from the center side of the lower surface electrode 10b to the peripheral edge and is easily released to the outside of the solder 36. This suppresses the formation of the void X inside the solder layer 36 joining the semiconductor device 10 and the lower heat dissipation plate 26.

  A modification of the semiconductor device 10 will be described with reference to FIG. In this modification, the configuration of the lower surface electrode 110b is changed, and in particular, the patterning shape of the first metal layer 120 is changed. As shown in FIG. 8, the surface of the lower surface electrode 110b has a first range R1 in which the first metal layer 120 is provided and a second range R2 in which the second metal layer 118 is exposed. The first range R1 (that is, the first metal layer 120) includes a circular portion C1 located at the center of the surface of the lower electrode 110b, and multiple annular portions C2 and C3 arranged so as to surround the circular portion C1. It has C4 and C5. These circular portion C1 and annular portions C2-C5 are arranged concentrically with respect to the center of the surface of the lower surface electrode 110b. The second range R2 (that is, the second metal layer 118) is a range (that is, the range other than the first range R1) located between the circular portion C1 and the annular portion C2-C5, and The first range R1 and the second range R2 are arranged alternately.

  The plurality of annular portions C2 to C5 forming the first range R1 have a wider width as they are located closer to the center of the lower surface electrode 110b, and have a smaller width as they are located closer to the peripheral edge. On the other hand, the width of the second range R2 located between them is narrower as it is located closer to the center of the lower surface electrode 110b and wider as it is located closer to the peripheral edge. As a result, the ratio of the area of the first range R1 to the area of the second range R2 decreases from the center of the surface of the lower surface electrode 110b toward the outer peripheral edge of the surface of the lower surface electrode 110b.

  The stacking form of the first metal layer 20 and the second metal layer 18 on the lower surface electrode 10b of the semiconductor device 10 is not particularly limited. It is sufficient that the first metal layer 20 and the second metal layer 18 are exposed on the surface of the lower surface electrode 10b. As illustrated in FIG. 3, the first metal layer 20 may be partially embedded in the second metal layer 18, or the first metal layer 20 may partially protrude from the second metal layer 18. Good.

  Although some specific examples have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations.

10: semiconductor device 10a: upper surface electrode 10b, 110b: lower surface electrode 12: semiconductor substrate 14: fourth metal layer 16: third metal layer 18, 118: second metal layer 20, 120: first metal layer 22: conductor spacer 24: Upper heat dissipation plate 26: Lower heat dissipation plate 28: Sealing bodies 32, 34, 36: Solder layer 38: Nickel-based metal layer 40: Laminated body 50: Semiconductor module K: Intermetallic compound R1: First range R2: Second range X: void

Claims (1)

A semiconductor substrate and a solder electrode disposed on the semiconductor substrate,
The surface of the solder electrode has a first range in which the first metal material is exposed and a second range in which the second metal material is exposed,
The first metal material has higher solder wettability than the second metal material,
The ratio of the area of the first range to the area of the second range decreases from the center of the surface toward the outer peripheral edge of the surface,
Semiconductor device.