JP2020065049A - Electronic apparatus - Google Patents

Abstract

To solve a problem of a conventional electronic apparatus and a manufacturing method of the conventional apparatus that resin, used for a wiring layer on a solder ball side, is limited and thus cost reduction of the electronic apparatus is inhibited.SOLUTION: An electronic apparatus 1 includes a wiring layer 10 (first wiring layer) and a wiring layer 20 (second wiring layer). The wiring layer 20 is formed on a lower surface of the wiring layer 10. The wiring layer 20 has area larger than that of the wiring layer 10 in a plane view and extends to the outside of the wiring layer 10.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic device and a manufacturing method thereof.

  As a conventional method for manufacturing an electronic device, there is one described in Patent Document 1, for example. In the manufacturing method described in the same document, the support substrate is removed after the multilayer wiring layer is formed by sequentially stacking a plurality of wiring layers on the support substrate. Then, solder balls are formed as external electrode terminals on one surface of the multilayer wiring layer exposed by removing the supporting substrate. Electronic components are flip-chip mounted on the other surface of the multilayer wiring layer. Thereby, the electronic device in which the electronic component is placed on the multilayer wiring layer is obtained.

  In addition to Patent Document 1, Patent Documents 2 to 5 can be cited as prior art documents related to the present invention.

JP, 2003-309215, A JP 57-7147 A JP, 9-321408, A JP-A-11-126978 JP, 2001-53413, A

  By the way, in the above electronic device, for fine connection between the wiring layer and the electronic component, a resin suitable for fine processing is used for the wiring layer on the electronic component side of the wiring layers forming the multilayer wiring layer. Is required. On the other hand, it is often not required to use a resin suitable for fine processing for the wiring layer on the solder ball side. In that case, in order to reduce the cost of the electronic device, it is preferable to use a relatively inexpensive resin for the wiring layer on the solder ball side.

  However, in the manufacturing method of Patent Document 1, as described above, the multilayer wiring layer is formed by sequentially stacking a plurality of wiring layers on the support substrate. Therefore, the wiring layer on the solder ball side is formed before the wiring layer on the electronic component side. Therefore, there is a restriction that a resin having a thermal decomposition temperature lower than that of the resin forming the wiring layer on the electronic component side cannot be used as the resin forming the wiring layer on the solder ball side. Due to such restrictions, the resin used for the wiring layer on the solder ball side is limited, which prevents the cost reduction of the electronic device.

  The method of manufacturing an electronic device according to the present invention includes a first wiring layer forming step of forming a first wiring layer on a supporting substrate, a supporting substrate removing step of removing the supporting substrate, and a step of removing the supporting substrate after the supporting substrate removing step. A second wiring layer forming step of forming a second wiring layer extending to the outside of the first wiring layer on the surface of the first wiring layer on which the support substrate was provided. It is characterized by

  In this manufacturing method, the first wiring layer on which the electronic component is placed is formed on the supporting substrate, while the second wiring layer is formed after removing the supporting substrate. Accordingly, it is possible to avoid the restriction that a resin having a lower thermal decomposition temperature than that of the resin forming the first wiring layer cannot be used as the resin forming the second wiring layer. Therefore, it is possible to use a resin suitable for microfabrication for the first wiring layer, while using a relatively inexpensive resin for the second wiring layer.

  Further, the electronic device according to the present invention includes a first wiring layer and a second wiring layer provided on the first wiring layer and extending to the outside of the first wiring layer. Characterize.

  In this electronic device, a resin having a lower thermal decomposition temperature than the resin forming the first wiring layer can be used as the resin forming the second wiring layer. Therefore, it is possible to use a resin suitable for microfabrication for the first wiring layer, while using a relatively inexpensive resin for the second wiring layer.

  According to the present invention, it is possible to realize an electronic device and a method for manufacturing the same that can obtain a fine connection between a wiring layer and an electronic component at low cost.

FIG. 3 is a sectional view showing a first embodiment of an electronic device according to the present invention. FIG. 6 is a cross-sectional view for describing an example of a structure near the interface between the first wiring layer and the second wiring layer. (A)-(e) is process drawing which shows the outline of 1st Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the electronic device by this invention. FIG. 6 is a process diagram showing a first embodiment of a method for manufacturing an electronic device according to the present invention. FIG. 7 is a sectional view showing a second embodiment of an electronic device according to the present invention. (A) And (b) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. (A)-(c) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. FIG. 7 is a sectional view showing a third embodiment of an electronic device according to the present invention. (A) And (b) is process drawing which shows 3rd Embodiment of the manufacturing method of the electronic device by this invention. It is a top view for explaining the modification of an embodiment. (A)-(c) is a top view for explaining a modification of an embodiment.

Hereinafter, preferred embodiments of an electronic device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.
(First embodiment)

  FIG. 1 is a sectional view showing a first embodiment of an electronic device according to the present invention. The electronic device 1 includes a wiring layer 10 (first wiring layer) and a wiring layer 20 (second wiring layer).

  The wiring layer 10 has a via plug 12 (first conductive plug), an insulating resin 14, and a conductor wiring 16. The via plug 12 is formed in the insulating resin 14. As can be seen from the figure, the via plug 12 has a taper shape in which the diameter becomes smaller as it approaches the wiring layer 20. Therefore, the area of the end surface of the via plug 12 on the wiring layer 20 side is smaller than the area of the end surface on the opposite side, that is, the end surface on the IC chip 32, 36 side described later.

  The conductor of the via plug 12 is Cu, Ni, Au, or Ag, for example. The insulating resin 14 is, for example, a polyimide resin, a PBO (polybenzoxazole) resin, a BCB (benzocyclobutene) resin, a cardo resin (cardo type polymer) or an epoxy resin. The polyimide resin may be a photosensitive polyimide resin or a non-photosensitive polyimide resin. A conductor wiring 16 connected to the via plug 12 is formed on the insulating resin 14.

  IC chips 32 and 36 (electronic components) are placed on the upper surface (first surface) of the wiring layer 10. These IC chips 32 and 36 are flip-chip connected to the conductor wiring 16 via bumps 33 and 37, respectively. An underfill resin 34 is filled in the gap between the IC chip 32 and the wiring layer 10. Similarly, a gap between the IC chip 36 and the wiring layer 10 is filled with an underfill resin 38. A plurality of IC chips 36 are provided and they are stacked on each other. The IC chip 32 and the IC chip 36 are, for example, a CPU and a laminated memory, respectively. The laminated memory is a three-dimensionally laminated IC chip (memory), and the chips (memory) are electrically connected.

  Further, the IC chips 32 and 36 are covered with the sealing resin 52 formed on the wiring layer 10. More specifically, the side surface of the IC chip 32 and the side surfaces and the upper surface of the IC chip 36 are covered with the sealing resin 52.

  The wiring layer 20 is formed on the lower surface (second surface) of the wiring layer 10. The wiring layer 20 has a larger area in plan view than the wiring layer 10 and extends to the outside of the wiring layer 10. That is, the wiring layer 20 protrudes from the wiring layer 10.

  The wiring layer 20 has a via plug 22 (second conductive plug) and an insulating resin 24. The via plug 22 is formed in the insulating resin 24. The via plug 22 is connected to the above-mentioned via plug 12. As can be seen from the drawing, the via plug 22 has a taper shape in which the diameter becomes smaller as it gets closer to the wiring layer 10. Therefore, the area of the end surface of the via plug 22 on the wiring layer 10 side is smaller than the area of the opposite end surface, that is, the end surface on the solder ball 60 side described later. The conductor of the via plug 22 is, for example, Cu, Ni, Au, or Ag, like the via plug 12. The insulating resin 24 is, for example, an epoxy resin or the like. The wiring body including the wiring layer 10 and the wiring layer 20 described above functions as an interposer in the electronic device 1.

  The thermal decomposition temperature of the insulating resin 14 forming the wiring layer 10 is higher than the thermal decomposition temperature of the insulating resin 24 forming the wiring layer 20. When PBO is used as the insulating resin 14, its thermal decomposition temperature is 540 ° C., for example. When an epoxy resin is used as the insulating resin 24, its thermal decomposition temperature is 310 ° C., for example. Here, the thermal decomposition temperature is a temperature at which the weight of the resin decreases by 5% by weight when measured using a thermobalance at a temperature rising rate of 10 ° C./min. Even when the same type of resin (for example, epoxy resin) is used as the insulating resins 14 and 24, the thermal decomposition temperature of the former is higher than that of the latter.

  An IC chip 42 and a passive component 44 are mounted as a second electronic component on a portion of the wiring layer 20 outside the wiring layer 10. The passive component 44 is, for example, a capacitor such as a decoupling capacitor. The IC chip 42 is covered with a sealing resin 54. The passive component 44 is covered with the resin 56 provided on the outer portion of the wiring layer 20. The resin 56 may be the same resin as the sealing resin 54 or a different resin.

  The wiring layer 20 has a multilayer wiring structure and has conductor wirings 26 provided in a plurality of layers and via plugs 28 connecting the conductor wirings 26 of different layers. Solder balls 60 are connected to the lowermost conductor wirings 26. A part of the solder ball 60 is embedded in the solder resist 62. The solder balls 60 function as external connection terminals of the electronic device 1.

  An example of the structure near the interface between the wiring layer 10 and the wiring layer 20 will be described with reference to FIG. In this example, the adhesion metal film 72 is formed so as to cover the via plug 22. The adhesion metal film 72 is in contact with the via plug 12 on the via plug 22. Further, the adhesion metal film 74 is also formed on the surface of the conductor wiring 16 in contact with the via plug 12.

  The adhesion metal films 72 and 74 are preferably films containing Ti (for example, Ti, TiN or TiW) or Cr films.

  A method of manufacturing the electronic device 1 will be described as a first embodiment of the method of manufacturing the electronic device according to the present invention with reference to FIGS. Prior to the detailed description, an outline of the present manufacturing method will be described with reference to FIGS. 3 (a) to 3 (e). First, as shown in FIG. 3A, the wiring layer 10 is formed on the support substrate 90 (first wiring layer forming step). As the support substrate 90, a silicon substrate, a ceramic substrate, a glass substrate, a metal substrate, or the like can be used.

  Next, as shown in FIG. 3B, the IC chips 32 and 36 are mounted on the wiring layer 10 (electronic component mounting step). Further, as shown in FIG. 3C, a sealing resin 52 is formed on the wiring layer 10 so as to cover the IC chips 32 and 36 (sealing resin forming step). Subsequently, as shown in FIG. 3D, the support substrate 90 is removed (support substrate removing step). Then, as shown in FIG. 3E, the wiring layer 20 is formed on the lower surface of the wiring layer 10 (second wiring layer forming step). Finally, although illustration is omitted, by forming the solder balls 60, the electronic device 1 shown in FIG. 1 is obtained.

  Subsequently, the present manufacturing method will be described in detail with reference to FIGS. First, the insulating resin 14 is formed on the support substrate 90, and the via plug 12 is formed therein. After that, the conductor wiring 16 is formed on the insulating resin 14 (FIG. 4A). Next, the IC chips 32 and 36 are flip-chip mounted on the conductor wiring 16 (FIG. 4B). Then, a sealing resin 52 is formed on the wiring layer 10 so as to cover the IC chips 32 and 36. The sealing resin 52 can be formed by, for example, molding, printing, or potting (FIG. 5A). Then, the support substrate 90 is removed to expose the lower surface of the wiring layer 10 (FIG. 5B).

  Next, the insulating resin 24 is formed on the lower surface of the wiring layer 10 so as to extend to the outside of the wiring layer 10. At this time, for example, an insulating film can be used as the insulating resin 24. Subsequently, the IC chip 42 and the passive component 44 are mounted on the portion of the insulating resin 24 outside the wiring layer 10. After that, the sealing resin 54 is formed so as to cover the IC chip 42 (FIG. 6A). Next, the resin 56 is formed so as to fill the gap above the outer portion of the insulating resin 24. As a result, the passive component 44 is covered with the resin 56 (FIG. 6B).

  Next, the via plug 22 is formed in the insulating resin 24 so as to be connected to the via plug 12. After that, a build-up wiring layer is formed on the insulating resin 24. For example, the conductor wiring 26 by the semi-additive method and the via plug 28 by laser processing may be alternately formed in an insulating resin layer such as an epoxy resin. As a result, the wiring layer 20 is formed (FIG. 7). Then, by forming the solder resist 62 and the solder balls 60, the electronic device 1 of FIG. 1 is obtained. The wiring layer 20 may be formed by adhering a previously formed multilayer wiring layer as the wiring layer 20 to the lower surface of the wiring layer 10.

  As is clear from the above description, the build-up directions of the wiring layers 10 and 20 are upward and downward in each figure. Accordingly, as described above, the end surface of the via plug 12 on the IC chip 32, 36 side has a larger area than the end surface of the wiring layer 20 side, and the end surface of the via plug 22 on the solder ball 60 side than the end surface on the wiring layer 10 side. The area is getting bigger.

  The effects of this embodiment will be described. In the above manufacturing method, the wiring layer 10 on which the IC chips 32 and 36 are mounted is formed on the support substrate 90, while the wiring layer 20 is formed after the support substrate 90 is removed. Thereby, it is possible to avoid the restriction that a resin having a lower thermal decomposition temperature than the insulating resin 14 cannot be used as the insulating resin 24. Therefore, it is possible to use a resin suitable for microfabrication as the insulating resin 14 and a relatively inexpensive resin as the insulating resin 24. As a result, a method of manufacturing the electronic device 1 that can obtain a fine connection between the wiring layer 10 and the IC chips 32 and 36 at a low cost is realized.

  Further, the wiring layer 20 extends to the outside of the wiring layer 10. Thereby, the area of the surface on which the solder balls 60 are provided (that is, the lower surface of the wiring layer 20) can be sufficiently increased while suppressing the area of the wiring layer 10 small. Therefore, the electronic device 1 can be easily mounted on another electronic device, a mother board, or the like without increasing the cost. On the other hand, when the areas of the wiring layer 10 and the wiring layer 20 are equal to each other, if the area of the wiring layer 20 is increased in order to improve the mounting ease, the area of the wiring layer 10 must be increased accordingly. I don't get. Then, since a relatively expensive resin suitable for fine processing is used for the wiring layer 10, the manufacturing cost of the electronic device 1 increases. On the other hand, if the area of the wiring layer 10 is reduced to reduce the cost, the area of the wiring layer 20 is also reduced and the ease of mounting is impaired. According to the present embodiment, it is possible to eliminate such a dilemma and achieve both low cost and ease of mounting.

  Since the wiring pattern of the conductor wiring 16 is formed on the supporting substrate 90 having high rigidity, the fine conductor wiring 16 can be obtained. Further, since the wiring layer 10 and the IC chips 32 and 36 are joined on the support substrate 90, the wiring layer 10 and the IC chips 32 and 36 can be bump-connected at a fine pitch. This leads to a reduction in the number of wiring layers and a reduction in the size of the IC chips 32 and 36.

  Furthermore, since the wiring layer 20 is formed after removing the support substrate 90, the insulating resin 24 forming the wiring layer 20 can be formed thicker than the insulating resin 14. As a result, the stress relaxation function of the insulating resin 24 is enhanced, and the reliability of the electronic device 1 is improved.

  In the second wiring layer forming step, a resin whose thermal decomposition temperature is lower than that of the insulating resin 14 forming the wiring layer 10 formed in the first wiring layer forming step is used as the insulating resin 24 forming the wiring layer 20. ing. Thereby, the wiring layer 20 can be preferably formed on the wiring layer 10.

  In the electronic device 1, as the insulating resin 24 forming the wiring layer 20, a resin having a lower thermal decomposition temperature than the insulating resin 14 forming the wiring layer 10 can be used. Therefore, it is possible to use a resin suitable for microfabrication as the insulating resin 14 and a relatively inexpensive resin as the insulating resin 24. As a result, the electronic device 1 that realizes fine connection between the wiring layer 10 and the IC chips 32 and 36 is realized at low cost.

  Further, in the electronic device 1, the wiring layer 10 and the wiring layer 20 are in direct contact with each other, and the core layer is not provided between these layers. The via plug formed in the core layer is generally more difficult to be miniaturized than the via plug formed in the normal wiring layer, and thus there is a problem that the miniaturization of the entire electronic device is hindered. In this respect, in the electronic device 1, since the core layer is not provided, such a problem does not occur.

  A sealing resin 52 is provided so as to cover the IC chips 32 and 36. Thereby, the shape of the wiring body can be maintained even after the support substrate 90 is removed. Therefore, a high coplanarity is obtained for the solder ball 60. Particularly in the present embodiment, the resin 56 is also formed on the portion of the wiring layer 20 outside the wiring layer 10. This further enhances this effect.

  When a silicon substrate is used as the support substrate 90, the influence of thermal expansion can be suppressed as compared with the case where an insulating substrate is used. As a result, the connection between the wiring layer 10 and the IC chips 32 and 36 can be further miniaturized.

  When a polyimide resin, a PBO resin, a BCB resin, or a cardo resin is used as the insulating resin 14, the insulating resin 14 suitable for fine processing is realized. When an epoxy resin is used as the insulating resin 24, the insulating resin 24 can be obtained at low cost.

  An adhesion metal film 72 is provided so as to cover the via plug 22 (see FIG. 2). As a result, a strong bond is obtained between the via plug 22 and the insulating resin 24. In addition, an adhesion metal film 74 is provided on the surface of the conductor wiring 16 in contact with the via plug 12 (see FIG. 2). As a result, a strong bond is obtained between the conductor wiring 16 and the insulating resin 14. These contribute to improving the reliability of the electronic device 1. When the adhesive metal films 72 and 74 contain Ti or are made of Cr, particularly high adhesiveness to the resin can be obtained.

The IC chip 42 and the passive component 44 are placed on a portion of the wiring layer 20 outside the wiring layer 10. As a result, it is possible to further enhance the functionality and performance of the electronic device 1.
(Second embodiment)

  FIG. 8 is a sectional view showing a second embodiment of the electronic device according to the present invention. The electronic device 2 includes a wiring layer 10 (first wiring layer) and a wiring layer 80 (second wiring layer). The structure of the wiring layer 10 is the same as that described in FIG.

  The wiring layer 80 is formed on the lower surface of the wiring layer 10 and extends to the outside of the wiring layer 10. The wiring layer 80 has a solder resist 84 and a conductor wiring 86 formed therein. As the solder resist 84, a resin whose thermal decomposition temperature is lower than that of the insulating resin 14 is used. A via plug 82 (second conductive plug) is formed in the wiring layer 80. The via plug 82 corresponds to a part of the solder ball 60, specifically, a part of the solder ball 60 buried in the solder resist 84. As can be seen from the figure, the via plug 82 has a taper shape in which the diameter becomes smaller as it gets closer to the wiring layer 10. Therefore, the area of the end surface of the via plug 82 on the wiring layer 10 side is smaller than the area of the end surface on the opposite side.

  Further, the IC chip 92 is flip-chip mounted on the lower surface of the wiring layer 10. That is, the IC chip 92 is connected to the lower surface via the bumps 93, and the gap between the wiring layer 10 and the IC chip 92 is filled with the underfill resin 94.

  A resin 56 is formed on a portion of the wiring layer 80 outside the wiring layer 10. In this embodiment, the resin 56 covers both the side surface and the upper surface of the sealing resin 52.

  A method of manufacturing the electronic device 2 will be described as a second embodiment of the method of manufacturing the electronic device according to the present invention with reference to FIGS. 9 to 12. First, the insulating resin 14, the via plug 12, and the conductor wiring 16 are formed on the support substrate 90 (FIG. 9A). Then, the IC chips 32 and 36 are flip-chip mounted on the conductor wiring 16 (FIG. 9B).

  Next, the sealing resin 52 is formed on the wiring layer 10 so as to cover the IC chips 32 and 36 (FIG. 10A). Then, the support substrate 90 is removed to expose the lower surface of the wiring layer 10 (FIG. 10B). Then, the support sheet 91 is formed on the lower surface of the wiring layer 10 so as to extend to the outside of the wiring layer 10 (FIG. 10C).

  Next, the resin 56 is formed on the portion of the support sheet 91 outside the wiring layer 10 so as to cover the sealing resin 52 (FIG. 11A). Then, the support sheet 91 is peeled off (FIG. 11B). Next, after forming the conductor wiring 86 on the lower surface of the wiring layer 10, the solder resist 84 is formed so as to cover the conductor wiring 86. Further, the solder resist 84 is patterned to open the portion where the solder ball 60 is formed and the portion where the IC chip 92 is mounted (FIG. 12A). As a result, the wiring layer 80 is formed. Then, the IC chip 92 is flip-chip mounted on the lower surface of the wiring layer 10 (FIG. 12B). Then, by forming the solder balls 60, the electronic device 2 of FIG. 8 is obtained.

The present embodiment can exert the following effects in addition to the effects of the above-described first embodiment. Since the solder resist 84 is used as the resin forming the wiring layer 80, the cost of the electronic device 2 can be further reduced. Further, electronic components (IC chips 92) are mounted not only on the upper surface of the wiring layer 10 but also on the lower surface thereof. As a result, it is possible to further enhance the functionality and performance of the electronic device 2.
(Third Embodiment)

  FIG. 13 is a cross-sectional view showing a third embodiment of the electronic device according to the present invention. The electronic device 3 includes a wiring layer 10 and a wiring layer 80. The electronic device 3 differs from the electronic device 2 of FIG. 8 in that the wiring layer 80 has a multilayer wiring structure. In this embodiment, the wiring layer 80 includes an insulating resin 84a provided on the lower surface of the wiring layer 10 and a solder resist 84b provided thereon.

  In the wiring layer 80 of the present embodiment, conductor wirings 86 provided in a plurality of layers and via plugs 83 (second conductive plugs) connected to the conductor wirings 86 are formed. As can be seen from the figure, the via plug 83 has a taper shape in which the diameter becomes smaller as it gets closer to the wiring layer 10. Therefore, the area of the end surface of the via plug 83 on the wiring layer 10 side is smaller than the area of the end surface on the opposite side. Further, in the electronic device 2, the bump 93 is directly connected to the via plug 12, whereas in the electronic device 3, the bump 93 is connected to the via plug 12 via the conductor wiring 86 (and the via plug 83). There is. Other configurations of the electronic device 3 are similar to those of the electronic device 2.

  A method for manufacturing the electronic device 3 will be described as a third embodiment of the method for manufacturing an electronic device according to the present invention with reference to FIGS. 14A and 14B. First, the structure shown in FIG. 11B is prepared in the same manner as described with reference to FIGS.

  Next, the first-layer conductor wiring 86 is formed on the lower surface of the wiring layer 10 so as to be connected to the via plug 12. After that, the insulating resin 84a is formed so as to cover it. Further, a via plug 83 is formed in the insulating resin 84a so as to be connected to the conductor wiring 86. Subsequently, a second-layer conductor wiring 86 is formed on the insulating resin 84a so as to be connected to the via plug 83. After that, a solder resist 84b is formed so as to cover it.

  Next, the solder resist 84b is patterned to open a portion where the solder ball 60 is formed and a portion where the IC chip 92 is mounted (FIG. 14A). As a result, the wiring layer 80 is formed. Then, the IC chip 92 is flip-chip mounted on the insulating resin 84a (FIG. 14B). Then, by forming the solder balls 60, the electronic device 3 of FIG. 13 is obtained. Also in this embodiment, the same effect as that of the second embodiment can be obtained.

  The electronic device and the method for manufacturing the electronic device according to the present invention are not limited to the above-described embodiments, and various modifications can be made. For example, in the above embodiment, the IC chip is exemplified as the electronic component placed on the upper surface or the lower surface of the wiring layer 10, but the electronic component may be a passive component such as a capacitor. Further, it is not essential to provide the electronic device with electronic components.

  In the above embodiment, the example in which the solder balls are provided in the electronic device has been shown, but it is not essential to provide the solder balls. When the solder ball is not provided, the land portion of the conductor wiring corresponds to the external electrode terminal. Taking the electronic device 1 of FIG. 1 as an example, a portion of the conductor wiring 26 to which the solder ball 60 is connected is a land portion.

  Further, the second wiring layer may protrude from the entire periphery of the first wiring layer or may protrude from only a part thereof. An example of the former is shown in FIG. 15, and an example of the latter is shown in FIGS. 16 (a) to 16 (c). In these plan views, the outer peripheries of the first and second wiring layers are indicated by lines L1 and L2, respectively, and the overlapping portions of both wiring layers are shaded. In FIG. 15, the second wiring layer protrudes from all four sides of the first wiring layer. On the other hand, in FIGS. 16A, 16B, and 16C, the second wiring layer protrudes from the three sides, the two sides, and the one side of the first wiring layer, respectively.

1 Electronic Device 2 Electronic Device 10 Wiring Layer 12 Via Plug 14 Insulating Resin 16 Conductor Wiring 20 Wiring Layer 22 Via Plug 24 Insulating Resin 26 Conductor Wiring 28 Via Plug 32 IC Chip 33 Bump 34 Underfill Resin 36 IC Chip 37 Bump 38 Underfill Resin 42 IC Chip 44 Passive component 52 Sealing resin 54 Sealing resin 56 Resin 60 Solder ball 62 Solder resist 72 Adhesion metal film 80 Wiring layer 82 Via plug 84 Solder resist 84a Insulating resin 84b Solder resist 86 Conductor wiring 90 Support substrate 91 Support sheet 92 IC chip 93 bump 94 underfill resin

Claims (18)

A first wiring layer having a first conductor wiring;
A second wiring layer having a second conductor wiring and formed on the first wiring layer;
A first electronic component flip-chip mounted on the second wiring layer and electrically connected to the second conductor wiring via a first bump;
A second electronic component, which is a memory, is flip-chip mounted on the second wiring layer, and is electrically connected to the second conductor wiring via a second bump;
An external connection terminal electrically connected to the first conductor wiring;
Including,
The thickness of the second conductor wiring is smaller than the thickness of the first conductor wiring,
An electronic device in which the number of layers of the second wiring layer in which the second conductor wiring is provided is smaller than the number of layers of the first wiring layer in which the first conductor wiring is provided. The electronic device according to claim 1,
The first wiring layer has a first insulating resin and the first conductor wiring,
The second wiring layer has a second insulating resin and the second conductor wiring,
An electronic device, wherein the thickness of the first insulating resin forming the first wiring layer is larger than the thickness of the second insulating resin forming the second wiring layer. The electronic device according to claim 2,
An electronic device, wherein a thermal decomposition temperature of the second insulating resin forming the second wiring layer is higher than a thermal decomposition temperature of the first insulating resin forming the first wiring layer. The electronic device according to claim 3,
The first insulating resin is an epoxy resin,
The second insulating resin is an electronic device including any one of a polyimide resin, a PBO (polybenzoxazole) resin, a BCB (benzocyclobutene) resin, and a cardo type polymer. The electronic device according to claim 1,
The said 2nd electronic component is an electronic device which is a laminated | stacked memory which laminated | stacked several memory chips and electrically connected these memory chips mutually. The electronic device according to claim 5,
An electronic device in which the first electronic component is a CPU. The electronic device according to claim 6,
A first underfill resin is filled between the first electronic component and the second wiring layer,
A second underfill resin is filled between the second electronic component and the second wiring layer,
The external connection terminal is a solder ball,
An electronic device in which the first electronic component and the second electronic component are covered with a sealing resin formed on the second wiring layer. The electronic device according to claim 1,
The first wiring layer includes a first insulating resin, a first via plug formed in the first insulating resin, and the first conductor wiring,
The second wiring layer has a second insulating resin, a second via plug formed in the second insulating resin, and the second conductor wiring,
The first via plug is made of Cu, Ni, Au, or Ag,
An electronic device in which the second via plug is made of Cu, Ni, Au, or Ag. The electronic device according to claim 8,
In a cross-sectional view, the first via plug has a taper shape whose diameter decreases toward the second wiring layer,
In a cross-sectional view, the second via plug is an electronic device having a taper shape in which a diameter of the second via plug becomes smaller toward the first wiring layer. The electronic device according to claim 8,
The area of the first end surface of the first via plug on the second wiring layer side is smaller than the area of the second end surface of the first via plug on the side opposite to the first end surface,
An electronic device in which an area of a third end surface of the second via plug on the second wiring layer side is smaller than an area of a fourth end surface of the second via plug on the side opposite to the third end surface. A first wiring layer having a plurality of first conductor wirings;
A second wiring layer having a plurality of second conductor wirings and formed on the first wiring layer;
It is flip-chip mounted on the second wiring layer and electrically connected to one of the plurality of second conductor wirings through one of the plurality of first bumps, and A first electronic component electrically connected to another one of the plurality of second conductor wirings via another one of the first bumps;
Of the plurality of second conductor wirings, which are flip-chip mounted on the second wiring layer, arranged next to the first electronic component, and through one of the plurality of second bumps. A second electronic component, which is a memory, electrically connected to the one;
An external connection terminal electrically connected to one of the plurality of first conductor wirings;
Including,
The other one of the plurality of second conductor wirings is electrically connected to the one of the plurality of first conductor wirings,
The thickness of each of the plurality of second conductor wirings is smaller than the thickness of each of the plurality of first conductor wirings,
The electronic device, wherein the number of layers of the second wiring layer provided with the plurality of second conductor wirings is smaller than the number of layers of the first wiring layer provided with the plurality of first conductor wirings. The electronic device according to claim 11,
The first wiring layer has a first insulating resin and the plurality of first conductor wirings,
The second wiring layer has a second insulating resin and the plurality of second conductor wirings,
An electronic device, wherein the thickness of the first insulating resin forming the first wiring layer is larger than the thickness of the second insulating resin forming the second wiring layer. The electronic device according to claim 12,
An electronic device, wherein a thermal decomposition temperature of the second insulating resin forming the second wiring layer is higher than a thermal decomposition temperature of the first insulating resin forming the first wiring layer. The electronic device according to claim 13,
The first insulating resin is an epoxy resin,
The second insulating resin is an electronic device including any one of a polyimide resin, a PBO (polybenzoxazole) resin, a BCB (benzocyclobutene) resin, and a cardo type polymer. The electronic device according to claim 11,
The said 2nd electronic component is an electronic device which is a laminated | stacked memory which laminated | stacked several memory chips and electrically connected these memory chips mutually. The electronic device according to claim 15,
An electronic device in which the first electronic component is a CPU. The electronic device according to claim 16,
A first underfill resin is filled between the first electronic component and the second wiring layer,
A second underfill resin is filled between the second electronic component and the second wiring layer,
The external connection terminal is a solder ball,
An electronic device in which the first electronic component and the second electronic component are covered with a sealing resin formed on the second wiring layer. The electronic device according to claim 11,
An electronic device, wherein a pitch of the plurality of second conductor wirings is narrower than a pitch of the plurality of first conductor wirings.

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