JP2005109037A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the heat-dissipating properties and high-frequency characteristics of a semiconductor device. <P>SOLUTION: The semiconductor device 100 includes a laminate comprising a first conductive film 102, first insulating resin films 106a, second conductive films 104, second insulating resin films 106b, a third conductive film 140, third insulating resin films 106c and fourth conductive films 142, and a circuit element 120. A recessed section 144 is formed to the laminate. The circuit element 120 is arranged just above the first conductive film 102 in the recessed section 144. The backside of the first conductive film 102 is exposed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including an element.

  As portable electronic devices such as mobile phones, PDAs, DVCs, and DSCs are accelerating their functions, miniaturization and weight reduction are essential for their acceptance in the market. There is a need for a system LSI. On the other hand, these electronic devices are required to be easier to use and convenient, and higher functionality and higher performance are required for LSIs used in the devices. For this reason, as the number of I / Os increases with higher integration of LSI chips, there is a strong demand for miniaturization of the package itself. In order to achieve both of these, a semiconductor package suitable for high-density board mounting of semiconductor components Development is strongly demanded. In order to meet such demands, various package technologies called CSP (Chip Size Package) have been developed.

  As an example of such a package, BGA (Ball Grid Array) is known. The BGA is obtained by mounting a semiconductor chip on a package substrate, resin molding it, and then forming a solder ball as an external terminal in an area on the opposite surface. In BGA, since the mounting area is achieved in terms of surface, the package can be reduced in size relatively easily. In addition, it is not necessary to support narrow pitches on the circuit board side, and high-precision mounting technology is not required. Therefore, if BGA is used, the total mounting cost can be reduced even if the package cost is somewhat high. Become.

  FIG. 6 is a diagram showing a schematic configuration of a general BGA. The BGA 300 has a structure in which an LSI chip 302 is mounted on a glass epoxy substrate 306 via an adhesive layer 308. The LSI chip 302 is molded with a sealing resin 316. The LSI chip 302 and the glass epoxy substrate 306 are electrically connected by a metal wire 304. Solder balls 312 are arranged in an array on the back surface of the glass epoxy substrate 306. The BGA 300 is mounted on the printed wiring board via the solder balls 312.

Patent Document 1 describes another example of CSP. The publication discloses a system-in-package in which a high-frequency LSI is mounted. In this package, a multilayer wiring structure is formed on a base substrate, and circuit elements such as a high frequency LSI are formed thereon. The multilayer wiring structure has a structure in which a core substrate, a copper foil with resin, and the like are laminated.
JP 2002-94247 A JP 2002-110717 A

  However, with these conventional CSPs, it has been difficult to achieve a level of size reduction, thickness reduction, and weight reduction that are currently desired in portable electronic devices and the like. This is because a conventional CSP has a substrate that supports a chip. Due to the presence of the support substrate, the entire package becomes thick, and there is a limit to miniaturization, thickness reduction, and weight reduction. There was also a certain limit to the improvement of heat dissipation.

  In view of such circumstances, the present applicant has developed a new package called ISB (Integrated System in Board; registered trademark). ISB is an original coreless system-in-package that does not use a core (base material) for supporting circuit components while having a wiring pattern made of copper in packaging of electronic circuits centering on semiconductor bare chips. Patent Document 2 describes such a system-in-package.

  FIG. 7 is a schematic configuration diagram showing an example of an ISB. Here, only a single wiring layer is shown for easy understanding of the entire structure of the ISB, but in actuality, a structure in which a plurality of wiring layers are laminated is shown. This ISB has a structure in which an LSI bare chip 201, a Tr bare chip 202, and a chip CR 203 are connected by a wiring made of a copper pattern 205. The LSI bare chip 201 is electrically connected to the lead electrode and wiring by gold wire bonding 204. A conductive paste 206 is provided directly under the LSI bare chip 201, and the ISB is mounted on the printed wiring board through the conductive paste 206. The entire ISB has a structure sealed with a resin package 207 made of an epoxy resin or the like.

According to this package, the following advantages are obtained.
(i) Since it can be mounted corelessly, it is possible to reduce the size and thickness of transistors, ICs and LSIs.
(ii) Since a circuit can be formed from a transistor, a system LSI, and further a chip type capacitor and resistor, a high-level SIP (System in Package) can be realized.
(iii) Since the existing semiconductor chips can be combined, the system LSI can be developed in a short time.
(iv) Since there is no core material under the semiconductor bare chip, good heat dissipation can be obtained.
(v) Since the circuit wiring is made of copper and has no core material, the circuit wiring has a low dielectric constant and exhibits excellent characteristics in high-speed data transfer and high-frequency circuits.
(vi) Since the electrode is embedded in the package, the generation of particle contamination of the electrode material can be suppressed.
(vii) The package size is free, and the amount of waste per package is about 1/10 of the amount of SQFP package with 64 pins, so the environmental load can be reduced.
(viii) A new concept system configuration can be realized from a printed circuit board on which components are placed to a circuit board with functions.
(ix) ISB pattern design is as easy as printed circuit board pattern design, and can be designed by set manufacturer engineers.

  As described above, by using the ISB, the semiconductor device can be reduced in size, thickness, and weight. The present applicant has arrived at the present invention in order to further improve heat dissipation and high-frequency performance when ISB is used.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique for improving the heat dissipation and high-frequency performance of a semiconductor device.

  According to the present invention, a laminate including a conductive film and an insulating resin film, the conductive film being disposed in the lowermost layer and the back surface of the conductive film disposed in the lowermost layer being exposed is formed. , A semiconductor device including an element electrically connected to a conductive film included in the stacked body, wherein the stacked body includes a recess, and the element is disposed in the recess. An apparatus is provided.

  Here, the element refers to a circuit element such as a semiconductor element or a passive element. Thus, the conductive film is provided with a recess in the laminate including the conductive film and the insulating resin film, and the element is disposed in the recess, whereby the distance from the element to the bottom of the laminate can be shortened. Thereby, the heat dissipation of the semiconductor device can be improved. Furthermore, when the conductive film disposed in the lowermost layer of the laminate is grounded, the electrical path between the element and the grounded conductive film can be shortened, so that the ground inductance can be reduced, and the high frequency The characteristics can be enhanced.

  According to the semiconductor device of the present invention, the recess can be formed to reach the upper surface of the conductive film disposed in the lowermost layer, and the element can be disposed on the conductive film disposed in the lowermost layer. it can.

  In this manner, by disposing the element immediately above the conductive film provided with the back surface exposed, the heat dissipation of the semiconductor device can be further improved. In this case, the ground inductance can be greatly reduced, and the high frequency characteristics can be enhanced.

  According to the semiconductor device of the present invention, the laminate can include the first conductive film and the second conductive film provided via the insulating resin film, and the first conductive film and the insulating resin The film and the second conductive film can be laminated in this order, and the insulating resin film is formed with a via plug that electrically connects the first conductive film and the second conductive film, The via plug may have a side wall formed in a tapered shape whose diameter decreases in the direction from the first conductive film to the second conductive film.

  As described above, the via plug has a tapered side wall whose diameter is reduced in the direction of the surface on which the element is provided, and thus has a tapered side wall whose diameter is increased in the direction of the surface on which the element is provided. Compared with the via plug, the area of the via plug on the surface where the element is provided can be reduced. It is necessary to form a wiring pattern on the via plug in order to make electrical connection with the element, etc., but in order to disperse thermal stress, between the end of the wiring pattern and the end of the via plug. It is necessary to provide a certain distance. Therefore, by reducing the area of the via plug on the surface where the element is provided, the region required for each via plug can be designed to be narrower than before, and the semiconductor device can be miniaturized. Further, by narrowing a necessary region for each via plug, it is possible to design a bonding wire for connecting the element and, for example, the second conductive film, to be short. Thereby, parasitic inductance can be reduced and high frequency performance can be improved.

  According to the semiconductor device of the present invention, the element may be electrically connected to the upper surface of the element by a bonding wire on the upper surface, and the upper surface of the element and the first conductive film are substantially flush with each other. It may be formed so that it may be located in.

  Thus, the length of the bonding wire can be shortened by adopting a configuration in which the element is electrically connected to the one conductive film located at the same height as the upper surface thereof via the bonding wire. Can do. Thereby, parasitic inductance can be reduced.

  In the present invention, the laminate can be the ISB described above. As a result, the advantages of ISB as described above and the advantages of the present invention, such as improved heat dissipation, reduction of parasitic inductance, reduction of ground inductance, and miniaturization of the semiconductor device, can be obtained.

  As mentioned above, although the structure of this invention was demonstrated, what combined these structures arbitrarily is effective as an aspect of this invention. Moreover, what converted the expression of this invention into the other category is also effective as an aspect of this invention.

  ADVANTAGE OF THE INVENTION According to this invention, the heat dissipation and high frequency performance of a semiconductor device can be improved.

(First embodiment)
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention.
The semiconductor device 100 includes a first conductive film 102, a first insulating resin film 106a formed thereon, a second conductive film 104 formed thereon, and a second conductive film 104 formed thereon. The second insulating resin film 106b, the third conductive film 140 formed thereon, the third insulating resin film 106c formed thereon, and the fourth conductive film formed thereon. A membrane 142. Via plugs 110 are respectively provided in the first insulating resin film 106a and the second insulating resin film 106b, and the first conductive film 102, the second conductive film 104, and the second conductive film 104 are provided. And the third conductive film 140 are electrically connected to each other. The first conductive film 102, the second conductive film 104, the third conductive film 140, and the fourth conductive film 142 are patterned into a predetermined shape.

  Note that in this embodiment, the first insulating resin film 106a, the second conductive film 104, the second insulating resin film 106b, the third conductive film 140, the third insulating resin film 106c, and the first The four conductive films 142 are selectively removed, and a recess 144 is formed in the semiconductor device 100. In the recess 144, the first conductive film 102 is exposed. The circuit element 120 is placed on the portion where the first conductive film 102 is exposed. Although not shown here, the circuit element 120 is fixed on the first conductive film 102 with a conductive paste or the like. The upper surface of the circuit element 120 and the second conductive film 104 are configured to be positioned at substantially the same height. The circuit element 120 is electrically connected to the second conductive film 104 via the bonding wire 122 on the upper surface thereof. The first conductive film 102 is grounded.

  The circuit element 120 is a semiconductor element such as a transistor, a diode, and an IC chip, or a passive element such as a chip capacitor and a chip resistor.

  In the present embodiment, since the circuit element 120 is electrically connected to the second conductive film 104 positioned at the same height as the upper surface thereof via the bonding wire 122, the length of the bonding wire 122. Can be shortened. Thereby, parasitic inductance can be reduced. Furthermore, since the circuit element 120 is formed in the recess 144, the electrical path between the first conductive film 102 to be grounded and the circuit element 120 can be shortened, so that the ground inductance can be reduced. High frequency performance can be improved. Moreover, the distance from the back surface of the semiconductor device 100 can be shortened, and the heat dissipation of the circuit element 120 can be improved. In particular, in the present embodiment, since the circuit element 120 is formed immediately above the first conductive film 102 at the bottom, the heat dissipation can be made very good.

FIG. 2 is a process cross-sectional view showing a manufacturing process of the semiconductor device 100 shown in FIG.
First, a sheet in which the first conductive film 102 and the second conductive film 104 are formed on both surfaces of the first insulating resin film 106a is prepared. Subsequently, a resist is placed on the surface on which the first conductive film 102 is formed, and an opening for forming a via hole is formed. Using this resist as a mask, the first conductive film 102 is selectively removed by wet etching. Thereby, the first conductive film 102 can be removed in the region where the via hole is formed. Subsequently, a carbon dioxide laser is irradiated from the surface on which the first conductive film 102 is formed (FIG. 2A). Here, the second conductive film 104 functions as a stopper layer.

  The carbon dioxide laser irradiates in two stages: a first condition and a second condition in which the pulse width is changed. Using a laser with a pulse period of 0.25 ms and an output of 1.0 W, the first condition may be, for example, a pulse width of 8 to 10 μs and a shot number of one. As the second condition, for example, the pulse width can be 3 to 5 μs, the pulse interval can be 25 ms or more, and the number of shots can be 3.

  As an example of the conditions for the carbon dioxide laser, a laser with a pulse period of 0.25 ms and an output of 1.0 W was used. As the first condition, the pulse width was 8 μs and the number of shots was 1. As the second condition, the pulse width can be 3 μs, the pulse interval can be 25 ms, and the number of shots can be 3.

  As another example of the condition of the carbon dioxide laser, a laser having a pulse period of 0.25 ms and an output of 1.0 W is used. As the first condition, the pulse width is 10 μs, the number of shots is 1, and the second condition The pulse width can be 5 μs, the pulse interval can be 25 ms, and the number of shots can be 3.

  As a result, a via hole 108 having a tapered sidewall whose diameter decreases in the direction from the first conductive film 102 to the second conductive film 104 is formed (FIG. 2B).

  The first conductive film 102 and the second conductive film 104 are, for example, a rolled metal such as a rolled copper foil. The same applies to the third conductive film 140 and the fourth conductive film 142. As the first insulating resin film 106a, for example, epoxy resin, melamine derivative such as BT resin, liquid crystal polymer, PPE resin, polyimide resin, fluorine resin, phenol resin, polyamide bismaleimide, or the like can be used. The same applies to the second insulating resin film 106b and the third insulating resin film 106c.

  Examples of the epoxy resin include bisphenol A type resin, bisphenol F type resin, bisphenol S type resin, phenol novolac resin, cresol novolac type epoxy resin, trisphenol methane type epoxy resin, and alicyclic epoxy resin.

  Melamine derivatives include melamine, melamine cyanurate, methylolated melamine, (iso) cyanuric acid, melam, melem, melon, succinoguanamine, melamine sulfate, acetoguanamine sulfate, melam sulfate, guanyl melamine sulfate, melamine resin, BT resin, cyanur Examples thereof include melamine derivatives such as acid, isocyanuric acid, isocyanuric acid derivatives, melamine isocyanurate, benzoguanamine and acetoguanamine, and guanidine compounds.

  Examples of the liquid crystal polymer include aromatic liquid crystal polyester, polyimide, polyester amide, and resin compositions containing them. Among these, a liquid crystal polyester or a composition containing a liquid crystal polyester that is excellent in the balance of heat resistance, workability, and hygroscopicity is preferable.

  Examples of liquid crystal polyesters are (1) those obtained by reacting aromatic dicarboxylic acids, aromatic diols and aromatic hydroxycarboxylic acids, and (2) obtained by reacting combinations of different types of aromatic hydroxycarboxylic acids. And (3) those obtained by reacting an aromatic dicarboxylic acid and an aromatic diol, and (4) those obtained by reacting an aromatic hydroxycarboxylic acid with a polyester such as polyethylene terephthalate. In addition, these ester derivatives may be used instead of these aromatic dicarboxylic acids, aromatic diols, and aromatic hydroxycarboxylic acids. Further, these aromatic dicarboxylic acids, aromatic diols and aromatic hydroxycarboxylic acids may be used in which the aromatic moiety is substituted with a halogen atom, an alkyl group, an aryl group or the like.

  As the repeating structural unit of the liquid crystal polyester, a repeating structural unit derived from an aromatic dicarboxylic acid (the following formula (i)), a repeating structural unit derived from an aromatic diol (the following formula (ii)), an aromatic hydroxycarboxylic acid, The derived repeating structural unit (the following formula (iii)) can be exemplified.

(i) -CO-A ₁ -CO-
(However, A ₁ represents a divalent linking group containing an aromatic ring.)
(ii) _-O-A 2 -O-
(However, A ₂ represents a divalent linking group containing an aromatic ring.)
(iii) _-CO-A 3 -O-
(Wherein A ₃ is a divalent linking group containing an aromatic ring.)

  Further, an aramid nonwoven fabric is preferably used as a material constituting the first insulating resin film 106a, the second insulating resin film 106b, and the third insulating resin film 106c. Thereby, workability can be made favorable. As the aramid fiber, para-aramid fiber or meta-aramid fiber can be used. For example, poly (p-phenylene terephthalamide) (PPD-T) can be used as the para-aramid fiber, and poly (m-phenylene isophthalamide) (MPD-I) can be used as the meta-aramid fiber, for example.

  Subsequently, a conductive material is embedded in the via hole 108 to form a via plug 110 (FIG. 2C). The via plug 110 can be formed by electroless plating, for example, or can be formed by an electrolytic plating method. The via plug 110 can be formed as follows, for example. First, after forming a thin film of about 0.5 to 1 μm on the entire surface by electroless copper plating, a film of about 20 μm is formed by electrolytic plating. In many cases, the electroless plating catalyst usually uses palladium. To attach the electroless plating catalyst to a flexible insulating substrate, palladium is included in an aqueous solution in the form of a complex. Forming a nucleus to start plating on the surface of a flexible insulating substrate by dipping the insulating substrate to attach a palladium complex to the surface and reducing it to metallic palladium directly using a reducing agent. Can do.

  A filling material can be appropriately embedded in the via plug 110. As the filling material, various materials such as an insulating material and a conductive material can be used. As the insulating material, a photo solder resist or a transfer mold resin can be used. As the conductive material, solder containing tin can be used. Also, copper can be embedded as a filling material by plating or the like.

  Thereafter, the first conductive film 102 and the second conductive film 104 are patterned into a predetermined shape to form a wiring. The wiring can be formed by using a photoresist as a mask and, for example, spraying a chemical etching solution on a portion exposed from the resist to remove unnecessary conductive films by etching. As the etching resist, an etching resist material that can be used for an ordinary printed wiring board can be used. In this case, the wiring is formed by silk screen printing of resist ink, or a photosensitive dry film for etching resist is laminated on the conductive film, and a photomask that transmits light in the shape of the wiring conductor thereon. Can be formed by exposing the ultraviolet rays and removing the unexposed portions with a developer. When copper foil is used as the first conductive film 102 or the second conductive film 104, the chemical etching solution includes a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide. Chemical etching solutions used for ordinary printed wiring boards, such as ammonium persulfate solution, can be used.

  A photo solder resist or the like can be appropriately embedded between the patterned wirings.

  In the same process, a plurality of insulating resin film layers are formed and laminated (FIG. 2D). In this embodiment mode, a three-layer (first insulating resin film 106a to third insulating resin film 106c) structure is employed.

  Subsequently, each layer other than the first conductive film 102 is selectively removed stepwise to form the recess 144 (FIG. 2E). Each layer can be removed by any one of punching, drilling, laser processing, and a combination thereof. In this embodiment, each layer is formed of a thin insulating resin film and a conductive film, so that the recess 144 can be easily formed.

  Thereafter, a conductive paste (not shown) such as a silver paste is formed in a region where the circuit element 120 is disposed on the first conductive film 102. The surface of the conductive paste can be flattened by pressing. Subsequently, the circuit element 120 is placed on the conductive paste. The circuit element 120 is fixed on the conductive paste with a brazing material such as solder or an adhesive. The circuit element 120 is connected to the second conductive film 104 via the bonding wire 122. Thereby, the semiconductor device 100 having the configuration shown in FIG. 1 is formed.

  Thereafter, the circuit element 120 may be sealed with a sealing resin. The circuit element 120 can be sealed using a mold. Although only one circuit element 120 is shown here, more circuit elements can be sealed simultaneously. The sealing resin can be realized by transfer molding, injection molding, potting or dipping. As the resin material, a thermosetting resin such as epoxy resin can be realized by transfer molding or potting, and a thermoplastic resin such as polyimide resin and polyphenylene sulfide can be realized by injection molding.

  Further, thereafter, bumps that are electrically connected to the first conductive film 102 can be formed on the back surface of the semiconductor device 100. The bump is grounded.

  In the present embodiment, since the circuit element 120 is electrically connected to the second conductive film 104 positioned at the same height as the upper surface thereof via the bonding wire 122, the length of the bonding wire 122. Can be shortened. Thereby, parasitic inductance can be reduced. Furthermore, since the circuit element 120 is formed in the recess 144, the electrical path between the first conductive film 102 to be grounded and the circuit element 120 can be shortened, so that the ground inductance can be reduced. High frequency performance can be improved. Further, since the semiconductor device 100 is formed immediately above the first conductive film 102 and the back surface of the first conductive film 102 is exposed, the heat dissipation of the circuit element 120 is very good. can do.

(Second embodiment)
FIG. 3 is a cross-sectional view showing a configuration of the semiconductor device 100 according to the second embodiment of the present invention. In the present embodiment, the first embodiment in which the circuit element 120 is electrically connected to the second conductive film 104 in that the circuit element 120 is electrically connected to the third conductive film 140. And different. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  Also in the present embodiment, the circuit element 120 is placed in the recess 144 so that the upper surface of the circuit element 120 is positioned at the same height as the third conductive film 140 electrically connected through the bonding wire 122. Be placed. Therefore, the length of the bonding wire 122 can be shortened. Thereby, parasitic inductance can be reduced.

  As described in the first embodiment, the thinner the layer disposed at the bottom of the circuit element 120, the better the heat dissipation of the circuit element 120. In the present embodiment, the semiconductor device 100 in the first embodiment is superior from the viewpoint of heat dissipation, but in this embodiment also, a thin insulating resin film 106 and a second insulating film 106 are formed on the bottom of the circuit element 120. Since only the conductive film 104 and the first conductive film 102 are disposed, the heat dissipation can be improved as compared with the case where the circuit element 120 is provided on a conventional substrate or the like. Also in the present embodiment, the circuit element 120 includes a recess 144 provided by selectively removing the fourth conductive film 142, the third insulating resin film 106c, and the third conductive film 140 step by step. Therefore, from this point of view, the layer disposed at the bottom of the circuit element 120 can be made thinner as compared with the case where the circuit element 120 is not provided in the recess 144, and the heat dissipation can be reduced. Can be good.

  Furthermore, since the circuit element 120 is formed in the recess 144, the electrical path between the first conductive film 102 to be grounded and the circuit element 120 can be shortened, so that the ground inductance can be reduced. High frequency performance can be improved.

  As shown in FIG. 4, also when the circuit element 120 is electrically connected to the fourth conductive film 142, the recess 144 is provided in the semiconductor device 100 and the circuit element 120 is disposed in the recess 144. Therefore, the height of the upper surface of the circuit element 120 and the fourth conductive film 142 can be made substantially the same, and the length of the bonding wire 122 can be shortened. Thereby, parasitic inductance can be reduced. Furthermore, the thickness of the layer disposed at the bottom of the circuit element 120 can be reduced, and heat dissipation can be improved. Furthermore, since the circuit element 120 is formed in the recess 144, the electrical path between the first conductive film 102 to be grounded and the circuit element 120 can be shortened. Thereby, a ground inductance can be reduced and high frequency performance can be improved.

  In the semiconductor device 100 described in the above second embodiment, for example, the second conductive film 104 is formed so as to cover the upper surface of the via plug 110 provided in the first insulating resin film 106a. . Thus, by covering the upper surface of the via plug 110 with the second conductive film 104, the surface of the second conductive film 104 on which the circuit element 120 is disposed can be flattened. Thereby, the circuit element 120 can be disposed on the region where the via plug 110 is formed. Therefore, a large number of via plugs 110 can be formed in the semiconductor device 100, and the heat dissipation of the semiconductor device 100 can be further improved.

  For example, the via plug 110 provided in the first insulating resin film 106 a is formed so that the diameter decreases from the first conductive film 102 toward the second conductive film 104. FIG. 5 is a diagram showing the shape of the via plug 110 formed as described above and the shape of the via plug 10 having a conventional shape. FIG. 5A shows the configuration of the via plug 110 formed in an opening on the surface opposite to the mounting surface of the circuit element 120. FIG. 5B shows a configuration of the conventional via 10 formed to be open on the mounting surface 126 side of the circuit element 120.

In the configuration shown in FIG. 5A, the via plug 110 is formed so that the diameter decreases in the direction from the first conductive film 102 to the second conductive film 104. The width of the wiring pattern of the second conductive film 104 to be formed can be reduced. As shown in FIGS. 5A and 5B, it is necessary to provide a certain distance between the end portion of the wiring pattern and the end portion of the via plug 110 in order to distribute the thermal stress. Further, when forming a via hole that opens on the second conductive film 104 side as in the prior art, it is necessary to increase the wiring width in consideration of misalignment of laser irradiation. Therefore, conventionally, the width L _{2 of the} wiring pattern is required for one via plug 10, whereas in the semiconductor device 100 according to the present embodiment, the width of the wiring pattern is set to L _{1 for} one via plug 110. (L ₂ > L ₁ ). As described above, since a necessary region can be narrowed for each via plug 110, the semiconductor device 100 can be reduced in size when the same number of via plugs as in the prior art are provided.

  Further, since the width of the wiring pattern for each via plug 110 can be narrowed, the circuit element 120 and the third conductive film 140 (second conductive film 104 or fourth conductive film 142) Can be shortened. Thereby, parasitic inductance can be reduced and high frequency performance can be improved.

  Here, the via plug 110 formed in the first insulating resin film 106a has been described as an example, but other via plugs included in the semiconductor device 100 may have the same configuration. The semiconductor device 100 can be reduced in size in the same manner in the first embodiment. Further, as shown in FIGS. 3 and 4, a via plug 111 having the same shape as the conventional one can be included except for the via plug 110 provided below the circuit element 120.

  The present invention has been described based on the embodiments and examples. It is to be understood by those skilled in the art that the embodiments and examples are merely examples, and various modifications are possible and that such modifications are within the scope of the present invention.

  In the above embodiment, the embodiment in which the filling material is embedded in the via plug 110 has been described. However, the filling material may not be embedded in the via plug 110. By not filling the filler material 112 in the via plug 110, the heat dissipation can be further improved.

  Further, the circuit element 120 may be configured such that a plurality of elements are stacked, such as a structure in which a second element is disposed on the first element. In this case, the combination of the first element and the second element can be, for example, SRAM and Flash memory, SRAM and PRAM.

  In the above embodiment, an example in which the via hole 108 is formed using a carbon dioxide laser has been described. However, other than this, machining, chemical etching using a chemical solution, dry etching using plasma, or the like is used. You can also.

It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the shape of the via plug in embodiment of this invention, and the shape of the conventional via plug, respectively. It is a figure for demonstrating the structure of BGA. It is a figure for demonstrating the structure of ISB (trademark).

Explanation of symbols

100 semiconductor device, 102 first conductive film, 104 second conductive film, 106a first insulating resin film, 106b second insulating resin film, 106c third insulating resin film, 108 via hole, 110 via plug, 111 via plug, 120 circuit element, 122 bonding wire, 140 third conductive film, 142 fourth conductive film, 144 recess.

Claims (4)

A laminate including a conductive film and an insulating resin film, the conductive film being disposed in the lowermost layer and the back surface of the conductive film disposed in the lowermost layer being exposed; and
An element electrically connected to the conductive film included in the laminate;
A semiconductor device comprising:
A recess is formed in the stacked body, and the element is disposed in the recess.   2. The concave portion is formed to reach an upper surface of a conductive film disposed in the lowermost layer, and the element is disposed on the conductive film disposed in the lowermost layer. The semiconductor device described. The laminate includes a first conductive film and a second conductive film provided via the insulating resin film, and includes the first conductive film, the insulating resin film, and the second conductive film. Are laminated in this order,
A via plug that electrically connects the first conductive film and the second conductive film is formed in the insulating resin film, and the via plug extends from the first conductive film to the second conductive film. 3. The semiconductor device according to claim 1, further comprising a side wall formed in a tapered shape whose diameter decreases in the direction of the film. The element is electrically connected to one conductive film by a bonding wire on an upper surface thereof,
4. The semiconductor device according to claim 1, wherein the concave portion is formed such that an upper surface of the element and the one conductive film are located on substantially the same plane. 5.

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