JP5607692B2 - Electronic equipment - Google Patents

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Publication number
JP5607692B2
JP5607692B2 JP2012182958A JP2012182958A JP5607692B2 JP 5607692 B2 JP5607692 B2 JP 5607692B2 JP 2012182958 A JP2012182958 A JP 2012182958A JP 2012182958 A JP2012182958 A JP 2012182958A JP 5607692 B2 JP5607692 B2 JP 5607692B2
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wiring layer
wiring
electronic device
surface
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JP2013012758A (en
Inventor
洋一郎 栗田
連也 川野
康志 副島
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ルネサスエレクトロニクス株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Description

  The present invention relates to an electronic device and a method for manufacturing the same.

  As a conventional method of manufacturing an electronic device, for example, there is one described in Patent Document 1. In the manufacturing method described in this document, the support substrate is removed after forming a multilayer wiring layer by sequentially laminating a plurality of wiring layers on the support substrate. Then, solder balls are formed as external electrode terminals on one surface of the multilayer wiring layer exposed by removing the support substrate. An electronic component is flip-chip mounted on the other surface of the multilayer wiring layer. As a result, an electronic device in which an electronic component is placed on the multilayer wiring layer is obtained.

  In addition to Patent Document 1, Patent Documents 2 to 5 are listed as prior art documents related to the present invention.

JP 2003-309215 A JP 57-7147 A JP-A-9-321408 Japanese Patent Laid-Open No. 11-126978 JP 2001-53413 A

  By the way, in the above electronic device, in order to make a fine connection between the wiring layer and the electronic component, a resin suitable for fine processing is used for the wiring layer on the electronic component side among the wiring layers constituting the multilayer wiring layer. Is required. On the other hand, it is often not required to use a resin suitable for microfabrication for the wiring layer on the solder ball side. In that case, in order to reduce the cost of the electronic device, it is preferable to use a relatively inexpensive resin for the wiring layer on the solder ball side.

  However, in the manufacturing method of Patent Document 1, as described above, a multilayer wiring layer is formed by sequentially stacking a plurality of wiring layers on a support substrate. Therefore, the wiring layer on the solder ball side is formed before the wiring layer on the electronic component side. For this reason, there is a restriction that a resin having a lower thermal decomposition temperature than a resin constituting the wiring layer on the electronic component side cannot be used as the resin constituting the wiring layer on the solder ball side. Due to such restrictions, the resin used for the wiring layer on the solder ball side is limited, which hinders cost reduction of the electronic device.

  The electronic device manufacturing method according to the present invention includes a first wiring layer forming step of forming a first wiring layer on a supporting substrate, a supporting substrate removing step of removing the supporting substrate, and a supporting substrate removing step. And a second wiring layer forming step of forming a second wiring layer extending outward from the first wiring layer on the surface of the first wiring layer on which the support substrate is provided. It is characterized by that.

  In this manufacturing method, the first wiring layer on which the electronic component is placed is formed on the support substrate, while the second wiring layer is formed after the support substrate is removed. As a result, it is possible to avoid the restriction that a resin having a lower thermal decomposition temperature than the resin constituting the first wiring layer cannot be used as the resin constituting the second wiring layer. Therefore, it is possible to use a resin suitable for microfabrication for the first wiring layer, while using a relatively inexpensive resin for the second wiring layer.

  According to another aspect of the invention, there is provided an electronic device comprising: a first wiring layer; and a second wiring layer provided on the first wiring layer and extending to the outside from the first wiring layer. Features.

  In this electronic device, as the resin constituting the second wiring layer, a resin having a lower thermal decomposition temperature than the resin constituting the first wiring layer can be used. Therefore, it is possible to use a resin suitable for microfabrication for the first wiring layer, while using a relatively inexpensive resin for the second wiring layer.

  ADVANTAGE OF THE INVENTION According to this invention, although it is low-cost, the electronic device and its manufacturing method which can obtain the fine connection of a wiring layer and an electronic component are implement | achieved.

1 is a cross-sectional view showing a first embodiment of an electronic device according to the present invention. It is sectional drawing for demonstrating an example of the structure of the interface vicinity of a 1st wiring layer and a 2nd wiring layer. (A)-(e) is process drawing which shows the outline | summary of 1st Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the electronic device by this invention. It is process drawing which shows 1st Embodiment of the manufacturing method of the electronic device by this invention. It is sectional drawing which shows 2nd Embodiment of the electronic device by this invention. (A) And (b) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. (A)-(c) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. (A) And (b) is process drawing which shows 2nd Embodiment of the manufacturing method of the electronic device by this invention. It is sectional drawing which shows 3rd Embodiment of the electronic device by this invention. (A) And (b) is process drawing which shows 3rd Embodiment of the manufacturing method of the electronic device by this invention. It is a top view for demonstrating the modification of embodiment. (A)-(c) is a top view for demonstrating the modification of embodiment.

Hereinafter, preferred embodiments of an electronic device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.
(First embodiment)

  FIG. 1 is a cross-sectional view showing a first embodiment of an electronic device according to the present invention. The electronic device 1 includes a wiring layer 10 (first wiring layer) and a wiring layer 20 (second wiring layer).

  The wiring layer 10 includes a via plug 12 (first conductive plug), an insulating resin 14, and a conductor wiring 16. The via plug 12 is formed in the insulating resin 14. As can be seen from the figure, the via plug 12 has a tapered shape whose diameter decreases as the wiring layer 20 is approached. Therefore, the area of the end face of the via plug 12 on the wiring layer 20 side is smaller than the area of the end face on the opposite side, that is, the end face on the side of the IC chips 32 and 36 described later.

  The conductor of the via plug 12 is, for example, Cu, Ni, Au, or Ag. The insulating resin 14 is, for example, a polyimide resin, a PBO (polybenzoxazole) resin, a BCB (benzocyclobutene) resin, a cardo resin (cardo type polymer), or an epoxy resin. The polyimide resin may be a photosensitive polyimide resin or a non-photosensitive polyimide resin. A conductor wiring 16 connected to the via plug 12 is formed on the insulating resin 14.

  IC chips 32 and 36 (electronic components) are placed on the upper surface (first surface) of the wiring layer 10. These IC chips 32 and 36 are flip-chip connected to the conductor wiring 16 via bumps 33 and 37, respectively. The gap between the IC chip 32 and the wiring layer 10 is filled with an underfill resin 34. Similarly, an underfill resin 38 is filled in the gap between the IC chip 36 and the wiring layer 10. A plurality of IC chips 36 are provided, and these are stacked on each other. The IC chip 32 and the IC chip 36 are, for example, a CPU and a stacked memory, respectively. A stacked memory is obtained by three-dimensionally stacking IC chips (memory) and electrically connecting the chips (memory).

  The IC chips 32 and 36 are covered with a sealing resin 52 formed on the wiring layer 10. More specifically, the side surface of the IC chip 32 and the side surface and the upper surface of the IC chip 36 are covered with the sealing resin 52.

  A wiring layer 20 is formed on the lower surface (second surface) of the wiring layer 10. The wiring layer 20 has a larger area in plan view than the wiring layer 10 and extends to the outside of the wiring layer 10. That is, the wiring layer 20 protrudes from the wiring layer 10.

  The wiring layer 20 includes a via plug 22 (second conductive plug) and an insulating resin 24. The via plug 22 is formed in the insulating resin 24. The via plug 22 is connected to the via plug 12 described above. As can be seen from the figure, the via plug 22 has a tapered shape whose diameter decreases as the wiring layer 10 is approached. Therefore, the area of the end face on the wiring layer 10 side of the via plug 22 is smaller than the area of the opposite end face, that is, the end face on the solder ball 60 side described later. The conductor of the via plug 22 is, for example, Cu, Ni, Au, or Ag, like the via plug 12. The insulating resin 24 is, for example, an epoxy resin. The wiring body including the wiring layer 10 and the wiring layer 20 described above functions as an interposer in the electronic device 1.

  The thermal decomposition temperature of the insulating resin 14 constituting the wiring layer 10 is higher than the thermal decomposition temperature of the insulating resin 24 constituting the wiring layer 20. When PBO is used as the insulating resin 14, the thermal decomposition temperature is 540 ° C., for example. Further, when an epoxy resin is used as the insulating resin 24, the thermal decomposition temperature is, for example, 310 ° C. Here, the thermal decomposition temperature is a temperature at which the weight of the resin is reduced by 5% by weight when measured using a thermobalance at a rate of temperature increase of 10 ° C./min. In addition, also when using the same kind of resin (for example, epoxy resin) as the insulating resins 14 and 24, the former has a higher thermal decomposition temperature than the latter.

  An IC chip 42 and a passive component 44 are placed as second electronic components on a portion of the wiring layer 20 outside the wiring layer 10. The passive component 44 is a capacitor such as a decoupling capacitor, for example. The IC chip 42 is covered with a sealing resin 54. The passive component 44 is covered with a resin 56 provided on the outer portion of the wiring layer 20. The resin 56 may be the same resin as the sealing resin 54 or may be a different resin.

  The wiring layer 20 has a multilayer wiring structure, and includes conductor wirings 26 provided in a plurality of layers and via plugs 28 that connect the conductor wirings 26 of different layers. A solder ball 60 is connected to the lowermost conductor wiring 26. A part of the solder ball 60 is buried in the solder resist 62. The solder ball 60 functions as an external connection terminal of the electronic device 1.

  An example of the structure near the interface between the wiring layer 10 and the wiring layer 20 will be described with reference to FIG. In this example, an adhesion metal film 72 is formed so as to cover the via plug 22. The adhesion metal film 72 is in contact with the via plug 12 on the via plug 22. Furthermore, an adhesive metal film 74 is also formed on the surface of the conductor wiring 16 in contact with the via plug 12.

  The adhesion metal films 72 and 74 are preferably films containing Ti (for example, Ti, TiN or TiW), or Cr films.

  The manufacturing method of the electronic device 1 will be described as a first embodiment of the manufacturing method of the electronic device according to the present invention with reference to FIGS. Prior to detailed description, an outline of the present manufacturing method will be described with reference to FIGS. 3 (a) to 3 (e). First, as shown in FIG. 3A, the wiring layer 10 is formed on the support substrate 90 (first wiring layer forming step). As the support substrate 90, a silicon substrate, a ceramic substrate, a glass substrate, a metal substrate, or the like can be used.

  Next, as shown in FIG. 3B, IC chips 32 and 36 are placed on the wiring layer 10 (electronic component placing step). Further, as shown in FIG. 3C, a sealing resin 52 is formed on the wiring layer 10 so as to cover the IC chips 32 and 36 (sealing resin forming step). Subsequently, as shown in FIG. 3D, the support substrate 90 is removed (support substrate removal step). Thereafter, as shown in FIG. 3E, the wiring layer 20 is formed on the lower surface of the wiring layer 10 (second wiring layer forming step). Finally, although not shown, the solder ball 60 is formed to obtain the electronic device 1 shown in FIG.

  Then, this manufacturing method is demonstrated in detail using FIGS. First, the insulating resin 14 is formed on the support substrate 90, and the via plug 12 is formed therein. Thereafter, the conductor wiring 16 is formed on the insulating resin 14 (FIG. 4A). Next, the IC chips 32 and 36 are flip-chip mounted on the conductor wiring 16 (FIG. 4B). Subsequently, a sealing resin 52 is formed on the wiring layer 10 so as to cover the IC chips 32 and 36. The sealing resin 52 can be formed, for example, by molding, printing, or potting (FIG. 5A). Thereafter, the support substrate 90 is removed to expose the lower surface of the wiring layer 10 (FIG. 5B).

  Next, an insulating resin 24 is formed on the lower surface of the wiring layer 10 so as to extend outside the wiring layer 10. At this time, for example, an insulating film can be used as the insulating resin 24. Subsequently, the IC chip 42 and the passive component 44 are mounted on a portion of the insulating resin 24 outside the wiring layer 10. Thereafter, a sealing resin 54 is formed so as to cover the IC chip 42 (FIG. 6A). Next, the resin 56 is formed so as to fill a gap on the outer portion of the insulating resin 24. Thereby, the passive component 44 is covered with the resin 56 (FIG. 6B).

  Next, the via plug 22 is formed in the insulating resin 24 so as to be connected to the via plug 12. Thereafter, a buildup wiring layer is formed on the insulating resin 24. For example, a conductor wiring 26 by a semi-additive method and a via plug 28 by laser processing may be alternately formed in an insulating resin layer such as an epoxy resin. Thereby, the wiring layer 20 is formed (FIG. 7). Thereafter, by forming the solder resist 62 and the solder balls 60, the electronic device 1 of FIG. 1 is obtained. The wiring layer 20 may be formed by adhering a previously formed multilayer wiring layer as the wiring layer 20 to the lower surface of the wiring layer 10.

  As is clear from the above description, the build-up directions of the wiring layers 10 and 20 are upward and downward in the drawings, respectively. Accordingly, as described above, the end surface of the via plug 12 on the IC chip 32, 36 side has a larger area than the end surface on the wiring layer 20 side, and the end surface on the solder ball 60 side of the via plug 22 is larger than the end surface on the wiring layer 10 side. The area is getting bigger.

  The effect of this embodiment will be described. In the above manufacturing method, the wiring layer 10 on which the IC chips 32 and 36 are placed is formed on the support substrate 90, while the wiring layer 20 is formed after the support substrate 90 is removed. As a result, it is possible to avoid the restriction that a resin having a lower thermal decomposition temperature than the insulating resin 14 cannot be used as the insulating resin 24. Therefore, a resin suitable for microfabrication can be used as the insulating resin 14, while a relatively inexpensive resin can be used as the insulating resin 24. As a result, a method of manufacturing the electronic device 1 that can obtain a fine connection between the wiring layer 10 and the IC chips 32 and 36 is realized at low cost.

  Further, the wiring layer 20 extends outside the wiring layer 10. Thereby, the area of the surface on which the solder balls 60 are provided (that is, the lower surface of the wiring layer 20) can be sufficiently increased while the area of the wiring layer 10 is kept small. For this reason, the electronic device 1 can be easily mounted on another electronic device, a motherboard, or the like without causing an increase in cost. On the other hand, when the area of the wiring layer 10 and the wiring layer 20 are equal to each other, if the area of the wiring layer 20 is increased in order to improve the ease of mounting, the area of the wiring layer 10 is not increased accordingly. I do not get. Then, since the wiring layer 10 is made of a relatively expensive resin suitable for fine processing, the manufacturing cost of the electronic device 1 increases. On the other hand, if the area of the wiring layer 10 is reduced in order to reduce the cost, the area of the wiring layer 20 is also reduced, and the ease of mounting is impaired. According to this embodiment, such a dilemma can be eliminated, and both low cost and ease of mounting can be achieved.

  Since the wiring pattern of the conductor wiring 16 is formed on the support substrate 90 having high rigidity, the fine conductor wiring 16 can be obtained. Further, since the wiring layer 10 and the IC chips 32 and 36 are bonded on the support substrate 90, the wiring layer 10 and the IC chips 32 and 36 can be bump-connected at a fine pitch. This leads to a decrease in the number of wiring layers and a reduction in the size of the IC chips 32 and 36.

  Furthermore, since the wiring layer 20 is formed after the support substrate 90 is removed, the insulating resin 24 constituting the wiring layer 20 can be formed thicker than the insulating resin 14. As a result, the stress relaxation function of the insulating resin 24 is enhanced, leading to an improvement in the reliability of the electronic device 1.

  In the second wiring layer forming step, a resin having a lower thermal decomposition temperature than the insulating resin 14 constituting the wiring layer 10 formed in the first wiring layer forming step is used as the insulating resin 24 constituting the wiring layer 20. ing. Thereby, the wiring layer 20 can be suitably formed on the wiring layer 10.

  In the electronic device 1, a resin having a lower thermal decomposition temperature than the insulating resin 14 constituting the wiring layer 10 can be used as the insulating resin 24 constituting the wiring layer 20. Therefore, a resin suitable for microfabrication can be used as the insulating resin 14, while a relatively inexpensive resin can be used as the insulating resin 24. As a result, the electronic device 1 that can obtain a fine connection between the wiring layer 10 and the IC chips 32 and 36 is realized at low cost.

  Further, in the electronic device 1, the wiring layer 10 and the wiring layer 20 are in direct contact with each other, and no core layer is provided between these layers. Since the via plug formed in the core layer is generally difficult to miniaturize compared to the via plug formed in the normal wiring layer, there is a problem in that miniaturization of the entire electronic device is hindered. In this respect, the electronic device 1 does not have such a problem because the core layer is not provided.

  A sealing resin 52 is provided so as to cover the IC chips 32 and 36. Thereby, the shape of the wiring body can be maintained even after the support substrate 90 is removed. For this reason, high coplanarity can be obtained for the solder ball 60. In particular, in the present embodiment, the resin 56 is also formed on the portion of the wiring layer 20 outside the wiring layer 10. Thereby, this effect is further enhanced.

  When a silicon substrate is used as the support substrate 90, the influence of thermal expansion can be suppressed as compared with the case where an insulating substrate is used. Thereby, the connection between the wiring layer 10 and the IC chips 32 and 36 can be further miniaturized.

  When polyimide resin, PBO resin, BCB resin, or cardo resin is used as the insulating resin 14, the insulating resin 14 suitable for fine processing is realized. Moreover, when an epoxy resin is used as the insulating resin 24, the insulating resin 24 can be obtained at low cost.

  An adhesion metal film 72 is provided so as to cover the via plug 22 (see FIG. 2). As a result, a strong bond is obtained between the via plug 22 and the insulating resin 24. Further, an adhesion metal film 74 is provided on the surface of the conductor wiring 16 in contact with the via plug 12 (see FIG. 2). Thereby, a strong bond is obtained between the conductor wiring 16 and the insulating resin 14. These contribute to the improvement of the reliability of the electronic device 1. When the adhesion metal films 72 and 74 contain Ti or are made of Cr, particularly high adhesion to the resin can be obtained.

An IC chip 42 and a passive component 44 are placed on a portion of the wiring layer 20 outside the wiring layer 10. As a result, the electronic device 1 can be further enhanced in functionality and performance.
(Second Embodiment)

  FIG. 8 is a sectional view showing a second embodiment of the electronic device according to the present invention. The electronic device 2 includes a wiring layer 10 (first wiring layer) and a wiring layer 80 (second wiring layer). The configuration of the wiring layer 10 is the same as that described in FIG.

  The wiring layer 80 is formed on the lower surface of the wiring layer 10 and extends to the outside from the wiring layer 10. The wiring layer 80 includes a solder resist 84 and a conductor wiring 86 formed therein. As the solder resist 84, a resin having a lower thermal decomposition temperature than the insulating resin 14 is used. A via plug 82 (second conductive plug) is formed in the wiring layer 80. The via plug 82 corresponds to a part of the solder ball 60, specifically, a part of the solder ball 60 that is buried in the solder resist 84. As can be seen from the figure, the via plug 82 has a tapered shape whose diameter decreases as it approaches the wiring layer 10. Therefore, the area of the end face of the via plug 82 on the wiring layer 10 side is smaller than the area of the end face on the opposite side.

  Further, an IC chip 92 is flip-chip mounted on the lower surface of the wiring layer 10. That is, the IC chip 92 is connected to the lower surface via the bumps 93, and the gap between the wiring layer 10 and the IC chip 92 is filled with the underfill resin 94.

  A resin 56 is formed on a portion of the wiring layer 80 outside the wiring layer 10. In the present embodiment, the resin 56 covers both the side surface and the upper surface of the sealing resin 52.

  A method for manufacturing the electronic device 2 will be described as a second embodiment of the method for manufacturing an electronic device according to the present invention with reference to FIGS. First, the insulating resin 14, the via plug 12, and the conductor wiring 16 are formed on the support substrate 90 (FIG. 9A). Subsequently, the IC chips 32 and 36 are flip-chip mounted on the conductor wiring 16 (FIG. 9B).

  Next, a sealing resin 52 is formed on the wiring layer 10 so as to cover the IC chips 32 and 36 (FIG. 10A). Thereafter, the support substrate 90 is removed to expose the lower surface of the wiring layer 10 (FIG. 10B). Subsequently, a support sheet 91 is formed on the lower surface of the wiring layer 10 so as to extend outside the wiring layer 10 (FIG. 10C).

  Next, a resin 56 is formed on the outer side of the wiring layer 10 of the support sheet 91 so as to cover the sealing resin 52 (FIG. 11A). Thereafter, the support sheet 91 is peeled off (FIG. 11B). Next, after forming the conductor wiring 86 on the lower surface of the wiring layer 10, a solder resist 84 is formed so as to cover it. Further, the solder resist 84 is patterned to open a portion where the solder ball 60 is formed and a portion where the IC chip 92 is mounted (FIG. 12A). Thereby, the wiring layer 80 is formed. Subsequently, the IC chip 92 is flip-chip mounted on the lower surface of the wiring layer 10 (FIG. 12B). Thereafter, by forming solder balls 60, the electronic device 2 of FIG. 8 is obtained.

In addition to the effect which 1st Embodiment mentioned above has, this embodiment can have the following effects. Since the solder resist 84 is used as the resin constituting the wiring layer 80, the cost of the electronic device 2 can be further reduced. Furthermore, an electronic component (IC chip 92) is mounted not only on the upper surface of the wiring layer 10 but also on the lower surface. As a result, the electronic device 2 can be further enhanced in function and performance.
(Third embodiment)

  FIG. 13 is a cross-sectional view showing a third embodiment of the electronic device according to the present invention. The electronic device 3 includes a wiring layer 10 and a wiring layer 80. The electronic device 3 is different from the electronic device 2 of FIG. 8 in that the wiring layer 80 has a multilayer wiring structure. In the present embodiment, the wiring layer 80 includes an insulating resin 84a provided on the lower surface of the wiring layer 10 and a solder resist 84b provided thereon.

  In the wiring layer 80 of the present embodiment, a conductor wiring 86 provided in a plurality of layers and a via plug 83 (second conductive plug) connected to the conductor wiring 86 are formed. As can be seen from the figure, the via plug 83 has a tapered shape whose diameter decreases as the wiring layer 10 is approached. Therefore, the area of the end face of the via plug 83 on the wiring layer 10 side is smaller than the area of the end face on the opposite side. In the electronic device 2, the bump 93 is directly connected to the via plug 12. In the electronic device 3, the bump 93 is connected to the via plug 12 via the conductor wiring 86 (and the via plug 83). Yes. Other configurations of the electronic device 3 are the same as those of the electronic device 2.

  With reference to FIGS. 14A and 14B, a method of manufacturing the electronic device 3 will be described as a third embodiment of the method of manufacturing the electronic device according to the present invention. First, the structure shown in FIG. 11B is prepared in the same manner as described with reference to FIGS.

  Next, a first-layer conductor wiring 86 is formed on the lower surface of the wiring layer 10 so as to be connected to the via plug 12. Thereafter, an insulating resin 84a is formed so as to cover it. Further, a via plug 83 is formed in the insulating resin 84 a so as to be connected to the conductor wiring 86. Subsequently, a second-layer conductor wiring 86 is formed on the insulating resin 84 a so as to be connected to the via plug 83. Thereafter, a solder resist 84b is formed so as to cover it.

  Next, the solder resist 84b is patterned to open a portion where the solder ball 60 is formed and a portion where the IC chip 92 is mounted (FIG. 14A). Thereby, the wiring layer 80 is formed. Subsequently, the IC chip 92 is flip-chip mounted on the insulating resin 84a (FIG. 14B). Thereafter, by forming solder balls 60, the electronic device 3 of FIG. 13 is obtained. In the present embodiment, the same effect as in the second embodiment is achieved.

  The electronic device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiment, and various modifications are possible. For example, in the above embodiment, the IC chip is exemplified as the electronic component placed on the upper surface or the lower surface of the wiring layer 10, but the electronic component may be a passive component such as a capacitor. In addition, it is not essential to provide electronic components in the electronic device.

  In the above embodiment, an example in which a solder ball is provided in the electronic device has been described. However, it is not essential to provide a solder ball. When the solder ball is not provided, the land portion of the conductor wiring corresponds to the external electrode terminal. Taking the electronic device 1 of FIG. 1 as an example, a portion of the conductor wiring 26 to which the solder ball 60 is connected is a land portion.

  Further, the second wiring layer may protrude from the entire periphery of the first wiring layer, or may protrude from only a part thereof. The former example is shown in FIG. 15, and the latter example is shown in FIGS. 16 (a) to 16 (c). In these plan views, the outer peripheries of the first and second wiring layers are indicated by lines L1 and L2, respectively, and the portions where both wiring layers overlap are hatched. In FIG. 15, the second wiring layer protrudes from all four sides of the first wiring layer. On the other hand, in FIG. 16A, FIG. 16B, and FIG. 16C, the second wiring layer protrudes from three sides, two sides, and one side of the first wiring layer, respectively.

DESCRIPTION OF SYMBOLS 1 Electronic device 2 Electronic device 10 Wiring layer 12 Via plug 14 Insulation resin 16 Conductor wiring 20 Wiring layer 22 Via plug 24 Insulation resin 26 Conductor wiring 28 Via plug 32 IC chip 33 Bump 34 Underfill resin 36 IC chip 37 Bump 38 Underfill resin 42 IC Chip 44 Passive component 52 Sealing resin 54 Sealing resin 56 Resin 60 Solder ball 62 Solder resist 72 Adhesive metal film 80 Wiring layer 82 Via plug 84 Solder resist 84a Insulating resin 84b Solder resist 86 Conductive wiring 90 Support substrate 91 Support sheet 92 IC chip 93 Bump 94 Underfill resin

Claims (9)

  1. An insulating layer having a surface on which the first wiring is installed and a back surface on the opposite side of the surface and on which the second wiring is installed ;
    A first chip installed on the surface and having a CPU circuit and a plurality of first electrodes on a main surface;
    A plurality of second chips installed on the surface, having a memory circuit on the main surface, stacked on each other and connected to each other via a plurality of penetrating electrodes;
    A third chip that is disposed directly below the plurality of second chips, overlaps the plurality of second chips in plan view, and has a plurality of second electrodes on a main surface;
    A plurality of external terminals installed on the back surface;
    A sealing body that seals the first chip, the plurality of second chips, and the surface and is made of a resin;
    Including
    The plurality of penetrating electrodes include a plurality of first penetrating electrodes disposed in a central portion of the plurality of second chips, and a plurality of second penetrating electrodes disposed outside the central portion, Including
    The plurality of first penetrating electrodes of the plurality of second chips and the plurality of second electrodes of the third chip are connected via a plurality of first conductive plugs, respectively.
    At least some of the plurality of second penetrating electrodes of the plurality of second chips are connected to the first electrode of the first chip via the first wiring;
    The second wiring is connected to the plurality of external terminals;
    The plurality of first penetrating electrodes, the plurality of first conductive plugs, and the plurality of second electrodes are arranged on a straight line in a sectional view,
    The first wiring is formed from the outer peripheral end of the insulating layer in plan view ,
    The second wiring is formed to extend from the inside of the insulating layer to the outside of the outer peripheral end of the insulating layer in plan view,
    A plurality of the insulating layer penetrating from the front surface to the back surface, one end of which is electrically and mechanically connected to the first wiring, and the other end is electrically and mechanically connected to the second wiring. An electronic device further comprising a second conductive plug .
  2. A first wiring layer including the insulating layer and the first wiring; and a second wiring layer including an insulating resin layer covering the second wiring and a part of the insulating layer;
    In a cross-sectional view, the first wiring layer is stacked on the second wiring layer,
    The electronic device according to claim 1 , wherein an area of the second wiring layer is larger than an area of the first wiring layer.
  3. In cross-sectional view, one of the plurality of second penetrating electrodes of the plurality of second chips is one of the plurality of first electrodes of the first chip via the first wiring and the second wiring. The electronic device according to claim 1, wherein the electronic device is connected to one another.
  4. In a cross-sectional view, another one of the plurality of second penetrating electrodes of the plurality of second chips is connected to the second through at least one of the plurality of second conductive plugs penetrating the insulating layer . The electronic device according to claim 3, wherein the electronic device is connected to wiring and connected to the plurality of external terminals.
  5. It said plurality of external terminals is said one surface opposite to the first wiring layer of the second wiring layer is formed in the opening opposite the other surface which is formed on the insulating resin layer,
    The opening has a first end surface and a second end surface opposite to the first end surface;
    Electronic device according to claim 2, wherein the area of said first end surface is equal to or larger than the area of the second end surface.
  6. 6. The cross-sectional view, wherein the first end surface of the opening is disposed farther than the second end surface of the opening as viewed from the one surface of the second wiring layer. Electronic equipment.
  7.   The electronic device according to claim 1, wherein the first chip, the second chip, and the third chip are flip-chip connected.
  8. 2. The electronic device according to claim 1, wherein in the cross-sectional view, the first conductive plug has a taper that decreases in diameter as it proceeds from the second chip side to the third chip side.
  9. 7. The electronic device according to claim 5, wherein the opening has a taper that decreases in diameter as it proceeds from the other surface side to the one surface side in a cross-sectional view.
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