JP2020058211A - Switching power supply - Google Patents

Abstract

To provide a highly efficient switching power supply.SOLUTION: A switching power supply 100 includes a switching output circuit that generates an output voltage from an input voltage by turning on/off an output transistor and charging a capacitor, a control circuit 180 that stops driving the switching output circuit when a charge to a capacitor by one switching is limited to a lower limit value and a feedback voltage FB according to the output voltage rises from a predetermined reference voltage REF, and a lower limit value setting circuit 700 that variably controls the lower limit value during the driving period of the switching output circuit. The lower limit value setting circuit 700 raises the lower limit value as the number of times of switching increases.SELECTED DRAWING: Figure 2

Description

  The invention disclosed in this specification relates to a switching power supply.

  Conventionally, a switching power supply (a so-called DC / DC converter) that generates a desired output voltage from an input voltage has been used as power supply means for various applications.

  In addition, as an example of the related art related to the above, Patent Literature 1 and Patent Literature 2 can be cited.

JP 2017-107551 A JP 2010-088218 A

  However, the conventional switching power supply has room for further improvement in efficiency.

  The first object of the invention disclosed in this specification is to provide a high-efficiency switching power supply in view of the above-mentioned problems found by the inventors of the present application.

  Further, in the conventional switching power supply, there is a possibility that an unpleasant noise sound is generated from the output capacitor due to a ripple component of the output voltage.

  The second object of the invention disclosed in the present specification is to provide a switching power supply that does not easily generate noise sound in view of the above-described problems found by the inventors of the present application.

  In order to achieve the first object, a switching power supply disclosed herein includes a switching output circuit that generates an output voltage from an input voltage by charging a capacitor by turning on / off an output transistor. A control circuit for stopping the driving of the switching output circuit when the charge on the capacitor by one switching operation is limited to a lower limit value and the output voltage or a feedback voltage corresponding thereto rises from a predetermined reference voltage; And a lower limit value setting circuit that variably controls the lower limit value during the drive period of the switching output circuit (first configuration).

  In the switching power supply having the first configuration, the lower limit value setting circuit may be configured to increase the lower limit value as the number of times of switching increases (second configuration).

  Further, in the switching power supply having the above first or second configuration, the lower limit value setting circuit may have a configuration (third configuration) in which the lower limit value is increased as the load becomes heavier.

  Further, in the switching power supply having any one of the first to third configurations, the lower limit value setting circuit compares the detection value of the inductor current flowing through the switching output circuit with a predetermined reference current value to set the lower limit value. A configuration for generating a signal (fourth configuration) may be used.

  In the switching power supply having the fourth configuration, the lower limit value setting circuit may have a configuration (fifth configuration) that variably controls the pulse generation timing of the lower limit value setting signal by changing the reference current value. Good.

  Further, the switching power supply having the fourth or fifth configuration is configured such that an error amplifier that generates an error signal corresponding to a difference between the output voltage or the feedback voltage and the reference voltage is pulse-driven at a predetermined switching frequency. An oscillator that generates an ON signal, and a PWM comparator that generates an OFF signal by comparing the error signal with a ramp signal, wherein the control circuit controls the output transistor at a pulse generation timing of the ON signal. The output transistor may be turned on and turned off at the later of the pulse generation timing of the off signal and the pulse generation timing of the lower limit setting signal (sixth configuration).

  Further, in the switching power supply having any one of the first to sixth configurations, the control circuit repeats driving and stopping of the switching output circuit when the output voltage or the feedback voltage rises from the reference voltage. A configuration (seventh configuration) in which the intermittent drive mode is set may be used.

  The switching power supply having the seventh configuration includes a first comparator that compares the output voltage or the feedback voltage with a predetermined upper threshold voltage to generate a first comparison signal; And a second comparator that compares a predetermined lower threshold voltage lower than the upper threshold voltage to generate a second comparison signal, wherein the control circuit is configured to perform the control in accordance with the first comparison signal. It is preferable that the driving of the switching output circuit is stopped while the driving of the switching output circuit is restarted in response to the second comparison signal (eighth configuration).

  In the switching power supply having the eighth configuration, the upper threshold voltage and the lower threshold voltage are each a voltage value obtained by multiplying the reference voltage by a coefficient greater than 1 (a ninth configuration). It is good to

  Further, in the switching power supply having any one of the first to ninth configurations, the switching output circuit may have a configuration of a step-down type, a step-up type, a step-up / step-down type, or an inversion type (tenth configuration).

  In order to achieve the second object, a switching power supply disclosed in the present specification includes a switching output for generating an output voltage from an input voltage by charging a capacitor by turning on / off an output transistor. A circuit, a lower limit value setting circuit for setting a lower limit value of the charge to be supplied to the capacitor by one switching, and a function of the lower limit value setting circuit, the output voltage or a feedback voltage corresponding to the output voltage being a predetermined reference. A control circuit that is in an intermittent drive mode that repeats driving and stopping the switching output circuit when the voltage rises from a voltage, wherein the control circuit controls the output voltage ripple frequency in the intermittent drive mode from the capacitor. A drive stop timing of the switching output circuit and a frequency that does not generate noise noise. Is configured for controlling at least one of the dynamic recommencement timing (eleventh configuration).

  In the switching power supply having the eleventh configuration, the control circuit forcibly drives the switching output circuit when a predetermined upper limit time has elapsed from a previous drive stop timing during driving of the switching output circuit. The configuration (the twelfth configuration) in which the operation is stopped temporarily may be used.

  Further, in the switching power supply having the eleventh or twelfth configuration, the control circuit is configured to switch the switching output circuit when a predetermined upper limit time has elapsed from the previous drive restart timing while the switching output circuit is stopped. It is preferable to adopt a configuration in which driving is forcibly restarted (a thirteenth configuration).

  In the switching power supply having the twelfth or thirteenth configuration, the upper limit time may be set to be shorter (a fourteenth configuration) than a reciprocal of a human audible upper limit frequency.

  Further, in the switching power supply having the eleventh configuration, the control circuit performs a slope determination of the output voltage or the feedback voltage after stopping the driving of the switching output circuit, and determines the switching output in accordance with the determination result. It is preferable to adopt a configuration (fifteenth configuration) for determining whether to stop driving the circuit.

  In the switching power supply having the fifteenth configuration, the control circuit forcibly restarts the driving of the switching output circuit when a slope of the feedback voltage is steeper than a predetermined value (a sixteenth configuration). ).

  In the switching power supply having the fifteenth or sixteenth configuration, the control circuit may include a part of a circuit necessary for restarting driving of the switching output circuit when a slope of the feedback voltage is not steeper than a predetermined value. Except for this, a configuration that shifts to a power saving mode in which power supply is cut off (a seventeenth configuration) may be adopted.

  Further, the switching power supply having any one of the first to seventeenth configurations includes: a first comparator that compares the output voltage or the feedback voltage with a predetermined upper threshold voltage to generate a first comparison signal; A second comparator for comparing a voltage or the feedback voltage with a predetermined lower threshold voltage lower than the upper threshold voltage to generate a second comparison signal, wherein the control circuit is configured to control the first comparison signal The driving of the switching output circuit may be stopped in response to the second comparison signal, and the driving of the switching output circuit may be restarted in response to the second comparison signal (an eighteenth configuration).

  Further, in the switching power supply having the eighteenth configuration, the upper threshold voltage and the lower threshold voltage are each a voltage value obtained by multiplying the reference voltage by a coefficient larger than 1 (a nineteenth configuration). It is good to

  In the switching power supply having any one of the first to nineteenth configurations, the switching output circuit may have a configuration of a step-down type, a step-up type, a step-up / step-down type, or an inversion type (a twentieth configuration).

  According to the invention disclosed in this specification, it is possible to provide a highly efficient switching power supply.

  Further, according to the invention disclosed in this specification, it is possible to provide a switching power supply that does not easily generate noise noise.

Diagram showing basic configuration of switching power supply Diagram showing main configuration of switching power supply The figure which shows the basic operation example of the intermittent drive mode The figure which shows the behavior when the lower limit of the charge charged by one switching is fixed. The figure which shows the behavior when the lower limit of the charge charged by one switching is variable Diagram showing a configuration example of a lower limit value setting circuit Diagram showing an operation example of a lower limit value setting circuit Diagram showing the behavior of the intermittent drive mode in the medium load region FIG. 6 is a diagram showing a first embodiment of ripple frequency limitation. FIG. 4 is a diagram showing a relationship between a human audible range and a ripple frequency in the first embodiment. FIG. 7 is a diagram showing a modification of the first embodiment. Diagram showing the behavior of the intermittent drive mode in the ultra-light load range Flowchart showing a second embodiment of ripple frequency limitation The figure which shows the relationship between the human audible range and the ripple frequency in 2nd Example. The figure which shows the 1st example of inclination determination The figure which shows the 2nd example of inclination determination The figure which shows the 3rd example of inclination determination

<Switching power supply (basic configuration)>
FIG. 1 is a diagram showing a basic configuration of a switching power supply. The switching power supply 100 of the present configuration example is a DC / DC converter of a PWM (pulse width modulation) drive system that generates an output voltage VOUT from an input voltage PVDD and supplies the output voltage VOUT to a load (not shown). It includes a voltage generation circuit 120, a reference voltage generation circuit 130, an error amplifier 140, a ramp signal generation circuit 150, an oscillator 160, a PWM comparator 170, a control circuit 180, and a switch drive circuit 190.

  The above components, except for some components included in the switching output circuit 110 (in this figure, the inductor 113 and the capacitor 114), are the semiconductor integrated circuit devices 200 (so-called power control ICs) that are the main control of the switching power supply 100. It is good to integrate in. Note that the semiconductor integrated circuit device 200 can appropriately incorporate optional components (such as various protection circuits) in addition to the above components.

  The semiconductor integrated circuit device 200 includes a plurality of external terminals (in this figure, a power terminal T1, an output terminal T2, a ground terminal T3, and a feedback terminal) as means for establishing an electrical connection with the outside of the device. T4).

  The switching output circuit 110 drives the inductor current IL to generate an output voltage VOUT from the input voltage PVDD by turning on / off an upper switch and a lower switch connected to form a half bridge. It is a switching output stage, and includes an output transistor 111, a synchronous rectification transistor 112, an inductor 113, and a capacitor 114 (corresponding to an output capacitor).

  The output transistor 111 is a PMOSFET (P-channel type metal oxide semiconductor field effect transistor) that functions as an upper switch of a switching output stage. Inside the semiconductor integrated circuit device 200, the source of the output transistor 111 is connected to the power supply terminal T1 (= application terminal of the input voltage PVDD). The drain of the output transistor 111 is connected to the output terminal T2 (= application terminal of the switch voltage SW). The gate of the output transistor 111 is connected to the application terminal of the upper gate signal G1. The output transistor 111 turns off when the upper gate signal G1 is at a high level, and turns on when the upper gate signal G1 is at a low level.

  The synchronous rectification transistor 112 is an NMOSFET [N channel type MOSFET] functioning as a lower switch of a switching output stage. Inside the semiconductor integrated circuit device 200, the source of the synchronous rectification transistor 112 is connected to the ground terminal T3 (= application terminal of the ground voltage PVSS). The drain of the synchronous rectification transistor 112 is connected to the output terminal T2. The gate of the synchronous rectification transistor 112 is connected to the application terminal of the lower gate signal G2. The synchronous rectification transistor 112 turns on when the lower gate signal G2 is at a high level, and turns off when the lower gate signal G2 is at a low level.

  The inductor 113 and the capacitor 114 are discrete components external to the semiconductor integrated circuit device 200, and form an LC filter that rectifies and smoothes the switch voltage SW to generate an output voltage VOUT. Outside the semiconductor integrated circuit device 200, a first end of the inductor 113 is connected to the output terminal T2 of the semiconductor integrated circuit device 200. A second terminal of the inductor 113 and a first terminal of the capacitor 114 are connected to an application terminal of the output voltage VOUT and the feedback terminal T4. The second terminal of the capacitor 114 is connected to the ground terminal.

  The output transistor 111 and the synchronous rectification transistor 112 are turned on / off complementarily according to the upper gate signal G1 and the lower gate signal G2. By such an on / off operation, a rectangular-wave-shaped switch voltage SW pulse-driven between the input voltage PVDD and the ground voltage GND is generated at the first end of the inductor 113. The term “complementary” is used not only when the ON / OFF states of the output transistor 111 and the synchronous rectification transistor 112 are completely reversed, but also when both transistors are simultaneously turned off (dead time). Including cases.

  The output form of the switching output circuit 110 is not limited to the above-described step-down type, but may be any of a step-up type, a step-up / step-down type, and an inversion type. Also, the rectification method of the switching output circuit 110 is not limited to the synchronous rectification method described above, and a diode rectification method using a rectifier diode as the lower switch may be employed.

  Further, the output transistor 111 can be replaced with an NMOSFET. However, in that case, a bootstrap circuit or a charge pump circuit is required to raise the high level of the upper gate signal G1 to a voltage value higher than the input voltage PVDD.

  Further, the output transistor 111 and the synchronous rectification transistor 112 can be externally attached to the semiconductor integrated circuit device 200. In that case, a terminal for externally outputting the upper gate signal G1 and the lower gate signal G2 is required instead of the output terminal T2.

  In particular, when a high voltage is applied to the switching output circuit 110, the output transistor 111 and the synchronous rectification transistor 112 have a high withstand voltage such as a power MOSFET, an IGBT (insulated gate bipolar transistor), and a SiC transistor, respectively. An element is preferably used.

  The feedback voltage generation circuit 120 includes resistors 121 and 122 connected in series between the feedback terminal T4 (= application terminal of the output voltage VOUT) and the ground terminal, and responds to the output voltage VOUT from a connection node between the two resistors. The feedback voltage FB (= the divided voltage of the output voltage VOUT) is output.

  When the output voltage VOUT falls within the input dynamic range of the error amplifier 140, the output voltage VOUT may be directly input to the error amplifier 140 by omitting the feedback voltage generation circuit 120.

  Further, the resistors 121 and 122 can be externally attached to the semiconductor integrated circuit device 200. In that case, a connection node between the resistors 121 and 122 may be connected to the feedback terminal T4.

  The reference voltage generation circuit 130 generates a predetermined reference voltage REF (= corresponding to a target set value of the output voltage VOUT). Note that as the reference voltage generation circuit 130, a DAC (digital-to-analog converter) that converts a digital reference voltage setting signal into an analog reference voltage REF may be used. With such a configuration, it is possible to realize a soft-start operation at the time of startup and adjust the output voltage VOUT by using the above-described reference voltage setting signal.

  The error amplifier 140 generates an error signal ERR corresponding to the difference between the feedback voltage FB applied to the inverting input terminal (-) and the reference voltage REF applied to the non-inverting input terminal (+). The error signal ERR increases when the feedback voltage FB is lower than the reference voltage REF, and decreases when the feedback voltage FB is higher than the reference voltage REF.

  The ramp signal generation circuit 150 generates a ramp signal RAMP having a triangular waveform, a sawtooth waveform, or an nth-order slope waveform (for example, n = 2) rising during the ON period Ton of the output transistor 111. The ramp signal RAMP starts rising from a zero value when the output transistor 111 is turned on, for example, and is reset to a zero value when the output transistor 111 is turned off.

  The oscillator 160 generates an ON signal ON (= clock signal) pulse-driven at a predetermined switching frequency fsw (= 1 / Tsw).

  The PWM comparator 170 compares the error signal ERR applied to the non-inverting input terminal (+) with the ramp signal RAMP applied to the inverting input terminal (-) to generate an OFF signal OFF. The off signal OFF is at a high level when the ramp signal RAMP is lower than the error signal ERR, and is at a low level when the ramp signal RAMP is higher than the error signal ERR. That is, the pulse generation timing of the OFF signal OFF is delayed as the error signal ERR is higher, and is earlier as the error signal ERR is lower.

  The control circuit 180 generates an upper control signal S1 and a lower control signal S2 according to the ON signal ON and the OFF signal OFF. Specifically, when a pulse is generated in the ON signal ON, the control circuit 180 sets both the upper control signal S1 and the lower control signal S2 to low level (= when the switch voltage SW is set to high level). When a pulse is generated with the OFF signal OFF, the upper control signal S1 and the lower control signal S2 are both set to a high level (= logic level when the switch voltage SW is set to a low level). Start up.

  Therefore, the on-period Ton (= high-level period of the switch voltage SW) of the output transistor 111 becomes longer as the pulse generation timing of the OFF signal OFF becomes longer, and conversely, becomes shorter as the pulse generation timing of the OFF signal OFF becomes earlier. That is, the on-duty D (= Ton / Tsw) of the output transistor 111 increases as the error signal ERR increases, and decreases as the error signal ERR decreases.

  The switch driving circuit 190 includes an upper driver 191 that receives an input of an upper control signal S1 and generates an upper gate signal G1, and a lower driver 192 that receives an input of a lower control signal S2 and generates a lower gate signal G2. Including. Buffers and inverters can be used as the upper drivers 191 and 192, respectively.

  Among the above components, the error amplifier 140, the ramp signal generation circuit 150, the oscillator 160, the PWM comparator 170, the control circuit 180, and the switch drive circuit 190 have the feedback voltage FB equal to the predetermined reference voltage REF. Thus, it can be understood as an output feedback control unit that performs duty control of the switching output circuit 110.

<Switching power supply (main part configuration)>
FIG. 2 is a diagram illustrating a main configuration of the switching power supply 100. The switching power supply 100 of the present configuration example includes, as means for realizing an intermittent drive mode at light load (details will be described later), the aforementioned components (the reference voltage generation circuit 130, the error amplifier 140, In addition to the generation circuit 150, the oscillator 160, the PWM comparator 170, and the control circuit 180), a lower limit value setting circuit 700 and comparators 710 and 720 are further provided. The following focuses on the new components.

  The lower limit value setting circuit 700 compares the detected value ISNS of the inductor current IL flowing through the switching output circuit 110 with a predetermined reference current value IREF, and charges the charging supplied to the capacitor 114 by one switching in the switching output circuit 110. A lower limit setting signal IMIN for setting the lower limit of the charge is generated. More specifically, a pulse is generated in the lower limit value setting signal IMIN at a timing when ISNS = IREF. When the ratio between the input voltage PVDD and the output voltage VOUT is constant, the lower limit value of the charge described above can be understood as the minimum on-period Tmin (or the minimum on-duty Dmin) of the switching output circuit 110.

  Further, the lower limit value setting circuit 700 also has a function of variably controlling the lower limit value of the charge charged by one switching during the driving period of the switching output circuit 110 in the intermittent drive mode. This lower limit variable function will be described later in detail.

  The comparator 710 compares the feedback voltage FB applied to the non-inverting input terminal (+) with the upper threshold voltage VthH (for example, VthH = 1.03 × REF) applied to the inverting input terminal (−) to sleep. A signal SLP (= corresponding to a first comparison signal) is generated. The sleep signal SLP goes high when the feedback voltage FB is higher than the upper threshold voltage VthH, and goes low when the feedback voltage FB is lower than the upper threshold voltage VthH.

  The comparator 720 compares the feedback voltage FB applied to the non-inverting input terminal (+) with the lower threshold voltage VthL (for example, VthL = 1.01 × REF) applied to the inverting input terminal (−). A resume signal RES (= corresponding to a second comparison signal) is generated. The resume signal RES goes high when the feedback voltage FB is higher than the lower threshold voltage VthL, and goes low when the feedback voltage FB is lower than the lower threshold voltage VthL.

  The control circuit 180 turns on the output transistor 111 and turns off the synchronous rectification transistor 112 by setting both the upper control signal S1 and the lower control signal S2 to low level at the pulse generation timing of the ON signal ON. At this time, the switch voltage SW becomes high level ($ PVDD).

  On the other hand, the control circuit 180 sets the upper control signal S1 and the lower control signal S2 to the high level in the later of the pulse generation timing of the OFF signal OFF and the pulse generation timing of the lower limit setting signal IMIN. Then, the output transistor 111 is turned off and the synchronous rectification transistor 112 is turned on. At this time, the switch voltage SW becomes low level (≒ PVSS). That is, when the pulse generation timing of the lower limit setting signal IMIN is later than the pulse generation timing of the off signal OFF, the off timing of the output transistor 111 is determined by the lower limit setting signal IMIN. This state corresponds to a state in which the charge of the capacitor 114 by one switching operation is limited to the lower limit.

  In addition, when the feedback voltage FB rises from the reference voltage REF, the control circuit 180 controls the feedback voltage FB to fall within a predetermined voltage range (VthL) by limiting the charge to the capacitor 114 by one switching operation to the lower limit value. ≤ FB ≤ VthH), and becomes an intermittent drive mode in which the switching output circuit 110 is repeatedly driven and stopped.

<Intermittent drive mode>
FIG. 3 is a diagram illustrating a basic operation example of the intermittent drive mode under a light load, in which a feedback voltage FB, a sleep signal SLP, a resume signal RES, and a switch voltage SW are depicted in order from the top.

  When the charge on the capacitor 114 by one switching operation is limited to a predetermined lower limit by the operation of the lower limit value setting circuit 700 described above, the charge on the capacitor 114 is output from the capacitor 114 when the load is light. Charge (= discharge charge). Therefore, the output voltage VOUT rises, and the feedback voltage FB becomes higher than the reference voltage REF. Therefore, the control circuit 180 detects such a rise in the output voltage VOUT and stops driving the switching output circuit 110.

  Referring to this drawing, the control circuit 180 controls the switching output circuit 110 at the timing when the feedback voltage FB becomes higher than the upper threshold voltage VthH and the sleep signal SLP rises to the high level (= time t102 and time t104). Stop driving. Specifically, the control circuit 180 turns off both the output transistor 111 and the synchronous rectification transistor 112, and sets the switch voltage SW to a high impedance state (Hi-Z).

  After that, the control circuit 180 restarts driving the switching output circuit 110 at the timing when the feedback voltage FB becomes lower than the lower threshold voltage VthL and the resume signal RES falls to the low level (= time t101, t103, t105). I do.

  By implementing such an intermittent drive mode, the number of times of switching under a light load can be reduced and switching loss can be reduced, so that the efficiency of the switching power supply 100 can be improved.

<Behavior when the lower limit is fixed>
FIG. 4 is a diagram illustrating a behavior when the lower limit of the charge charged by one switching operation is fixed, in which a feedback voltage FB is depicted.

  For example, when the lower limit value of the charge charged by one switching is much larger than the consumed charge of the load (= when the load is extremely light), the output voltage VOUT (and thus the feedback voltage FB) is changed every switching. Soaring. Therefore, at the timing when the feedback voltage FB becomes higher than the upper threshold voltage VthH (= time t112), even if the driving of the switching output circuit 110 is stopped immediately, by the time the rise of the output voltage VOUT actually stops, In addition, the output voltage VOUT may overshoot to a voltage value higher than the target value, and in the worst case, overvoltage protection may be activated (see the solid line in the figure).

  Conversely, if the lower limit of the charge charged by one switching operation is very close to the load consumption of the load, the output voltage VOUT (and thus the feedback voltage FB) rises very slowly, and the switching output circuit 110 is driven. Requires a very large number of switching times before stopping (see the broken line in the figure).

  In order to solve such a problem, the lower limit value setting circuit 700 has a function of variably controlling the lower limit value of the charge charged by one switching during the driving period of the switching output circuit 110 in the intermittent drive mode.

<Behavior when the lower limit is variable>
FIG. 5 is a diagram illustrating a behavior when the lower limit value of the charge charged by one switching operation is variable, in which the feedback voltage FB is depicted. The thick line shows the behavior when the lower limit is variable, and the thin line shows the behavior when the lower limit is fixed (the same behavior as in FIG. 4).

  The lower limit value setting circuit 700 increases the lower limit value of the charge charged by one switching as the number of switching increases during the driving period (= time t121 to t124) of the switching output circuit 110 in the intermittent driving mode.

  Specifically, the lower limit value of the charge charged by one switching is set to Q1 from time t121 to t122, set to Q2 (> Q1) from time t122 to t123, and is set from time t123 to t124. Is set to Q3 (> Q2).

  That is, in the drive period of the switching output circuit 110 (= time t121 to t124), immediately after the start of switching, the lower limit of the charge is narrowed down, and as the number of times of switching increases, the lower limit of the charge also increases. It will be raised.

  By performing such a lower limit variable control, when the load is light (= when it is considered that not so many switching times are required until the feedback voltage FB reaches the upper threshold voltage VthH), one operation is performed. Overshoot can be prevented by suppressing an increase in the output voltage VOUT (and, consequently, the feedback voltage FB) due to switching.

  Further, when the load is heavy (= when it is considered that a certain number of switchings are required until the feedback voltage FB reaches the upper threshold voltage VthH), the output voltage VOUT (and thus the feedback voltage FB ) Can be greatly increased, so that the number of times of switching (and hence switching loss) can be reduced and the efficiency of the switching power supply 100 can be increased.

<Lower limit value setting circuit>
FIG. 6 is a diagram illustrating a configuration example of the lower limit value setting circuit 700. The lower limit value setting circuit 700 of this configuration example includes an inductor current detection unit 701, a reference current setting unit 702, and a comparison unit 703.

  The inductor current detector 701 generates a sense signal ISNS (= corresponding to a detected value of the inductor current IL) corresponding to the inductor current IL flowing through the switching output circuit 110. Note that the method of detecting the inductor current IL includes a method of detecting the voltage between the drain and source of the output transistor 111 or the synchronous rectification transistor 112, and a method of detecting the drain / source of the current detection transistor connected in parallel to the output transistor 111 or the synchronous rectification transistor 112. A method of detecting a voltage between sources, a method of detecting a voltage between both ends of a sense resistor provided on a path where the inductor current IL flows, or the like can be adopted.

  The reference current setting unit 702 sets a reference current value IREF (= corresponding to a current clamp value) according to a reference current setting signal SET input from the control circuit 180.

  Comparing section 703 compares sense signal ISNS with reference current value IREF to generate lower limit value setting signal IMIN.

  FIG. 7 is a diagram illustrating an operation example of the lower limit value setting circuit 700, in which the sense signal ISNS, the ON signal ON, and the lower limit value setting signal IMIN are depicted in order from the top. It is assumed that one of set values IREF1 to IREF3 (where IREF1 <IREF2 <IREF3) is set as reference current value IREF to be compared with sense signal ISNS.

  At time t130, when a pulse is generated as the ON signal ON, the inductor current IL starts to increase, so that the signal value of the sense signal ISNS increases.

  First, consider a case where a set value IREF1 is set as the reference current value IREF. In this case, at time t131 when ISNS = IREF1, a pulse is generated in lower limit value setting signal IMIN (see IMIN1 in the figure). That is, the minimum ON period Tmin1 of the output transistor 111 is from time t130 to time t131.

  Next, a case where the set value IREF2 is set as the reference current value IREF is considered. In this case, at time t132 when ISNS = IREF2, a pulse is generated in lower limit value setting signal IMIN (see IMIN2 in the figure). That is, the minimum ON period Tmin2 of the output transistor 111 is from time t130 to time t132.

  Also, consider a case where a set value IREF3 is set as the reference current value IREF. In this case, at time t133 when ISNS = IREF3, a pulse is generated in lower limit value setting signal IMIN (see IMIN3 in the figure). That is, the minimum ON period Tmin3 of the output transistor 111 is from time t130 to time t133.

  As described above, in the lower limit value setting circuit 700, the reference current value IREF is changed in accordance with the reference current setting signal SET, so that the pulse generation timing of the lower limit value setting signal IMIN (therefore, the minimum ON period Tmin of the output transistor 111) ) Can be variably controlled.

  In FIG. 5 described above, the operation of raising the lower limit value of the charged charge by one switching in accordance with the number of switchings has been described. However, in order to realize such an operation, for example, the reference current value The reference current setting signal SET may be generated according to the number of times of switching so that IREF is switched from IREF1 to IREF2 to IREF3.

  However, the method of the lower limit variable control is not limited to the above. For example, it is possible to variably control the lower limit of the charge by one switching according to the load weight instead of the number of switching. It is.

  Specifically, the reference current setting signal SET may be generated so that the lower the load, the higher the lower limit of the charge charged by one switching operation.

  For example, in a power supply IC for a vehicle, a function of converting a detection value (analog value) of an inductor current into a digital signal and then monitoring it with a logic circuit has begun to be mounted. With such a power supply IC, it is possible to realize the lower limit variable control according to the load weight without adding a separate circuit element.

<Ripple frequency limitation (first embodiment)>
FIG. 8 is a diagram illustrating the behavior of the intermittent drive mode in the middle load region, in which the feedback voltage FB and the switch voltage SW are depicted in order from the top.

  In a load region where the lower limit value of the charge charged by one switching and the charge consumption of the load are very close (referred to as “medium load region” in this specification), as shown in FIG. The rise in the output voltage VOUT (and, consequently, the feedback voltage FB) in the drive period (= time t141 to t142) becomes extremely slow.

  Therefore, in the middle load region, the ripple period Trpl (= time t141 to t143) of the output voltage VOUT (and thus the feedback voltage FB) becomes longer, and the reciprocal, the ripple frequency Frpl, decreases.

  In particular, when the ripple frequency Frpl falls within a human audible range (generally, about 20 Hz to 20 kHz), annoying noise sound may be generated from the capacitor 114.

  In order to solve such a problem, the control circuit 180 performs switching so that the ripple frequency Frpl of the output voltage VOUT (and thus the feedback voltage FB) in the intermittent drive mode becomes a frequency at which noise noise is not generated from the capacitor 114. It has a function of controlling at least one of the drive stop timing and the drive restart timing of the output circuit 110 (= ripple frequency limiting function).

  FIG. 9 is a diagram showing a first embodiment of ripple frequency limitation, in which a feedback voltage FB, a switch voltage SW, and a count value CNT1 are depicted in order from the top. The thick line shows the behavior when the ripple frequency Frpl is restricted, and the thin line shows the behavior when the ripple frequency Frpl is not restricted (the same behavior as in FIG. 8).

  The control circuit 180 starts from the drive stop timing of the switching output circuit 110 in the intermittent drive mode (= see the circle at time t150, t152, and t154) and measures the elapsed time (= count value CNT1) from there. It has one counter.

  When a predetermined upper limit time (equivalent to the upper limit time of the ripple cycle Trpl) has elapsed from the previous drive stop timing during the driving of the switching output circuit 110, the control circuit 180 sets the feedback voltage FB to the upper threshold voltage VthH. , The driving of the switching output circuit 110 is forcibly stopped.

  This will be described in detail with reference to FIG. For example, at time t150, when driving of the switching output circuit 110 is stopped, the feedback voltage FB changes from rising to falling. Thereafter, at time t151, when the feedback voltage FB falls below the lower threshold voltage VthL, the driving of the switching output circuit 110 is restarted, and the feedback voltage FB starts to increase again.

  On the other hand, the count value CNT1 is reset to a zero value at time t150 when the driving of the switching output circuit 110 is stopped, and thereafter, is incremented at a predetermined cycle.

  When the count value CNT1 reaches the upper limit LMT1 during the driving of the switching output circuit 110 (= time t152), the driving of the switching output circuit 110 is forcibly performed even if the feedback voltage FB does not exceed the upper threshold voltage VthH. Will be suspended.

  As a result, the ripple period Trpl (= time t150 to t152) of the output voltage VOUT (and thus the feedback voltage FB) can be shortened, so that a decrease in the ripple frequency Frpl, which is the reciprocal thereof, can be suppressed. . The same operation as above is repeated after time t152.

  FIG. 10 is a diagram illustrating the relationship between the human audible range (the audible upper limit frequency FH and the audible lower limit frequency FL) and the ripple frequency Frpl in the first embodiment.

  By setting the above-mentioned upper limit LMT1 of the count value CNT1 so that the ripple cycle Trpl is shorter than the reciprocal of the human audible upper limit frequency FH (generally, about 50 μs), the ripple frequency Frpl is set to the audible upper limit frequency FH. (Generally about 20 kHz) (see the hatched area in the figure). Therefore, it is possible to reduce or prevent annoying noise generated from the capacitor 114.

  In this figure, for the sake of simplicity, the ripple frequency Frpl is compared with the human audible range to depict that Frpl> FH. However, if the ripple frequency Frpl is supposed to be the human audible upper limit frequency FH Even if the noise is slightly lower, if noise noise is not generated from the capacitor 114 (or noise noise is reduced), it can be said that the ripple frequency limitation effectively functions. That is, it is sufficient that the ripple frequency Frpl is limited to a frequency that does not generate noise noise from the capacitor 114.

  FIG. 11 is a diagram illustrating a modification of the first embodiment, in which a feedback voltage FB, a switch voltage SW, and count values CNT1 and CNT2 are depicted in order from the top.

  The control circuit 180 according to the present modification starts at the drive restart timing of the switching output circuit 110 in the intermittent drive mode (= see triangles at times t161, t163, and t165) in addition to the first counter described above. And a second counter for measuring the elapsed time (= count value CNT2) from the time.

  Then, while the switching output circuit 110 is stopped, when the predetermined upper limit time has elapsed from the previous drive restart timing, the control circuit 180 may switch the switching output circuit even if the feedback voltage FB does not fall below the lower threshold voltage VthL. Driving of 110 is forcibly restarted.

  This will be described in detail with reference to FIG. For example, at time t161, when the driving of the switching output circuit 110 is restarted, the feedback voltage FB changes from a decrease to an increase. After that, at time t162, when the driving of the switching output circuit 110 is stopped, the feedback voltage FB starts to decrease again.

  On the other hand, the count value CNT2 is reset to a zero value at a time t161 when the driving of the switching output circuit 110 is restarted, and thereafter is incremented at a predetermined cycle.

  When the count value CNT2 reaches the upper limit LMT2 while the switching output circuit 110 is stopped (= time t163), the driving of the switching output circuit 110 is performed even if the feedback voltage FB does not fall below the lower threshold voltage VthL. Forced restart.

  As a result, the ripple period Trpl (= time t161 to t163) of the output voltage VOUT (and thus the feedback voltage FB) can be shortened, so that it is possible to suppress a decrease in the reciprocal of the ripple frequency Frpl. . The same operation as described above is repeated after time t163.

<Ripple frequency limitation (second embodiment)>
FIG. 12 is a diagram illustrating the behavior of the intermittent drive mode in the ultra-light load region, in which the feedback voltage FB and the switch voltage SW are depicted in order from the top.

  In a load region where the lower limit value of the charge charged by one switching operation is much larger than the load consumption of the load (referred to as “ultra light load region” in this specification), as shown in FIG. In the drive suspension period (= time t172 to t173), the decrease of the output voltage VOUT (and thus the feedback voltage FB) becomes extremely slow.

  Therefore, in the ultra-light load region, the ripple period Trpl (= time t171 to t173) of the output voltage VOUT (and thus the feedback voltage FB) becomes longer, and the reciprocal thereof, the ripple frequency Frpl, decreases.

  In particular, when the ripple frequency Frpl falls within a human audible range (generally, about 20 Hz to 20 kHz), annoying noise sound may be generated from the capacitor 114.

  In order to solve such a problem, the control circuit 180 controls the switching output so that the ripple frequency Frpl of the output voltage VOUT (and thus the feedback voltage FB) in the intermittent drive mode becomes a frequency at which noise noise is not generated from the capacitor 114. A function (= ripple frequency limiting function) of controlling the drive restart timing of the circuit 110 is provided.

  FIG. 13 is a flowchart showing a second embodiment of ripple frequency limitation. When the driving of the switching output circuit 110 is stopped in step # 1, in the following step # 2, a slope determination (to be described in detail later) of the feedback voltage FB is performed.

  If it is determined in step # 3 that the slope of the feedback voltage FB is steeper than the predetermined value (= the absolute value is large), the flow proceeds to step # 4, and the driving of the switching output circuit 110 is performed. Forced restart (forced resume).

  On the other hand, when it is determined in step # 3 that the slope of the feedback voltage FB is not steeper than the predetermined value (= the absolute value is small), the flow proceeds to step # 5, and the driving of the switching output circuit 110 is stopped. To be continued.

  As described above, after stopping the driving of the switching output circuit 110, the control circuit 180 performs the slope determination of the feedback voltage FB (the output voltage VOUT), and drives the switching output circuit 110 according to the determination result. Decide whether to keep stopping.

  It should be noted that the threshold value of the inclination determination in step # 3 determines whether the ripple frequency Frpl becomes lower than the human audible lower limit frequency FL (generally about 20 Hz) when the driving of the switching output circuit 110 is stopped, or What is necessary is just to set to a value which can determine whether the frequency Frpl becomes higher than the human audible lower limit frequency FL and enters the human audible range.

  Further, the drive restart timing in step # 4 does not necessarily have to be immediately after the YES determination in step # 3, and is appropriate so that the ripple frequency Frpl becomes higher than the human audible upper limit frequency FH (generally about 20 kHz). The driving of the switching output circuit 110 may be restarted at the timing.

  Further, when the drive stop is continued in step # 5, the mode is shifted to the power saving mode in which the power supply is cut off except for some circuits (the resume comparator 720 and the control circuit 180) necessary for restarting the driving of the switching output circuit 110. Good to do. Such mode switching makes it possible to increase efficiency in an ultra-light load region.

  FIG. 14 is a diagram showing the relationship between the human audible range (the audible upper limit frequency FH and the audible lower limit frequency FL) and the ripple frequency Frpl in the second embodiment.

  When the switching output circuit 110 is forcibly resumed (= when the slope of the feedback voltage FB is determined to be steep in step # 3 of FIG. 13 and the driving of the switching output circuit 110 is forcibly restarted in step # 4). , The ripple frequency Frpl is maintained at a value higher than the human audible upper limit frequency FH (generally, about 20 kHz).

  On the other hand, when the switching output circuit 110 continues Hi-Z (= when it is determined that the feedback voltage FB is not steep in step # 3 of FIG. 13 and the driving stop of the switching output circuit 110 is continued in step # 4). , The ripple frequency Frpl is maintained at a value lower than the human audible lower limit frequency FL (generally about 20 Hz).

  As described above, according to the ripple frequency limitation of the second embodiment, since the ripple frequency Frpl does not fall within the human audible range, it is possible to reduce or prevent the harsh noise sound generated from the capacitor 114.

  In this figure, for the sake of simplicity, the ripple frequency Frpl is compared with the human audible range to illustrate that Frpl <FL (or Frpl> FH). Even if the frequency is slightly higher than the human audible lower limit frequency FL, as long as no noise sound is generated from the capacitor 114 (or the noise sound is reduced), it can be said that the ripple frequency limitation effectively functions. That is, it is sufficient that the ripple frequency Frpl is limited to a frequency that does not generate noise noise from the capacitor 114.

  For example, the upper limit value of the ripple frequency Frpl during the Hi-Z continuation in the ultra-light load region does not necessarily have to be lower than the human audible lower limit frequency FL (for example, about 20 Hz), and noise noise is generated from the capacitor 114. No frequency will be a realistic value.

<Tilt determination>
FIG. 15 is a diagram illustrating a first example of the inclination determination in steps # 2 and # 3 of FIG. 13, in which the feedback voltage FB is depicted.

  In the inclination determination of the first example, a measured value Vdet of the feedback voltage FB is acquired at time t183 after a predetermined standby time Tw has elapsed since the driving of the switching output circuit 110 was stopped at time t182. Then, by dividing the difference value (= Vdet−VthH) between the upper threshold voltage VthH and the measured value Vdet by the standby time Tw, the slope M of the feedback voltage FB (= (Vdet−VthH) / Tw, where M < 0) is calculated.

  As the slope M calculated in this way is steeper, the suspension period Tslp (= time t182 to t184) of the switching output circuit 110 is shorter, and the ripple period Trpl (= time t181 to t184) is shorter. Become.

  Accordingly, by determining whether the slope M of the feedback voltage FB is steeper than a predetermined threshold Mth (<0), it is determined whether the ripple frequency Frpl is higher than the human audible lower limit frequency FL (= human). Or not into the audible range of the).

  In the above description, for convenience of explanation, the calculation value of the slope M (= (Vdet−VthH) / Tw) is compared with a predetermined threshold value Mth (<0). What is necessary is just to compare the measured value Vdet of FB with a predetermined threshold value Vth (= VthH + Mth × Tw).

  FIG. 16 is a diagram illustrating a second example of the inclination determination in steps # 2 and # 3 of FIG. 13, in which the feedback voltage FB is depicted.

  As shown in the figure, when driving of the switching output circuit 110 is stopped at the time t192, the feedback voltage FB overshoots a little (FB = VthH + α). Therefore, by setting the standby time Tw to an appropriate length (= −Mth / α, where Mth <0), the upper threshold voltage VthH can be used as the aforementioned threshold Vth.

  That is, in the inclination determination of the second example, after a predetermined standby time Tw (= −Mth / α) has elapsed since the driving of the switching output circuit 110 was stopped at time t192, the feedback voltage FB was determined at time t193. Is determined whether the measured value Vdet is higher than the upper threshold voltage VthH, it is determined whether the ripple frequency Frpl is higher than the human audible lower limit frequency FL (whether or not to enter the human audible range). It is possible to do.

  In order to determine the inclination of the first embodiment (FIG. 15) or the second embodiment (FIG. 16), only one comparator for comparing the measured value Vdet of the feedback voltage FB with a predetermined threshold Vth is required. Since it is sufficient to prepare, the configuration is extremely easy. However, it should be noted that since a relatively long standby time Tw (about several tens of μs) is required to increase the accuracy of determining the slope M, the transition timing to the power saving mode is delayed.

  FIG. 17 is a diagram illustrating a third example of the inclination determination in steps # 2 and # 3 in FIG. 13, in which the feedback voltage FB is depicted.

  In the inclination determination of the third embodiment, the feedback voltage FB is obtained at times t203 and t204 at which predetermined standby times Tw1 and Tw2 (= Tw1 + Tw) have elapsed since the driving of the switching output circuit 110 was stopped at time t202. Measurement values Vdet1 and Vdet2 are obtained.

  Further, by dividing the difference value (= Vdet2−Vdet1) between the measured value Vdet1 and the measured value Vdet2 by the standby time Tw (= the difference value between the standby times Tw1 and Tw2), the slope M of the feedback voltage FB (= (Vdet2) −Vdet1) / Tw, where M <0) is calculated.

  By determining whether the slope M of the feedback voltage FB is steeper than a predetermined threshold value Mth (<0), it is determined whether the ripple frequency Frpl is higher than the human audible lower limit frequency FL (= human). Is included in the audible range).

  As described above, in the inclination determination of the third embodiment, the inclination M of the feedback voltage FB is calculated with high accuracy from the two measured values Vdet1 and Vdet2. Accordingly, the standby time Tw can be reduced as compared with the first embodiment (FIG. 15) and the second embodiment (FIG. 16), and the transition timing to the power saving mode can be advanced. . However, it should be noted that a means (such as a multi-bit ADC) for acquiring the measured values Vdet1 and Vdet2 of the feedback voltage FB is required in order to perform the inclination determination of the third embodiment.

<Other modifications>
Various technical features disclosed in this specification can be modified in various ways in addition to the above-described embodiment without departing from the spirit of the technical creation. That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive. The technical scope of the present invention is not limited to the above-described embodiment, and It is to be understood that all changes that fall within the meaning and range equivalent to the range are included.

  The switching power supply disclosed in this specification can be used as power supply means for various applications.

Reference Signs List 100 switching power supply 110 switching output circuit 111 output transistor (PMOSFET)
112 Synchronous rectification transistor (NMOSFET)
113 Inductor 114 Capacitor (output capacitor)
Reference Signs List 120 feedback voltage generation circuit 121, 122 resistor 130 reference voltage generation circuit 140 error amplifier 150 ramp signal generation circuit 160 oscillator 170 PWM comparator 180 control circuit 190 switch drive circuit 191, 192 driver 200 semiconductor integrated circuit device (power control IC)
700 Lower limit value setting circuit 701 Inductor current detection section 702 Reference current setting section 703 Comparison section 710 Comparator 720 Comparator T1, T2, T3, T4 External terminal

Claims (20)

A switching output circuit that generates an output voltage from an input voltage by turning on / off an output transistor and charging a capacitor;
A control circuit for stopping the driving of the switching output circuit when the charge on the capacitor by one switching operation is limited to a lower limit value and the output voltage or a feedback voltage corresponding thereto rises from a predetermined reference voltage; ,
A lower limit value setting circuit that variably controls the lower limit value during a drive period of the switching output circuit;
A switching power supply comprising:   The switching power supply according to claim 1, wherein the lower limit value setting circuit increases the lower limit value as the number of times of switching increases.   3. The switching power supply according to claim 1, wherein the lower limit setting circuit increases the lower limit as the load increases.   4. The lower limit value setting circuit according to claim 1, wherein the lower limit value setting circuit generates a lower limit value setting signal by comparing a detection value of an inductor current flowing through the switching output circuit with a predetermined reference current value. The switching power supply according to claim 1.   The switching power supply according to claim 4, wherein the lower limit value setting circuit variably controls the pulse generation timing of the lower limit value setting signal by changing the reference current value. An error amplifier that generates an error signal between the output voltage or the feedback voltage and the reference voltage;
An oscillator that generates an ON signal that is pulsed at a predetermined switching frequency,
A PWM comparator for comparing the error signal and the ramp signal to generate an off signal;
Further having
The control circuit turns on the output transistor at the pulse generation timing of the on signal, and turns off the output transistor at the later of the pulse generation timing of the off signal and the pulse generation timing of the lower limit setting signal. The switching power supply according to claim 4 or 5, wherein:   7. The control circuit according to claim 1, wherein the control circuit is in an intermittent drive mode in which the drive and stop of the switching output circuit are repeated when the output voltage or the feedback voltage rises from the reference voltage. A switching power supply according to any one of the preceding claims. A first comparator that generates a first comparison signal by comparing the output voltage or the feedback voltage with a predetermined upper threshold voltage;
A second comparator that generates a second comparison signal by comparing the output voltage or the feedback voltage with a predetermined lower threshold voltage lower than the upper threshold voltage;
Further having
8. The control circuit according to claim 7, wherein the control circuit stops driving the switching output circuit in response to the first comparison signal, and restarts driving of the switching output circuit in response to the second comparison signal. The described switching power supply.   9. The switching power supply according to claim 8, wherein the upper threshold voltage and the lower threshold voltage are each a voltage value obtained by multiplying the reference voltage by a coefficient greater than one.   The switching power supply according to any one of claims 1 to 9, wherein the switching output circuit is a step-down type, a step-up type, a step-up / step-down type, or an inverting type. A switching output circuit that generates an output voltage from an input voltage by turning on / off an output transistor and charging a capacitor;
A lower limit value setting circuit for setting a lower limit value of the charge charged to be supplied to the capacitor by one switching;
A control circuit which is in an intermittent drive mode in which the output voltage or a feedback voltage corresponding thereto is raised from a predetermined reference voltage by the operation of the lower limit value setting circuit to repeatedly drive and stop the switching output circuit,
Has,
The control circuit controls at least one of drive stop timing and drive restart timing of the switching output circuit so that a ripple frequency of the output voltage in the intermittent drive mode is a frequency that does not generate noise noise from the capacitor. A switching power supply.   12. The method according to claim 11, wherein the control circuit forcibly stops driving of the switching output circuit when a predetermined upper limit time has elapsed from a previous drive stop timing during driving of the switching output circuit. The described switching power supply.   The control circuit for forcibly restarting the driving of the switching output circuit when a predetermined upper limit time has elapsed from a previous driving restart timing while the switching output circuit is stopped, or The switching power supply according to claim 12.   14. The switching power supply according to claim 12, wherein the upper limit time is shorter than a reciprocal of a human audible upper limit frequency.   The control circuit performs a slope determination of the output voltage or the feedback voltage after stopping the driving of the switching output circuit, and determines whether to continue stopping the driving of the switching output circuit according to the determination result. The switching power supply according to claim 11, wherein:   16. The switching power supply according to claim 15, wherein the control circuit forcibly restarts the driving of the switching output circuit when a slope of the feedback voltage is steeper than a predetermined value.   When the slope of the feedback voltage is not steeper than a predetermined value, the control circuit shifts to a power saving mode in which power supply is cut off except for some circuits necessary for restarting driving of the switching output circuit. 17. The switching power supply according to claim 15 or claim 16. A first comparator that generates a first comparison signal by comparing the output voltage or the feedback voltage with a predetermined upper threshold voltage;
A second comparator that generates a second comparison signal by comparing the output voltage or the feedback voltage with a predetermined lower threshold voltage lower than the upper threshold voltage;
Further having
The control circuit stops driving of the switching output circuit in response to the first comparison signal, and restarts driving of the switching output circuit in response to the second comparison signal. The switching power supply according to claim 17.   19. The switching power supply according to claim 18, wherein the upper threshold voltage and the lower threshold voltage are each a voltage value obtained by multiplying the reference voltage by a coefficient greater than one.   The switching power supply according to any one of claims 11 to 19, wherein the switching output circuit is a step-down type, a step-up type, a step-up / step-down type, or an inverting type.

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