JP2020050573A - Manufacturing method of group iii nitride semiconductor substrate, and group iii nitride semiconductor substrate - Google Patents

Abstract

To suppress generation of a crack in a group III nitride semiconductor layer.SOLUTION: A manufacturing method of a group III nitride semiconductor substrate has a growth step for forming a group III nitride semiconductor layer by epitaxially growing a group III nitride semiconductor crystal on a principal plane of a ground substrate using, as the principal plane, a plane formed by tilting {-1-12-3} plane within 10°, by maintaining a state where irregularities constituted of a plurality of {-h0h-l} planes (h is a natural number, l is 0 or a natural number and satisfies a relation of 0≤l/h≤4) exist on a growth plane.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing a group III nitride semiconductor substrate and a group III nitride semiconductor substrate.

  Patent Document 1 discloses that a group III nitride semiconductor layer is formed on a base substrate having a c-plane as a main surface by HVPE (Hydride Vapor Phase Epitaxy).

  Patent Documents 2 and 3 disclose methods of forming a group III nitride semiconductor layer having a semipolar plane as a main surface on a sapphire substrate.

JP 2015-187043 A Patent No. 6266742 Patent No. 6232150

  When a group III nitride semiconductor layer is grown to a large thickness by a conventional method, sharp holes (pits) or cracks may occur in the group III nitride semiconductor layer. An object of the present invention is to suppress generation of sharp holes and cracks in a group III nitride semiconductor layer.

According to the present invention,
Maintaining a state in which the growth surface has irregularities composed of a plurality of {-h0hl} surfaces (h is a natural number, l is 0 or a natural number and satisfies the relationship of 0 ≦ l / h ≦ 4), A growth in which a group III nitride semiconductor layer is formed by epitaxially growing a group III nitride semiconductor crystal on the main surface of the base substrate having a main surface having a surface inclined at an angle of 10 ° or less within 10 °. A method for manufacturing a group III nitride semiconductor substrate having steps is provided.

According to the present invention,
A base substrate having, as a main surface, a surface in which the {-1-12-3} plane is inclined within 10 °;
The main surface has irregularities located on the base substrate and composed of a plurality of {-h0h-l} planes (h is a natural number, l is 0 or a natural number and satisfies the relationship of 0 ≦ 1 / h ≦ 4). A group III nitride semiconductor layer,
A group III nitride semiconductor substrate having:

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that a sharp hole and a crack generate in a group III nitride semiconductor layer.

1 is a schematic side view of a group III nitride semiconductor substrate according to an embodiment. FIG. 3 is a diagram for explaining unevenness maintained on a growth surface. FIG. 7 is a diagram for explaining a change in unevenness maintained on a growth surface. FIG. 3 is a diagram for explaining unevenness maintained on a growth surface. 3 is a flowchart showing an example of a processing flow of a method for manufacturing a group III nitride semiconductor substrate of the present embodiment. It is a flowchart showing an example of a flow of processing of a manufacturing method of a semipolar self-standing substrate of this embodiment. It is a flowchart which shows an example of the flow of a process of the preparation process of this embodiment. It is a process figure showing an example of a flow of processing of a preparation process of this embodiment. It is a schematic diagram which shows an example of the semipolar seed board | substrate obtained by the preparation process of this embodiment. It is a schematic diagram which shows an example of the semipolar seed board | substrate obtained by the preparation process of this embodiment. It is a schematic diagram which shows an example of the semipolar seed board | substrate obtained by the preparation process of this embodiment. FIG. 3 is a diagram illustrating a surface of a base substrate according to the first embodiment. FIG. 9 is a diagram illustrating a surface of a base substrate of Comparative Example 1. FIG. 3 is a diagram illustrating a surface of a GaN layer according to the first embodiment. FIG. 2 is an enlarged view showing a surface of a GaN layer of Example 1. FIG. 4 is a diagram illustrating a surface of a GaN layer of Comparative Example 1. 9 is an SEM image showing the surface of a GaN layer of Example 2. 9 is an SEM image showing the surface of a GaN layer of Comparative Example 2. FIG. 9 is a view showing a result of measuring the surface shape of the surface of the GaN layer of Example 3 along a m-axis projection direction with a surface roughness meter. FIG. 11 is a diagram showing the results of measuring the surface shape of the surface of the GaN layer of Comparative Example 3 along a m-axis projection direction with a surface roughness meter.

  Hereinafter, embodiments of a group III nitride semiconductor substrate and a method of manufacturing the same according to the present invention will be described with reference to the drawings. The drawings are merely schematic diagrams for describing the configuration of the present invention, and the size, shape, number of each member, the ratio of the sizes of different members, and the like are not limited to those illustrated. Further, in the present embodiment, the m-axis and the −c axis of the group III nitride semiconductor crystal constituting the group III nitride semiconductor layer or the group III nitride semiconductor substrate are aligned with the group III nitride semiconductor layer or the group III nitride semiconductor. The directions projected onto the main surface (growth surface) of the substrate are referred to as “m-axis projection direction” and “−c-axis projection direction”, respectively.

<First embodiment>
First, an outline of the method for manufacturing a group III nitride semiconductor substrate of the present embodiment will be described. The present inventors have found that when a group III nitride semiconductor crystal is epitaxially grown on a characteristic base substrate under characteristic growth conditions, the group III nitride semiconductor crystal is maintained while maintaining a state in which characteristic irregularities are present on the growth surface. It has been found that crystals grow. Then, it has been found that when the group III nitride semiconductor crystal is epitaxially grown as described above, sharp holes and cracks are hardly generated in the obtained crystal.

  The present embodiment has been completed based on this fact, and a group III nitride semiconductor layer is formed by epitaxially growing a group III nitride semiconductor crystal while maintaining a state where characteristic irregularities are present on the growth surface. This suppresses the formation of sharp holes and cracks in the group III nitride semiconductor layer.

  Next, the configuration of the method for manufacturing a group III nitride semiconductor substrate of the present embodiment will be described in detail. The method for manufacturing a group III nitride semiconductor substrate according to the present embodiment includes forming a group II nitride semiconductor layer by epitaxially growing a group III nitride semiconductor crystal on a characteristic underlying substrate under characteristic growth conditions. Having a process.

  The base substrate is a substrate whose main surface is a plane in which the {-1-12-3} plane is inclined within 10 °. The undersubstrate includes a group III nitride semiconductor layer. Then, the exposed surface of the group III nitride semiconductor layer becomes the main surface. The base substrate may be a single layer composed of one group III nitride semiconductor layer, or may be a laminate in which a plurality of layers are laminated. As an example of the laminate, a laminate in which a sapphire substrate, a buffer layer, and a group III nitride semiconductor layer are laminated in this order is exemplified, but the laminate is not limited thereto. For example, the sapphire substrate may be replaced with another different substrate. Further, the buffer layer may not be included. Further, other layers may be included.

  The growth conditions for epitaxially growing a group III nitride semiconductor crystal on the main surface of the undersubstrate are as follows.

Growth method: HVPE (Hydride Vapor Phase Epitaxy) method Growth Temperature: 970 ° C. or higher GaCl partial pressure (calculated from Ga on HCl flow rate): 0.1 kPa or more 3.4Pa or less NH ₃ partial pressure: 1.5 kPa or more 51kPa or less V / III ratio: 0.5 or more and 25 or less Pressure: 70 kPa or more and 150 kPa or less

  By this manufacturing method, a group III nitride semiconductor substrate having a base substrate 100 and a group III nitride semiconductor layer 101 as shown in FIG. 1 is formed.

  When a group III nitride semiconductor crystal is epitaxially grown on the base substrate as described above under the growth conditions as described above, a state where characteristic unevenness is present on the growth surface 102 of the group III nitride semiconductor layer 101 is maintained. , A group III nitride semiconductor crystal is epitaxially grown.

  Here, the unevenness existing on the growth surface 102 of the group III nitride semiconductor layer 101 will be described. The growth surface 102 has irregularities formed of a plurality of {-h0hl} surfaces (h is a natural number, l is 0 or a natural number, and satisfies the relationship of 0 ≦ l / h ≦ 4).

  Specifically, on the growth surface 102, first {-h0hl-1} surfaces and second {-h0hl-1} surfaces which are different from each other are alternately arranged along the -c axis projection direction. There are irregularities. At least one of h and l is different between the first {-h0hl-1} plane and the second {-h0hl-1} plane. The angle formed by the first {-h0hl-1} plane and the second {-h0hl-1} plane depends on the values of h and l, and the thickness of the group III nitride semiconductor layer 101 is large. It may change as it grows (as the growth progresses), but in any state it is 100 ° or more and less than 180 °.

  Further, on the growth surface 102, irregularities in which third {-h0hl-1} planes and fourth {-h0hl-1} planes equivalent to each other are alternately arranged along the m-axis projection direction. Exists. That is, h and l of the third {-h0hl-1} plane and the fourth {-h0hl-1} plane match. The angle formed between the third {-h0hl-1} plane and the fourth {-h0hl-1} plane depends on the values of h and l, and the thickness of the group III nitride semiconductor layer 101 increases. It may change as it grows (as the growth progresses), but in any state it is 100 ° or more and less than 160 °.

  The mode of the unevenness existing on the growth surface 102 changes as the film thickness of the group III nitride semiconductor layer 101 increases (as the growth proceeds). Specifically, as the thickness of the group III nitride semiconductor layer increases, the area of the first {-h0hl-1} plane decreases and the area of the second {-h0hl-1} plane increases. Further, as the film thickness of the group III nitride semiconductor layer increases, the length of the first {-h0hl-1} plane in the -c axis projection direction decreases, and the length of the second {-h0hl-1} plane decreases. The length in the c-axis projection direction increases.

  The {-h0h-1} plane is, for example, {-1010}, {-101-1}, {-101-2}, {−101-3}, {−202-3}, {−202-5}. , {-202-7}, {-303-4}, {-303-5}, {-303-7}, {-303-8}, {-303-10}, {-303-11} and , {-101-4}.

  Here, the irregularities formed on the growth surface 102 will be described using a specific example. It should be noted that the surface index shown in the description is merely an example, and the present invention is not limited to this.

  The growth surface 102 of the group III nitride semiconductor layer 101 has irregularities as shown in FIG. FIG. 2 is a schematic diagram based on data obtained from surface shape measurement on the unevenness existing on the growth surface 102 when the film thickness of the group III nitride semiconductor layer 101 is 80 to 230 μm.

  In the illustrated example, irregularities formed by the {-101-2} plane of the first plane and the {−h0h−1} plane (0 ≦ l / h <2) of the second plane are shown. . Specifically, along the −c-axis projection direction, there are concavities and convexities in which {-101-2} planes and {-h0hl−1} planes are alternately arranged. Further, along the m-axis projection direction, equivalent surfaces of {-101-2} surfaces and equivalent surfaces of {-h0h-1} surfaces are alternately arranged as third and fourth surfaces. There are irregularities.

  The length of the {-101-2} plane in the −c axis projection direction is 2 to 20 μm, and the length of the {−h0h−1} plane (0 ≦ l / h <2) in the −c axis projection direction is 1 ５5 μm. The length of the {-101-2} plane in the −c-axis projection direction is longer than the length of the {−h0h−1} plane in the −c-axis projection direction.

  The lengths of two {-101-2} planes adjacent in the m-axis projection direction in the m-axis projection direction are 2 to 12 μm and 1 to 5 μm.

  The mode of the unevenness changes as the film thickness of the group III nitride semiconductor layer 101 increases. However, the irregularities do not disappear and continue to exist. The present inventors have confirmed that even when the film thickness of the group III nitride semiconductor layer 101 is increased to 230 μm or more and 15 mm or less, unevenness does not disappear and continues to exist.

  FIG. 3 shows an example of a mode of change in the unevenness along the −c-axis projection direction. As the thickness of the group III nitride semiconductor layer 101 increases, the value of 1 / h on the {-h0h-l} plane increases, and as a result, {-h0h-l} as indicated by the arrow (1) in the drawing. The tilt angle of the surface changes.

  FIG. 4 shows a schematic diagram of the unevenness existing on the growth surface 102 when the film thickness of the group III nitride semiconductor layer 101 is several mm. In the figure, the {-h0h-1} plane is the {-202-3} plane.

  As shown in FIGS. 2 and 4, in this example, as the thickness of the group III nitride semiconductor layer 101 increases, the area of the {-101-2} plane decreases, and the film of the group III nitride semiconductor layer 101 decreases. As the thickness increases, the area of the {-h0h-l} (0 ≦ l / h <2) plane increases.

  In addition, as shown in FIGS. 2 and 4, in this example, as the film thickness of the group III nitride semiconductor layer 101 increases, the {-101-2} plane is projected in the −c-axis projection direction (first direction). As the length decreases and the thickness of the group III nitride semiconductor layer 101 increases, the length of the {-h0hl} (0 ≦ l / h <2) plane in the −c-axis projection direction increases.

  Note that the plane index shown in the description is merely an example, and a plurality of {-h0hl} planes (h is a natural number, l is 0 or a natural number) formed in the initial stage of the growth of the group III nitride semiconductor layer 101. 0 ≦ l / h ≦ 4), the area ratio, and the surface that becomes more dominant (the surface where the area becomes larger) as the film thickness of the group III nitride semiconductor layer increases, and the surface is inferior. The surface (the surface whose area is reduced) is predicted to change according to the inclination angle of the base substrate 100 in the c-axis projection direction or the like.

  Further, in the schematic diagrams of FIGS. 2 and 4, for convenience, the first, second, third, and fourth {−h0h−1} planes are linearly and regularly written, but show a tendency. However, the present invention is not limited to this, and the surface area, the length in each axial direction, the arrangement configuration, and the like of the {-h0hl} plane may be irregular.

  Next, the function and effect of the method for manufacturing a group III nitride semiconductor substrate of the present embodiment will be described.

  In the case of the method for manufacturing a group III nitride semiconductor substrate of the present embodiment in which a group III nitride semiconductor layer 101 is formed by epitaxially growing a group III nitride semiconductor crystal on a characteristic underlying substrate 100 under characteristic growth conditions In addition, characteristic irregularities can be formed on the growth surface of the group III nitride semiconductor layer 101. The characteristic unevenness shows a characteristic change as the film thickness of the group III nitride semiconductor layer 101 increases, but the characteristic unevenness does not disappear but continues to exist on the growth surface 102. Even when the film thickness of the group III nitride semiconductor layer 101 is increased to 230 μm or more and 15 mm or less, the unevenness can be maintained without disappearing.

  Then, according to the method for manufacturing a group III nitride semiconductor substrate of the present embodiment, the group III nitride semiconductor crystal is epitaxially grown while maintaining the state where the unevenness is present on the growth surface to form the group III nitride semiconductor layer 101. In addition, it is possible to suppress the inconvenience that the group III nitride semiconductor layer 101 is cracked, as compared with the case where the group III nitride semiconductor crystal is epitaxially grown while the growth surface is flat and the group III nitride semiconductor layer is formed.

  The reason for this is not clear, but is considered as follows. In heteroepitaxial growth of a group III nitride semiconductor (eg, GaN), bending stress occurs before and after growth due to lattice irregularities and differences in thermal expansion coefficients. In addition, even in homoepitaxial growth, three-dimensional crystal growth is often performed in the initial stage, so that stress and strain similarly occur. In the case of a crystal that grows with a flat growth surface, if abnormal growth or defect concentration occurs in a part of the crystal, that part becomes a stress concentration point, and the crystal breaks (= breaks). On the other hand, in the case of a crystal that grows in a state where the growth surface has irregularities, it is considered that stress concentration hardly occurs, and as a result, cracking hardly occurs.

  In the growth technique on a c-plane substrate, facets such as {1-101} and {1-102} are likely to be formed as planes other than the (0002) plane. (And the ratio of depth / valley width) are relatively acute angles of ~ 56 ° (0.94) and ~ 94 ° (0.47), so that deep holes are formed. Cracks and cracks often occur at the starting point. On the other hand, in the present embodiment, the angle formed by the first {-h0hl-1} plane and the second {-h0hl-1} plane, which form the unevenness, and the third {-h0hl-1}. The angle between the surface and the fourth {-h0hl} surface is a relatively obtuse angle of 100 ° or more. For example, the angle (and the ratio of depth / valley width) formed when irregularities are formed between {−101-4} and {−1010} in the −c-axis projection direction is 112 ° (0.34), and ｛. The angle (and the ratio of depth / valley width) formed when irregularities are formed between −101-2} and {−202-3} is １７172 ° (0.03), while ｛in the m-axis projection direction. The angle (and the ratio of depth / valley width) formed when the unevenness is formed on the −1010} equivalent surface is up to 100 ° (0.42), and when the unevenness is formed on the {-101-2} equivalent surface. Angle (and the ratio of depth / valley width) is 140 ° (0.18), and the angle formed when unevenness is formed on the {-202-3} equivalent surface is 134 ° (0.21). , {-101-4} when the unevenness is formed on the equivalent surface is up to 154 ° (0.12). According to the present embodiment, a deep hole is formed by obtusely forming the angle formed by the facet plane to 100 ° or more and less than 180 ° in the −c-axis projection direction and 100 ° or more and less than 160 ° in the m-axis projection direction. It is considered that the formation of cracks can be suppressed and the stress concentration of cracks can be further reduced.

<Second embodiment>
In the present embodiment, a semipolar free-standing substrate is manufactured using the method for manufacturing a group III nitride semiconductor substrate described in the first embodiment.

  The flowchart in FIG. 5 shows an example of the processing flow of the method for manufacturing a semipolar free-standing substrate of the present embodiment. As shown in the figure, in the method for manufacturing a semipolar free-standing substrate of the present embodiment, a preparing step S10, a group III nitride semiconductor layer forming step S20, and a cutting step S30 are performed in this order.

  Here, the outline of each step will be described with reference to the step diagram of FIG.

  In the preparation step S10, as shown in FIG. 6A, a semipolar seed substrate 1 having a semipolar surface as a main surface and made of a group III nitride semiconductor is prepared.

  In the group III nitride semiconductor layer forming step S20, a group III nitride semiconductor is epitaxially grown on the semipolar seed substrate 1 to form the group III nitride semiconductor layer 2, as shown in FIG. In the group III nitride semiconductor layer forming step S20, the growth step described in the first embodiment is applied.

  In the cutting step S30, as shown in FIG. 6C, a part of the group III nitride semiconductor layer 2 (separation part 2-2 of the group III nitride semiconductor layer) is separated from the semipolar seed substrate 1. A semi-polar free-standing substrate having a semi-polar surface as a main surface is obtained. Note that a plurality of semipolar free-standing substrates may be obtained by slicing the separation part 2-2 of the group III nitride semiconductor layer.

  Next, each step will be described in detail.

"Preparation step S10"
In the preparation step S10, as shown in FIG. 6A, a semipolar seed substrate 1 having a semipolar surface as a main surface and made of a group III nitride semiconductor is prepared. The main surface of the semipolar seed substrate 1 is a surface having an off angle within 10 ° from the {-1-12-3} plane.

  In the preparation step S10, the semipolar seed substrate 1 is manufactured by executing the processing shown in the flowchart of FIG. As shown in FIG. 7, in the preparation step S10, a fixing step S11, a first growth step S12, a cooling step S13, a second growth step S14, and a seed substrate cutting step S15 are performed in this order. .

  In the fixing step S11, the base substrate 10 is fixed to the susceptor. For example, a base substrate 10 as shown in FIG. 8A is fixed to a susceptor 20 as shown in FIG.

  Base substrate 10 includes a group III nitride semiconductor layer 12 having a semipolar plane as a main surface. The group III nitride semiconductor layer 12 is, for example, a GaN layer.

  The semipolar plane is a plane other than the polar plane and the nonpolar plane. The main surface (exposed surface in the figure) of the group III nitride semiconductor layer 12 is represented by a semipolar plane on the −c side (a semipolar plane on the N plane: Miller index (hkml); Less than semipolar plane).

  Undersubstrate 10 may be a laminate including layers other than group III nitride semiconductor layer 12, or may be a single layer of group III nitride semiconductor layer 12 alone. As an example of the laminated body, for example, as shown in FIG. 8A, a laminated body in which a sapphire substrate 11, a buffer layer (omitted in the drawing), and a group III nitride semiconductor layer 12 are laminated in this order. Although illustrated, it is not limited to this. For example, the sapphire substrate 11 may be replaced by another different substrate. Further, the buffer layer may not be included. Further, other layers may be included.

  The method of manufacturing the base substrate 10 is not particularly limited, and any technique can be adopted. For example, a group III nitride semiconductor layer 12 is formed on a sapphire substrate 11 having a predetermined plane orientation by epitaxially growing a group III nitride semiconductor by MOCVD (metal organic chemical vapor deposition) via a buffer layer. May be. In this case, the plane orientation of the main surface of the sapphire substrate 11, the presence or absence of nitriding during heat treatment performed on the sapphire substrate 11 before the formation of the buffer layer, the growth conditions for forming the buffer layer, the group III Growth conditions for forming the nitride semiconductor layer 12, processing for supplying a metal-containing gas (eg, trimethylaluminum, triethylaluminum) onto the main surface of the sapphire substrate 11 to form a metal film and a metal carbide film, By adjusting the growth conditions and the like when forming the buffer layer and the group III nitride semiconductor layer 12, the group III nitride semiconductor whose main surface becomes a desired semipolar surface on either the N polarity side or the Ga polarity side Layer 12 can be formed. Details are disclosed in Patent Documents 2 and 3.

  As another example of the method of manufacturing base substrate 10, a group III nitride semiconductor layer obtained by processing a group III nitride semiconductor layer obtained by c-plane growth (eg, slice or the like) and having a desired semipolar plane as a main surface is used. A semiconductor layer (base substrate 10) may be obtained. Further, a plurality of processed group III nitride semiconductor layers (base substrate 10) may be joined by any method to obtain a substrate having an enlarged area.

  The maximum diameter of the group III nitride semiconductor layer 12 is, for example, not less than 50 mm and not more than 6 inches. The thickness of the group III nitride semiconductor layer 12 is, for example, not less than 50 nm and not more than 500 μm. The diameter of the sapphire substrate 11 is, for example, not less than 50 mm and not more than 6 inches. The thickness of the sapphire substrate 11 is, for example, not less than 100 μm and not more than 10 mm.

  Next, the susceptor 20 will be described. The susceptor 20 has such a characteristic that the base substrate 10 that can be warped by the heating in the first growth step S12 and the second growth step S14 is not deformed by the warping force. Examples of such a susceptor 20 include, but are not limited to, a carbon susceptor, a silicon carbide coated carbon susceptor, a boron nitride coated carbon susceptor, a quartz susceptor, and the like.

  Next, a method of fixing the base substrate 10 to the susceptor 20 will be described. In this embodiment, as shown in FIG. 8B, the back surface of the base substrate 10 (the back surface of the sapphire substrate 11) is fixed to the surface of the susceptor 20. Thereby, the deformation of the base substrate 10 is suppressed. As a fixing method, a method is required in which the substrate is not peeled off by the heating in the first growth step S12 or the second growth step S14 or the warping force of the base substrate 10 which may be warped by the heating. For example, a fixing method using an adhesive such as an alumina-based, carbon-based, zirconia-based, silica-based, or nitride-based adhesive is exemplified.

  Returning to FIG. 7, in the first growth step S12, as shown in FIG. 8 (3), with the base substrate 10 fixed to the susceptor 20, HVPE (HVPE) is formed on the main surface of the group III nitride semiconductor layer 12. A group III nitride semiconductor is grown by the Hydride Vapor Phase Epitaxy method. Thus, a first growth layer 30 made of a single-crystal group III nitride semiconductor is formed. For example, GaN is epitaxially grown under the following growth conditions to form a GaN layer (first growth layer 30).

Growth temperature: 970 ° C to 1100 ° C
Growth time: 1h-50h
V / III ratio: 1-20
Growth film thickness: 100 μm to 10 mm

  In the first growth step S12, a polycrystalline group III nitride semiconductor is formed along the side surface of the stacked body including the susceptor 20, the base substrate 10, and the first growth layer 30. The polycrystalline group III nitride semiconductor adheres to all or most of the side surfaces of the laminate. The attached polycrystalline group III nitride semiconductors are connected to each other to form a ring. Then, the stacked body is held inside the annular polycrystalline group III nitride semiconductor.

  In the first growth step S12, a polycrystalline group III nitride semiconductor can be formed on the back surface of the susceptor 20 in addition to the side surface of the stacked body. The polycrystalline group III nitride semiconductor adheres to all or most of the side surface of the stacked body and the back surface of the susceptor 20. The attached polycrystalline group III nitride semiconductors are connected to each other to form a cup shape. Then, the stacked body is held inside a cup-shaped polycrystalline group III nitride semiconductor.

  Returning to FIG. 7, in the cooling step S13, the stacked body including the susceptor 20, the base substrate 10, and the first growth layer 30 is cooled. The purpose of the cooling here is to generate cracks in the first growth layer 30 using strain (stress) generated due to a difference in linear expansion coefficient between the first growth layer 30 and the sapphire substrate 11. Is to relieve the stress. Prior to the second growth step S14, it is desired that the stress is relaxed. If the object can be achieved, the cooling method is not particularly limited. For example, after the first growth step S12, the laminate may be temporarily taken out of the HVPE apparatus and cooled to room temperature.

  As shown in FIG. 8C, cracks (cracks, cracks, etc.) 31 exist in the first growth layer 30 after the cooling step S13. The crack 31 may be present on the surface of the first growth layer 30 as shown. The crack 31 may be generated during the first growth step S12 or may be generated during the cooling step S13.

  Returning to FIG. 7, in the second growth step S14, as shown in FIG. 8 (4), with the base substrate 10 fixed to the susceptor 20, the III layer is formed on the first growth layer 30 by HVPE. A group nitride semiconductor is grown. Thus, a second growth layer 40 made of a single crystal group III nitride semiconductor is formed. For example, GaN is epitaxially grown under the following growth conditions to form a GaN layer (second growth layer 40). The growth conditions for forming the first growth layer 30 and the growth conditions for forming the second growth layer 40 may be the same or different.

Growth temperature: 970 ° C to 1100 ° C
Growth time: 1h-50h
V / III ratio: 1-20
Growth film thickness: 100 μm to 10 mm

  In the second growth step S14, the second growth layer 40 is formed on the first growth layer 30 with the ring-shaped polycrystalline group III nitride semiconductor formed in the first growth step S12 remaining. Form. The purpose of leaving the ring-shaped polycrystalline group III nitride semiconductor is to suppress the separation by holding the first growth layer 30 which can be separated into a plurality of portions due to the cracks 31 from the outer periphery. . If the first growth layer 30 is separated into a plurality of portions, the plane orientation shift, the handling property, the workability, and the like of each of the plurality of portions deteriorate. In addition, the original shape may not be able to be reproduced because some parts are missing or shattered. According to the present embodiment, since the plane orientation deviation and separation can be suppressed, the inconvenience can be suppressed.

  Note that the entire polycrystalline group III nitride semiconductor formed in the first growth step S12 may be left as it is, but it is sufficient if the above object can be realized, and the polycrystalline group III nitride semiconductor formed in the first growth step S12 is not necessarily required. It is not necessary to leave all of the crystalline group III nitride semiconductor. That is, a part of the polycrystalline group III nitride semiconductor may be removed.

  Also in the second growth step S14, a polycrystalline group III nitride semiconductor is formed. The polycrystalline group III nitride semiconductor can be formed along the side surface of the stacked body including the susceptor 20, the base substrate 10, the first growth layer 30, and the second growth layer 40, and along the back surface of the susceptor 20.

  In the second growth step S14, a group III nitride semiconductor is grown by HVPE on the surface of the first growth layer 30 where the cracks 31 are present to form the second growth layer 40. In this case, the growth surface (the surface of the first growth layer 30) is discontinuous at the crack 31 portion. The group III nitride semiconductor grown from each of the first surface region and the second surface region separated from each other by the crack 31 joins and integrates as the growth proceeds.

  In the second growth step S14, the growth step described in the first embodiment may be applied. That is, the growth conditions and the plane orientation of the main surface of the underlying substrate 10 may be the conditions described in the first embodiment.

  Returning to FIG. 7, in the seed substrate cutting step S15, at least a part of the second growth layer 40 is cut as the semipolar seed substrate 1.

  For example, as shown in FIG. 8 (5), a laminate including the susceptor 20, the base substrate 10, the first growth layer 30, and the second growth layer 40 is sliced to form at least a part of the second growth layer 40. Is separated from the susceptor 20 to obtain a semipolar seed substrate 1. Note that a plurality of semipolar seed substrates 1 may be obtained by slicing at least a part of the second growth layer 40 separated from the susceptor 20. In addition, at least a part of the second growth layer 40 may be separated from the susceptor 20 by using a method such as grinding, polishing, burning, decomposing, and melting in addition to slicing.

  Thus, a semipolar seed substrate 1 having a semipolar plane as a main surface and made of a group III nitride semiconductor is obtained.

  According to the preparation step S10, a semiconductor can be epitaxially grown on the first growth layer 30 in which the stress has been relaxed, and the second growth layer 40 can be formed (second growth step S14). For this reason, cracks and cracks are less likely to occur in the second growth layer 40 than when the first growth layer 30 is thickened to have the same thickness without relaxing the stress.

  Therefore, according to the preparation step S10, it becomes possible to grow a Group III nitride semiconductor having a semipolar surface as a main surface and a sufficient diameter in a thick film. As a result, a bulk crystal including the first growth layer 30 and the second growth layer 40 is obtained. For example, the thickness of the second growth layer 40 is not less than 500 μm and not more than 20 mm, and the maximum diameter thereof is not less than Φ50 mm and not more than Φ6 inches. The thickness of the first growth layer 30 is not less than 100 μm and not more than 10 mm. When the first growth layer 30 and the second growth layer 40 are combined, the film thickness becomes 600 μm or more and 30 mm or less. The surface of the second growth layer 40 is uneven, and there is a {-h0h-1} facet (h is a natural number, l is 0 or a natural number and satisfies the relationship of 0 ≦ 1 / h ≦ 4).

  According to the preparation step S10 in which a bulk crystal having a sufficient diameter and a sufficient film thickness can be manufactured as described above, a semipolar surface is obtained by cutting out a part (the group III nitride semiconductor layer) from the bulk crystal. And the semipolar seed substrate 1 having a sufficient diameter and a sufficient thickness can be efficiently manufactured. For example, the maximum diameter of the semipolar seed substrate 1 is Φ50 mm or more and Φ6 inches or less, and the thickness of the semipolar seed substrate 1 is 100 μm or more and 10 mm or less.

  When relaxing the stress, cracks 31 occur in the first growth layer 30. The second growth layer 40 grown on the first growth layer 30 has a first surface region and a second surface region of the first growth layer 30 separated from each other by the crack 31. The crystals grown from each are formed by joining each other. Here, dislocations may occur on the interface between the first surface region and the second surface region. If the plane orientations of the first surface region and the second surface region are shifted, the number of dislocations on the interface increases. In the present embodiment, the first growth layer 30 is held from the outer periphery by an annular polycrystalline group III nitride semiconductor. For this reason, the deviation of the plane orientation can be suppressed. As a result, an increase in dislocation on the interface can be suppressed.

  Further, according to the preparation step S10 in which the first growth step S12 and the cooling step S13 are performed in a state where the base substrate 10 is restrained by the susceptor 20, compared to the case where the same processing is performed in a state in which the restraint is not performed, The number of cracks 31 generated in one growth layer 30 can be reduced.

  Further, according to the preparation step S10 in which the second growth step S14 is performed with the stacked body including the base substrate 10 and the first growth layer 30 constrained by the susceptor 20, the same processing is performed without the constrain. The number of cracks generated in the first growth layer 30 and the second growth layer 40 can be reduced and separation can be suppressed as compared with the case where the formation is performed.

  According to the preparation step S10, as shown in FIGS. 9A and 9B, the first portion 51 made of a single crystal and the second portion 52 made of a polycrystal are used. The configured semipolar seed substrate 1 can be manufactured. 9 (1) and 9 (2) are plan views of the semipolar seed substrate 1, showing the main surface.

  The second portion 52 is attached to the outer periphery of the first portion 51. The second portion 52 has an annular shape and holds the first portion 51 therein. The second portion 52 may be in a state of being randomly attached as shown in FIG. 9A, or may be prepared by polishing or grinding as shown in FIG. 9B.

  According to the semipolar seed substrate 1 of this embodiment, the diameter can be increased by the second portion 52. As a result, handleability and workability are improved, and when the semipolar seed substrate 1 is used as a seed substrate, a large growth area of the first portion 51 made of a single crystal can be secured. For example, the maximum diameter of the first portion 51 is Φ50 mm or more and Φ6 inches or less, and the maximum diameter of the group III nitride semiconductor layer having the first portion 51 and the second portion 52 is Φ51 mm or more and Φ6.5 inches or less. is there.

  The semipolar seed substrate 1 composed of only the first portion 51 made of single crystal may be obtained by removing the second portion 52 made of polycrystal.

  Further, according to the preparing step S10 of the present embodiment, as shown in FIGS. 10 and 11, the semipolar seed substrate 1 including a plurality of portions having different crystal axis directions is manufactured. FIG. 11 is a sectional view taken along line AA ′ of FIG. Each of the illustrated regions A and B is a portion grown from each of the first surface region and the second surface region of the first growth layer 30 separated from each other by the crack 31.

  The crystals in the regions A and B have different crystal axes due to a shift of the crystal axis between the first surface region and the second surface region of the first growth layer 30 (a shift caused by the crack 31). The directions are different from each other. The direction Y of the crystal axis in the illustrated region A and the direction Z of the crystal axis in the region B indicate the same crystal axis direction. This feature is a feature that appears in the semipolar seed substrate 1 manufactured in the preparation step. As described above, in the present embodiment, a shift in plane orientation can be suppressed by the presence of the annular polycrystalline group III nitride semiconductor that holds the first growth layer 30 from the outer periphery. As a result, the angle between the direction Y of the crystal axis of the region A and the direction Z of the crystal axis of the region B can be suppressed to 2 ° or less.

  In addition, when the growth step described in the first embodiment is applied to the second growth step S14, it is possible to suppress a disadvantage that the second growth layer 40 is cracked.

"Group III nitride semiconductor layer forming step S20"
Returning to FIG. 5, in the group III nitride semiconductor layer forming step S20, as shown in FIG. 6 (2), the group III nitride semiconductor is epitaxially grown on the semipolar seed substrate 1, and the group III nitride semiconductor layer is formed. Form 2 In the group III nitride semiconductor layer forming step S20, the growth step described in the first embodiment is applied. The semipolar seed substrate 1 prepared in the preparing step S10 becomes the base substrate 100 described in the first embodiment. As a result, the inconvenience of cracking in the group III nitride semiconductor layer 2 can be suppressed.

"Cutting step S30"
Returning to FIG. 5, in the cutting step S30, a semipolar self-standing substrate having a semipolar plane as a main surface is cut out from the group III nitride semiconductor layer 2.

  For example, in the cutting step S30, as shown in FIG. 6 (3), a stacked body composed of the semipolar seed substrate 1 and the group III nitride semiconductor layer 2 is sliced, and the group III nitride semiconductor By separating a part of the layer 2 (separating part 2-2 of the group III nitride semiconductor layer), a semipolar free-standing substrate having a semipolar surface as a main surface can be obtained. Note that a plurality of semipolar free-standing substrates may be obtained by slicing the separation part 2-2 of the group III nitride semiconductor layer. The slice position for obtaining the separation part 2-2 of the group III nitride semiconductor layer is, for example, the group III nitride semiconductor layer along the stacking direction from the interface between the semipolar seed substrate 1 and the group III nitride semiconductor layer 2. The position can be moved to 100 μm or more and 500 μm or less toward 2.

  The plane orientation of the main surface of the semipolar freestanding substrate may be the same as the plane orientation of the main surface of the semipolar seed substrate 1. In addition, the plane orientation of the main surface of the semipolar free-standing substrate may be different from the plane orientation of the main surface of the semipolar seed substrate 1. Both can be realized by adjusting the inclination of the slice plane in the slice. For example, when the main surface of the semipolar seed substrate 1 is a surface having an off angle within 10 ° from a {hk- (h + k) l} plane (eg, {1-1-12-3} plane), the semipolar self-supporting substrate is used. The principal surface of the substrate may be a {hk- (h + k) l} plane.

  Next, the operation and effect of the method for manufacturing a semipolar free-standing substrate of the present embodiment will be described. According to the method for manufacturing a semipolar free-standing substrate of the present embodiment, the same operation and effect as those of the first embodiment are realized. That is, it is possible to suppress the disadvantage that the group III nitride semiconductor layer is cracked. In addition, the inconvenience of forming a deep hole in the group III nitride semiconductor layer can be suppressed. Further, according to the method for manufacturing a semi-polar free-standing substrate of the present embodiment, a semi-polar free-standing substrate whose main surface is a semi-polar surface can be manufactured, so that the internal quantum efficiency of a device formed on the free-standing substrate can be improved. Is realized.

<About deep holes and cracks>
A group III nitride semiconductor layer formed by epitaxially growing a group III nitride semiconductor crystal while maintaining a state in which a plurality of {-h0hl-1} planes exist on the growth surface has a flat growth surface. This indicates that cracks are less likely to occur than a group III nitride semiconductor layer generated by epitaxially growing a group III nitride semiconductor crystal in a proper state. It also indicates that a deep hole is unlikely to occur.

"Example 1"
FIG. 12 shows a base substrate according to the first embodiment. The undersubstrate of Example 1 is made of GaN, and has some cracks (cracks extending in the vertical direction in the figure located near the outer periphery of the substrate), but no through holes. The main surface was a surface inclined at about 3 ° in the + c-axis projection direction and about 8 ° in the m-axis projection direction, with a diameter of Φ60 mm and a thickness of 800 μm.

  GaN was epitaxially grown on the base substrate under the following growth conditions to form a GaN layer having a thickness of about 5 mm.

Growth method: HVPE method Growth temperature: 1040 ° C
V / III ratio: 10
GaCl partial pressure: 1.9 kPa
NH ₃ partial pressure: 19 kPa
Impurity: undoped Growth time: 20h

"Comparative Example 1"
FIG. 13 shows a base substrate of Comparative Example 1. The undersubstrate of Comparative Example 1 was made of GaN, had no cracks, and had recessed holes on the surface. The main surface was a c-plane, the diameter was Φ50 mm, and the thickness was 400 μm.

  GaN was epitaxially grown on the base substrate to form a GaN layer having a thickness of about 5 mm. The growth conditions were the same as in Example 1 except that the growth time was 25 hours.

"Comparison between Example 1 and Comparative Example 1"
FIG. 14 shows a photograph of the surface of the GaN layer of Example 1. No crack was present on the surface of the GaN layer. Further, cracks existing on the surface of the semipolar seed substrate 1 disappeared on the surface of the GaN layer. As a result of the surface shape measurement, the depth of the surface irregularities of the GaN layer was 600 μm or less. When the GaN layer having a thickness of 5 mm was sliced, no dent holes or through holes were present in the sliced substrate other than the surface layer.

  FIG. 15 is a diagram of the surface of the GaN layer of Example 1 observed with a stereoscopic microscope. As shown in the figure, the characteristic facet plane {−h0h−l} plane (h is a natural number, l is 0 or a natural number and 0 ≦ l / h ≦ 4).

  FIG. 16 shows the surface of the GaN layer of Comparative Example 1. It can be confirmed that cracks not existing on the underlying substrate exist in the GaN layer. The surface of the GaN layer of Comparative Example 1 was flat except for the deep hole, and there was no unevenness constituted by the characteristic facet surface described in the first embodiment. In addition, a deep hole having a depth of about 4 mm was present, and when a GaN layer having a thickness of 5 mm was sliced, a plurality of through-holes having a width of mm were formed in a plurality of sliced substrates.

<Maintaining irregularities composed of facet surfaces>
Unless the growth conditions of the group III nitride semiconductor crystal are optimized, it is impossible to realize the crystal growth while maintaining the irregularities constituted by the plurality of {-h0hl-1} planes.

"Example 2"
GaN was epitaxially grown on the base substrate to form a GaN layer having a thickness of about 200 μm. The growth conditions were the same as in Example 1 except that the growth time was 45 minutes.

"Comparative Example 2"
GaN was epitaxially grown on the base substrate to form a GaN layer having a thickness of about 250 μm. The growth conditions were the same as in Example 2 except that the growth temperature was 960 ° C.

"Example 3"
In the manufacturing method shown in the flowchart of FIG. 7, the first growth layer 30 (GaN) and the second growth layer 40 (GaN) are epitaxially grown on the underlying substrate to form a GaN layer (first (Including the growth layer 30 and the second growth layer). The growth conditions of the first growth layer 30 and the second growth layer 40 are the same as the growth conditions of the GaN layer of the first embodiment, except that each growth time is set to 8 hours. Then, a GaN layer having a thickness of about 0.8 mm was formed on the second growth layer 40. The conditions for growing the GaN layer are the same as those in Example 1 except that the growth time was set to 4 hours.
"Comparative Example 3"
A GaN layer having a thickness of about 0.8 mm was formed on the same second growth layer 40 as in the third embodiment. The growth conditions were the same as in Example 1 except that the GaCl partial pressure was 3.5 kPa, the NH ₃ partial pressure was 52 kPa, and the growth time was 1 h.

"Comparison between Examples 1 to 3 and Comparative Examples 1 to 3"
FIG. 17 shows an image obtained by observing the surface of the GaN layer of Example 2 with a scanning electron microscope (SEM). FIG. 18 shows an image obtained by observing the surface of the GaN layer of Comparative Example 2 with a scanning electron microscope (SEM). From the figure, it can be seen that in Example 2, there was unevenness formed on the surface of the GaN layer on the surface of the GaN layer, but in Comparative Example 2, there was no unevenness on the surface of the GaN layer.

  Next, FIG. 19 shows the results of measuring the surface roughness of the surface of the GaN layer of Example 3 with a surface roughness meter along the m-axis projection direction. FIG. 20 shows the result of measuring the surface roughness of the surface of the GaN layer of Comparative Example 3 along the m-axis projection direction with a surface roughness meter. As can be seen from the drawing, in Example 3, the surface of the GaN layer has irregularities formed of facet surfaces inclined at a regular angle from the main surface, whereas in Comparative Example 3, the surface of the GaN layer has facets inclined at a regular angle. It can be seen that there are almost no surface irregularities.

  As described above, Comparative Example 1 in which the crystal growth was performed with the c-plane as the growth plane, and Comparative Examples 2 and 3 in which the crystal growth was performed with the semipolar plane as the growth plane but the growth conditions were not optimized, were constituted by characteristic facet planes. It was not possible to realize the crystal growth while maintaining the irregularities. However, in Example 1, in which the crystal growth was performed with the semipolar plane as the growth plane and the growth conditions were optimized, the crystal growth in which the unevenness constituted by the characteristic facet plane was maintained was realized.

Hereinafter, examples of the reference embodiment will be additionally described.
1. Maintaining a state in which the growth surface has irregularities composed of a plurality of {-h0hl} surfaces (h is a natural number, l is 0 or a natural number and satisfies the relationship of 0 ≦ l / h ≦ 4), A growth in which a group III nitride semiconductor layer is formed by epitaxially growing a group III nitride semiconductor crystal on the main surface of the base substrate having a main surface having a surface inclined at an angle of 10 ° or less within 10 °. A method for manufacturing a group III nitride semiconductor substrate having a step.
2. 1. The method for producing a group III nitride semiconductor substrate according to item 1,
The {-h0h-1} plane is {-1010}, {-101-1}, {-101-2}, {-101-3}, {-202-3}, {-202-5}, {} -202-7}, {-303-4}, {-303-5}, {-303-7}, {-303-8}, {-303-10}, {-303-11}, and { -101-4}. A method of manufacturing a group III nitride semiconductor substrate according to any one of -101-4}.
3. 1. The method for producing a group III nitride semiconductor substrate according to item 1,
The method for manufacturing a group III nitride semiconductor substrate, wherein the {-h0hl} plane is {-101-2} or {-202-3}.
4. The method for producing a group III nitride semiconductor substrate according to any one of 1 to 3,
A first {-h0hl-1} plane and a second {-h0hl-1} different from each other along a -c axis projection direction in which the -c axis direction of the group III nitride semiconductor crystal is projected onto the growth plane. A method for manufacturing a group III nitride semiconductor substrate, wherein the irregularities are formed alternately with surfaces.
5. 4. The method for producing a group III nitride semiconductor substrate according to item 4,
As the film thickness of the group III nitride semiconductor layer increases in the growth step, the area of the first {-h0hl-1} plane decreases, and the area of the second {-h0hl-1} plane increases. A method for manufacturing a group III nitride semiconductor substrate.
6. The method for producing a group III nitride semiconductor substrate according to 4 or 5, wherein
As the film thickness of the group III nitride semiconductor layer increases in the growth step, the length of the first {-h0hl-1} plane in the -c axis projection direction decreases, and the second {-h0h- A method for manufacturing a group III nitride semiconductor substrate in which the length of an l｝ plane in a −c-axis projection direction is increased.
7. 7. The method for producing a group III nitride semiconductor substrate according to any one of 4 to 6,
A method for manufacturing a group III nitride semiconductor substrate, wherein an angle between the first {-h0hl-1} plane and the second {-h0hl-1} plane is 100 ° or more and less than 180 °.
8. The method for producing a group III nitride semiconductor substrate according to any one of 1 to 7,
A third {-h0hl-1} plane and a fourth {-h0hl-1} plane, which are equivalent to each other, along an m-axis projection direction in which the m-axis direction of the group III nitride semiconductor crystal is projected on the growth plane. Are alternately arranged to form the irregularities.
9. 8. The method for producing a group III nitride semiconductor substrate according to item 8,
A method for manufacturing a group III nitride semiconductor substrate, wherein an angle formed by the third {-h0hl-1} plane and the fourth {-h0hl-1} plane is 100 ° or more and less than 160 °.
10. The method for producing a group III nitride semiconductor substrate according to any one of 1 to 9,
In the growing step, the V / III ratio is 0.5 or more and 25 or less, the pressure is 70 kPa or more and 150 kPa or less, and the growth temperature is 970 ° C. or more. A method for producing a group III nitride semiconductor group, wherein a group III nitride semiconductor is epitaxially grown while maintaining a state of being present on the growth surface.
11. A base substrate having, as a main surface, a surface in which the {-1-12-3} plane is inclined within 10 °;
The main surface has irregularities located on the base substrate and composed of a plurality of {-h0h-l} planes (h is a natural number, l is 0 or a natural number and satisfies the relationship of 0 ≦ 1 / h ≦ 4). A group III nitride semiconductor layer,
A group III nitride semiconductor substrate having:
12. 11. The group III nitride semiconductor substrate according to 11,
The {-h0h-1} plane is {-1010}, {-101-1}, {-101-2}, {-101-3}, {-202-3}, {-202-5}, {} -202-7}, {-303-4}, {-303-5}, {-303-7}, {-303-8}, {-303-10}, {-303-11}, and { A group III nitride semiconductor substrate according to any one of -101-4}.
13. 11. The group III nitride semiconductor substrate according to 11,
A group III nitride semiconductor substrate in which the {-h0hl} plane is {-101-2} or {-202-3}.
14． The group III nitride semiconductor substrate according to any one of 11 to 13, wherein
The first {-h0h-l} plane and the second {-h0h-l} plane, which are different from each other, along the -c-axis projection direction obtained by projecting the -c-axis direction of the group III nitride semiconductor crystal onto the growth plane. A group III nitride semiconductor substrate in which the irregularities are alternately arranged.
15. 14. The group III nitride semiconductor substrate according to 14,
A group III nitride semiconductor substrate, wherein an angle between the first {-h0hl-1} plane and the second {-h0hl-1} plane is 100 ° or more and less than 180 °.
16. The group III nitride semiconductor substrate according to any one of 11 to 15, wherein
Along the m-axis projection direction in which the m-axis direction of the group III nitride semiconductor crystal is projected on the growth surface, a third {-h0hl-1} plane and a fourth {-h0hl-1} plane equivalent to each other are formed. A group III nitride semiconductor substrate in which the irregularities are alternately arranged.
17． 16. The group III nitride semiconductor substrate according to 16,
A group III nitride semiconductor substrate, wherein an angle between the third {-h0hl-1} plane and the fourth {-h0hl-1} plane is 100 ° or more and less than 160 °.

Reference Signs List 1 semipolar seed substrate 2 group III nitride semiconductor layer 2-1 remaining part of group III nitride semiconductor layer 2-2 separation part of group III nitride semiconductor layer 10 base substrate 11 sapphire substrate 12 group III nitride semiconductor layer 20 Susceptor 30 First growth layer 31 Crack 40 Second growth layer 51 First part 52 Second part 100 Base substrate 101 Group III nitride semiconductor layer 102 Growth surface

Claims (17)

  Maintaining a state in which the growth surface has irregularities composed of a plurality of {-h0hl} surfaces (h is a natural number, l is 0 or a natural number and satisfies the relationship of 0 ≦ l / h ≦ 4), A growth in which a group III nitride semiconductor layer is formed by epitaxially growing a group III nitride semiconductor crystal on the main surface of the base substrate having a main surface having a surface inclined at an angle of 10 ° or less within 10 °. A method for manufacturing a group III nitride semiconductor substrate having a step. The method for manufacturing a group III nitride semiconductor substrate according to claim 1,
The {-h0h-1} plane is {-1010}, {-101-1}, {-101-2}, {-101-3}, {-202-3}, {-202-5}, {} -202-7}, {-303-4}, {-303-5}, {-303-7}, {-303-8}, {-303-10}, {-303-11}, and { -101-4}. A method of manufacturing a group III nitride semiconductor substrate according to any one of -101-4}. The method for manufacturing a group III nitride semiconductor substrate according to claim 1,
The method for manufacturing a group III nitride semiconductor substrate, wherein the {-h0hl} plane is {-101-2} or {-202-3}. The method for producing a group III nitride semiconductor substrate according to claim 1,
A first {-h0hl-1} plane and a second {-h0hl-1} different from each other along a -c axis projection direction in which the -c axis direction of the group III nitride semiconductor crystal is projected onto the growth plane. A method for manufacturing a group III nitride semiconductor substrate, wherein the irregularities are formed alternately with surfaces. The method for manufacturing a group III nitride semiconductor substrate according to claim 4,
As the film thickness of the group III nitride semiconductor layer increases in the growth step, the area of the first {-h0hl-1} plane decreases, and the area of the second {-h0hl-1} plane increases. A method for manufacturing a group III nitride semiconductor substrate. The method for manufacturing a group III nitride semiconductor substrate according to claim 4 or 5,
As the film thickness of the group III nitride semiconductor layer increases in the growth step, the length of the first {-h0hl-1} plane in the -c axis projection direction decreases, and the second {-h0h- A method for manufacturing a group III nitride semiconductor substrate in which the length of an l｝ plane in a −c-axis projection direction is increased. The method for manufacturing a group III nitride semiconductor substrate according to any one of claims 4 to 6,
A method for manufacturing a group III nitride semiconductor substrate, wherein an angle between the first {-h0hl-1} plane and the second {-h0hl-1} plane is 100 ° or more and less than 180 °. The method for manufacturing a group III nitride semiconductor substrate according to any one of claims 1 to 7,
A third {-h0hl-1} plane and a fourth {-h0hl-1} plane, which are equivalent to each other, along an m-axis projection direction in which the m-axis direction of the group III nitride semiconductor crystal is projected on the growth plane. Are alternately arranged to form the irregularities. The method for manufacturing a group III nitride semiconductor substrate according to claim 8,
A method for manufacturing a group III nitride semiconductor substrate, wherein an angle formed by the third {-h0hl-1} plane and the fourth {-h0hl-1} plane is 100 ° or more and less than 160 °. The method for manufacturing a group III nitride semiconductor substrate according to any one of claims 1 to 9,
In the growing step, the V / III ratio is 0.5 or more and 25 or less, the pressure is 70 kPa or more and 150 kPa or less, and the growth temperature is 970 ° C. or more. A method for producing a group III nitride semiconductor group, wherein a group III nitride semiconductor is epitaxially grown while maintaining a state of being present on the growth surface. A base substrate having, as a main surface, a surface in which the {-1-12-3} plane is inclined within 10 °;
The main surface has irregularities located on the base substrate and composed of a plurality of {-h0h-l} planes (h is a natural number, l is 0 or a natural number and satisfies the relationship of 0 ≦ 1 / h ≦ 4). A group III nitride semiconductor layer,
A group III nitride semiconductor substrate having: The group III nitride semiconductor substrate according to claim 11,
The {-h0h-1} plane is {-1010}, {-101-1}, {-101-2}, {-101-3}, {-202-3}, {-202-5}, {} -202-7}, {-303-4}, {-303-5}, {-303-7}, {-303-8}, {-303-10}, {-303-11}, and { A group III nitride semiconductor substrate according to any one of -101-4}. The group III nitride semiconductor substrate according to claim 11,
A group III nitride semiconductor substrate in which the {-h0hl} plane is {-101-2} or {-202-3}. The group III nitride semiconductor substrate according to any one of claims 11 to 13,
The first {-h0h-l} plane and the second {-h0h-l} plane, which are different from each other, along the -c-axis projection direction obtained by projecting the -c-axis direction of the group III nitride semiconductor crystal onto the growth plane. A group III nitride semiconductor substrate in which the irregularities are alternately arranged. The group III nitride semiconductor substrate according to claim 14,
A group III nitride semiconductor substrate, wherein an angle between the first {-h0hl-1} plane and the second {-h0hl-1} plane is 100 ° or more and less than 180 °. The group III nitride semiconductor substrate according to any one of claims 11 to 15,
Along the m-axis projection direction in which the m-axis direction of the group III nitride semiconductor crystal is projected on the growth surface, a third {-h0hl-1} plane and a fourth {-h0hl-1} plane equivalent to each other are formed. A group III nitride semiconductor substrate in which the irregularities are alternately arranged. The group III nitride semiconductor substrate according to claim 16,
A group III nitride semiconductor substrate, wherein an angle between the third {-h0hl-1} plane and the fourth {-h0hl-1} plane is 100 ° or more and less than 160 °.