JP2020046876A5 - - Google Patents

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Publication number
JP2020046876A5
JP2020046876A5 JP2018174191A JP2018174191A JP2020046876A5 JP 2020046876 A5 JP2020046876 A5 JP 2020046876A5 JP 2018174191 A JP2018174191 A JP 2018174191A JP 2018174191 A JP2018174191 A JP 2018174191A JP 2020046876 A5 JP2020046876 A5 JP 2020046876A5
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JP
Japan
Prior art keywords
control circuit
selection signal
memory included
switching selection
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018174191A
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English (en)
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JP2020046876A (ja
JP7401050B2 (ja
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Publication date
Application filed filed Critical
Priority claimed from JP2018174191A external-priority patent/JP7401050B2/ja
Priority to JP2018174191A priority Critical patent/JP7401050B2/ja
Priority to EP19193097.3A priority patent/EP3627331B1/en
Priority to US16/561,328 priority patent/US10872051B2/en
Priority to KR1020190111857A priority patent/KR102549085B1/ko
Priority to CN201910880361.2A priority patent/CN110908936B/zh
Publication of JP2020046876A publication Critical patent/JP2020046876A/ja
Publication of JP2020046876A5 publication Critical patent/JP2020046876A5/ja
Publication of JP7401050B2 publication Critical patent/JP7401050B2/ja
Application granted granted Critical
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Claims (1)

  1. 前記制御回路が有する前記メモリは、前記切替選択信号をＦＩＦＯ形式で保持することを特徴とする請求項２に記載のバス制御回路。
JP2018174191A 2018-09-18 2018-09-18 バス制御回路 Active JP7401050B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2018174191A JP7401050B2 (ja) 2018-09-18 2018-09-18 バス制御回路
EP19193097.3A EP3627331B1 (en) 2018-09-18 2019-08-22 Bus control circuit
US16/561,328 US10872051B2 (en) 2018-09-18 2019-09-05 Bus control circuit
KR1020190111857A KR102549085B1 (ko) 2018-09-18 2019-09-10 버스 제어회로
CN201910880361.2A CN110908936B (zh) 2018-09-18 2019-09-18 总线控制电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018174191A JP7401050B2 (ja) 2018-09-18 2018-09-18 バス制御回路

Publications (3)

Publication Number Publication Date
JP2020046876A JP2020046876A (ja) 2020-03-26
JP2020046876A5 true JP2020046876A5 (ja) 2021-10-21
JP7401050B2 JP7401050B2 (ja) 2023-12-19

Family

ID=67734547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018174191A Active JP7401050B2 (ja) 2018-09-18 2018-09-18 バス制御回路

Country Status (5)

Country Link
US (1) US10872051B2 (ja)
EP (1) EP3627331B1 (ja)
JP (1) JP7401050B2 (ja)
KR (1) KR102549085B1 (ja)
CN (1) CN110908936B (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111752875A (zh) * 2020-06-22 2020-10-09 深圳鲲云信息科技有限公司 一种模块间通信方法及系统
CN113158260B (zh) * 2021-03-30 2023-03-31 西南电子技术研究所（中国电子科技集团公司第十研究所） SoC芯片内部数据分级防护电路

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5887134A (en) * 1997-06-30 1999-03-23 Sun Microsystems System and method for preserving message order while employing both programmed I/O and DMA operations
US6243829B1 (en) * 1998-05-27 2001-06-05 Hewlett-Packard Company Memory controller supporting redundant synchronous memories
US6323755B1 (en) * 1998-08-19 2001-11-27 International Business Machines Corporation Dynamic bus locking in a cross bar switch
US6842104B1 (en) * 1999-03-19 2005-01-11 Matsushita Electric Industrial Co., Ltd. System lsi and a cross-bus switch apparatus achieved in a plurality of circuits in which two or more pairs of a source apparatus and a destination apparatus are connected simultaneously and buses are wired without concentration
US7376811B2 (en) * 2001-11-06 2008-05-20 Netxen, Inc. Method and apparatus for performing computations and operations on data using data steering
JP2005062946A (ja) 2003-08-12 2005-03-10 Fuji Xerox Co Ltd メモリ制御装置
KR100618817B1 (ko) * 2003-12-17 2006-08-31 삼성전자주식회사 소비 전력을 절감시키는 ａｍｂａ 버스 구조 시스템 및 그방법
US7395361B2 (en) * 2005-08-19 2008-07-01 Qualcomm Incorporated Apparatus and methods for weighted bus arbitration among a plurality of master devices based on transfer direction and/or consumed bandwidth
US7302510B2 (en) * 2005-09-29 2007-11-27 International Business Machines Corporation Fair hierarchical arbiter
US20080059674A1 (en) * 2006-09-01 2008-03-06 Jiaxiang Shi Apparatus and method for chained arbitration of a plurality of inputs
US20080082707A1 (en) * 2006-09-29 2008-04-03 Synfora, Inc. Non-blocking bus controller for a pipelined, variable latency, hierarchical bus with point-to-point first-in first-out ordering
JP2008117068A (ja) 2006-11-01 2008-05-22 Denso Corp 情報処理システム
US7734856B2 (en) * 2007-08-22 2010-06-08 Lantiq Deutschland Gmbh Method for operating a plurality of arbiters and arbiter system
JP5035469B2 (ja) * 2009-03-31 2012-09-26 富士通株式会社 データ転送回路及びデータ転送方法
JP2010282405A (ja) 2009-06-04 2010-12-16 Renesas Electronics Corp データ処理システム
US8972821B2 (en) * 2010-12-23 2015-03-03 Texas Instruments Incorporated Encode and multiplex, register, and decode and error correction circuitry
JP5776306B2 (ja) * 2011-04-25 2015-09-09 富士ゼロックス株式会社 画像データ処理装置及びプログラム
US9117022B1 (en) * 2011-10-07 2015-08-25 Altera Corporation Hierarchical arbitration
US8874680B1 (en) * 2011-11-03 2014-10-28 Netapp, Inc. Interconnect delivery process
US9176911B2 (en) * 2012-12-11 2015-11-03 Intel Corporation Explicit flow control for implicit memory registration
CN106301337B (zh) * 2015-05-13 2019-12-06 恩智浦有限公司 双向通信的方法和系统
GB2557225A (en) * 2016-11-30 2018-06-20 Nordic Semiconductor Asa Interconnect system

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