JP2020043324A - Electronic component - Google Patents

Abstract

To provide an electronic component capable of appropriately incorporating a resistance layer into a multilayer wiring structure.SOLUTION: An electronic component 1 includes: a third insulating layer 15; a fourth insulating layer 16 formed on the third insulating layer 15; a first via electrode 23 embedded in the third insulating layer 15; a second via electrode 24 embedded in the third insulating layer 15 at a distance from the first via electrode 23; and a resistance layer 10, composed of a metal thin film, interposed in a region between the third insulating layer 15 and the fourth insulating layer 16, electrically connected to the first via electrode 23 and the second via electrode 24.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an electronic component.

Patent Document 1 discloses a semiconductor substrate, an insulating film formed on the semiconductor substrate, a polysilicon resistance layer formed on the insulating film, an insulating film formed on the polysilicon resistance layer, And a wiring connected to the polysilicon resistance layer on the silicon resistance layer.
Patent Document 2 discloses a silicon substrate, a LOCOS oxide film formed on the silicon substrate, a polysilicon resistor formed on the LOCOS oxide film, and a wiring connected to the polysilicon resistor on the polysilicon resistor. And a semiconductor device including:

  Patent Document 3 discloses a silicon substrate, an insulating layer formed on the silicon substrate, a polysilicon resistor formed on the insulating layer, and a polysilicon resistor connected on the polysilicon resistor. And a semiconductor device including wiring.

JP 2009-038099 A JP 2013-172000 A JP-A-2015-012259

The resistance layer including polysilicon is formed with a relatively large thickness and a relatively large plane area. Since the resistance layer including polysilicon is arranged in a region close to the main surface of the substrate, a contact to the resistance layer is formed on the resistance layer.
On the other hand, in a multilayer wiring structure formed on a main surface of a substrate, a plurality of wiring layers are required to be closely routed and to be flat. Therefore, it is not preferable to incorporate a resistance layer containing polysilicon into the multilayer wiring structure from the viewpoint of the formation region of the resistance layer and the flatness of the multilayer wiring structure.

  One embodiment of the present invention provides an electronic component that can appropriately incorporate a resistance layer into a multilayer wiring structure.

  One embodiment of the present invention includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, and the first via electrode. A second via electrode buried in the lower insulating layer separated from the first insulating film, and a metal thin film interposed in a region between the lower insulating layer and the upper insulating layer; And a resistive layer electrically connected to the two via electrodes.

  According to this electronic component, the resistance layer is made of a metal thin film. According to the metal thin film, the planar area of the resistance layer can be reduced while reducing the thickness of the resistance layer. Accordingly, the resistance layer can be appropriately interposed in a region between the lower insulating layer and the upper insulating layer while ensuring flatness. Further, since the contact to the resistance layer can be formed by the via electrode embedded in the lower insulating layer, the flatness of the upper layer of the resistance layer can be appropriately improved. As a result, it is possible to provide an electronic component that can appropriately incorporate the resistance layer into the multilayer wiring structure.

  One embodiment of the present invention includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, and the first via electrode. A second via electrode buried in the lower insulating layer apart from the first insulating layer; a first upper wiring layer formed on the upper insulating layer; and the upper insulating layer separated from the first upper wiring layer. A second upper wiring layer formed thereon and a metal thin film, the lower insulating layer and the lower insulating layer being located in a region between the first upper wiring layer and the second upper wiring layer in plan view. An electronic component, comprising: a resistive layer interposed in a region between upper insulating layers and electrically connected to the first via electrode and the second via electrode.

  According to this electronic component, the resistance layer is made of a metal thin film. According to the metal thin film, the planar area of the resistance layer can be reduced while reducing the thickness of the resistance layer. Accordingly, the resistance layer can be appropriately interposed in a region between the lower insulating layer and the upper insulating layer while ensuring flatness. Further, since the contact to the resistance layer can be formed by the via electrode embedded in the lower insulating layer, the flatness of the upper layer of the resistance layer can be appropriately improved. That is, the flatness of the upper insulating layer can be appropriately increased.

  Thereby, the first upper wiring layer and the second upper wiring layer can be appropriately formed on the upper insulating layer having improved flatness. As a result, it is possible to provide an electronic component that can appropriately incorporate the resistance layer into the multilayer wiring structure.

FIG. 1 is a schematic plan view illustrating an electronic component according to a first embodiment of the present invention, and is a plan view illustrating a mode in which a resistance layer according to the first embodiment is incorporated. FIG. 2 is a sectional view taken along the line II-II shown in FIG. FIG. 3 is an enlarged view of a region III shown in FIG. FIG. 4 is an enlarged view of a region IV shown in FIG. FIG. 5 is a plan view for explaining the planar shape of the resistance layer. FIG. 6 is a graph for explaining the temperature characteristics of the resistance layer. FIG. 7A is a plan view showing a resistance layer according to the second embodiment. FIG. 7B is a plan view showing a resistance layer according to the third embodiment. FIG. 7C is a plan view showing a resistance layer according to the fourth embodiment. FIG. 7D is a plan view showing a resistance layer according to the fifth embodiment. FIG. 7E is a plan view showing a resistance layer according to the sixth embodiment. FIG. 8A is a cross-sectional view of a part corresponding to FIG. 2 and is a cross-sectional view for explaining an example of a method for manufacturing the electronic component shown in FIG. 1. FIG. 8B is a cross-sectional view for explaining a step subsequent to FIG. 8A. FIG. 8C is a cross-sectional view for explaining a step subsequent to FIG. 8B. FIG. 8D is a cross-sectional view for describing a step subsequent to FIG. 8C. FIG. 8E is a cross-sectional view for explaining a step subsequent to FIG. 8D. FIG. 8F is a cross-sectional view for explaining a step subsequent to FIG. 8E. FIG. 8G is a cross-sectional view for explaining a step subsequent to FIG. 8F. FIG. 8H is a cross-sectional view for explaining a step subsequent to FIG. 8G. FIG. 8I is a cross-sectional view for describing a step subsequent to FIG. 8H. FIG. 8J is a cross-sectional view for explaining a step subsequent to FIG. 8I. FIG. 8K is a cross-sectional view for explaining a step subsequent to FIG. 8J. FIG. 8L is a cross-sectional view for explaining a step subsequent to FIG. 8K. FIG. 8M is a cross-sectional view for explaining a step subsequent to FIG. 8L. FIG. 8N is a cross-sectional view for explaining a step subsequent to FIG. 8M. FIG. 8O is a cross-sectional view for describing a step subsequent to FIG. 8N. FIG. 8P is a cross-sectional view for describing a step subsequent to FIG. 8O. FIG. 8Q is a cross-sectional view for explaining a step subsequent to FIG. 8P. FIG. 8R is a cross-sectional view for explaining a step subsequent to FIG. 8Q. FIG. 8S is a cross-sectional view for explaining a step subsequent to FIG. 8R. FIG. 9 is a schematic plan view illustrating an electronic component according to the second embodiment of the present invention, and is a plan view illustrating a mode in which the resistance layer according to the first embodiment is incorporated. FIG. 10 is a schematic cross-sectional view showing an electronic component according to a third embodiment of the present invention, and is a cross-sectional view showing a mode in which the fuse resistance layer according to the first embodiment is incorporated. FIG. 11 is an enlarged view of the area XI shown in FIG. FIG. 12 is an enlarged view of a region XII shown in FIG. FIG. 13 is a plan view showing a planar shape of the fuse resistance layer. FIG. 14A is a plan view showing a fuse resistance layer according to the second embodiment. FIG. 14B is a plan view showing a fuse resistance layer according to the third embodiment. FIG. 14C is a plan view showing a fuse resistance layer according to the fourth embodiment. FIG. 15 is an example of a main circuit of the electronic component shown in FIG. FIG. 16 is a circuit diagram illustrating an electrical structure according to a first example of the electronic component according to the first to third embodiments. FIG. 17 is a circuit diagram showing an electrical structure according to a second embodiment of the electronic component according to the first to third embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view showing an electronic component 1 according to a first embodiment of the present invention, and is a plan view showing a mode in which a resistance layer 10 according to a first embodiment is incorporated.
The electronic component 1 is a semiconductor device including a conductive material or a semiconductor material, or various functional devices formed using the properties of the semiconductor material. The electronic component 1 includes a chip-shaped semiconductor layer 2 formed in a rectangular parallelepiped shape. The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4.

The first main surface 3 is a device formation surface. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view (hereinafter, simply referred to as “plan view”) viewed from the normal direction.
The semiconductor layer 2 may be a Si semiconductor layer containing Si (silicon) as an example of a semiconductor material. The Si semiconductor layer may have a laminated structure including the Si semiconductor substrate and the Si epitaxial layer. The Si semiconductor layer may have a single-layer structure made of a Si semiconductor substrate.

The semiconductor layer 2 may be a SiC semiconductor layer containing SiC (silicon carbide) as an example of a semiconductor material. The SiC semiconductor layer may have a laminated structure including the SiC semiconductor substrate and the SiC epitaxial layer. The SiC semiconductor layer may have a single-layer structure made of a SiC semiconductor substrate.
The semiconductor layer 2 may be a compound semiconductor layer including a compound semiconductor material as an example of a semiconductor material. The compound semiconductor layer may have a laminated structure including a compound semiconductor substrate and a compound semiconductor epitaxial layer. The compound semiconductor layer may have a single-layer structure composed of a compound semiconductor substrate.

The compound semiconductor material may be a III-V compound semiconductor material. The semiconductor layer 2 includes at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide) as an example of a III-V compound semiconductor material. Is also good.
Semiconductor layer 2 includes device region 6 and outer region 7. The device area 6 is an area where a functional device is formed. The device region 6 is formed at an interval from the side surfaces 5A to 5D of the semiconductor layer 2 to an inner region. In this embodiment, the device region 6 is formed in an L shape in plan view. The planar shape of the device region 6 is arbitrary and is not limited to the planar shape shown in FIG.

  The functional device is formed on the semiconductor layer 2. More specifically, the functional device is formed using the first main surface 3 of the semiconductor layer 2 and / or the surface layer portion of the first main surface 3. The functional device may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. Passive devices may include semiconductor passive devices.

The passive device (semiconductor passive device) may include at least one of a resistor, a capacitor, and a coil. The semiconductor rectifying device may include at least one of a pn junction diode, a zener diode, a Schottky barrier diode, and a fast recovery diode.
The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). Good.

The functional device may include a network in which at least two of a passive device (semiconductor passive device), a semiconductor rectifying device, and a semiconductor switching device are selectively combined. The network may form part or all of an integrated circuit.
The integrated circuit may include SSI (Small Scale Integration), LSI (Large Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), and ULSI (Ultra-Very Large Scale Integration).

The outer region 7 is a region outside the device region 6. The outer region 7 does not contain any functional devices. In this embodiment, the outer region 7 is partitioned into regions between the side surfaces 5A to 5D of the semiconductor layer 2 and the device region 6. The outer region 7 is formed in a quadrangular shape in plan view in this embodiment.
The planar shape of the outer region 7 is arbitrary and is not limited to the planar shape shown in FIG. The arrangement and planar shape of the outer region 7 are arbitrary, and are not limited to the arrangement and planar shape shown in FIG. The outer region 7 may be formed at the center of the first main surface 3 in plan view.

In the outer region 7, a resistance circuit 11 including a resistance layer 10 made of a metal thin film is formed at a distance from the first main surface 3 of the semiconductor layer 2. That is, in this embodiment, the resistance circuit 11 (the resistance layer 10) is formed so as to avoid the device region 6 in plan view. The resistance circuit 11 (resistance layer 10) is electrically connected to the function device.
By arranging the resistance circuit 11 (the resistance layer 10) in the outer region 7, the electric influence of the resistance circuit 11 on the device region 6 is suppressed, and the electric influence of the device region 6 on the resistance circuit 11 is suppressed. it can. As an example, the parasitic capacitance between the device region 6 and the resistance circuit 11 can be suppressed. That is, the noise can be reduced and the Q value can be improved.

In this embodiment, an example in which the resistance circuit 11 includes one resistance layer 10 will be described. However, the resistance circuit 11 may include a plurality of (two or more) resistance layers 10. Hereinafter, the resistance layer 10 (resistance circuit 11) will be specifically described with reference to FIGS. 2 to 5 in addition to FIG.
FIG. 2 is a sectional view taken along the line II-II shown in FIG. FIG. 3 is an enlarged view of a region III shown in FIG. FIG. 4 is an enlarged view of a region IV shown in FIG. FIG. 5 is a plan view for explaining the planar shape of the resistance layer 10.

Referring to FIGS. 2 to 4, in device region 6 and outer region 7, a multilayer wiring structure 12 is formed on first main surface 3 of semiconductor layer 2. The multilayer wiring structure 12 has a stacked structure in which a plurality of insulating layers are stacked, and includes a plurality of wiring layers selectively formed in the plurality of insulating layers.
In this embodiment, the multilayer wiring structure 12 includes a first insulating layer 13, a second insulating layer 14, a third insulating layer 15 (lower insulating layer), and a second insulating layer 13 stacked in this order from the first main surface 3 of the semiconductor layer 2. The fourth insulating layer 16 (upper insulating layer) is included. The terms “first”, “second”, “third” and “fourth” relating to the first to fourth insulating layers 13 to 16 are used to identify the insulating layers in the drawings. , Not intended to be permuted.

The number of stacked insulating layers in the multilayer wiring structure 12 is arbitrary, and is not limited to the number of stacked layers shown in FIG. Therefore, the multilayer wiring structure 12 may include less than four insulating layers, or may include five or more insulating layers.
The first to fourth insulating layers 13 to 16 each have a main surface. The main surfaces of the first to fourth insulating layers 13 to 16 are each formed flat. The main surfaces of the first to fourth insulating layers 13 to 16 extend in parallel with the first main surface 3 of the semiconductor layer 2, respectively. The main surfaces of the first to fourth insulating layers 13 to 16 may be ground surfaces, respectively. That is, the main surfaces of the first to fourth insulating layers 13 to 16 may each have grinding marks.

Each of the first to fourth insulating layers 13 to 16 may have a stacked structure including a silicon oxide film and a silicon nitride film. In this case, a silicon nitride film may be formed over the silicon oxide film, or a silicon oxide film may be formed over the silicon nitride film.
Each of the first to fourth insulating layers 13 to 16 may have a single-layer structure made of a silicon oxide film or a silicon nitride film. The first to fourth insulating layers 13 to 16 are preferably formed of the same kind of insulating material. In this embodiment, the first to fourth insulating layers 13 to 16 each have a single-layer structure made of a silicon oxide film.

  The thickness TI of each of the first to fourth insulating layers 13 to 16 may be 100 nm or more and 3500 nm or less. The thickness TI may be 100 nm or more and 500 nm or less, 500 nm or more and 1000 nm or less, 1000 nm or more and 1500 nm or less, 1500 nm or more and 2000 nm or less, 2000 nm or more and 2500 nm or less, 2500 nm or more and 3000 nm or less, or 3000 nm or more and 3500 nm or less. Preferably, the thicknesses TI are each 100 nm or more and 1500 nm or less. The thicknesses TI of the first to fourth insulating layers 13 to 16 may be equal to each other or may be different from each other.

In this embodiment, the multilayer wiring structure 12 includes a connection circuit formation layer 21 and a resistance circuit formation layer 22 formed in different layers.
The connection circuit forming layer 21 is formed on the first main surface 3 side of the semiconductor layer 2. The connection circuit forming layer 21 includes a first insulating layer 13 and a second insulating layer 14. The connection circuit forming layer 21 is a layer for one purpose of electrical connection between the device region 6 (functional device) and the outer region 7 (resistance circuit 11). The specific structure of the connection circuit forming layer 21 will be described later.

The resistance circuit forming layer 22 is formed on the connection circuit forming layer 21. The resistance circuit forming layer 22 includes a third insulating layer 15 and a fourth insulating layer 16. The resistance circuit forming layer 22 is a layer whose purpose is to form the resistance circuit 11 (the resistance layer 10) in the outer region 7.
The resistance circuit 11 includes a first via electrode 23 and a second via electrode 24. The first via electrode 23 is embedded in the third insulating layer 15 and is exposed from the main surface of the third insulating layer 15. The second via electrode 24 is embedded in the third insulating layer 15 at a distance from the first via electrode 23 and is exposed from the main surface of the third insulating layer 15.

In this embodiment, the first via electrode 23 is formed in a circular shape in plan view. The planar shape of the first via electrode 23 is arbitrary. The first via electrode 23 may be formed in a polygonal shape such as a triangular shape, a quadrangular shape, or a hexagonal shape, or an elliptical shape in plan view, instead of the circular shape.
Referring to FIG. 3, first via electrode 23 includes a first end 23a on one side and a second end 23b on the other side with respect to the normal direction of the main surface of third insulating layer 15. The first end 23 a of the first via electrode 23 is exposed from the main surface of the third insulating layer 15. The second end 23 b of the first via electrode 23 is located in the third insulating layer 15. The first via electrode 23 is formed in a tapered shape in which the width is reduced from the first end 23a toward the second end 23b in a sectional view.

In this embodiment, the first end 23a of the first via electrode 23 includes a first protrusion 23c protruding from the main surface of the third insulating layer 15 toward the fourth insulating layer 16. The first protrusion 23c is formed by the main surface and the side surface of the first via electrode 23.
The first via electrode 23 has a laminated structure including a main body layer 25 and a barrier layer 26. The main body layer 25 is embedded in the third insulating layer 15. The main body layer 25 may include tungsten (W) or copper (Cu). In this embodiment, the main body layer 25 has a single-layer structure including the tungsten layer 27.

  The barrier layer 26 is interposed between the third insulating layer 15 and the main body layer 25. In this embodiment, the barrier layer 26 has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer 26 includes a Ti layer 28 and a TiN layer 29 formed in this order from the third insulating layer 15. The Ti layer 28 is in contact with the third insulating layer 15. The TiN layer 29 is in contact with the main body layer 25. The barrier layer 26 may have a single-layer structure including a Ti layer 28 or a TiN layer 29.

In this embodiment, the second via electrode 24 is formed in a circular shape in plan view. The planar shape of the second via electrode 24 is arbitrary. The second via electrode 24 may be formed in a polygonal shape such as a triangular shape, a quadrangular shape, a hexagonal shape, or an elliptical shape in plan view, instead of the circular shape.
Referring to FIG. 4, second via electrode 24 includes a first end 24a on one side and a second end 24b on the other side with respect to the normal direction of the main surface of third insulating layer 15. The first end 24 a of the second via electrode 24 is exposed from the main surface of the third insulating layer 15. The second end 24 b of the second via electrode 24 is located in the third insulating layer 15. The second via electrode 24 is formed in a tapered shape in which the width decreases from the first end 24a toward the second end 24b in a cross-sectional view.

In this embodiment, the first end 24a of the second via electrode 24 includes a second protrusion 24c protruding from the main surface of the third insulating layer 15 toward the fourth insulating layer 16. The second projection 24c is formed by the main surface and the side surface of the second via electrode 24.
The second via electrode 24 has a laminated structure including the main body layer 30 and the barrier layer 31. The main body layer 30 is embedded in the third insulating layer 15. The main body layer 30 may include tungsten (W) or copper (Cu). In this embodiment, main body layer 30 has a single-layer structure including tungsten layer 32.

  The barrier layer 31 is interposed between the third insulating layer 15 and the main body layer 30. In this embodiment, the barrier layer 31 has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer 31 includes a Ti layer 33 and a TiN layer 34 formed in this order from the third insulating layer 15. The Ti layer 33 is in contact with the third insulating layer 15. TiN layer 34 is in contact with main body layer 30. The barrier layer 31 may have a single-layer structure including the Ti layer 33 or the TiN layer 34.

  The resistance layer 10 is preferably made of a metal thin film containing at least one of CrSi (chromium silicon alloy), TaN (tantalum nitride) and TiN (titanium nitride). It is particularly preferable that the resistance layer 10 contains CrSi. The resistance layer 10 may have a single-layer structure made of a CrSi film, a TaN film, or a TiN film. The resistance layer 10 may have a laminated structure including a CrSi film and a TaN film laminated in an arbitrary order.

  The resistance layer 10 may have a laminated structure including a CrSi film and a TiN film laminated in any order. The resistance layer 10 may have a laminated structure including a TaN film and a TiN film laminated in an arbitrary order. The resistance layer 10 may have a laminated structure including a CrSi film, a TaN film, and a TiN film laminated in an arbitrary order. In this embodiment, the resistance layer 10 has a single-layer structure made of a CrSi film.

  The sheet resistance value of the resistance layer 10 may be 100Ω / □ or more and 50000Ω / □ or less. The sheet resistance value of the resistance layer 10 is 100Ω / □ or more and 5000Ω / □ or less, 5000Ω / □ or more and 10000Ω / □ or less, 10000Ω / □ or more and 15000Ω / □ or less, 15000Ω / □ or more and 20000Ω / □ or less and 20,000Ω / □ or more and 25000Ω. / □ or less, 25000Ω / □ or more and 30000Ω / □ or less, 30000Ω / □ or more and 35000Ω / □ or less, 35000Ω / □ or more and 40000Ω / □ or less, 40000Ω / □ or more and 45,000Ω / □ or less, or 45000Ω / □ or more and 50000Ω / □ or less. It may be.

  The content of Cr with respect to the total weight of the resistance layer 10 may be 5% by weight or more and 50% by weight or less. The content of Cr is 5 wt% to 10 wt%, 10 wt% to 15 wt%, 15 wt% to 20 wt%, 20 wt% to 25 wt%, 25 wt% to 30 wt%. , 30 wt% to 35 wt%, 35 wt% to 40 wt%, 40 wt% to 45 wt%, or 45 wt% to 50 wt%.

  The resistance layer 10 has a thickness TR (TR <TI) smaller than the thickness TI of the third insulating layer 15. The ratio TR / TI of the thickness TR of the resistance layer 10 to the thickness TI of the third insulating layer 15 may be 0.001 or more and 0.01 or less. The ratio TR / TI is 0.001 to 0.002, 0.002 to 0.004, 0.004 to 0.006, 0.006 to 0.008, or 0.008 to 0.00. 01 or less.

  The thickness TR may be 0.1 nm or more and 100 nm or less. The thickness TR is 0.1 to 10 nm, 10 to 20 nm, 20 to 30 nm, 30 to 40 nm, 40 to 50 nm, 50 to 60 nm, 60 to 70 nm, 70 to 80 nm, 80 to 90 nm. The thickness may be 90 nm or more and 100 nm or less. The thickness TR is preferably 1 nm or more and 20 nm or less.

  The resistance layer 10 is interposed between the third insulating layer 15 and the fourth insulating layer 16. More specifically, the resistance layer 10 is formed in a film shape on the main surface of the third insulating layer 15. The resistance layer 10 occupies the main surface of the third insulating layer 15. On the main surface of the third insulating layer 15, no film-shaped or layered wiring other than the resistance layer 10 is formed in the device region 6 and the outer region 7. The third insulating layer 15 is provided for forming the resistance layer 10.

By arranging the resistance layer 10 in the outer region 7, the electrical influence of the resistance layer 10 on the device region 6 can be suppressed, and the electric influence of the device region 6 on the resistance layer 10 can be suppressed. As an example, the parasitic capacitance between the device region 6 and the resistance layer 10 can be suppressed. That is, the noise can be reduced and the Q value can be improved.
Referring to FIG. 5, resistance layer 10 is formed so as to straddle first via electrode 23 and second via electrode 24. Thus, the resistance layer 10 is electrically connected to the first via electrode 23 and the second via electrode 24. In this embodiment, the resistance layer 10 is formed in a square shape (more specifically, a rectangular shape) in plan view.

  The resistance layer 10 includes a first end 10a on one side, a second end 10b on the other side, and a connection 10c connecting the first end 10a and the second end 10b. The first end 10 a of the resistance layer 10 covers the first via electrode 23. More specifically, the first end 10a covers the first end 23a (first protrusion 23c) of the first via electrode 23. The first end 10a is formed in a film shape along the main surface and side surfaces of the first via electrode 23.

The second end 10b of the resistance layer 10 covers the second via electrode 24. More specifically, the second end 10b covers the first end 24a (the second protrusion 24c) of the second via electrode 24. The second end 10b is formed in a film shape along the main surface and side surfaces of the second via electrode 24.
The connecting portion 10c extends in a band shape in a region between the first end 10a and the second end 10b. The connecting portion 10c extends in a band along a straight line connecting the first end 10a and the second end 10b. The first end 10a, the second end 10b, and the connection 10c of the resistance layer 10 are formed with a uniform width in this embodiment.

  FIG. 6 is a graph for explaining the temperature characteristics of the resistance layer 10. In the graph of FIG. 6, the vertical axis indicates the resistance value (Ω), and the horizontal axis indicates the temperature (° C.). FIG. 6 shows the first line L1 and the second line L2. The first line L1 shows the characteristics when the resistance layer 10 includes conductive polysilicon. The second line L2 shows the characteristics when the resistance layer 10 contains CrSi.

  Referring to the first line L1, in the case of the resistance layer 10 containing conductive polysilicon, the sheet resistance value monotonously decreased with the temperature rise. It has been found that the resistance layer 10 containing conductive polysilicon has a relatively large variation rate with respect to a temperature rise. On the other hand, referring to the second line L2, in the case of the resistance layer 10 made of a metal thin film containing CrSi, the rate of change of the sheet resistance value with respect to temperature rise is smaller than the rate of change of the sheet resistance value of the first line L1. Was also found to be small.

That is, CrSi has a relatively small temperature dependency as compared with polysilicon, and has a sheet resistance value superior to the sheet resistance of polysilicon. Although not shown, CrSi has a relatively small voltage dependency as compared with polysilicon.
Therefore, by adopting CrSi for the resistance layer 10, the plane area of the resistance layer 10 can be appropriately reduced while appropriately reducing the thickness of the resistance layer 10. Accordingly, the resistance layer 10 can be appropriately interposed in a region between the third insulating layer 15 and the fourth insulating layer 16 while ensuring flatness.

  Further, since the plane area of the resistance layer 10 can be appropriately reduced, the design rule for the resistance layer 10 can be relaxed. That is, the resistance layer 10 can be appropriately arranged in the outer region 7 instead of the device region 6. Therefore, the electrical influence between the resistance layer 10 and the device region 6 can be appropriately suppressed. Even when the resistance layer 10 contains TaN and / or TiN in addition to or instead of CrSi, the same effect as described above can be obtained.

The resistance layer 10 can take various forms. Hereinafter, other embodiments of the resistance layer 10 will be described with reference to FIGS. 7A to 7E.
FIG. 7A is a plan view showing the resistance layer 10 according to the second embodiment. In the following, structures corresponding to the structures described for the electronic component 1 are denoted by the same reference numerals, and description thereof is omitted.
Referring to FIG. 7A, resistance layer 10 according to the second embodiment includes one notch 110 formed in connection portion 10c. The notch 110 extends in a direction crossing the direction in which the connecting portion 10c extends. In this embodiment, the cutout portion 110 extends in a direction orthogonal to the direction in which the connection portion 10c extends.

The cutout portion 110 is a laser beam processing mark in which a part of the region of the connection portion 10c is blown by a laser beam irradiation method. The notch 110 extends the current path of the resistance layer 10. Thereby, the resistance value of the resistance layer 10 is increased. The resistance value of the resistance layer 10 can be adjusted in the increasing direction by the notch 110.
FIG. 7B is a plan view showing the resistance layer 10 according to the third embodiment. In the following, structures corresponding to the structures described for the electronic component 1 are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 7B, resistance layer 10 according to the third embodiment includes a plurality of notches 110 formed in connection portion 10c. The plurality of notches 110 extend in directions that intersect with the direction in which the connecting portions 10c extend. In this embodiment, the plurality of notches 110 extend in a direction orthogonal to the direction in which the connecting portion 10c extends. More specifically, the plurality of notches 110 include one or more (three in this embodiment) first notches 110A and one or more (four in this embodiment) second notches 110B. .

The plurality of first notches 110A are formed at intervals on one side extending in the longitudinal direction in the connection portion 10c. The plurality of first notches 110A each extend in a direction intersecting the direction in which the connecting portion 10c extends.
The plurality of second notches 110B are formed at intervals on the other side extending in the longitudinal direction in the connection portion 10c. The plurality of second notches 110B extend in directions that intersect with the direction in which the connecting portions 10c extend.

In this embodiment, the plurality of first notches 110A and the plurality of second notches 110B are alternately formed along the direction in which the connecting portion 10c extends. Thereby, the resistance layer 10 is formed in a zigzag shape as a whole in plan view.
Each of the plurality of first notches 110A and the plurality of second notches 110B is a laser beam processing mark in which a partial region of the connection portion 10c is melted by a laser beam irradiation method. The current paths of the resistance layer 10 extend by the plurality of first notches 110A and the plurality of second notches 110B. Thereby, the resistance value of the resistance layer 10 is increased. The resistance value of the resistance layer 10 can be adjusted in the increasing direction by the plurality of first notches 110A and the plurality of second notches 110B.

FIG. 7C is a plan view showing the resistance layer 10 according to the fourth embodiment. In the following, structures corresponding to the structures described for the electronic component 1 are denoted by the same reference numerals, and description thereof is omitted.
Referring to FIG. 7C, in resistance layer 10 according to the fourth embodiment, first end portion 10a, second end portion 10b, and connection portion 10c have different widths. More specifically, the first end 10a has a width different from that of the connection 10c. The second end 10b is formed with a width different from that of the connection 10c. In this embodiment, the second end 10b is formed to have the same width as the first end 10a. The second end 10b may be formed with a different width from the first end 10a.

In this embodiment, the first end 10a is formed in a quadrangular shape (a square shape in this embodiment) in plan view. The second end 10b is formed in a quadrangular shape (a square shape in this embodiment) in plan view. Further, the connecting portion 10c has a width smaller than the width of the first end 10a and the width of the second end 10b.
FIG. 7D is a plan view showing the resistance layer 10 according to the fifth embodiment. In the following, structures corresponding to the structures described for the electronic component 1 are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 7D, in resistance layer 10 according to the fifth embodiment, first end portion 10a, second end portion 10b, and connection portion 10c are formed in strip shapes having different widths from each other. More specifically, the first end 10a has a width different from that of the connection 10c. The second end 10b is formed with a width different from that of the connection 10c. In this embodiment, the second end 10b is formed to have the same width as the first end 10a. The second end 10b may be formed with a different width from the first end 10a.

  In this embodiment, the first end 10a is formed in a quadrangular shape (a square shape in this embodiment) in plan view. The second end 10b is formed in a quadrangular shape (a square shape in this embodiment) in plan view. Further, the connecting portion 10c has a width smaller than the width of the first end 10a and the width of the second end 10b. The connection portion 10c further extends in a region between the first end portion 10a and the second end portion 10b in plan view in a plan view.

FIG. 7E is a plan view showing the resistance layer 10 according to the sixth embodiment. In the following, structures corresponding to the structures described for the electronic component 1 are denoted by the same reference numerals, and description thereof is omitted.
With reference to FIG. 7E, the resistance layer 10 according to the sixth embodiment includes a plurality (two or more; four in this embodiment) of first via electrodes 23 and a plurality (two or more; four in this embodiment) of second electrodes. It is electrically connected to the via electrode 24.

That is, a plurality (two or more; four in this embodiment) of first via electrodes 23 and a plurality of (two or more, four in this embodiment) second via electrodes 24 may be formed in the outer region 7. . In this case, the resistance layer 10 collectively covers a plurality of (two or more; four in this embodiment) first via electrodes 23 and a plurality of (two or more, four in this embodiment) second via electrodes 24. You may.
The number of the first via electrodes 23 and the number of the second via electrodes 24 are arbitrary. The number of the first via electrodes 23 and the number of the second via electrodes 24 may be different from each other. The number of the first via electrodes 23 may be equal to or less than the number of the second via electrodes 24. The number of the first via electrodes 23 may be equal to or greater than the number of the second via electrodes 24.

Further, while one first via electrode 23 is formed, a plurality of second via electrodes 24 may be formed. While the plurality of first via electrodes 23 are formed, one second via electrode 24 may be formed.
The characteristics of the resistance layer 10 according to the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, and the sixth embodiment are in an arbitrary mode and an arbitrary mode between them. Can be combined. The resistance layer 10 having a form in which at least two of the characteristics of the resistance layer 10 according to the first to sixth embodiments are combined may be employed.

For example, the features of the resistance layer 10 according to the sixth embodiment may be incorporated in the resistance layer 10 according to the first to fifth embodiments. In this case, the first end 10a according to the first to fifth embodiments covers a plurality of the first via electrodes 23 at a time. Further, the second end 10b according to the first to fifth embodiments covers the plurality of second via electrodes 24 in a lump.
Referring to FIGS. 2 to 4 again, resistance circuit 11 further includes a protection layer 40 for protecting resistance layer 10. The protective layer 40 is interposed in a region between the third insulating layer 15 and the fourth insulating layer 16 and covers the resistance layer 10. The protection layer 40 is formed in a film shape along the resistance layer 10.

The protective layer 40 has a planar shape that matches the planar shape of the resistance layer 10. The protective layer 40 has a side surface connected to the side surface of the resistance layer 10. That is, the side surface of the protective layer 40 is formed flush with the side surface of the resistance layer 10.
The protection layer 40 may have a stacked structure including a silicon oxide film and a silicon nitride film. In this case, a silicon nitride film may be formed over the silicon oxide film, or a silicon oxide film may be formed over the silicon nitride film. The protective layer 40 may have a single-layer structure made of a silicon oxide film or a silicon nitride film. In this embodiment, the protective layer 40 has a single-layer structure made of a silicon oxide film.

  The thickness of the protective layer 40 may be 1 nm or more and 5 μm or less. The thickness of the protective layer 40 is 1 nm to 10 nm, 10 nm to 50 nm, 50 nm to 100 nm, 100 nm to 200 nm, 200 nm to 400 nm, 400 nm to 600 nm, 600 nm to 800 nm, or 800 nm to 1 μm. There may be.

The thickness of the protective layer 40 is 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, It may be 4 μm or more and 4.5 μm or less, or may be 4.5 μm or more and 5 μm or less. The thickness of the protective layer 40 is preferably equal to or larger than the thickness TR of the resistance layer 10.
The resistance circuit 11 further includes a first lower wiring layer 41 and a second lower wiring layer 42. The first lower wiring layer 41 is formed in a region on the third insulating layer 15 side with respect to the resistance layer 10. More specifically, the first lower wiring layer 41 is formed on the connection circuit forming layer 21 (the second insulating layer 14), and is covered with the third insulating layer 15. The first lower wiring layer 41 is embedded in the third insulating layer 15. The first lower wiring layer 41 is electrically connected to the resistance layer 10 via the first via electrode 23.

  The second lower wiring layer 42 is formed in a region on the third insulating layer 15 side with respect to the resistance layer 10. More specifically, the second lower wiring layer 42 is formed on the connection circuit forming layer 21 (the second insulating layer 14), and is covered with the third insulating layer 15. The second lower wiring layer 42 is embedded in the third insulating layer 15. The second lower wiring layer 42 is formed at an interval from the first lower wiring layer 41. The second lower wiring layer 42 is electrically connected to the resistance layer 10 via the second via electrode 24.

Thereby, the resistance layer 10 is connected in series to the first lower wiring layer 41 and the second lower wiring layer 42. The resistance layer 10 is formed on a line connecting the first lower wiring layer 41 and the second lower wiring layer 42 in plan view. In this embodiment, the resistance layer 10 linearly extends in a region between the first lower wiring layer 41 and the second lower wiring layer 42 in plan view.
The first lower wiring layer 41 and the second lower wiring layer 42 each have a first thickness TL1. The first thickness TL1 may be 100 nm or more and 3000 nm or less. The first thickness TL1 may be 100 nm or more and 500 nm or less, 500 nm or more and 1000 nm or less, 1000 nm or more and 1500 nm or less, 1500 nm or more and 2000 nm or less, 2000 nm or more and 2500 nm or less, or 2500 nm or more and 3000 nm or less.

The first thickness TL1 is preferably 100 nm or more and 1500 nm or less. The first thickness TL1 of the first lower wiring layer 41 and the first thickness TL1 of the second lower wiring layer 42 may be different from each other. The first thickness TL1 of the first lower wiring layer 41 and the first thickness TL1 of the second lower wiring layer 42 are preferably equal to each other.
Referring to FIG. 3, first lower wiring layer 41 connects first end 41a on one side, second end 41b on the other side, and first end 41a and second end 41b. It includes the connection part 41c. The first end 41a overlaps the first end 10a of the resistance layer 10 in plan view. The first end 41a is electrically connected to the first end 10a of the resistance layer 10 via the first via electrode 23.

The second end 41b is located in a region outside the resistance layer 10 in plan view. The second end 41b is located in the outer region 7 in this embodiment. The connection portion 41c extends in a band shape in a region between the first end portion 41a and the second end portion 41b in plan view. In this embodiment, the connecting portion 41c extends in a band along a straight line connecting the first end portion 41a and the second end portion 41b.
In this embodiment, the first lower wiring layer 41 has a laminated structure in which a plurality of electrode layers are laminated. The first lower wiring layer 41 includes a first barrier layer 43, a main body layer 44, and a second barrier layer 45 stacked in this order from above the connection circuit forming layer 21 (second insulating layer 14).

In this embodiment, the first barrier layer 43 has a stacked structure including a Ti layer 46 and a TiN layer 47 stacked in this order from above the connection circuit forming layer 21 (second insulating layer 14). The first barrier layer 43 may have a single-layer structure including the Ti layer 46 or the TiN layer 47.
The main body layer 44 has a resistance value lower than the resistance value of the first barrier layer 43 and the resistance value of the second barrier layer 45. The main body layer 44 has a thickness exceeding the thickness of the first barrier layer 43 and the thickness of the second barrier layer 45. The main body layer 44 may include at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. The main body layer 44 has a single-layer structure composed of an AlCu alloy layer 48 in this embodiment.

In this embodiment, the second barrier layer 45 has a laminated structure including a Ti layer 49 and a TiN layer 50 laminated in this order from above the main body layer 44. The second barrier layer 45 may have a single-layer structure including the Ti layer 49 or the TiN layer 50.
Referring to FIG. 4, second lower wiring layer 42 connects first end 42a on one side, second end 42b on the other side, and first end 42a and second end 42b. It includes the connection part 42c. The first end 42a overlaps the second end 10b of the resistance layer 10 in plan view. The first end 42a is electrically connected to the second end 10b of the resistance layer 10 via the second via electrode 24.

The second end 42b is located in a region outside the resistance layer 10 in plan view. The second end 42b is located in the outer region 7 in this embodiment. The connection portion 42c extends in a band shape in a region between the first end portion 42a and the second end portion 42b in plan view. In this embodiment, the connecting portion 42c extends in a band along a straight line connecting the first end 42a and the second end 42b.
In this embodiment, the second lower wiring layer 42 has a laminated structure in which a plurality of electrode layers are laminated. The second lower wiring layer 42 includes a first barrier layer 53, a main body layer 54, and a second barrier layer 55 stacked in this order from above the connection circuit forming layer 21 (the second insulating layer 14).

In this embodiment, the first barrier layer 53 has a laminated structure including a Ti layer 56 and a TiN layer 57 laminated in this order from above the connection circuit forming layer 21 (second insulating layer 14). The first barrier layer 53 may have a single-layer structure including the Ti layer 56 or the TiN layer 57.
The main body layer 54 has a resistance value lower than the resistance value of the first barrier layer 53 and the resistance value of the second barrier layer 55. The main body layer 54 has a thickness exceeding the thickness of the first barrier layer 53 and the thickness of the second barrier layer 55. The main body layer 54 may include at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. In this embodiment, main body layer 54 has a single-layer structure including AlCu alloy layer 58.

In this embodiment, the second barrier layer 55 has a stacked structure including a Ti layer 59 and a TiN layer 60 stacked in this order from above the main body layer 54. The second barrier layer 55 may have a single-layer structure including the Ti layer 59 or the TiN layer 60.
The resistance circuit 11 further includes a first upper wiring layer 61 and a second upper wiring layer 62. The first upper wiring layer 61 is formed on the third insulating layer 15. The first upper wiring layer 61 forms one of the uppermost wiring layers of the multilayer wiring structure 12. The first upper wiring layer 61 is electrically connected to the first lower wiring layer 41.

The second upper wiring layer 62 is formed on the third insulating layer 15 at a distance from the first upper wiring layer 61. The second upper wiring layer 62 forms one of the uppermost wiring layers of the multilayer wiring structure 12. The second upper wiring layer 62 is electrically connected to the second lower wiring layer 42.
Thus, the resistance layer 10 is electrically connected to the first upper wiring layer 61 via the first lower wiring layer 41. The resistance layer 10 is electrically connected to the second upper wiring layer 62 via the second lower wiring layer 42. The resistance layer 10 is connected in series to a first upper wiring layer 61 and a second upper wiring layer 62 via a first lower wiring layer 41 and a second lower wiring layer 42.

The first upper wiring layer 61 is formed at an interval from the resistance layer 10 in plan view. The first upper wiring layer 61 does not overlap the resistance layer 10 in plan view. The entire resistance layer 10 is exposed from the first upper wiring layer 61 in plan view.
The second upper wiring layer 62 is formed at an interval from the resistance layer 10 in plan view. The second upper wiring layer 62 does not overlap the resistance layer 10 in plan view. The entire resistive layer 10 is exposed from the second upper wiring layer 62 in plan view.

That is, the resistance layer 10 is formed in a region between the first upper wiring layer 61 and the second upper wiring layer 62 in plan view. Thereby, the parasitic capacitance can be suppressed in a region between the resistance layer 10 and the first upper wiring layer 61. Further, parasitic capacitance can be suppressed in a region between the resistance layer 10 and the second upper wiring layer 62.
In this embodiment, the resistance layer 10 is formed at a distance from the first upper wiring layer 61 and the second upper wiring layer 62 in plan view. Thereby, the parasitic capacitance can be appropriately suppressed in a region between the resistance layer 10 and the first upper wiring layer 61.

The first upper wiring layer 61 and the second upper wiring layer 62 each have a second thickness TL2. The second thickness TL2 is equal to or greater than the first thickness TL1 (TL1 ≦ TL2). More specifically, the second thickness TL2 exceeds the first thickness TL1 (TL1 <TL2).
The second thickness TL2 may be 100 nm or more and 15000 nm or less. The second thickness TL2 is 100 nm to 1500 nm, 1500 nm to 3000 nm, 3000 nm to 4500 nm, 4500 nm to 6000 nm, 6000 nm to 7500 nm, 7500 nm to 9000 nm, 9000 nm to 10500 nm, 10500 nm to 12000 nm, 12000 nm to 13500 nm Hereinafter, it may be 13500 nm or more and 15000 nm or less.

The second thickness TL2 of the first upper wiring layer 61 and the second thickness TL2 of the second upper wiring layer 62 may be different from each other. It is preferable that the second thickness TL2 of the first upper wiring layer 61 and the second thickness TL2 of the second upper wiring layer 62 are equal to each other.
With reference to FIG. 3, the first upper wiring layer 61 has a first end 61a on one side, a second end 61b on the other side, and a connection connecting the first end 61a and the second end 61b. Section 61c. The first end 61a is located in a region overlapping the first end 41a of the first lower wiring layer 41 in plan view.

  The second end 61b is located in a region outside the resistance layer 10 in plan view. In this embodiment, the second end 61b is located in the device region 6 in plan view. The second end 61b may be located in the outer region 7. The connection portion 61c extends in a band shape in a region between the first end portion 61a and the second end portion 61b in plan view. In this embodiment, the connecting portion 61c extends in a band along a straight line connecting the first end 61a and the second end 61b.

In this embodiment, the first upper wiring layer 61 has a laminated structure in which a plurality of electrode layers are laminated. The first upper wiring layer 61 includes a first barrier layer 63, a main body layer 64, and a second barrier layer 65 laminated in this order from above the connection circuit forming layer 21 (second insulating layer 14).
In this embodiment, the first barrier layer 63 has a laminated structure including a Ti layer 66 and a TiN layer 67 laminated in this order from above the connection circuit forming layer 21 (second insulating layer 14). The first barrier layer 63 may have a single-layer structure including the Ti layer 66 or the TiN layer 67.

  The main body layer 64 has a resistance value lower than the resistance value of the first barrier layer 63 and the resistance value of the second barrier layer 65. The main body layer 64 has a thickness exceeding the thickness of the first barrier layer 63 and the thickness of the second barrier layer 65. The main body layer 64 may include at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. In this embodiment, the main body layer 64 has a single-layer structure including the AlCu alloy layer 68.

In this embodiment, the second barrier layer 65 has a laminated structure including a Ti layer 69 and a TiN layer 70 laminated in this order from above the main body layer 64. The second barrier layer 65 may have a single-layer structure including the Ti layer 69 or the TiN layer 70.
Referring to FIG. 4, second upper wiring layer 62 has a first end 62a on one side, a second end 62b on the other side, and a connection connecting first end 62a and second end 62b. Section 62c. The first end 62a is located in a region overlapping the second end 42b of the second lower wiring layer 42 in plan view.

  The second end 62b is located in a region outside the resistance layer 10 in plan view. In this embodiment, the second end 62b is located in the device region 6 in plan view. The second end 62b may be located in the outer region 7 in a plan view. The connecting portion 62c extends in a band shape in a region between the first end 62a and the second end 62b in plan view. In this embodiment, the connecting portion 62c extends in a band along a straight line connecting the first end portion 62a and the second end portion 62b.

In this embodiment, the second upper wiring layer 62 has a laminated structure in which a plurality of electrode layers are laminated. The second upper wiring layer 62 includes a first barrier layer 73, a main body layer 74, and a second barrier layer 75 stacked in this order from above the connection circuit forming layer 21 (second insulating layer 14).
In this embodiment, the first barrier layer 73 has a stacked structure including a Ti layer 76 and a TiN layer 77 stacked in this order from above the connection circuit forming layer 21 (second insulating layer 14). The first barrier layer 73 may have a single-layer structure including the Ti layer 76 or the TiN layer 77.

  The main body layer 74 has a resistance value lower than the resistance value of the first barrier layer 73 and the resistance value of the second barrier layer 75. The main body layer 74 has a thickness exceeding the thickness of the first barrier layer 73 and the thickness of the second barrier layer 75. The main body layer 74 may include at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. In this embodiment, main body layer 74 has a single-layer structure including AlCu alloy layer 78.

In this embodiment, the second barrier layer 75 has a laminated structure including a Ti layer 79 and a TiN layer 80 laminated in this order from above the main body layer 74. The second barrier layer 75 may have a single-layer structure including the Ti layer 79 or the TiN layer 80.
Referring to FIGS. 1 to 4, resistance circuit 11 includes a first long via electrode 83 and a second long via electrode 84. The first long via electrode 83 is electrically connected to the first lower wiring layer 41 and the first upper wiring layer 61. The second long via electrode 84 is electrically connected to the second lower wiring layer 42 and the second upper wiring layer 62.

Thereby, the resistance layer 10 is electrically connected to the first upper wiring layer 61 via the first via electrode 23, the first lower wiring layer 41, and the first long via electrode 83. Further, the resistance layer 10 is electrically connected to the second upper wiring layer 62 via the second via electrode 24, the second lower wiring layer 42, and the second long via electrode 84.
The first long via electrode 83 is formed on the side of the resistance layer 10. In this embodiment, the first long via electrode 83 is located on a straight line connecting the first via electrode 23 and the second via electrode 24.

The second long via electrode 84 is formed on the side of the resistance layer 10 at a distance from the first long via electrode 83. In this embodiment, the second long via electrode 84 faces the first long via electrode 83 with the resistance layer 10 interposed therebetween. The second long via electrode 84 is located on a straight line connecting the first via electrode 23 and the second via electrode 24.
Thus, the resistance layer 10 is located on a straight line connecting the first long via electrode 83 and the second long via electrode 84. The resistance layer 10 is located on a straight line connecting the first via electrode 23, the second via electrode 24, the first long via electrode 83, and the second long via electrode 84. In this embodiment, the resistance layer 10 extends along a straight line connecting the first long via electrode 83 and the second long via electrode 84.

In this embodiment, the first long via electrode 83 is formed in a circular shape in plan view. The planar shape of the first long via electrode 83 is arbitrary. The first long via electrode 83 may be formed in a polygonal shape such as a triangular shape, a quadrangular shape or a hexagonal shape, or an elliptical shape in plan view, instead of the circular shape.
The first long via electrode 83 crosses the resistance layer 10 in a direction normal to the main surface of the third insulating layer 15. The first long via electrode 83 penetrates through the third insulating layer 15 and the fourth insulating layer 16 and is embedded in the third insulating layer 15 and the fourth insulating layer 16, and is exposed from the main surface of the fourth insulating layer 16. .

The first long via electrode 83 includes a first end 83a on one side and a second end 83b on the other side with respect to the direction of the normal to the main surface of the third insulating layer 15. The first end 83a is exposed from the main surface of the fourth insulating layer 16. The first end 83a is electrically connected to the first end 61a of the first upper wiring layer 61.
The second end 83b is located in the third insulating layer 15. The second end 83b is electrically connected to the second end 41b of the first lower wiring layer 41. The first long via electrode 83 is formed in a tapered shape in which the width decreases from the first end 83a toward the second end 83b in a cross-sectional view.

  The first long via electrode 83 has a lower portion 83c located on the third insulating layer 15 side with respect to the resistive layer 10, and an upper portion 83d located on the fourth insulating layer 16 side with respect to the resistive layer 10. ing. In the normal direction of the main surface of the third insulating layer 15, the length of the upper portion 83d is equal to or longer than the length of the lower portion 83c. More specifically, the length of the upper portion 83d exceeds the length of the lower portion 83c.

The first long via electrode 83 has a laminated structure including a main body layer 85 and a barrier layer 86. The main body layer 85 is embedded in the third insulating layer 15 and the fourth insulating layer 16. The main body layer 85 may include tungsten (W) or copper (Cu). In this embodiment, the first long via electrode 83 has a single-layer structure including the tungsten layer 87.
The barrier layer 86 is interposed between the main body layer 85 and the third insulating layer 15 and between the main body layer 85 and the fourth insulating layer 16. In this embodiment, the barrier layer 86 has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer 86 includes a Ti layer 88 and a TiN layer 89 formed in this order from the third insulating layer 15.

The Ti layer 88 is in contact with the third insulating layer 15 and the fourth insulating layer 16. The TiN layer 89 is in contact with the main body layer 85. The barrier layer 86 may have a single-layer structure including a Ti layer 88 or a TiN layer 89.
In this embodiment, the second long via electrode 84 is formed in a circular shape in plan view. The planar shape of the second long via electrode 84 is arbitrary. The second long via electrode 84 may be formed in a polygonal shape such as a triangular shape, a quadrangular shape, or a hexagonal shape, or an elliptical shape in plan view, instead of the circular shape.

The second long via electrode 84 crosses the resistance layer 10 in a direction normal to the main surface of the third insulating layer 15. The second long via electrode 84 penetrates through the third insulating layer 15 and the fourth insulating layer 16, is embedded in the third insulating layer 15 and the fourth insulating layer 16, and is exposed from the main surface of the fourth insulating layer 16. .
The second long via electrode 84 includes a first end 84a on one side and a second end 84b on the other side in a direction normal to the main surface of the third insulating layer 15. The first end 84a is exposed from the main surface of the fourth insulating layer 16. The first end 84a is electrically connected to the first end 62a of the second upper wiring layer 62.

The second end 84b is located in the third insulating layer 15. The second end 84b is electrically connected to the second end 42b of the second lower wiring layer 42. The second long via electrode 84 is formed in a tapered shape in which the width is reduced from the first end 84a toward the second end 84b in a sectional view.
The second long via electrode 84 has a lower portion 84c located on the third insulating layer 15 side with respect to the resistive layer 10, and an upper portion 84d located on the fourth insulating layer 16 side with respect to the resistive layer 10. ing. With respect to the normal direction of the main surface of the third insulating layer 15, the length of the upper portion 84d is equal to or longer than the length of the lower portion 84c. The length of the upper portion 84d more specifically exceeds the length of the lower portion 84c.

The second long via electrode 84 has a laminated structure including the main body layer 90 and the barrier layer 91. The main body layer 90 is embedded in the third insulating layer 15 and the fourth insulating layer 16. The main body layer 90 may include tungsten (W) or copper (Cu). In this embodiment, the second long via electrode 84 has a single-layer structure including the tungsten layer 92.
The barrier layer 91 is interposed between the main body layer 90 and the third insulating layer 15 and between the main body layer 90 and the fourth insulating layer 16. In this embodiment, the barrier layer 91 has a laminated structure in which a plurality of electrode layers are laminated. In this embodiment, the barrier layer 91 includes a Ti layer 93 and a TiN layer 94 formed in this order from the third insulating layer 15.

The Ti layer 93 is in contact with the third insulating layer 15 and the fourth insulating layer 16. The TiN layer 94 is in contact with the main body layer 90. The barrier layer 91 may have a single-layer structure including the Ti layer 93 or the TiN layer 94.
Referring to FIG. 2, connection circuit forming layer 21 includes a wiring 95 for electrically connecting the functional device and resistance layer 10. The wiring 95 is selectively formed in the first insulating layer 13 and the second insulating layer 14, and is routed from the device region 6 to the outside region 7.

More specifically, the wiring 95 includes one or more connection wiring layers 96 electrically connected to the functional device in the device region 6. One or more connection wiring layers 96 are formed on one or both of the first insulating layer 13 and the second insulating layer 14. FIG. 2 shows an example in which two connection wiring layers 96 are formed on the first insulating layer 13.
One or more connection wiring layers 96 are selectively routed from the device region 6 to the outer region 7. The connection wiring layer 96 has the same laminated structure as the first lower wiring layer 41 (second lower wiring layer 42) and the first upper wiring layer 61 (second upper wiring layer 62). A specific description of the connection wiring layer 96 is omitted.

The wiring 95 includes one or a plurality of connection via electrodes 97. One or a plurality of connection via electrodes 97 may be used to connect one or a plurality of connection wiring layers 96 to any of the first lower wiring layers 41 (the second lower wiring layers 42) or any of the first upper wiring layers 61 (the 2 upper wiring layer 62).
One or more connection via electrodes 97 are formed on one or both of the first insulating layer 13 and the second insulating layer 14. FIG. 2 shows an example in which one connection wiring layer 96 is connected to the first lower wiring layer 41 by two connection via electrodes 97.

The connection via electrode 97 has the same laminated structure as the first via electrode 23 (second via electrode 24) and the first long via electrode 83 (second long via electrode 84). A specific description of the connection via electrode 97 is omitted.
The second end 61b of the first upper wiring layer 61 may be connected to an arbitrary connection wiring layer 96 via the connection via electrode 97. The second end 62b of the second upper wiring layer 62 may be connected to an arbitrary connection wiring layer 96 via the connection via electrode 97.

  Referring to FIG. 2, uppermost insulating layer 101 is formed on multilayer wiring structure 12. The uppermost insulating layer 101 selectively covers the first upper wiring layer 61 and the second upper wiring layer 62. The top insulating layer 101 covers the connection between the first upper wiring layer 61 and the first long via electrode 83 in plan view. The uppermost insulating layer 101 covers the connection between the second upper wiring layer 62 and the second long via electrode 84 in plan view.

  A first pad opening 102 and a second pad opening 103 are formed in the uppermost insulating layer 101 in the outer region 7. The first pad opening 102 exposes a partial area of the first upper wiring layer 61 as a first pad area 104. More specifically, the first pad opening 102 exposes a region other than a connection portion between the first upper wiring layer 61 and the first long via electrode 83 in the first upper wiring layer 61 as a first pad region 104.

The second pad opening 103 exposes a partial area of the second upper wiring layer 62 as a second pad area 105. More specifically, the second pad opening 103 exposes a region other than a connection portion between the second upper wiring layer 62 and the second long via electrode 84 in the second upper wiring layer 62 as a second pad region 105.
In this embodiment, the uppermost insulating layer 101 has a laminated structure including the passivation layer 106 and the resin layer 107. In FIG. 1, the resin layer 107 is indicated by hatching for clarity.

The passivation layer 106 may have a stacked structure including a silicon oxide film and a silicon nitride film. In this case, a silicon nitride film may be formed over the silicon oxide film, or a silicon oxide film may be formed over the silicon nitride film.
Passivation layer 106 may have a single-layer structure made of a silicon oxide film or a silicon nitride film. It is preferable that the passivation layer 106 is formed of an insulating material made of a different kind from the multilayer wiring structure 12. In this embodiment, the passivation layer 106 has a single-layer structure made of a silicon nitride film.

The resin layer 107 may include a photosensitive resin. The photosensitive resin may be of a positive type or a negative type. In this embodiment, the resin layer 107 contains polyimide as an example of a negative type photosensitive resin. The resin layer 107 may include polybenzoxazole as an example of a positive type photosensitive resin.
As described above, according to the electronic component 1, since the resistance layer 10 is made of a metal thin film, the resistance layer 10 can be appropriately incorporated into the multilayer wiring structure 12. That is, CrSi, TaN, and TiN employed as the metal material of the resistance layer 10 have relatively small temperature dependence and voltage dependence, and have a sheet resistance value superior to the sheet resistance of polysilicon. ing.

Therefore, by adopting a metal thin film containing at least one of CrSi, TaN and TiN for the resistance layer 10, the plane area of the resistance layer 10 is appropriately reduced while appropriately reducing the thickness of the resistance layer 10. it can.
Accordingly, the resistance layer 10 can be appropriately interposed in a region between the third insulating layer 15 and the fourth insulating layer 16 while ensuring flatness. Further, since the contact with the resistance layer 10 can be formed by the first via electrode 23 and the second via electrode 24 embedded in the third insulating layer 15, the flatness of the upper layer of the resistance layer 10 can be appropriately improved. That is, the flatness of the fourth insulating layer 16 can be appropriately improved.

Thereby, the first upper wiring layer 61 and the second upper wiring layer 62 can be appropriately formed on the fourth insulating layer 16 having improved flatness. As a result, it is possible to provide the electronic component 1 that can appropriately incorporate the resistance layer 10 into the multilayer wiring structure 12.
8A to 8S are cross-sectional views illustrating an example of a method for manufacturing the electronic component 1 shown in FIG. 8A to 8S are cross-sectional views of a portion corresponding to FIG.

Referring to FIG. 8A, in manufacturing electronic component 1, first, semiconductor layer 2 on which device region 6 and outer region 7 are formed is prepared. Next, the connection circuit forming layer 21 of the multilayer wiring structure 12 is formed on the first main surface 3 of the semiconductor layer 2.
The connection circuit forming layer 21 includes the first insulating layer 13, the second insulating layer 14, one or more connection wiring layers 96, and one or more connection via electrodes 97. The description of the step of forming the connection circuit forming layer 21 is omitted.

Next, referring to FIG. 8B, first base wiring layer 111 serving as a base of first lower wiring layer 41 and second lower wiring layer 42 is formed on connection circuit forming layer 21. The step of forming the first base wiring layer 111 includes a step of forming the first barrier layer 112, the main body layer 113, and the second barrier layer 114 in this order from above the connection circuit forming layer 21.
The step of forming the first barrier layer 112 includes a step of forming a Ti layer and a TiN layer in this order from above the connection circuit formation layer 21. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 113 includes a step of forming an AlCu alloy layer on the first barrier layer 112. The AlCu alloy layer may be formed by a sputtering method.

The step of forming the second barrier layer 114 includes a step of forming a Ti layer and a TiN layer in this order from above the main body layer 113. The Ti layer and the TiN layer may each be formed by a sputtering method.
Next, referring to FIG. 8C, mask 115 having a predetermined pattern is formed on first base wiring layer 111. The mask 115 has an opening 116 that covers a region in the first base wiring layer 111 where the first lower wiring layer 41 and the second lower wiring layer 42 are to be formed, and exposes other regions.

Next, unnecessary portions of the first base wiring layer 111 are removed by an etching method through the mask 115. Thus, the first base wiring layer 111 is divided into the first lower wiring layer 41 and the second lower wiring layer 42. The mask 115 is then removed.
Next, referring to FIG. 8D, third insulating layer 15 covering first lower wiring layer 41 and second lower wiring layer 42 is formed on connection circuit forming layer 21. The third insulating layer 15 may be formed by a CVD (Chemical Vapor Deposition) method.

Next, referring to FIG. 8E, first via hole 117 exposing first lower wiring layer 41 and second via hole 118 exposing second lower wiring layer 42 are formed in third insulating layer 15. .
In this step, first, a mask 119 having a predetermined pattern is formed on the third insulating layer 15. The mask 119 has a plurality of openings 120 exposing regions in the third insulating layer 15 where the first via holes 117 and the second via holes 118 are to be formed.

Next, unnecessary portions of the third insulating layer 15 are removed by an etching method via the mask 119. Thereby, the first via hole 117 and the second via hole 118 are formed in the third insulating layer 15. The mask 119 is then removed.
Next, referring to FIG. 8F, base electrode layer 121 serving as a base of first via electrode 23 and second via electrode 24 is formed on third insulating layer 15. The step of forming the base electrode layer 121 includes a step of forming the barrier layer 122 and the body layer 123 in this order from above the third insulating layer 15.

The step of forming the barrier layer 122 includes a step of forming a Ti layer and a TiN layer in this order from above the third insulating layer 15. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 123 includes a step of forming a tungsten layer on the barrier layer 122. The tungsten layer may be formed by a CVD method.
Next, referring to FIG. 8G, a step of removing base electrode layer 121 is performed. The base electrode layer 121 is removed until the third insulating layer 15 is exposed. The step of removing the base electrode layer 121 may include a step of removing the base electrode layer 121 by grinding.

  In this embodiment, the grinding step of the base electrode layer 121 is performed by a CMP (Chemical Mechanical Polishing) method using an abrasive (abrasive grains). The step of grinding the base electrode layer 121 may include a step of planarizing the main surface of the third insulating layer 15. Thereby, the first via electrode 23 is formed in the first via hole 117. Further, the second via electrode 24 is formed in the second via hole 118.

Next, referring to FIG. 8H, the polishing agent (abrasive particles) attached to the main surface of third insulating layer 15 is removed by cleaning using a chemical solution. In this step, a part of the third insulating layer 15 together with the abrasive (abrasive grains) is removed by a chemical.
As a result, a part of the first via electrode 23 is formed as a first protrusion 23 c protruding from the third insulating layer 15. Further, a part of the second via electrode 24 is formed as a second protrusion 24 c protruding from the third insulating layer 15.

Next, referring to FIG. 8I, base resistance layer 124 serving as a base of resistance layer 10 is formed on the main surface of third insulating layer 15. The base resistance layer 124 contains CrSi. The base resistance layer 124 may be formed by a sputtering method.
Next, a base protection layer 125 serving as a base of the protection layer 40 is formed on the base resistance layer 124. The base protection layer 125 includes silicon oxide. The base protective layer 125 may be formed by a CVD method.

  Next, the base resistance layer 124 (CrSi) is crystallized. The crystallization step of the base resistance layer 124 includes a step of annealing at a temperature and for a time at which the base resistance layer 124 (CrSi) is crystallized. The base resistance layer 124 may be heated at a temperature of 400 ° to 600 ° for 60 minutes to 120 minutes. The crystallization step of the base resistance layer 124 may be performed after the formation step of the base resistance layer 124 and before the formation step of the protective layer 40.

Next, referring to FIG. 8J, a mask 126 having a predetermined pattern is formed on base protective layer 125. The mask 126 has an opening 127 that covers a region where the protective layer 40 is to be formed in the base protective layer 125 and exposes other regions.
Next, unnecessary portions of the base protective layer 125 are removed by an etching method through the mask 126. Thereby, the protective layer 40 is formed.

Next, unnecessary portions of the base resistance layer 124 are removed by an etching method using the mask 126 and the protective layer 40 as a mask. Thereby, the resistance layer 10 is formed. The mask 126 is then removed. The mask 126 may be removed after the step of forming the protective layer 40 and before the step of forming the resistance layer 10.
Next, referring to FIG. 8K, a fourth insulating layer 16 covering protective layer 40 and resistance layer 10 is formed on third insulating layer 15. The fourth insulating layer 16 may be formed by a CVD method.

Next, referring to FIG. 8L, a first via hole 128 exposing the first lower wiring layer 41 and a second via hole 129 exposing the second lower wiring layer 42 are formed by the third insulating layer 15 and the fourth insulating layer. Formed on layer 16.
In this step, first, a mask 130 having a predetermined pattern is formed on the fourth insulating layer 16. The mask 130 has a plurality of openings 131 exposing regions where the first via holes 128 and the second via holes 129 are to be formed in the fourth insulating layer 16.

Next, unnecessary portions of the third insulating layer 15 and the fourth insulating layer 16 are removed by an etching method through the mask 130. Thereby, the first via hole 128 and the second via hole 129 are formed in the third insulating layer 15 and the fourth insulating layer 16. The mask 130 is then removed.
Next, referring to FIG. 8M, base electrode layer 132 serving as a base of first long via electrode 83 and second long via electrode 84 is formed on fourth insulating layer 16. The step of forming the base electrode layer 132 includes the step of forming the barrier layer 133 and the body layer 134 in this order from above the fourth insulating layer 16.

The step of forming the barrier layer 133 includes a step of forming a Ti layer and a TiN layer in this order from above the fourth insulating layer 16. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 134 includes a step of forming a tungsten layer on the barrier layer 133. The tungsten layer may be formed by a CVD method.
Next, referring to FIG. 8N, a step of removing base electrode layer 132 is performed. The base electrode layer 132 is removed until the fourth insulating layer 16 is exposed. The step of removing the base electrode layer 132 may include a step of removing the base electrode layer 132 by grinding.

In this embodiment, the step of grinding the base electrode layer 132 is performed by a CMP method using an abrasive (abrasive grains). The step of grinding the base electrode layer 132 may include a step of planarizing the main surface of the fourth insulating layer 16. Thereby, the first long via electrode 83 and the second long via electrode 84 are formed in the first via hole 128 and the second via hole 129, respectively.
After the step of grinding the base electrode layer 132, the abrasive (abrasive) attached to the main surface of the fourth insulating layer 16 may be removed by cleaning using a chemical. A part of the fourth insulating layer 16 may be removed together with the abrasive (abrasive) by a chemical solution. In this case, a part of the first long via electrode 83 may be formed as a protrusion protruding from the fourth insulating layer 16. Further, a part of the second long via electrode 84 may be formed as a projecting portion projecting from the fourth insulating layer 16.

Next, referring to FIG. 8O, a second base wiring layer 135 serving as a base of first upper wiring layer 61 and second upper wiring layer 62 is formed on fourth insulating layer 16. The step of forming the second base wiring layer 135 includes the step of forming the first barrier layer 136, the main body layer 137, and the second barrier layer 138 in this order from above the fourth insulating layer 16.
The step of forming the first barrier layer 136 includes a step of forming a Ti layer and a TiN layer in this order from above the fourth insulating layer 16. The Ti layer and the TiN layer may each be formed by a sputtering method. The step of forming the main body layer 137 includes a step of forming an AlCu alloy layer on the first barrier layer 136. The AlCu alloy layer may be formed by a sputtering method.

The step of forming the second barrier layer 138 includes a step of forming a Ti layer and a TiN layer in this order from above the main body layer 137. The Ti layer and the TiN layer may each be formed by a sputtering method.
Next, referring to FIG. 8P, a mask 139 having a predetermined pattern is formed on second base wiring layer 135. The mask 139 has an opening 140 that covers a region of the second base wiring layer 135 where the first upper wiring layer 61 and the second upper wiring layer 62 are to be formed in the outer region 7 and exposes other regions. I have.

  Next, unnecessary portions of the second base wiring layer 135 are removed by an etching method through the mask 139. Thus, the second base wiring layer 135 is divided into the first upper wiring layer 61 and the second upper wiring layer 62. Thereby, the multilayer wiring structure 12 including the connection circuit formation layer 21 and the resistance circuit formation layer 22 is formed on the first main surface 3 of the semiconductor layer 2. The mask 139 is then removed.

Next, referring to FIG. 8Q, passivation layer 106 is formed on multilayer wiring structure 12. Passivation layer 106 includes silicon nitride. The passivation layer 106 may be formed by a CVD method.
Next, a resin layer 107 is applied on the passivation layer 106. The resin layer 107 may include polyimide as an example of a negative type photosensitive resin.

Next, referring to FIG. 8R, resin layer 107 is developed after being selectively exposed. Thereby, a plurality of openings 141 serving as bases of the first pad opening 102 and the second pad opening 103 are formed in the resin layer 107.
Next, referring to FIG. 8S, an unnecessary portion of passivation layer 106 is removed by an etching method via resin layer 107. Thus, a first pad opening 102 and a second pad opening 103 exposing the first upper wiring layer 61 and the second upper wiring layer 62 are formed. Through the steps including the above, the electronic component 1 is manufactured.

FIG. 9 is a schematic plan view illustrating an electronic component 151 according to the second embodiment of the present invention, and is a plan view illustrating a mode in which the resistance layer 10 according to the first embodiment is incorporated. In the following, structures corresponding to the structures described for the electronic component 1 are denoted by the same reference numerals, and description thereof is omitted.
Electronic component 1 includes one resistance circuit 11 (resistance layer 10) formed in outer region 7. On the other hand, referring to FIG. 9, electronic component 151 includes a plurality (two or more, four in this embodiment) of resistance circuits 11 (resistance layers 10) formed in outer region 7. The number of the resistance circuits 11 (resistance layers 10) is arbitrary, and five or more resistance circuits may be formed according to the form of the functional device.

  The plurality of resistance circuits 11 (resistance layers 10) are each electrically connected to the device region 6 (functional device) via the connection circuit formation layer 21. The plurality of resistance circuits 11 (resistance layers 10) may be independently and electrically connected to the device region 6. At least two of the plurality of resistance circuits 11 (resistance layers 10) may be connected to each other in parallel or in series.

In this embodiment, the plurality of resistance circuits 11 each include the resistance layer 10 according to the first embodiment. However, the plurality of resistance circuits 11 may each include any one of the resistance layers 10 according to the first to sixth embodiments.
At least two of the plurality of resistance circuits 11 may include the resistance layer 10 according to the same embodiment. The plurality of resistance circuits 11 may include the resistance layers 10 according to different embodiments. The plurality of resistance circuits 11 may include the resistance layer 10 having a form in which at least two of the characteristics of the resistance layer 10 according to the first to sixth embodiments are combined.

As described above, the electronic component 151 can also achieve the same effects as those described for the electronic component 1.
FIG. 10 is a schematic cross-sectional view showing an electronic component 161 according to the third embodiment of the present invention, and is a cross-sectional view showing a mode in which the fuse resistance layer 162 according to the first embodiment is incorporated. FIG. 11 is an enlarged view of the area XI shown in FIG. FIG. 12 is an enlarged view of a region XII shown in FIG. In the following, structures corresponding to the structures described for the electronic component 1 are denoted by the same reference numerals, and description thereof is omitted.

Referring to FIGS. 10 to 12, resistance circuit 11 according to electronic component 161 includes a fuse resistance layer 162 (resistance layer) made of a metal thin film. The fuse resistance layer 162 is melted by a predetermined voltage (current) and opens a current path. The fuse resistance layer 162 is formed by changing the layout of the mask 126 in the step of forming the resistance layer 10 (see FIG. 8J).
The fuse resistance layer 162 is preferably made of a metal thin film containing at least one of CrSi (chromium silicon alloy), TaN (tantalum nitride), and TiN (titanium nitride). It is particularly preferable that the metal thin film contains CrSi. The fuse resistance layer 162 may have a single-layer structure made of a CrSi film, a TaN film, or a TiN film. The fuse resistance layer 162 may have a stacked structure including a CrSi film and a TaN film stacked in any order.

  The fuse resistance layer 162 may have a laminated structure including a CrSi film and a TiN film laminated in any order. The fuse resistance layer 162 may have a stacked structure including a TaN film and a TiN film stacked in an arbitrary order. The fuse resistance layer 162 may have a laminated structure including a CrSi film, a TaN film, and a TiN film laminated in an arbitrary order. In this embodiment, the fuse resistance layer 162 has a single-layer structure made of a CrSi film.

By employing CrSi for the fuse resistance layer 162, the planar area of the fuse resistance layer 162 can be appropriately reduced while appropriately reducing the thickness of the fuse resistance layer 162. Thus, the fuse resistance layer 162 can be appropriately interposed in the multilayer wiring structure 12 while ensuring flatness.
Further, since the plane area of the fuse resistance layer 162 can be appropriately reduced, the design rule for the fuse resistance layer 162 can be relaxed. That is, the fuse resistance layer 162 can be appropriately disposed not in the device region 6 but in the outer region 7. Therefore, the electrical influence between the fuse resistance layer 162 and the device region 6 can be appropriately suppressed. Even when the fuse resistance layer 162 contains TaN and / or TiN in addition to or instead of CrSi, the same effect as described above can be obtained.

  Further, since the fuse resistance layer 162 made of a metal thin film is thinner than polysilicon or the like, damage to surroundings due to fusing can be suppressed. The fuse resistance layer 162 is used as a trimming device for adjusting a resistance value of an electronic circuit or a protection device for protecting the electronic circuit from overvoltage (overcurrent). In this embodiment, the fuse resistance layer 162 is a trimming device for adjusting the resistance value of the electronic circuit.

When the fuse resistance layer 162 is used for adjusting the resistance value, the step of cutting the fuse resistance layer 162 can be performed at the time of a wafer test or after the packaging step. In addition, since the resistance value can be adjusted without performing the laser irradiation method, the number of steps can be reduced.
The sheet resistance value of the fuse resistance layer 162 may be 100Ω / □ or more and 50000Ω / □ or less. The sheet resistance value of the fuse resistance layer 162 is 100Ω / □ or more and 5000Ω / □ or less, 5000Ω / □ or more and 10000Ω / □ or less, 10000Ω / □ or more and 15000Ω / □ or less, 15000Ω / □ or more and 20000Ω / □ or less and 20000Ω / □ or more. 25,000Ω / □ or less, 25000Ω / □ or more and 30000Ω / □ or less, 30000Ω / □ or more and 30000Ω / □ or less, 35000Ω / □ or more and 40000Ω / □ or less, 40000Ω / □ or more and 45000Ω / □ or less, or 45000Ω / □ or more and 50000Ω / □. It may be as follows.

  The content of Cr with respect to the total weight of the fuse resistance layer 162 may be 5% by weight or more and 50% by weight or less. The content of Cr is 5 wt% to 10 wt%, 10 wt% to 15 wt%, 15 wt% to 20 wt%, 20 wt% to 25 wt%, 25 wt% to 30 wt%. , 30 wt% to 35 wt%, 35 wt% to 40 wt%, 40 wt% to 45 wt%, or 45 wt% to 50 wt%.

  The fuse resistance layer 162 has a thickness TR (TR <TI) smaller than the thickness TI of the third insulating layer 15. The ratio TR / TI of the thickness TR of the fuse resistance layer 162 to the thickness TI of the third insulating layer 15 may be 0.001 or more and 0.01 or less. The ratio TR / TI is 0.001 to 0.002, 0.002 to 0.004, 0.004 to 0.006, 0.006 to 0.008, or 0.008 to 0.00. 01 or less.

  The thickness TR may be 0.1 nm or more and 100 nm or less. The thickness TR is 0.1 to 10 nm, 10 to 20 nm, 20 to 30 nm, 30 to 40 nm, 40 to 50 nm, 50 to 60 nm, 60 to 70 nm, 70 to 80 nm, 80 to 90 nm. The thickness may be 90 nm or more and 100 nm or less. The thickness TR is preferably 1 nm or more and 20 nm or less.

  In this embodiment, the fuse resistance layer 162 is formed in a portion of the multilayer wiring structure 12 located in the outer region 7 in the same manner as the resistance layer 10. By arranging the fuse resistance layer 162 in the outer region 7, the electrical influence of the fuse resistance layer 162 on the device region 6 can be suppressed, and the electrical influence of the device region 6 on the fuse resistance layer 162 can be suppressed. As an example, the parasitic capacitance between the device region 6 and the fuse resistance layer 162 can be suppressed. That is, the noise can be reduced and the Q value can be improved.

  More specifically, the fuse resistance layer 162 is interposed in a region between the third insulating layer 15 and the fourth insulating layer 16 in the outer region 7. The fuse resistance layer 162 is formed in a film shape on the main surface of the third insulating layer 15. The above-described resistance layer 10 may be formed on the main surface of the third insulating layer 15. In this case, the third insulating layer 15 is preferably occupied by the resistance layer 10 and the fuse resistance layer 162. The fuse resistance layer 162 may be directly connected to the resistance layer 10 or may be electrically connected to the resistance layer 10 via a wiring.

The fuse resistance layer 162 is formed so as to straddle the first via electrode 23 and the second via electrode 24. As a result, the fuse resistance layer 162 is electrically connected to the first via electrode 23 and the second via electrode 24.
The fuse resistance layer 162 is electrically connected to the first upper wiring layer 61 via the first via electrode 23, the first lower wiring layer 41, and the first long via electrode 83. The fuse resistance layer 162 is electrically connected to the second upper wiring layer 62 via the second via electrode 24, the second lower wiring layer 42, and the second long via electrode 84.

  Fuse resistance layer 162 is located on a straight line connecting first long via electrode 83 and second long via electrode 84. The fuse resistance layer 162 is located on a straight line connecting the first via electrode 23, the second via electrode 24, the first long via electrode 83, and the second long via electrode 84. In this embodiment, the fuse resistance layer 162 extends along a straight line connecting the first long via electrode 83 and the second long via electrode 84.

FIG. 13 is a plan view showing a planar shape of the fuse resistance layer 162. FIG. Referring to FIG. 13, fuse resistance layer 162 extends in a belt shape along first direction X. The fuse resistance layer 162 includes a first end 162a on one side, a second end 162b on the other side, and a fusible portion 162c connecting the first end 162a and the second end 162b.
In this embodiment, the fuse resistance layer 162 has a first constricted portion 162d interposed between the first end 162a and the fusible portion 162c, and a second constricted portion 162d interposed between the second end 162b and the fusible portion 162c. Including the constriction 162e.

The first end 162a covers the first via electrode 23. More specifically, the first end 162a covers the first end 23a (first protrusion 23c) of the first via electrode 23. The first end 162a is formed in a film shape along the main surface and the side surface of the first via electrode 23.
The first end 162a is formed in a square shape in plan view. The planar shape of the first end 162a is arbitrary. The first end 162a may be formed in a polygonal shape other than a square shape, a circular shape, or an elliptical shape in plan view. The first end 162a has a first width W1 in a second direction Y orthogonal to the first direction X.

The second end 162b covers the second via electrode 24. More specifically, the second end 162b covers the first end 24a (the second protrusion 24c) of the second via electrode 24. The second end 162b is formed in a film shape along the main surface and side surfaces of the second via electrode 24.
The second end 162b is formed in a square shape in plan view. The planar shape of the second end 162b is arbitrary. The second end 162b may be formed in a polygonal shape other than a square shape, a circular shape, or an elliptical shape in plan view. The second end 162b has a second width W2 in the second direction Y.

The fusible portion 162c extends in a band between the first end 162a and the second end 162b. The fusible portion 162c extends in a band along a straight line connecting the first end 162a and the second end 162b. The fusible portion 162c has a third width W3 smaller than the first width W1 in the second direction Y. The third width W3 of the fusible portion 162c is smaller than the second width W2.
The first constricted portion 162d is formed in a tapered shape from the first end 162a toward the fusible portion 162c in plan view. The first constricted portion 162d narrows a current path from the first end 162a to the fusible portion 162c.

The second constricted portion 162e is formed in a tapered shape from the second end 162b toward the fusible portion 162c in plan view. The second constricted portion 162e narrows the current path from the second end 162b to the fusible portion 162c.
When a predetermined voltage is applied between the first end 162a and the second end 162b, the fusible portion 162c is blown off by Joule heat. As a result, the first end 162a and the second end 162b are electrically opened.

The fuse resistance layer 162 can take various forms. Hereinafter, another embodiment of the fuse resistance layer 162 will be described with reference to FIGS. 14A to 14C.
FIG. 14A is a plan view showing a fuse resistance layer 162 according to the second embodiment. Hereinafter, structures corresponding to the structures described in FIGS. 10 to 13 are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 14A, fuse resistance layer 162 according to the second embodiment is formed with a uniform width. More specifically, the fuse resistance layer 162 according to the second embodiment has a fusible portion having a third width W3 equal to the first width W1 of the first end 162a and the second width W2 of the second end 162b. 162c. The fuse resistance layer 162 according to the second embodiment does not include the first constricted portion 162d and the second constricted portion 162e.

FIG. 14B is a plan view showing the fuse resistance layer 162 according to the second embodiment. Hereinafter, structures corresponding to the structures described in FIGS. 10 to 13 are denoted by the same reference numerals, and description thereof is omitted.
Referring to FIG. 14B, the fuse resistance layer 162 according to the third embodiment includes a fusible portion 162c directly connected to the first end 162a and the second end 162b. That is, the fuse resistance layer 162 according to the third embodiment does not include the first constricted portion 162d and the second constricted portion 162e.

FIG. 14C is a plan view showing a fuse resistance layer 162 according to the fourth embodiment. Hereinafter, structures corresponding to the structures described in FIGS. 10 to 13 are denoted by the same reference numerals, and description thereof is omitted.
Referring to FIG. 14C, fuse resistance layer 162 according to the third embodiment includes a fusible portion 162c having a portion extending along first direction X and a portion extending along second direction Y in plan view. In this embodiment, the fusible portion 162c extends in a zigzag manner in plan view.

  Referring to FIGS. 10 to 12, the above-described protective layer 40 is interposed in a region between third insulating layer 15 and fourth insulating layer 16 and covers fuse resistance layer 162. The protection layer 40 is formed in a film shape along the fuse resistance layer 162. The protection layer 40 has a planar shape that matches the planar shape of the fuse resistance layer 162. The protection layer 40 has a side surface connected to the side surface of the fuse resistance layer 162. That is, the side surface of the protection layer 40 is formed flush with the side surface of the fuse resistance layer 162.

FIG. 15 is an example of a main circuit of the electronic component 161 shown in FIG.
The electronic component 161 includes a reference voltage electrode 171, a high voltage electrode 172, and a resistance parallel circuit 173 electrically connected between the reference voltage electrode 171 and the high voltage electrode 172. The resistance parallel circuit 173 includes a plurality of resistance circuits 174A, 174B, 174C, 174D, 174E connected in parallel with each other.

The number of resistance circuits 174A to 174E is arbitrary, and is adjusted according to the resistance value to be achieved. In this embodiment, the plurality of resistance circuits 174A to 174E include a first resistance circuit 174A, a second resistance circuit 174B, a third resistance circuit 174C, a fourth resistance circuit 174D, and a fifth resistance circuit 174E.
The first resistor circuit 174A includes a first resistor R1 serving as a reference resistor. Second resistance circuit 174B includes a series circuit having first fuse F1 and second resistance R2. Third resistor circuit 174C includes a series circuit having second fuse F2 and third resistor R3. Fourth resistor circuit 174D includes a series circuit having third fuse F3 and fourth resistor R4. Fifth resistor circuit 174E includes a series circuit having fourth fuse F4 and fifth resistor R5.

  At least one or all of the first to fifth resistors R1 to R5 may be formed by the resistance layer 10. At least one or all of the first to fifth resistors R1 to R5 may be formed by a resistive layer other than the resistive layer 10 (for example, a polysilicon resistive layer). The first to fifth resistors R1 to R5 may have different resistance values, or may have the same resistance values. The first to fourth fuses F1 to F4 are formed by the fuse resistance layers 162, respectively.

The electronic component 161 includes a first input electrode 175, a second input electrode 176, a third input electrode 177, and a fourth input electrode 178.
The first input electrode 175 is connected between the first fuse F1 and the second resistor R2 in the second resistor circuit 174B. The second input electrode 176 is connected between the second fuse F2 and the third resistor R3 in the third resistor circuit 174C. The third input electrode 177 is connected between the third fuse F3 and the fourth resistor R4 in the fourth resistor circuit 174D. The fourth input electrode 178 is connected between the fourth fuse F4 and the fifth resistor R5 in the fifth resistor circuit 174E.

When a predetermined voltage is applied between the reference voltage electrode 171 and the first input electrode 175, a current flows through the first fuse F1, and the first fuse F1 is blown. As a result, the second resistor R2 is electrically released from the reference voltage electrode 171 and the high voltage electrode 172.
When a predetermined voltage is applied between the reference voltage electrode 171 and the second input electrode 176, a current flows through the second fuse F2, and the second fuse F2 is blown. As a result, the third resistor R3 is electrically released from the reference voltage electrode 171 and the high voltage electrode 172.

When a predetermined voltage is applied between the reference voltage electrode 171 and the third input electrode 177, a current flows through the third fuse F3, and the third fuse F3 is blown. As a result, the fourth resistor R4 is electrically released from the reference voltage electrode 171 and the high voltage electrode 172.
When a predetermined voltage is applied between the reference voltage electrode 171 and the fourth input electrode 178, a current flows through the fourth fuse F4, and the fourth fuse F4 is blown. As a result, the fifth resistor R5 is electrically released from the reference voltage electrode 171 and the high voltage electrode 172.

The resistance value between the reference voltage electrode 171 and the high voltage electrode 172 is adjusted by cutting any one or all of the first to fourth fuses F1 to F4. When the adjustment of the resistance value is not required, the first to fourth fuses F1 to F4 are not cut.
The first to input electrodes 175 to 178 are not necessarily required. For example, the first to fourth fuses F1 to F4 may have different resistance values and may be formed to be cut at different current values (voltage values). In this case, the voltage value applied between the reference voltage electrode 171 and the high voltage electrode 172 is adjusted according to the number of the first to fourth fuses F1 to F4 to be cut.

The resistance value between the reference voltage electrode 171 and the high voltage electrode 172 is determined by the combined resistance of the first to fifth resistors R1 to R5 electrically connected to the reference voltage electrode 171 and the high voltage electrode 172. The resistance value between the reference voltage electrode 171 and the high voltage electrode 172 is digitally adjusted by the first to fourth fuses F1 to F4.
As described above, the electronic component 161 includes the fuse resistance layer 162 made of a metal thin film. The fuse resistance layer 162 is preferably made of a metal thin film containing at least one of CrSi (chromium silicon alloy), TaN (tantalum nitride), and TiN (titanium nitride).

  The fuse resistance layer 162 is melted by a predetermined voltage (current) and opens a current path. According to the fuse resistance layer 162 made of a metal thin film, it can be formed relatively thin as compared with polysilicon or the like. Thereby, surrounding damage due to fusing of the fuse resistance layer 162 can be suppressed. As a result, the fuse resistance layer 162 can be appropriately incorporated into the multilayer wiring structure 12 as a trimming device for adjusting the resistance value of the electronic circuit or a protection device for protecting the electronic circuit from overvoltage (overcurrent).

When the fuse resistance layer 162 is used for adjusting the resistance value, the step of cutting the fuse resistance layer 162 can be performed at the time of a wafer test or after the packaging step. In addition, since the resistance value can be adjusted without performing the laser irradiation method, the number of steps can be reduced.
In each of the above-described embodiments, an example has been described in which one or a plurality of resistance circuits 11 (the resistance layer 10 and the fuse resistance layer 162) are formed in the outer region 7. However, in each of the above-described embodiments, one or more resistance circuits 11 (the resistance layer 10 and the fuse resistance layer 162) may be formed in the device region 6.

In each of the above-described embodiments, one or a plurality of resistance circuits 11 (the resistance layer 10 and the fuse resistance layer 162) may be formed in the device region 6 and the outer region 7, respectively. Further, one or a plurality of resistance circuits 11 (the resistance layer 10 and the fuse resistance layer 162) may be formed only in the device region 6 instead of the outer region 7.
In each of the embodiments described above, the example in which the first upper wiring layer 61 and the second upper wiring layer 62 form the uppermost wiring layer of the multilayer wiring structure 12 has been described. However, the first upper wiring layer 61 and the second upper wiring layer 62 need not be the uppermost wiring layers of the multilayer wiring structure 12. In this case, an insulating layer having the same structure as the first to fourth insulating layers 13 to 16 and the first lower wiring layer 41 (second lower wiring layer 42) or the first upper wiring layer 61 (second upper wiring) A wiring layer having the same structure as that of the layer 62) is laminated on the fourth insulating layer 16 in an arbitrary mode and an arbitrary cycle.

  In each of the above-described embodiments, an example has been described in which the resistance layer 10 and / or the fuse resistance layer 162 occupy the main surface of the third insulating layer 15. However, in each of the above embodiments, a wiring layer having the same structure as the first lower wiring layer 41 (second lower wiring layer 42) and the first upper wiring layer 61 (second upper wiring layer 62) is used. It may be formed on the main surface of the third insulating layer 15. However, in such a structure, there is a concern that an increase in the number of manufacturing steps and difficulty in securing the flatness may occur. Therefore, a structure in which the resistance layer 10 and / or the fuse resistance layer 162 occupy the main surface of the third insulating layer 15 is considered. It is preferable.

The electronic component 1 according to the first embodiment, the electronic component 151 according to the second embodiment, and the electronic component 161 according to the third embodiment may have the electrical structure illustrated in FIG. FIG. 16 is a circuit diagram showing an electrical structure according to a first embodiment of the electronic components 1, 151, 161 according to the first to third embodiments.
Referring to FIG. 16, electronic components 1, 151, and 161 include operational amplifier circuit 201. The operational amplifier circuit 201 includes a positive power supply terminal 202, a negative power supply terminal 203, a non-inverted positive power supply terminal 204, an inverted positive power supply terminal 205, an output terminal 206, transistors TrA1 to TrA14 (semiconductor switching devices), and resistors RA1 to RA1. RA4 (passive device) is included.

  The power supply voltage VDD is input to the positive power supply terminal 202. The reference voltage VSS is input to the negative power supply terminal 203. The reference voltage VSS may be a ground voltage. The non-inverting positive power supply terminal 204 receives a non-inverting voltage VIN +. An inverted voltage VIN− is input to the inverted positive power supply terminal 205. The operational amplifier circuit 201 amplifies the difference voltage between the non-inverted voltage VIN + and the inverted voltage VIN−, and outputs the amplified voltage from the output terminal 206. That is, the operational amplifier circuit 201 is a differential operational amplifier circuit.

  The transistors TrA1 to TrA14 are respectively formed in the device region 6 in the semiconductor layer 2. That is, the functional device formed in the device region 6 includes a circuit network formed by the transistors TrA1 to TrA14. Each of the transistors TrA1 to TrA3 and TrA7 to TrA10 is formed of a p-type MISFET. The transistors TrA4 to TrA6 and TrA11 to TrA14 are each formed of an n-type MISFET.

  On the other hand, the resistors RA1 to RA4 are formed in the outer region 7 in the semiconductor layer 2. At least one or all of the resistors RA1 to RA4 are formed by the resistor layer 10 (CrSi). The resistances RA1 to RA4 are selectively connected to a circuit network formed by the transistors TrA1 to TrA14 via the connection circuit formation layer 21 (the connection wiring layer 96 and the connection via electrode 97). The resistances RA1 to RA4 may each have a resistance value adjusted by the fuse resistance layer 162. The resistors RA1 to RA4 form a current value setting resistor, and determine a current amplification factor.

  The bias voltage Vb1 is input to the gate of the transistor TrA1. The drain of the transistor TrA1 is connected to the positive power supply terminal 202. The source of the transistor TrA1 is connected to the source of the transistor TrA2 and the source of the transistor TrA3. The gate of the transistor TrA2 is connected to the non-inverting positive power supply terminal 204. The gate of the transistor TrA3 is connected to the inverted positive power supply terminal 205.

The bias voltage Vb2 is input to the gate of the transistor TrA4. The drain of the transistor TrA4 is connected to the source of the transistor TrA5 and the source of the transistor TrA6.
The source of the transistor TrA4 is connected to the negative power supply terminal 203. The gate of the transistor TrA5 is connected to the non-inverting positive power supply terminal 204. The gate of the transistor TrA6 is connected to the inverted positive power supply terminal 205.

The gate of the transistor TrA7 is connected to the gate of the transistor TrA8. The bias voltage Vb3 is input to the gate of the transistor TrA7 and the gate of the transistor TrA8. The source of the transistor TrA7 is connected to the positive power supply terminal 202 via the resistor RA1.
The drain of the transistor TrA7 is connected to the source of the transistor TrA9. The source of the transistor TrA8 is connected to the positive power supply terminal 202 via the resistor RA2. The drain of the transistor TrA8 is connected to the source of the transistor TrA10.

The gate of the transistor TrA9 is connected to the gate of the transistor TrA10. The bias voltage Vb4 is input to the gate of the transistor TrA9 and the gate of the transistor TrA10.
The drain of the transistor TrA9 is connected to the drain of the transistor TrA11. The drain of the transistor TrA10 is connected to the drain of the transistor TrA12.

The drain of the transistor TrA6 is connected to the connection between the drain of the transistor TrA7 and the source of the transistor TrA9. The drain of the transistor TrA5 is connected to a connection between the drain of the transistor TrA8 and the source of the transistor TrA10.
The gate of the transistor TrA11 is connected to the gate of the transistor TrA12. The bias voltage Vb5 is input to the gate of the transistor TrA11 and the gate of the transistor TrA12.

The source of the transistor TrA11 is connected to the drain of the transistor TrA13. The source of the transistor TrA12 is connected to the drain of the transistor TrA14.
The gate of the transistor TrA13 is connected to the gate of the transistor TrA14. The gate of the transistor TrA13 and the gate of the transistor TrA14 are connected to the drain of the transistor TrA11.

The source of the transistor TrA13 is connected to the negative power supply terminal 203 via the resistor RA3. The source of the transistor TrA14 is connected to the negative power supply terminal 203 via the resistor RA4.
In this embodiment, the example in which the operational amplifier circuit 201 includes the transistors TrA1 to TrA6 has been described. However, the operational amplifier circuit 201 without the transistors TrA1 to TrA3 may be employed, or the operational amplifier circuit 201 without the transistors TrA4 to TrA6 may be employed.

The electronic component 1 according to the first embodiment, the electronic component 151 according to the second embodiment, and the electronic component 161 according to the third embodiment may have the electrical structure illustrated in FIG. FIG. 17 is a circuit diagram showing an electrical structure according to a second embodiment of the electronic components 1, 151, 161 according to the first to third embodiments.
Referring to FIG. 17, electronic components 1, 151, 161 include a current amplification type constant current regulator 211. The constant current regulator 211 includes a positive power supply terminal 212, a negative power supply terminal 213, an output terminal 214, transistors TrB1 to TrB12 (semiconductor switching device), resistors RB1 to RB3 (passive device), and a capacitor C (passive device).

The power supply voltage VDD is input to the positive power supply terminal 212. The reference voltage VSS is input to the negative power supply terminal 213. The reference voltage VSS may be a ground voltage. The constant current regulator 211 outputs a constant current from the output terminal 214 according to the potential difference between the power supply voltage VDD and the reference voltage VSS.
The transistors TrB1 to TrB12, the resistors RB1 and RB3, and the capacitor C are respectively formed in the device region 6 in the semiconductor layer 2. That is, the functional device formed in the device region 6 includes a circuit network formed by the transistors TrB1 to TrB12, the resistors RB1 and RB3, and the capacitor C.

Each of the transistors TrB1 to TrB4 and TrB7 is formed of an n-type MISFET. Each of the transistors TrB5 and TrB6 is formed of an npn-type BJT. Each of the transistors TrB8 to TrB12 is formed of a p-type MISFET. Each of the resistors RB1 and RB3 may be formed by a polysilicon resistor.
The resistance RB2 is formed in the outer region 7 in the semiconductor layer 2. The resistance RB2 is formed by the resistance layer 10 (CrSi). The resistance RB2 may have a resistance value adjusted by the fuse resistance layer 162. The resistor RB2 forms a current value setting resistor and determines a current amplification factor. The resistor RB2 is selectively connected to a circuit network formed by the transistors TrB1 to TrB12, the resistors RB1, RB3, and the capacitor C via the connection circuit formation layer 21 (the connection wiring layer 96 and the connection via electrode 97).

The gate of the transistor TrB1 is connected to the gate of the transistor TrB2. The gate of the transistor TrB1 and the gate of the transistor TrB2 are connected to the drain of the transistor TrB1.
The drain of the transistor TrB1 is connected to the positive power supply terminal 212 via the resistor RB1. The source of the transistor TrB1 is connected to the negative power supply terminal 213. The source of the transistor TrB2 is connected to the source of the transistor TrB1.

The gate of the transistor TrB3 is connected to the gate of the transistor TrB4. The gate of the transistor TrB3 and the gate of the transistor TrB4 are connected to the drain of the transistor TrB3.
The source of the transistor TrB3 is connected to the negative power supply terminal 213. The drain of the transistor TrB2 is connected to the gate of the transistor TrB1 and the gate of the transistor TrB2. The source of the transistor TrB4 is connected to the negative power supply terminal 213.

  The base of the transistor TrB5 is connected to the base of the transistor TrB6. The base of the transistor TrB5 and the base of the transistor TrB6 are connected to the collector of the transistor TrB5. The emitter of the transistor TrB5 is connected to the negative power supply terminal 213 via the resistor RB2. The emitter of the transistor TrB6 is connected to the negative power supply terminal 213.

The gate of the transistor TrB7 is connected to the collector of the transistor TrB6. The drain of the transistor TrB7 is connected to the drain of the transistor TrB2. The source of the transistor TrB7 is connected to the negative power supply terminal 213.
The resistor RB3 and the capacitor C form an RC series circuit 215. The RC series circuit 215 is connected between the gate of the transistor TrB7 and the negative power supply terminal 213.

The gates of the transistors TrB8 to TrB12 are connected to each other. The gates of the transistors TrB8 to TrB12 are respectively connected to the gate of the transistor TrB7. The drains of the transistors TrB8 to TrB12 are connected to the positive power supply terminal 212, respectively.
The source of the transistor TrB8 is connected to the drain of the transistor TrB3. The source of the transistor TrB9 is connected to the collector of the transistor TrB5. The source of the transistor TrB10 is connected to the collector of the transistor TrB6.

The source of the transistor TrB11 is connected to the gates of the transistors TrB8, TrB9, TrB10, TrB12 and the drain of the transistor TrB7. The source of the transistor TrB12 is connected to the output terminal 214.
Although the embodiments of the present invention have been described, the embodiments of the present invention can be embodied in other forms.

In each of the above-described embodiments, an example in which one or a plurality of resistance circuits 11 (resistance layers 10) are formed in the outer region 7 has been described. However, in each of the above embodiments, one or a plurality of resistance circuits 11 (resistance layers 10) may be formed in the device region 6.
In each of the above embodiments, one or more resistance circuits 11 (resistance layers 10) may be formed in the device region 6 and the outer region 7, respectively. Further, one or a plurality of resistance circuits 11 (resistance layers 10) may be formed only in the device region 6 instead of the outer region 7.

Hereinafter, examples of features extracted from the specification and the drawings will be described.
[Item 1] A semiconductor layer having a main surface including a device region in which a functional device is formed and an outer region outside the device region, and a plurality of insulating layers stacked on the main surface of the semiconductor layer. A connection circuit having a multilayer wiring structure, the wiring circuit being selectively formed in a plurality of the insulating layers so as to be routed from the device region to the outer region, and including a wiring layer electrically connected to the functional device Formation layer and selectively in the plurality of insulating layers different from the connection circuit formation layer in the outer region so as to be electrically connected to the functional device via the wiring layer of the connection circuit formation layer. And a multilayer wiring structure having a resistance circuit forming layer including a resistance layer made of a metal thin film.

  According to this electronic component, the resistance layer is made of a metal thin film. According to the metal thin film, the planar area of the resistance layer can be reduced while reducing the thickness of the resistance layer. Thus, the resistance layer can be appropriately interposed in the multilayer wiring structure while ensuring flatness. Particularly, in this electronic component, the resistance layer is formed in the outer region. Thus, the electrical effect of the resistance layer on the device region can be suppressed, and the electrical effect of the device region on the resistance layer can be suppressed. Therefore, the resistance layer can be appropriately incorporated into the multilayer wiring structure.

[Item 2] The electronic component according to item 1, wherein the functional device includes at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device.
[Item 3] The electronic component according to item 1, wherein the functional device includes a network in which any two or more devices selected from a passive device, a semiconductor rectifier device, and a semiconductor switching device are selectively combined.

[Item 4] The electronic component according to item 2 or 3, wherein the passive device includes at least one of a resistor, a capacitor, and a coil.
[Item 5] The electronic component according to item 2 or 3, wherein the semiconductor rectifying device includes at least one of a pn junction diode, a zener diode, a Schottky barrier diode, and a fast recovery diode.

[Item 6] The semiconductor switching device is at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). 4. The electronic component according to item 2 or 3, comprising:
[Item 7] The electronic component according to item 1, including an amplifier circuit formed by the functional device and the resistance layer.

[Item 8] The electronic component according to item 1, including a differential operational amplifier circuit formed by the functional device and the resistance layer.
[Item 9] The electronic component according to item 1, including a constant current regulator circuit formed by the functional device and the resistance layer.
[Item 10] The electronic component according to any one of Items 1 to 9, wherein the resistance layer is made of a metal thin film containing at least one of CrSi, TaN, and TiN.

  In addition, various design changes can be made within the scope of the matters described in the claims.

REFERENCE SIGNS LIST 1 electronic component 2 semiconductor layer 6 device region 7 outer region 10 resistive layer 15 third insulating layer 16 fourth insulating layer 23 first via electrode 23c first protrusion of first via electrode 24 second via electrode 24c second via electrode 2nd projecting part 41 1st lower wiring layer 42 2nd lower wiring layer 61 1st upper wiring layer 62 2nd upper wiring layer 83 1st long via electrode 83c 1st long via electrode Lower part 83d 1st long via electrode Upper portion 84 of the second long via electrode 84c Lower portion 84d of the second long via electrode Upper portion 101 of the second long via electrode 101 Uppermost insulating layer 102 First pad opening 103 Second pad opening 161 Electronic component 162 Fuse resistance layer TL1 First wiring Thickness TL2 Second wiring thickness

Claims (28)

A lower insulating layer,
An upper insulating layer formed on the lower insulating layer,
A first via electrode embedded in the lower insulating layer;
A second via electrode separated from the first via electrode and embedded in the lower insulating layer;
A resistive layer comprising a metal thin film, interposed in a region between the lower insulating layer and the upper insulating layer, and electrically connected to the first via electrode and the second via electrode. . A first lower wiring layer formed in a region on the lower insulating layer side with respect to the resistance layer and electrically connected to the first via electrode;
2. The electronic component according to claim 1, further comprising: a second lower wiring layer formed in a region on the lower insulating layer side with respect to the resistance layer, and electrically connected to the second via electrode. 3. .   The electronic component according to claim 2, wherein the resistance layer is connected in series to the first lower wiring layer and the second lower wiring layer. A first upper wiring layer formed on the upper insulating layer and electrically connected to the first lower wiring layer;
4. The electronic component according to claim 2, further comprising: a second upper wiring layer formed on the upper insulating layer and electrically connected to the second lower wiring layer. 5.   The electronic component according to claim 4, wherein the resistance layer is connected in series to the first upper wiring layer and the second upper wiring layer. The first upper wiring layer is separated from the resistance layer in plan view,
The electronic component according to claim 4, wherein the second upper wiring layer is separated from the resistance layer in a plan view. The first upper wiring layer forms an uppermost wiring layer;
The electronic component according to claim 4, wherein the second upper wiring layer forms an uppermost wiring layer.   The electronic component according to claim 4, wherein the first upper wiring layer has a thickness equal to or greater than a thickness of the first lower wiring layer.   The electronic component according to claim 4, wherein the second upper wiring layer has a thickness equal to or greater than a thickness of the second lower wiring layer. A first long via electrode buried through the lower insulating layer and the upper insulating layer and electrically connected to the first lower wiring layer and the first upper wiring layer;
A second long via electrode buried through the lower insulating layer and the upper insulating layer and electrically connected to the second lower wiring layer and the second upper wiring layer, further comprising: The electronic component according to any one of claims 4 to 9.   The electronic component according to claim 10, wherein the resistance layer is located on a straight line connecting the first long via electrode and the second long via electrode in a plan view.   A first lower via portion located on the first lower wiring layer side with respect to the resistance layer, and a first lower via portion located on the first upper wiring layer side with respect to the resistance layer; The electronic component according to claim 10, further comprising a first upper portion having a length equal to or longer than a length of the first lower portion.   A second lower via electrode located on the second lower wiring layer side with respect to the resistance layer, and a second lower via electrode located on the second upper wiring layer side with respect to the resistance layer; The electronic component according to claim 10, further comprising a second upper portion having a length equal to or longer than a length of the second lower portion.   An insulating layer that covers the first upper wiring layer and the second upper wiring layer and has a first pad opening that exposes the first upper wiring layer and a second pad opening that exposes the second upper wiring layer; The electronic component according to any one of claims 10 to 13, comprising:   The electronic component according to claim 14, wherein the insulating layer covers a connection portion between the first upper wiring layer and the first long via electrode in a plan view.   The electronic component according to claim 14, wherein the insulating layer covers a connection portion between the second upper wiring layer and the second long via electrode in a plan view. The first via electrode has a first protrusion protruding toward the upper insulating layer with respect to a main surface of the lower insulating layer,
The electronic component according to claim 1, wherein the resistance layer covers the first protrusion of the first via electrode. The second via electrode has a second protrusion protruding toward the upper insulating layer with respect to a main surface of the lower insulating layer,
The electronic component according to claim 1, wherein the resistance layer covers the second protrusion of the second via electrode. A semiconductor layer having a main surface;
The electronic component according to claim 1, wherein the lower insulating layer is formed on a main surface of the semiconductor layer. The semiconductor layer includes a device region in which a functional device is formed and an outer region outside the device region,
The electronic component according to claim 19, wherein the resistance layer is formed in the outer region in a plan view.   The electronic component according to claim 1, wherein the resistance layer is formed of a metal thin film including at least one of CrSi, TaN, and TiN. A lower insulating layer,
An upper insulating layer formed on the lower insulating layer,
A first via electrode embedded in the lower insulating layer;
A second via electrode separated from the first via electrode and embedded in the lower insulating layer;
A first upper wiring layer formed on the upper insulating layer;
A second upper wiring layer formed on the upper insulating layer apart from the first upper wiring layer;
A metal thin film, interposed in a region between the lower insulating layer and the upper insulating layer so as to be located in a region between the first upper wiring layer and the second upper wiring layer in plan view; An electronic component, comprising: a first via electrode and a resistance layer electrically connected to the second via electrode. A first long via electrode buried through the lower insulating layer and the upper insulating layer so as to cross the side of the resistance layer, and electrically connected to the first upper wiring layer;
A second long via electrode buried through the lower insulating layer and the upper insulating layer so as to cross the side of the resistance layer, and electrically connected to the second upper wiring layer. The electronic component according to claim 22.   24. The electronic component according to claim 23, wherein the resistance layer is located on a straight line connecting the first long via electrode and the second long via electrode in plan view.   25. The electronic component according to claim 23, wherein the first long via electrode is located on a straight line connecting the first via electrode and the second via electrode in a plan view.   The electronic component according to any one of claims 23 to 25, wherein the second long via electrode is located on a straight line connecting the first via electrode and the second via electrode in a plan view.   The electronic component according to any one of claims 22 to 26, wherein the resistance layer is electrically connected to the first upper wiring layer and the second upper wiring layer.   The electronic component according to any one of claims 23 to 27, wherein the resistance layer is made of a metal thin film containing at least one of CrSi, TaN, and TiN.

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