JP7440212B2 - Thin film resistor and its manufacturing method, as well as electronic components equipped with thin film resistor - Google Patents

Description

The present invention relates to a thin film resistor, a method for manufacturing the same, and an electronic component including the thin film resistor.

Patent Document 1 discloses an electronic component including a thin film resistor made of chromium silicide. The resistance value of the thin film resistor is adjusted in an increasing direction by trimming using laser light.

Japanese Patent Application Publication No. 2005-235995

One embodiment of the present invention provides a thin film resistor that includes a resistive layer containing chromium silicide and has a resistance value less than the resistance value of the resistive layer, a method for manufacturing the same, and an electronic device equipped with such a thin film resistor. Provide parts.

One embodiment of the present invention provides a thin film resistor that includes a resistive layer comprising chromium silicide and a chromium agglomerate formed in the resistive layer.
According to this thin film resistor, chromium aggregates having a resistivity lower than that of chromium silicide are formed in the resistance layer. Thereby, it is possible to provide a thin film resistor that includes a resistance layer containing chromium silicide and has a resistance value lower than the resistance value of the resistance layer.

One embodiment of the present invention includes the step of preparing a resistive layer containing chromium silicide, irradiating the resistive layer with a laser beam, and aggregating chromium in the portion of the resistive layer irradiated with the laser beam. and forming a chromium aggregate consisting of an agglomerate of chromium in the resistance layer.
According to this method for manufacturing a thin film resistor, chromium aggregates having a resistivity lower than that of chromium silicide are formed in the resistance layer. Thereby, it is possible to manufacture and provide a thin film resistor that is provided with a resistance layer containing chromium silicide but has a resistance value that is less than the resistance value of the resistance layer.

One embodiment of the present invention includes a support substrate having a main surface, a resistance layer containing chromium silicide, and a chromium agglomerate, and includes a chromium agglomerate formed in the resistance layer, and a support substrate having a main surface. A thin film resistor formed thereon.
According to this electronic component, chromium aggregates having a resistivity lower than the resistivity of chromium silicide are formed in the resistance layer. Thereby, it is possible to provide an electronic component that includes a resistive layer containing chromium silicide, but also includes a thin film resistor having a resistance value lower than the resistance value of the resistive layer.

One embodiment of the present invention includes an insulating laminated structure in which a plurality of insulating layers are laminated, a resistance layer containing chromium silicide, and a chromium agglomerate, and the resistance layer includes a chromium agglomerate. , and a thin film resistor formed within the insulating layered structure.
According to this electronic component, chromium aggregates having a resistivity lower than the resistivity of chromium silicide are formed in the resistance layer. Thereby, it is possible to provide an electronic component that includes a resistive layer containing chromium silicide, but also includes a thin film resistor having a resistance value lower than the resistance value of the resistive layer.

FIG. 1 is a schematic plan view showing an electronic component according to a first embodiment of the present invention, in which a thin film resistor according to the first embodiment is incorporated. FIG. 2 is a sectional view taken along the line II-II shown in FIG. FIG. 3 is an enlarged view of region III shown in FIG. 2. FIG. 4 is an enlarged view of region IV shown in FIG. 2. FIG. 5 is a plan view showing a thin film resistor. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. FIG. 7 is a schematic cross-sectional view showing an enlarged region in which chromium aggregates are formed. FIG. 8 is a schematic cross-sectional view showing an enlarged area in which trimming marks are formed. FIG. 9A is a plan view showing a thin film resistor according to a second embodiment. FIG. 9B is a plan view showing a thin film resistor according to the third embodiment. FIG. 9C is a plan view showing a thin film resistor according to a fourth embodiment. FIG. 9D is a plan view showing a thin film resistor according to the fifth embodiment. FIG. 9E is a plan view showing a thin film resistor according to the sixth embodiment. FIG. 9F is a plan view showing a thin film resistor according to the seventh embodiment. FIG. 10A is a cross-sectional view of a portion corresponding to FIG. 2, and is a cross-sectional view for explaining an example of a method for manufacturing the electronic component shown in FIG. FIG. 10B is a cross-sectional view for explaining the process after FIG. 10A. FIG. 10C is a cross-sectional view for explaining the process after FIG. 10B. FIG. 10D is a cross-sectional view for explaining the process after FIG. 10C. FIG. 10E is a cross-sectional view for explaining the process after FIG. 10D. FIG. 10F is a cross-sectional view for explaining the process after FIG. 10E. FIG. 10G is a cross-sectional view for explaining the process after FIG. 10F. FIG. 10H is a cross-sectional view for explaining the process after FIG. 10G. FIG. 10I is a cross-sectional view for explaining the process after FIG. 10H. FIG. 10J is a cross-sectional view for explaining the process after FIG. 10I. FIG. 10K is a cross-sectional view for explaining the process after FIG. 10J. FIG. 10L is a cross-sectional view for explaining the process after FIG. 10K. FIG. 10M is a cross-sectional view for explaining the process after FIG. 10L. FIG. 10N is a cross-sectional view for explaining the process after FIG. 10M. FIG. 10O is a cross-sectional view for explaining the process after FIG. 10N. FIG. 10P is a cross-sectional view for explaining the process after FIG. 10O. FIG. 10Q is a cross-sectional view for explaining the process after FIG. 10P. FIG. 10R is a cross-sectional view for explaining the process after FIG. 10Q. FIG. 10S is a cross-sectional view for explaining the process after FIG. 10R. FIG. 10T is a cross-sectional view for explaining the process after FIG. 10S. FIG. 10U is a cross-sectional view for explaining the process after FIG. 10T. FIG. 11 is a schematic plan view showing an electronic component according to the second embodiment of the present invention, in which the thin film resistor according to the first embodiment is incorporated. FIG. 12 is a circuit diagram showing an electrical structure according to a first example of the electronic component according to the first embodiment and the electronic component according to the second embodiment. FIG. 13 is a circuit diagram showing an electrical structure according to a first example of the electronic component according to the first embodiment and the electronic component according to the second embodiment.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a schematic plan view showing an electronic component 1 according to a first embodiment of the present invention, in which a thin film resistor 35 according to the first embodiment is incorporated.
The electronic component 1 is a semiconductor device including various functional devices formed using a conductive material, a semiconductor material, or the properties of a semiconductor material. Electronic component 1 includes semiconductor layer 2 as an example of a support substrate.

The semiconductor layer 2 is formed into a rectangular parallelepiped shape. The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 is a device forming surface. The first main surface 3 and the second main surface 4 are formed into a quadrangular shape (in this form, a square shape) in a planar view (hereinafter simply referred to as "planar view") seen from the normal direction thereof.

The semiconductor layer 2 may be a Si semiconductor layer containing Si (silicon). The Si semiconductor layer may have a stacked structure including a Si semiconductor substrate and a Si epitaxial layer. The Si semiconductor layer may have a single layer structure made of a Si semiconductor substrate.
The semiconductor layer 2 may be a SiC semiconductor layer containing SiC (silicon carbide). The SiC semiconductor layer may have a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer. The SiC semiconductor layer may have a single layer structure made of a SiC semiconductor substrate.

The semiconductor layer 2 may be a compound semiconductor layer containing a compound semiconductor material. The compound semiconductor layer may have a stacked structure including a compound semiconductor substrate and a compound semiconductor epitaxial layer. The compound semiconductor layer may have a single layer structure made of a compound semiconductor substrate.
The compound semiconductor material may be a III-V compound semiconductor material. The semiconductor layer 2 contains at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide), which are examples of III-V compound semiconductor materials. Good too.

Semiconductor layer 2 includes a device region 6 and an outer region 7 . The device area 6 is an area where functional devices are formed. The device region 6 is spaced apart from the side surfaces 5A to 5D of the semiconductor layer 2 in the inner region. In this embodiment, the device region 6 is formed into an L-shape in plan view. The planar shape of the device region 6 is arbitrary and is not limited to the planar shape shown in FIG.

The functional device is formed using the first main surface 3 and/or the surface layer portion of the first main surface 3. The functional device may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. Passive devices may include semiconductor passive devices.
The passive device (semiconductor passive device) may include at least one of a resistor, a capacitor, and a coil. The semiconductor rectifier device may include at least one of a pn junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode.

The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). good.
The functional device may include a circuitry in which at least two of a passive device (semiconductor passive device), a semiconductor rectifying device, and a semiconductor switching device are combined. The circuitry may form part or all of an integrated circuit. The integrated circuit may include SSI (Small Scale Integration), LSI (Large Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), or ULSI (Ultra-Very Large Scale Integration).

The outer area 7 is an area outside the device area 6. The outer region 7 does not contain any functional devices. In this embodiment, the outer region 7 is divided into a region between the side surfaces 5A to 5D and the device region 6. In this form, the outer region 7 is formed into a rectangular shape in plan view. The arrangement and planar shape of the outer region 7 are arbitrary and are not limited to the arrangement and planar shape shown in FIG. The outer region 7 may be formed at the center of the first main surface 3 in plan view.

Electronic component 1 includes a resistance circuit 10. In this embodiment, an example in which one resistance circuit 10 is formed will be described, but a plurality of (two or more) resistance circuits 10 may be formed. Resistance circuit 10 is electrically connected to the functional device.
A resistor circuit 10 is formed in the outer region 7. Thereby, the electrical influence that the resistance circuit 10 has on the device region 6 can be suppressed, and the electrical influence that the device region 6 has on the resistance circuit 10 can be suppressed. As an example, parasitic capacitance between device region 6 and resistance circuit 10 can be suppressed. In other words, it is possible to reduce noise and improve the Q value.

The structure of the resistance circuit 10 will be specifically explained below. FIG. 2 is a sectional view taken along the line II-II shown in FIG. FIG. 2 is a sectional view taken along the line II-II shown in FIG. FIG. 3 is an enlarged view of region III shown in FIG. 2. FIG. 4 is an enlarged view of region IV shown in FIG. 2.
Referring to FIGS. 2 to 4, electronic component 1 includes an insulating stacked structure 12 formed on first main surface 3 of semiconductor layer 2 in device region 6 and outer region 7. Referring to FIGS. The insulating laminated structure 12 has a laminated structure in which a plurality of (four layers in this embodiment) insulating layers are laminated. The number of laminated insulating layers is arbitrary and is not limited to the number of laminated layers shown in FIG. 2. The insulating layered structure 12 may include less than four insulating layers, or may include five or more insulating layers.

In this embodiment, the insulating layered structure 12 includes a first insulating layer 13, a second insulating layer 14, a third insulating layer 15, and a fourth insulating layer 16, which are stacked in this order from the first main surface 3 side of the semiconductor layer 2. include. The terms “first,” “second,” “third,” and “fourth” regarding the first to fourth insulating layers 13 to 16 are used to identify the insulating layers in the drawings. , not intended to be permuted.
The first to fourth insulating layers 13 to 16 each have an insulating main surface. The main insulating surfaces of the first to fourth insulating layers 13 to 16 are each formed flat. The main insulating surfaces of the first to fourth insulating layers 13 to 16 extend parallel to the first main surface 3, respectively. The main insulating surfaces of the first to fourth insulating layers 13 to 16 may each be a ground surface. The main insulating surfaces of the first to fourth insulating layers 13 to 16 may each have grinding marks.

The first to fourth insulating layers 13 to 16 may each have a laminated structure including a silicon oxide layer and a silicon nitride layer. In this case, a silicon nitride layer may be formed on the silicon oxide layer, or a silicon oxide layer may be formed on the silicon nitride layer.
The first to fourth insulating layers 13 to 16 may each have a single-layer structure made of a silicon oxide layer or a silicon nitride layer. The first to fourth insulating layers 13 to 16 may be formed of the same type of insulating material, or may be formed of different insulating materials. The first to fourth insulating layers 13 to 16 are preferably formed of the same type of insulating material. In this embodiment, the first to fourth insulating layers 13 to 16 each have a single-layer structure made of a silicon oxide layer.

The thickness TI of the first to fourth insulating layers 13 to 16 may be 100 nm or more and 3500 nm or less, respectively. The thickness TI may be from 100 nm to 500 nm, from 500 nm to 1000 nm, from 1000 nm to 1500 nm, from 1500 nm to 2000 nm, from 2000 nm to 2500 nm, from 2500 nm to 3000 nm, or from 3000 nm to 3500 nm. The thickness TI is preferably 100 nm or more and 1500 nm or less, respectively. The thicknesses TI of the first to fourth insulating layers 13 to 16 may be equal to each other or may be different from each other.

The insulating layered structure 12 includes a plurality of wirings formed in first to fourth insulating layers 13 to 16. More specifically, the insulating laminated structure 12 includes a wiring circuit formation layer 21 and a resistance circuit formation layer 22.
The wiring circuit formation layer 21 includes a first insulating layer 13 and a second insulating layer 14. Further, the wired circuit forming layer 21 includes a wired circuit formed in the first insulating layer 13 and the second insulating layer 14. The wiring circuit of the wiring circuit forming layer 21 is routed from the device region 6 to the outer region 7. The specific structure of the wiring circuit forming layer 21 will be described later.

The resistance circuit formation layer 22 is formed on the wiring circuit formation layer 21. The resistance circuit formation layer 22 includes a third insulating layer 15 and a fourth insulating layer 16. Further, the resistance circuit forming layer 22 includes the resistance circuit 10 formed in the third insulating layer 15 and the fourth insulating layer 16. The resistance circuit 10 is electrically connected to the device region 6 (functional device) via the wiring circuit of the wiring circuit formation layer 21.

Referring to FIGS. 1 to 3, resistance circuit 10 includes a first via electrode 23 and a second via electrode 24. The first via electrode 23 is embedded in the third insulating layer 15 and exposed from the main insulating surface of the third insulating layer 15 . The second via electrode 24 is embedded in the third insulating layer 15 at a distance from the first via electrode 23 and is exposed from the main insulating surface of the third insulating layer 15 .
In this form, the first via electrode 23 is formed into a circular shape in plan view. The planar shape of the first via electrode 23 is arbitrary. The first via electrode 23 may be formed in a polygonal shape such as a triangular, quadrangular or hexagonal shape, or an elliptical shape in a plan view.

The first via electrode 23 includes a first end 23 a on one side and a second end 23 b on the other side with respect to the normal direction of the main insulating surface of the third insulating layer 15 . The first end portion 23a is exposed from the main insulating surface of the third insulating layer 15. The second end portion 23b is located within the third insulating layer 15. The first via electrode 23 is formed in a tapered shape whose width narrows from the first end 23a toward the second end 23b when viewed in cross section.

In this embodiment, the first end portion 23 a includes a first protrusion 23 c that protrudes from the main insulating surface of the third insulating layer 15 toward the fourth insulating layer 16 . The first protrusion 23c is formed by the main surface and side surfaces of the first via electrode 23.
The first via electrode 23 has a laminated structure including a main body layer 25 and a barrier layer 26. The main body layer 25 is embedded in the third insulating layer 15 . The main body layer 25 may contain tungsten (W) or copper (Cu). In this form, the main body layer 25 has a single layer structure consisting of a tungsten layer 27.

Barrier layer 26 is interposed between third insulating layer 15 and main body layer 25 . In this form, the barrier layer 26 has a laminated structure in which a plurality of electrode layers are laminated. In this form, the barrier layer 26 includes a Ti layer 28 and a TiN layer 29 formed in this order from the third insulating layer 15. The Ti layer 28 is in contact with the third insulating layer 15. The TiN layer 29 is in contact with the main body layer 25. The barrier layer 26 may have a single layer structure consisting of a Ti layer 28 or a TiN layer 29.

In this form, the second via electrode 24 is formed into a circular shape in plan view. The planar shape of the second via electrode 24 is arbitrary. The second via electrode 24 may be formed in a polygonal shape such as a triangular, quadrangular, or hexagonal shape, or an elliptical shape in a plan view.
The second via electrode 24 includes a first end 24 a on one side and a second end 24 b on the other side with respect to the normal direction of the main insulating surface of the third insulating layer 15 . The first end portion 24a is exposed from the main insulating surface of the third insulating layer 15. The second end portion 24b is located within the third insulating layer 15. The second via electrode 24 is formed in a tapered shape whose width narrows from the first end 24a toward the second end 24b when viewed in cross section.

In this embodiment, the first end portion 24 a includes a second protrusion 24 c that protrudes from the main insulating surface of the third insulating layer 15 toward the fourth insulating layer 16 . The second protrusion 24c is formed by the main surface and side surfaces of the second via electrode 24.
The second via electrode 24 has a laminated structure including a main body layer 30 and a barrier layer 31. The main body layer 30 is embedded in the third insulating layer 15 . Body layer 30 may include tungsten (W) or copper (Cu). In this form, the main body layer 30 has a single layer structure consisting of a tungsten layer 32.

Barrier layer 31 is interposed between third insulating layer 15 and main body layer 30 . In this form, the barrier layer 31 has a laminated structure in which a plurality of electrode layers are laminated. In this form, the barrier layer 31 includes a Ti layer 33 and a TiN layer 34 formed in this order from the third insulating layer 15. The Ti layer 33 is in contact with the third insulating layer 15. The TiN layer 34 is in contact with the main body layer 30. The barrier layer 31 may have a single layer structure consisting of a Ti layer 33 or a TiN layer 34.

Referring to FIGS. 2-4, resistance circuit 10 includes a thin film resistor 35 formed within insulating laminate structure 12. Referring to FIGS. The thin film resistor 35 is formed in the resistance circuit formation layer 22. That is, the thin film resistor 35 is formed on the first main surface 3. More specifically, the thin film resistors 35 are formed at intervals from the first main surface 3 in the stacking direction of the insulating stacked structure 12.
A thin film resistor 35 is formed in the outer region 7. Thereby, the electrical influence that the thin film resistor 35 has on the device region 6 can be suppressed, and the electrical influence that the device region 6 has on the thin film resistor 35 can be suppressed. As an example, parasitic capacitance between device region 6 and thin film resistor 35 can be suppressed. In other words, it is possible to reduce noise and improve the Q value.

More specifically, the thin film resistor 35 is interposed in a region between the third insulating layer 15 and the fourth insulating layer 16. The thin film resistor 35 is formed in the form of a film on the main insulating surface of the third insulating layer 15 . The thin film resistor 35 occupies the main insulating surface of the third insulating layer 15. On the main insulating surface of the third insulating layer 15, no film or layered wiring other than the thin film resistor 35 is formed in the device region 6 and the outer region 7. The third insulating layer 15 is provided to form a thin film resistor 35.

FIG. 5 is a plan view showing the thin film resistor 35. As shown in FIG. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. FIG. 7 is a schematic cross-sectional view showing an enlarged region in which the chromium aggregates 37 are formed. FIG. 8 is a schematic cross-sectional view showing an enlarged region in which the trimming marks 38 are formed.
Referring to FIGS. 5 and 6, thin film resistor 35 is formed so as to straddle first via electrode 23 and second via electrode 24. As shown in FIG. Thereby, the thin film resistor 35 is electrically connected to the first via electrode 23 and the second via electrode 24. In this embodiment, the thin film resistor 35 is formed into a square shape (more specifically, a rectangular shape) in plan view. The planar shape of the thin film resistor 35 is arbitrary and is not limited to a rectangular shape.

The thin film resistor 35 includes a first end 35a on one side, a second end 35b on the other side, and a connecting portion 35c connecting the first end 35a and the second end 35b. The first end portion 35a covers the first via electrode 23. More specifically, the first end 35a covers the first end 23a (first protrusion 23c) of the first via electrode 23. The first end portion 35a is formed in a film shape along the main surface and side surfaces of the first via electrode 23.

The second end portion 35b covers the second via electrode 24. More specifically, the second end 35b covers the first end 24a (second protrusion 24c) of the second via electrode 24. The second end portion 35b is formed in a film shape along the main surface and side surfaces of the second via electrode 24.
The connecting portion 35c extends in a band shape in a region between the first end 35a and the second end 35b. In this embodiment, the connecting portion 35c extends in a belt shape along a straight line connecting the first end 35a and the second end 35b. In this embodiment, the first end 35a, the second end 35b, and the connecting portion 35c are formed with a uniform width.

The thin film resistor 35 includes a resistance layer 36 containing chromium silicide, and a chromium agglomerate 37 formed in the resistance layer 36 . Resistive layer 36, in this form, includes crystallized chromium silicide. The resistance layer 36 is a so-called metal silicide thin film resistance. According to the resistance layer 36 made of a metal silicide thin film resistor, unlike conductive polysilicon or the like, the film thickness and the planar area can be appropriately reduced.

Thereby, the resistance layer 36 can be appropriately interposed in the region between the third insulating layer 15 and the fourth insulating layer 16 while ensuring flatness. Furthermore, since the planar area of the resistance layer 36 can be appropriately reduced, design rules can be relaxed. Thereby, the resistance layer 36 can be appropriately arranged in the outer region 7. Therefore, electrical influence between the resistance layer 36 and the device region 6 can be appropriately suppressed.

The resistance layer 36 may contain at least one of CrSi, CrSi ₂ , CrSiN, and CrSiO as an example of chromium silicide. CrSiN is also a chromium nitride. CrSiO is also a chromium oxide. In this form, the resistance layer 36 is made of CrSi.
The resistance layer 36 has a thickness TR of 1 μm or less. The thickness TR is preferably 500 nm or less. It is more preferable that the thickness TR is 0.1 nm or more and 100 nm or less. The thickness TR may be from 0.1 nm to 5 nm, from 5 nm to 10 nm, from 10 nm to 20 nm, from 20 nm to 40 nm, from 40 nm to 60 nm, from 60 nm to 80 nm, or from 80 nm to 100 nm. The thickness TR is most preferably 1 nm or more and 5 nm or less.

The sheet resistance value RT of the resistance layer 36 may be 100 Ω/□ or more and 50000 Ω/□ or less. Sheet resistance value RT is 100Ω/□ or more and 5000Ω/□ or less, 5000Ω/□ or more and 10000Ω/□ or less, 10000Ω/□ or more and 15000Ω/□ or less, 15000Ω/□ or more and 20000Ω/□ or less, 20000Ω/□ or more and 25000Ω/□ or less , 25,000 Ω/□ to 30,000 Ω/□, 30,000 Ω/□ to 35,000 Ω/□, 35,000 Ω/□ to 40,000 Ω/□, 40,000 Ω/□ to 45,000 Ω/□, or 45,000 Ω/□ to 50,000 Ω/□ Good too.

The content of chromium based on the total weight of the resistance layer 36 may be 5% by weight or more and 50% by weight or less. The content of Cr is 5% to 10% by weight, 10% to 20% by weight, 20% to 30% by weight, 30% to 40% by weight, or 40% to 50% by weight. It may be the following.
Referring to FIGS. 5 to 7, a plurality of chromium aggregates 37 are irregularly formed in any region of the resistance layer 36. In FIGS. 5 and 6, regions in which chromium aggregates 37 are formed are shown by cross hatching. The chromium aggregate 37 is made of chromium. The chromium aggregate 37 may contain a trace amount of silicon. The chromium aggregate 37 has a specific resistance ρ2 (ρ2<ρ1) that is less than the specific resistance ρ1 of the resistance layer 36.

Chromium aggregate 37 is electrically connected to resistance layer 36 . The chromium aggregate 37 may be connected in series to the resistance layer 36 or in parallel to the resistance layer 36. The plurality of chromium aggregates 37 may be directly connected to each other or may be electrically connected to each other via the resistance layer 36. The plurality of chromium aggregates 37 are electrically connected to each other to form a low resistance region 37a having a resistance value less than the resistance value of the resistance layer 36 as a whole in the resistance layer 36.

The resistance value of the resistance layer 36 is reduced by the chromium aggregates 37. The resistance value of the resistance layer 36 is adjusted in the decreasing direction by adjusting the proportion of the chromium aggregates 37 in the resistance layer 36. By increasing the proportion of the chromium aggregates 37 in the resistance layer 36, the resistance value of the resistance layer 36 can be brought closer to the resistance value of chromium. On the contrary, by reducing the proportion of chromium aggregates 37 in the resistance layer 36, the resistance value of the resistance layer 36 can be brought closer to the resistance value of chromium silicide.

The chromium aggregate 37 is formed by agglomeration of chromium contained in the chromium silicide when the chromium silicide is melted and hardened again. In this embodiment, the chromium aggregate 37 is formed by irradiating the resistive layer 36 with a laser beam and causing chromium to aggregate in the portion of the resistive layer 36 that is irradiated with the laser beam.
Before and after laser light irradiation, the planar area and thickness TR of the resistance layer 36 hardly change. According to the laser irradiation method, the chromium aggregate 37 can be formed while maintaining the size of the resistance layer 36. Moreover, according to the laser irradiation method, the proportion of the chromium aggregates 37 in the resistance layer 36 can be appropriately controlled. Thereby, the resistance value of the resistance layer 36 can be flexibly adjusted in the decreasing direction.

The plurality of chromium aggregates 37 may be formed over the entire area of the resistance layer 36, or may be formed in a part of the resistance layer 36. However, when forming a plurality of chromium aggregates 37 over the entire area of the resistance layer 36, it is necessary to irradiate the entire area of the resistance layer 36 with laser light, which increases manufacturing time. Furthermore, when forming a plurality of chromium aggregates 37 over the entire area of the resistance layer 36, it is more rational to form the thin film resistance 35 made of chromium. Therefore, it is preferable that the plurality of chromium aggregates 37 be formed in such a manner that a portion of the resistance layer 36 remains.

As an example, it is preferable that the plurality of chromium aggregates 37 be formed in an area of more than 0% and less than 50% of the resistance layer 36. The plurality of chromium aggregates 37 are present in the resistance layer 36 in an area of more than 0% and less than 5%, an area of more than 5% and less than 10%, an area of more than 10% and less than 15%, and an area of more than 15% and less than 20%. , 20% or more and 30% or less, 30% or more and 40% or less, or 40% or more and 50% or less. In these cases, the resistance value of the resistance layer 36 can be appropriately fine-tuned in a decreasing direction while suppressing manufacturing delays.

As another example, the plurality of chromium aggregates 37 may be formed such that the resistance value of the resistance layer 36 is reduced by more than 0% and less than 50%. The plurality of chromium aggregates 37 have a resistance value of the resistance layer 36 of more than 0% and less than 5%, more than 5% and less than 10%, more than 10% and less than 15%, more than 15% and less than 20%, and more than 20% and less than 30%. % or less, 30% or more and 40% or less, or 40% or more and 50% or less. In these cases, the resistance value of the resistance layer 36 can be appropriately fine-tuned in a decreasing direction while suppressing manufacturing delays.

The thin film resistor 35 includes one or more chromium aggregates 37 formed in a granular or layered (film-like) manner. The thin film resistor 35 may include one or more layered (film-like) chromium aggregates 37 in which a plurality of chromium aggregates 37 are connected to each other. Thin film resistor 35 includes one or more chromium aggregates 37 having a width WC that exceeds thickness TR of resistive layer 36 (TR<TC).

Thin film resistor 35 may include one or more chromium aggregates 37 having a thickness TC less than the thickness TR of resistive layer 36 (TC<TR). Thin film resistor 35 may include one or more chromium aggregates 37 having a thickness TC that exceeds thickness TR of resistive layer 36 (TR<TC).
Thin film resistor 35 may include one or more chromium aggregates 37 exposed from the bottom and top surfaces of resistive layer 36. Thin film resistor 35 may include one or more chromium aggregates 37 partially exposed from the bottom or top surface of resistive layer 36. Thin film resistor 35 may include one or more chromium aggregates 37 covered entirely by a resistive layer 36 .

Referring to FIGS. 5, 6, and 8, thin film resistor 35 includes trimming marks 38 formed in resistance layer 36. In FIGS. 5 and 6, the trimming marks 38 are shown by dotted hatching.
The trimming trace 38 is a region where a portion of the resistance layer 36 (chromium silicide) has disappeared. More specifically, the trimming marks 38 are laser processing marks where a part of the resistance layer 36 (chromium silicide) has disappeared by the laser irradiation method.

In this embodiment, the trimming marks 38 are formed at a distance from the region (low resistance region 37a) in which the chromium aggregate 37 is formed in the resistance layer 36 (connection portion 35c). The trimming marks 38 may be formed on either or both of the first end 35a and the second end 35b.
The trimming marks 38 extend in a direction intersecting the direction in which the resistive layer 36 extends. In this form, the trimming marks 38 extend in a direction perpendicular to the direction in which the resistive layer 36 extends. The trimming marks 38 may extend in the direction in which the resistive layer 36 extends.

The trimming trace 38 includes a plurality of conductive residues 39a that are irregularly formed at intervals from the resistive layer 36. The plurality of conductive residues 39a are portions separated from the resistance layer 36. More specifically, the plurality of conductive residues 39a are portions removed from the resistance layer 36 by laser irradiation. The plurality of conductive residues 39a are electrically insulated from the resistive layer 36.

The trimming mark 38 includes an insulator 39b covering a plurality of conductive residues 39a. Insulator 39b is interposed between resistance layer 36 and conductive residue 39a. The insulator 39b is interposed between the plurality of conductive residues 39a.
Insulator 39b includes silicon oxide in this form. The insulator 39b may include silicon oxide formed from silicon of chromium silicide, or may include a part of the protective layer 40 described later. The insulator 39b increases the insulation between the resistive layer 36 and the plurality of conductive residues 39a.

The resistance value of the resistance layer 36 is adjusted in an increasing direction depending on the number, shape, length, arrangement, etc. of the trimming marks 38. The resistance value of the resistance layer 36 is adjusted in both the decreasing and increasing directions by the combination of the chromium aggregates 37 and the trimming marks 38. Thereby, the resistance value of the thin film resistor 35 can be adjusted appropriately. The trimming marks 38 do not necessarily have to be formed. Therefore, a resistive layer 36 without trimming marks 38 may be formed.

Thin film resistor 35 can take various forms. Other embodiments of the thin film resistor 35 will be described below with reference to FIGS. 9A to 9F.
FIG. 9A is a plan view showing a thin film resistor 35 according to the second embodiment. In the following, structures corresponding to those described in FIGS. 1 to 8 will be given the same reference numerals and their descriptions will be omitted. Referring to FIG. 9A, thin film resistor 35 may have trimming marks 38 that overlap the region (low resistance region 37a) containing chromium aggregates 37 in resistance layer 36 in plan view.

In this form, all of the trimming marks 38 are formed in the region including the chromium aggregates 37 (low resistance region 37a). A portion of the trimming mark 38 may be located in a region (low resistance region 37a) containing the chromium aggregate 37. That is, trimming marks 38 may be formed across the region (low resistance region 37a) including the chromium aggregate 37.
FIG. 9B is a plan view showing a thin film resistor 35 according to the third embodiment. In the following, structures corresponding to those described in FIGS. 1 to 8 will be given the same reference numerals and their descriptions will be omitted. Referring to FIG. 9B, a thin film resistor 35 including a plurality of trimming marks 38 may be formed.

The plurality of trimming marks 38 each extend in a direction intersecting the direction in which the connecting portion 35c extends. In this embodiment, the plurality of trimming marks 38 each extend in a direction perpendicular to the direction in which the connecting portion 35c extends. In this form, the plurality of trimming marks 38 include one or more (three in this form) first trimming marks 38A and one or more (three in this form) second trimming marks 38B.

The plurality of first trimming marks 38A are formed at intervals on one side extending in the longitudinal direction of the connecting portion 35c. The plurality of second trimming marks 38B are formed at intervals on the other side extending along the longitudinal direction of the connecting portion 35c. The plurality of second trimming marks 38B are formed alternately with the plurality of first trimming marks 38A along the longitudinal direction. Thereby, the thin film resistor 35 is formed in a meandering shape as a whole when viewed from above.

FIG. 9C is a plan view showing a thin film resistor 35 according to the fourth embodiment. In the following, structures corresponding to those described in FIGS. 1 to 8 will be given the same reference numerals and their descriptions will be omitted. Referring to FIG. 9C, a thin film resistor 35 may be formed that includes a first end 35a, a second end 35b, and a connecting portion 35c, each having a different width.
More specifically, the first end portion 35a is formed with a width different from that of the connecting portion 35c. The second end portion 35b is formed with a width different from that of the connecting portion 35c. In this embodiment, the second end 35b is formed to have the same width as the first end 35a. The second end 35b may be formed with a width different from that of the first end 35a. The connecting portion 35c has a width narrower than the width of the first end 35a and the width of the second end 35b.

In this form, the first end portion 35a is formed into a rectangular shape (square shape in this form) in plan view. The planar shape of the first end portion 35a is arbitrary. The first end portion 35a may be formed in a polygonal shape such as a triangular shape or a hexagonal shape in a plan view. The first end portion 35a may be formed in a circular or elliptical shape in plan view.
The second end portion 35b is formed into a rectangular shape (square shape in this embodiment) in plan view. The planar shape of the second end portion 35b is arbitrary. The second end portion 35b may be formed in a polygonal shape such as a triangular shape or a hexagonal shape in a plan view. The second end portion 35b may be formed in a circular or elliptical shape in plan view.

FIG. 9D is a plan view showing a thin film resistor 35 according to the fifth embodiment. In the following, structures corresponding to those described in FIGS. 1 to 8 will be given the same reference numerals and their descriptions will be omitted. Referring to FIG. 9D, a thin film resistor 35 may be formed that includes a first end 35a, a second end 35b, and a connecting portion 35c, each having a different width.
The first end portion 35a is formed with a width different from that of the connecting portion 35c. The second end portion 35b is formed with a width different from that of the connecting portion 35c. In this embodiment, the second end 35b is formed to have the same width as the first end 35a. The second end 35b may be formed with a width different from that of the first end 35a.

The connecting portion 35c has a width narrower than the width of the first end 35a and the width of the second end 35b. In this form, the connecting portion 35c extends in a meandering shape in a region between the first end 35a and the second end 35b in plan view.
In this form, the first end portion 35a is formed into a rectangular shape (square shape in this form) in plan view. The planar shape of the first end portion 35a is arbitrary. The first end portion 35a may be formed in a polygonal shape such as a triangular shape or a hexagonal shape in a plan view. The first end portion 35a may be formed in a circular or elliptical shape in plan view.

The second end portion 35b is formed into a rectangular shape (square shape in this embodiment) in plan view. The planar shape of the second end portion 35b is arbitrary. The second end portion 35b may be formed in a polygonal shape such as a triangular shape or a hexagonal shape in a plan view. The second end portion 35b may be formed in a circular or elliptical shape in plan view.
FIG. 9E is a plan view showing a thin film resistor 35 according to the sixth embodiment. In the following, structures corresponding to those described in FIGS. 1 to 8 will be given the same reference numerals and their descriptions will be omitted. Referring to FIG. 9F, a thin film resistor 35 may be formed that further includes a lead-out portion 35d in addition to the first end 35a, the second end 35b, and the connection portion 35c.

The drawn-out portion 35d is drawn out from the connecting portion 35c in a direction intersecting the direction in which the connecting portion 35c extends. More specifically, the drawn-out portion 35d is drawn out in a direction perpendicular to the direction in which the connecting portion 35c extends. In this embodiment, the drawer portion 35d is formed into a rectangular shape in plan view.
The extraction portion 35d is an area where the trimming marks 38 are formed. In this form, one trimming mark 38 is formed on the drawer portion 35d. A plurality of trimming marks 38 may be formed on the drawer portion 35d. A drawer portion 35d without trimming marks 38 may be formed.

The chromium aggregate 37 may be formed in the connecting portion 35c and/or the drawing portion 35d. FIG. 9E shows an example in which the chromium aggregates 37 are formed in the connecting portion 35c and the pull-out portion 35d.
FIG. 9F is a plan view showing a thin film resistor 35 according to the seventh embodiment. In the following, structures corresponding to those described in FIGS. 1 to 8 will be given the same reference numerals and their descriptions will be omitted. Referring to FIG. 9F, a thin film resistor 35 is formed which is electrically connected to a plurality (in this embodiment, two) of first via electrodes 23 and a plurality (in this embodiment, two) of second via electrodes 24. may be done. That is, the resistance circuit 10 may include a plurality of first via electrodes 23 and a plurality of second via electrodes 24.

The number of first via electrodes 23 and the number of second via electrodes 24 are arbitrary. The number of first via electrodes 23 and the number of second via electrodes 24 may be different from each other. The number of first via electrodes 23 may be less than the number of second via electrodes 24.
The number of first via electrodes 23 may exceed the number of second via electrodes 24. While one first via electrode 23 is formed, a plurality of second via electrodes 24 may be formed. While the plurality of first via electrodes 23 are formed, one second via electrode 24 may be formed.

The characteristics of the thin film resistor 35 according to the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, and the seventh embodiment may be any aspect among them. and can be combined in any form. A thin film resistor 35 having a configuration in which at least two of the features of the thin film resistor 35 according to the first to seventh embodiments are combined may be employed. For example, the features of the thin film resistor 35 according to the seventh embodiment may be incorporated into the thin film resistor 35 according to the first to sixth embodiments.

Referring again to FIGS. 2-4, resistance circuit 10 includes a protective layer 40 covering thin film resistor 35. Referring again to FIGS. The protective layer 40 is interposed in a region between the third insulating layer 15 and the fourth insulating layer 16, and covers the thin film resistor 35. More specifically, the protective layer 40 is formed in a film shape along the exposed surface of the resistance layer 36 and the exposed surface of the chromium aggregate 37.
The protective layer 40 further covers the trimming marks 38. The protective layer 40 may cover the conductive residue 39a at the trimming mark 38. The protective layer 40 may form part or all of the insulator 39b at the trimming mark 38.

The protective layer 40 has a planar shape that matches the planar shape of the resistance layer 36 (thin film resistor 35). The protective layer 40 may have a side surface continuous with the side surface of the resistance layer 36. The side surface of the protective layer 40 may be formed flush with the side surface of the resistance layer 36.
The protective layer 40 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. In this case, a silicon nitride layer may be formed on the silicon oxide layer, or a silicon oxide layer may be formed on the silicon nitride layer. The protective layer 40 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer. In this form, the protective layer 40 has a single layer structure made of a silicon oxide layer.

The thickness of the protective layer 40 may be 1 nm or more and 5 μm or less. The thickness of the protective layer 40 is 1 nm to 10 nm, 10 nm to 50 nm, 50 nm to 100 nm, 100 nm to 200 nm, 200 nm to 400 nm, 400 nm to 600 nm, 600 nm to 800 nm, or 800 nm to 1 μm. There may be.

The thickness of the protective layer 40 is 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, It may be 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less.
The thickness of the protective layer 40 is preferably greater than or equal to the thickness TR of the resistance layer 36. With the protective layer 40 having a thickness equal to or greater than the thickness TR of the resistance layer 36, the protuberances formed in the resistance layer 36 can be appropriately filled.

Resistance circuit 10 includes a first lower wiring layer 41 and a second lower wiring layer 42 . The first lower wiring layer 41 is formed within the third insulating layer 15 . More specifically, the first lower wiring layer 41 is formed on the wiring circuit formation layer 21 (second insulating layer 14) and covered with the third insulating layer 15. The first lower wiring layer 41 is electrically connected to the thin film resistor 35 via the first via electrode 23 .

The second lower wiring layer 42 is formed within the third insulating layer 15. More specifically, the second lower wiring layer 42 is formed on the wiring circuit forming layer 21 (second insulating layer 14) and covered with the third insulating layer 15. The second lower wiring layer 42 is formed at a distance from the first lower wiring layer 41. The second lower wiring layer 42 is electrically connected to the thin film resistor 35 via the second via electrode 24.

Thereby, the thin film resistor 35 is connected in series to the first lower wiring layer 41 and the second lower wiring layer 42. The thin film resistor 35 is formed on a line connecting the first lower wiring layer 41 and the second lower wiring layer 42 in plan view. In this form, the thin film resistor 35 extends linearly in a region between the first lower wiring layer 41 and the second lower wiring layer 42 in plan view.
The first lower wiring layer 41 and the second lower wiring layer 42 each have a first thickness TL1. The first thickness TL1 may be greater than or equal to 100 nm and less than or equal to 3000 nm. The first thickness TL1 may be from 100 nm to 500 nm, from 500 nm to 1000 nm, from 1000 nm to 1500 nm, from 1500 nm to 2000 nm, from 2000 nm to 2500 nm, or from 2500 nm to 3000 nm, respectively.

The first thickness TL1 is preferably 100 nm or more and 1500 nm or less. The first thickness TL1 of the first lower wiring layer 41 and the first thickness TL1 of the second lower wiring layer 42 may be different from each other. The first thickness TL1 of the first lower wiring layer 41 and the first thickness TL1 of the second lower wiring layer 42 are preferably equal to each other.
Referring to FIG. 3, the first lower wiring layer 41 connects a first end 41a on one side, a second end 41b on the other side, and connects the first end 41a and the second end 41b. It includes a connecting portion 41c. The first end 41a overlaps the first end 35a of the thin film resistor 35 in plan view. The first end 41 a is electrically connected to the first end 35 a of the thin film resistor 35 via the first via electrode 23 .

The second end portion 41b is located in a region outside the thin film resistor 35 in plan view. The second end 41b is located in the outer region 7 in this embodiment. The connecting portion 41c extends in a band shape in a region between the first end 41a and the second end 41b in plan view. In this embodiment, the connecting portion 41c extends in a belt shape along a straight line connecting the first end 41a and the second end 41b.

In this embodiment, the first lower wiring layer 41 has a stacked structure in which a plurality of electrode layers are stacked. The first lower wiring layer 41 includes a first barrier layer 43, a main body layer 44, and a second barrier layer 45, which are laminated in this order from above the wiring circuit forming layer 21 (second insulating layer 14).
In this embodiment, the first barrier layer 43 has a stacked structure including a Ti layer 46 and a TiN layer 47 stacked in this order from above the wiring circuit forming layer 21 (second insulating layer 14). The first barrier layer 43 may have a single layer structure consisting of a Ti layer 46 or a TiN layer 47.

The main body layer 44 has a resistance value that is less than the resistance value of the first barrier layer 43 and the resistance value of the second barrier layer 45 . The main body layer 44 has a thickness that exceeds the thickness of the first barrier layer 43 and the thickness of the second barrier layer 45. The main body layer 44 may contain at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. In this form, the main body layer 44 has a single layer structure consisting of an AlCu alloy layer 48.

In this embodiment, the second barrier layer 45 has a laminated structure including a Ti layer 49 and a TiN layer 50 laminated in this order from above the main body layer 44 . The second barrier layer 45 may have a single layer structure consisting of a Ti layer 49 or a TiN layer 50.
Referring to FIG. 4, the second lower wiring layer 42 connects a first end 42a on one side, a second end 42b on the other side, and connects the first end 42a and the second end 42b. It includes a connecting portion 42c. The first end 42a overlaps the second end 35b of the thin film resistor 35 in plan view. The first end 42 a is electrically connected to the second end 35 b of the thin film resistor 35 via the second via electrode 24 .

The second end portion 42b is located in a region outside the thin film resistor 35 in plan view. The second end 42b is located in the outer region 7 in this embodiment. The connecting portion 42c extends in a band shape in a region between the first end 42a and the second end 42b in plan view. In this embodiment, the connecting portion 42c extends in a belt shape along a straight line connecting the first end 42a and the second end 42b.

In this embodiment, the second lower wiring layer 42 has a laminated structure in which a plurality of electrode layers are laminated. The second lower wiring layer 42 includes a first barrier layer 53, a main body layer 54, and a second barrier layer 55, which are laminated in this order from above the wiring circuit forming layer 21 (second insulating layer 14).
In this embodiment, the first barrier layer 53 has a stacked structure including a Ti layer 56 and a TiN layer 57 stacked in this order from above the wiring circuit forming layer 21 (second insulating layer 14). The first barrier layer 53 may have a single layer structure consisting of a Ti layer 56 or a TiN layer 57.

The main body layer 54 has a resistance value that is less than the resistance value of the first barrier layer 53 and the resistance value of the second barrier layer 55. The main body layer 54 has a thickness that exceeds the thickness of the first barrier layer 53 and the thickness of the second barrier layer 55. The main body layer 54 may contain at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. In this form, the main body layer 54 has a single layer structure consisting of an AlCu alloy layer 58.

In this embodiment, the second barrier layer 55 has a laminated structure including a Ti layer 59 and a TiN layer 60 laminated in this order from above the main body layer 54 . The second barrier layer 55 may have a single layer structure consisting of a Ti layer 59 or a TiN layer 60.
Resistance circuit 10 includes a first upper wiring layer 61 and a second upper wiring layer 62. The first upper wiring layer 61 is formed on the third insulating layer 15. The first upper wiring layer 61 forms one of the uppermost wiring layers of the insulating laminated structure 12. The first upper wiring layer 61 is electrically connected to the first lower wiring layer 41.

The second upper wiring layer 62 is formed on the third insulating layer 15 at a distance from the first upper wiring layer 61 . The second upper wiring layer 62 forms one of the uppermost wiring layers of the insulating laminated structure 12. The second upper wiring layer 62 is electrically connected to the second lower wiring layer 42 .
Thereby, the thin film resistor 35 is electrically connected to the first upper wiring layer 61 via the first lower wiring layer 41. Further, the thin film resistor 35 is electrically connected to the second upper wiring layer 62 via the second lower wiring layer 42 . The thin film resistor 35 is connected in series to the first upper wiring layer 61 and the second upper wiring layer 62 via the first lower wiring layer 41 and the second lower wiring layer 42 .

The first upper wiring layer 61 is formed at a distance from the thin film resistor 35 in plan view. The first upper wiring layer 61 does not overlap the thin film resistor 35 in plan view. The entire thin film resistor 35 is exposed from the first upper wiring layer 61 in plan view.
The second upper wiring layer 62 is formed at a distance from the thin film resistor 35 in plan view. The second upper wiring layer 62 does not overlap the thin film resistor 35 in plan view. The entire thin film resistor 35 is exposed from the second upper wiring layer 62 in plan view.

That is, the thin film resistor 35 is formed in a region between the first upper wiring layer 61 and the second upper wiring layer 62 in plan view. Thereby, parasitic capacitance can be suppressed in the region between the thin film resistor 35 and the first upper wiring layer 61. Furthermore, parasitic capacitance can be suppressed in the region between the thin film resistor 35 and the second upper wiring layer 62.
In this embodiment, the thin film resistor 35 is formed at a distance from the first upper wiring layer 61 and the second upper wiring layer 62 in plan view. Thereby, parasitic capacitance can be appropriately suppressed in the region between the thin film resistor 35 and the first upper wiring layer 61.

The first upper wiring layer 61 and the second upper wiring layer 62 each have a second thickness TL2. The second thickness TL2 is greater than or equal to the first thickness TL1 (TL1≦TL2). More specifically, the second thickness TL2 exceeds the first thickness TL1 (TL1<TL2).
The second thickness TL2 may be greater than or equal to 100 nm and less than or equal to 15000 nm. The second thickness TL2 is from 100 nm to 1500 nm, from 1500 nm to 3000 nm, from 3000 nm to 4500 nm, from 4500 nm to 6000 nm, from 6000 nm to 7500 nm, from 7500 nm to 9000 nm, from 9000 nm to 10500 nm, and from 10500 nm to 12 000nm or less, 12000nm or more 13500nm Hereinafter, it may also be 13,500 nm or more and 15,000 nm or less.

The second thickness TL2 of the first upper wiring layer 61 and the second thickness TL2 of the second upper wiring layer 62 may be different from each other. The second thickness TL2 of the first upper wiring layer 61 and the second thickness TL2 of the second upper wiring layer 62 are preferably equal to each other.
Referring to FIG. 3, the first upper wiring layer 61 includes a first end 61a on one side, a second end 61b on the other side, and a connection connecting the first end 61a and the second end 61b. 61c. The first end 61a is located in a region overlapping the first end 41a of the first lower wiring layer 41 in plan view.

The second end portion 61b is located in a region outside the thin film resistor 35 in plan view. In this form, the second end portion 61b is located in the device region 6 in plan view. The second end 61b may be located in the outer region 7. The connecting portion 61c extends in a band shape in a region between the first end 61a and the second end 61b in plan view. In this embodiment, the connecting portion 61c extends in a band shape along a straight line connecting the first end 61a and the second end 61b.

In this embodiment, the first upper wiring layer 61 has a laminated structure in which a plurality of electrode layers are laminated. The first upper wiring layer 61 includes a first barrier layer 63, a main body layer 64, and a second barrier layer 65, which are laminated in this order from above the wiring circuit forming layer 21 (second insulating layer 14).
In this embodiment, the first barrier layer 63 has a stacked structure including a Ti layer 66 and a TiN layer 67 stacked in this order from above the wiring circuit forming layer 21 (second insulating layer 14). The first barrier layer 63 may have a single layer structure consisting of a Ti layer 66 or a TiN layer 67.

The main body layer 64 has a resistance value that is less than the resistance value of the first barrier layer 63 and the resistance value of the second barrier layer 65. The main body layer 64 has a thickness that exceeds the thickness of the first barrier layer 63 and the thickness of the second barrier layer 65. The main body layer 64 may contain at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. In this form, the main body layer 64 has a single layer structure consisting of an AlCu alloy layer 68.

In this embodiment, the second barrier layer 65 has a laminated structure including a Ti layer 69 and a TiN layer 70 laminated in this order from above the main body layer 64 . The second barrier layer 65 may have a single layer structure consisting of a Ti layer 69 or a TiN layer 70.
Referring to FIG. 4, the second upper wiring layer 62 includes a first end 62a on one side, a second end 62b on the other side, and a connection connecting the first end 62a and the second end 62b. 62c. The first end 62a is located in a region overlapping the second end 42b of the second lower wiring layer 42 in plan view.

The second end portion 62b is located in a region outside the thin film resistor 35 in plan view. In this form, the second end portion 62b is located in the device region 6 in plan view. The second end 62b may be located in the outer region 7 in plan view. The connecting portion 62c extends in a band shape in a region between the first end 62a and the second end 62b in plan view. In this form, the connecting portion 62c extends in a belt shape along a straight line connecting the first end 62a and the second end 62b.

In this embodiment, the second upper wiring layer 62 has a laminated structure in which a plurality of electrode layers are laminated. The second upper wiring layer 62 includes a first barrier layer 73, a main body layer 74, and a second barrier layer 75, which are laminated in this order from above the wiring circuit forming layer 21 (second insulating layer 14).
In this embodiment, the first barrier layer 73 has a stacked structure including a Ti layer 76 and a TiN layer 77 stacked in this order from above the wiring circuit forming layer 21 (second insulating layer 14). The first barrier layer 73 may have a single layer structure consisting of a Ti layer 76 or a TiN layer 77.

The main body layer 74 has a resistance value that is less than the resistance value of the first barrier layer 73 and the resistance value of the second barrier layer 75. The main body layer 74 has a thickness that exceeds the thickness of the first barrier layer 73 and the thickness of the second barrier layer 75. The main body layer 74 may contain at least one of Al, Cu, AlSiCu alloy, AlSi alloy, and AlCu alloy. In this form, the main body layer 74 has a single layer structure consisting of an AlCu alloy layer 78.

In this embodiment, the second barrier layer 75 has a laminated structure including a Ti layer 79 and a TiN layer 80 laminated in this order from above the main body layer 74 . The second barrier layer 75 may have a single layer structure consisting of a Ti layer 79 or a TiN layer 80.
Referring to FIGS. 1 to 4, resistance circuit 10 includes a first long via electrode 83 and a second long via electrode 84. The first long via electrode 83 is electrically connected to the first lower wiring layer 41 and the first upper wiring layer 61. The second long via electrode 84 is electrically connected to the second lower wiring layer 42 and the second upper wiring layer 62.

Thereby, the thin film resistor 35 is electrically connected to the first upper wiring layer 61 via the first via electrode 23, the first lower wiring layer 41, and the first long via electrode 83. Alternatively, the thin film resistor 35 is electrically connected to the second upper wiring layer 62 via the second via electrode 24, the second lower wiring layer 42, and the second long via electrode 84.
The first long via electrode 83 is formed on the side of the thin film resistor 35. In this form, the first long via electrode 83 is located on a straight line connecting the first via electrode 23 and the second via electrode 24.

The second long via electrode 84 is formed on the side of the thin film resistor 35 at a distance from the first long via electrode 83 . In this embodiment, the second long via electrode 84 faces the first long via electrode 83 with the thin film resistor 35 in between. The second long via electrode 84 is located on a straight line connecting the first via electrode 23 and the second via electrode 24.
Thereby, the thin film resistor 35 is located on the straight line connecting the first long via electrode 83 and the second long via electrode 84. The thin film resistor 35 is located on a straight line connecting the first via electrode 23, the second via electrode 24, the first long via electrode 83, and the second long via electrode 84. In this form, the thin film resistor 35 extends along a straight line connecting the first long via electrode 83 and the second long via electrode 84.

In this form, the first long via electrode 83 is formed into a circular shape in plan view. The planar shape of the first long via electrode 83 is arbitrary. The first long via electrode 83 may be formed in a polygonal shape such as a triangular, quadrangular, or hexagonal shape, or an elliptical shape in plan view.
The first long via electrode 83 crosses the thin film resistor 35 in the normal direction to the main insulating surface of the third insulating layer 15 . The first long via electrode 83 is embedded in the third insulating layer 15 and the fourth insulating layer 16 through the third insulating layer 15 and the fourth insulating layer 16, and is exposed from the main insulating surface of the fourth insulating layer 16. There is.

The first long via electrode 83 includes a first end 83 a on one side and a second end 83 b on the other side with respect to the normal direction of the main insulating surface of the third insulating layer 15 . The first end portion 83a is exposed from the main insulating surface of the fourth insulating layer 16. The first end 83a is electrically connected to the first end 61a of the first upper wiring layer 61.
The second end portion 83b is located within the third insulating layer 15. The second end 83b is electrically connected to the second end 41b of the first lower wiring layer 41. The first long via electrode 83 is formed in a tapered shape whose width narrows from the first end 83a toward the second end 83b when viewed in cross section.

The first long via electrode 83 has a lower portion 83c located on the third insulating layer 15 side with respect to the thin film resistor 35, and an upper portion 83d located on the fourth insulating layer 16 side with respect to the thin film resistor 35. ing. With respect to the normal direction of the main insulating surface of the third insulating layer 15, the length of the upper portion 83d is greater than or equal to the length of the lower portion 83c. More specifically, the length of the upper portion 83d exceeds the length of the lower portion 83c.

The first long via electrode 83 has a laminated structure including a main body layer 85 and a barrier layer 86. The main body layer 85 is embedded in the third insulating layer 15 and the fourth insulating layer 16. Main body layer 85 may include tungsten (W) or copper (Cu). In this form, the first long via electrode 83 has a single layer structure consisting of a tungsten layer 87.
The barrier layer 86 is interposed between the main body layer 85 and the third insulating layer 15 and between the main body layer 85 and the fourth insulating layer 16. In this form, the barrier layer 86 has a laminated structure in which a plurality of electrode layers are laminated. In this form, the barrier layer 86 includes a Ti layer 88 and a TiN layer 89 formed in this order from the third insulating layer 15.

The Ti layer 88 is in contact with the third insulating layer 15 and the fourth insulating layer 16. TiN layer 89 is in contact with main body layer 85 . The barrier layer 86 may have a single layer structure consisting of a Ti layer 88 or a TiN layer 89.
In this form, the second long via electrode 84 is formed into a circular shape in plan view. The planar shape of the second long via electrode 84 is arbitrary. The second long via electrode 84 may be formed in a polygonal shape such as a triangular, quadrangular, or hexagonal shape, or an elliptical shape in plan view.

The second long via electrode 84 crosses the thin film resistor 35 in the normal direction to the main insulating surface of the third insulating layer 15 . The second long via electrode 84 is embedded in the third insulating layer 15 and the fourth insulating layer 16 through the third insulating layer 15 and the fourth insulating layer 16, and is exposed from the main insulating surface of the fourth insulating layer 16. There is.
The second long via electrode 84 includes a first end 84 a on one side and a second end 84 b on the other side with respect to the normal direction of the main insulating surface of the third insulating layer 15 . The first end portion 84a is exposed from the main insulating surface of the fourth insulating layer 16. The first end 84a is electrically connected to the first end 62a of the second upper wiring layer 62.

The second end portion 84b is located within the third insulating layer 15. The second end 84b is electrically connected to the second end 42b of the second lower wiring layer 42. The second long via electrode 84 is formed in a tapered shape whose width narrows from the first end 84a toward the second end 84b when viewed in cross section.
The second long via electrode 84 has a lower portion 84c located on the third insulating layer 15 side with respect to the thin film resistor 35, and an upper portion 84d located on the fourth insulating layer 16 side with respect to the thin film resistor 35. ing. With respect to the normal direction of the main insulating surface of the third insulating layer 15, the length of the upper portion 84d is greater than or equal to the length of the lower portion 84c. More specifically, the length of the upper portion 84d exceeds the length of the lower portion 84c.

The second long via electrode 84 has a laminated structure including a main body layer 90 and a barrier layer 91. The main body layer 90 is embedded in the third insulating layer 15 and the fourth insulating layer 16. Body layer 90 may include tungsten (W) or copper (Cu). In this form, the second long via electrode 84 has a single layer structure consisting of a tungsten layer 92.
The barrier layer 91 is interposed between the main body layer 90 and the third insulating layer 15 and between the main body layer 90 and the fourth insulating layer 16. In this form, the barrier layer 91 has a laminated structure in which a plurality of electrode layers are laminated. In this form, the barrier layer 91 includes a Ti layer 93 and a TiN layer 94 formed in this order from the third insulating layer 15.

The Ti layer 93 is in contact with the third insulating layer 15 and the fourth insulating layer 16. TiN layer 94 is in contact with main body layer 90 . The barrier layer 91 may have a single layer structure consisting of a Ti layer 93 or a TiN layer 94.
Referring to FIG. 2, wired circuit forming layer 21 includes wiring 95 that electrically connects functional devices and thin film resistor 35. As shown in FIG. The wiring 95 is selectively formed in the first insulating layer 13 and the second insulating layer 14 and routed from the device region 6 to the outer region 7 .

More specifically, the wiring 95 includes one or more connection wiring layers 96 electrically connected to the functional devices in the device region 6. One or more connection wiring layers 96 are formed on either or both of the first insulating layer 13 and the second insulating layer 14 . FIG. 2 shows an example in which two connection wiring layers 96 are formed on the first insulating layer 13.
One or more connection wiring layers 96 are selectively routed from the device region 6 to the outer region 7 . The connection wiring layer 96 has the same laminated structure as the first lower wiring layer 41 (second lower wiring layer 42) and the first upper wiring layer 61 (second upper wiring layer 62). A detailed description of the connection wiring layer 96 will be omitted.

Wiring 95 includes one or more connection via electrodes 97 . One or more connection via electrodes 97 connect one or more connection wiring layers 96 to any first lower wiring layer 41 (second lower wiring layer 42) or any first upper wiring layer 61 (second lower wiring layer 42). 2 upper wiring layer 62).
One or more connection via electrodes 97 are formed on either or both of the first insulating layer 13 and the second insulating layer 14 . FIG. 2 shows an example in which one connection wiring layer 96 is connected to the first lower wiring layer 41 by two connection via electrodes 97 .

The connection via electrode 97 has the same laminated structure as the first via electrode 23 (second via electrode 24) and the first long via electrode 83 (second long via electrode 84). A detailed description of the connection via electrode 97 will be omitted.
The second end 61b of the first upper wiring layer 61 may be connected to any connection wiring layer 96 via a connection via electrode 97. The second end 62b of the second upper wiring layer 62 may be connected to any connection wiring layer 96 via a connection via electrode 97.

Referring to FIG. 2, a top insulating layer 101 is formed on the insulating layered structure 12. As shown in FIG. The uppermost insulating layer 101 covers the first upper wiring layer 61 and the second upper wiring layer 62. The uppermost insulating layer 101 covers the connection portion between the first upper wiring layer 61 and the first long via electrode 83 in a plan view. The uppermost insulating layer 101 covers the connection portion between the second upper wiring layer 62 and the second long via electrode 84 in a plan view.

A first pad opening 102 and a second pad opening 103 are formed in the uppermost insulating layer 101 in the outer region 7 . The first pad opening 102 exposes a part of the first upper wiring layer 61 as a first pad region 104 . More specifically, the first pad opening 102 exposes a region of the first upper wiring layer 61 other than the connecting portion between the first upper wiring layer 61 and the first long via electrode 83 as a first pad region 104 .

The second pad opening 103 exposes a part of the second upper wiring layer 62 as a second pad region 105 . More specifically, the second pad opening 103 exposes a region of the second upper wiring layer 62 other than the connecting portion between the second upper wiring layer 62 and the second long via electrode 84 as a second pad region 105 .
In this embodiment, the uppermost insulating layer 101 has a laminated structure including a passivation layer 106 and a resin layer 107. In FIG. 1, the resin layer 107 is shown by hatching for clarity.

Passivation layer 106 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. In this case, a silicon nitride layer may be formed on the silicon oxide layer, or a silicon oxide layer may be formed on the silicon nitride layer.
The passivation layer 106 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer. Preferably, the passivation layer 106 is made of an insulating material different from that of the insulating layered structure 12. In this form, the passivation layer 106 has a single layer structure made of a silicon nitride layer.

The resin layer 107 may contain a photosensitive resin. The photosensitive resin may be of positive type or negative type. The resin layer 107 may contain at least one of polyimide, polyamide, and polybenzoxazole. The resin layer 107 is preferably made of polyamide or polybenzoxazole.
The first via electrode 23 , the first lower wiring layer 41 , the first long via electrode 83 , and the first upper wiring layer 61 form a first wiring connected to the thin film resistor 35 . One end of the first wiring (first via electrode 23) is connected to the thin film resistor 35 within the insulating laminated structure 12, and the other end of the first wiring (first upper wiring layer 61) serves as an external terminal exposed to the outside. .

The second via electrode 24 , the second lower wiring layer 42 , the second long via electrode 84 and the second upper wiring layer 62 form a second wiring connected to the thin film resistor 35 . One end of the second wiring (second via electrode 24) is connected to the thin film resistor 35 within the insulating laminated structure 12, and the other end of the second wiring (second upper wiring layer 62) serves as an external terminal exposed to the outside. . A high voltage may be applied to the first wiring, and a low voltage may be applied to the second wiring. A low voltage may be applied to the first wiring, and a high voltage may be applied to the second wiring.

As described above, the electronic component 1 includes the thin film resistor 35. The thin film resistor 35 includes a resistance layer 36 containing chromium silicide, and a chromium agglomerate 37 formed in the resistance layer 36 . According to this thin film resistor 35, a chromium aggregate 37 having a specific resistance ρ2 (ρ2<ρ1) that is less than the specific resistance ρ1 of chromium silicide is formed in the resistance layer 36. Thereby, it is possible to provide a thin film resistor 35 that includes a resistance layer 36 containing chromium silicide but has a resistance value lower than the resistance value of the resistance layer 36, and an electronic component 1 that includes the thin film resistor 35.

The resistance value of the resistance layer 36 can be adjusted in a decreasing direction by changing the proportion of the chromium aggregates 37 in the resistance layer 36. By increasing the proportion of the chromium aggregates 37 in the resistance layer 36, the resistance value of the resistance layer 36 can be brought closer to the resistance value of chromium.
On the contrary, by reducing the proportion of chromium aggregates 37 in the resistance layer 36, the resistance value of the resistance layer 36 can be brought closer to the resistance value of chromium silicide. Therefore, by forming the chromium aggregates 37 in some regions of the resistance layer 36, the resistance value of the resistance layer 36 can be adjusted in a decreasing direction.

In the thin film resistor 35, the resistance layer 36 may have trimming marks 38 where chromium silicide has disappeared. The trimming marks 38 allow the resistance value of the resistance layer 36 to be adjusted in an increasing direction. Therefore, by forming both the chromium aggregates 37 and the trimming marks 38, the resistance value of the resistance layer 36 can be adjusted in the decreasing and increasing directions. Thereby, the resistance value of the resistance layer 36 can be appropriately fine-tuned.

10A to 10U are cross-sectional views for explaining an example of a method for manufacturing the electronic component 1 shown in FIG. 1. 10A to 10U are cross-sectional views of portions corresponding to FIG. 2.
Referring to FIG. 10A, semiconductor layer 2 is prepared. Semiconductor layer 2 includes a device region 6 and an outer region 7 . Next, the wiring circuit formation layer 21 of the insulating laminated structure 12 is formed on the first main surface 3 of the semiconductor layer 2. The wiring circuit forming layer 21 includes a first insulating layer 13 , a second insulating layer 14 , one or more connection wiring layers 96 , and one or more connection via electrodes 97 . A description of the process of forming the wiring circuit forming layer 21 will be omitted.

Next, referring to FIG. 10B, a first base wiring layer 111 that becomes the base of the first lower wiring layer 41 and the second lower wiring layer 42 is formed on the wiring circuit forming layer 21. The step of forming the first base wiring layer 111 includes the step of forming the first barrier layer 112, the main body layer 113, and the second barrier layer 114 in this order from above the wiring circuit formation layer 21.
The step of forming the first barrier layer 112 includes a step of forming a Ti layer and a TiN layer in this order from above the wiring circuit forming layer 21. The Ti layer and the TiN layer may each be formed by sputtering. The step of forming the main body layer 113 includes the step of forming an AlCu alloy layer on the first barrier layer 112 . The AlCu alloy layer may be formed by sputtering.

The step of forming the second barrier layer 114 includes a step of forming a Ti layer and a TiN layer in this order from above the main body layer 113. The Ti layer and the TiN layer may each be formed by sputtering.
Next, referring to FIG. 10C, a mask 115 having a predetermined pattern is formed on the first base wiring layer 111. The mask 115 has an opening 116 that covers the region of the first base wiring layer 111 where the first lower wiring layer 41 and the second lower wiring layer 42 are to be formed, and exposes the other region.

Next, unnecessary portions of the first base wiring layer 111 are removed by etching through the mask 115. As a result, the first base wiring layer 111 is divided into the first lower wiring layer 41 and the second lower wiring layer 42. Mask 115 is then removed.
Next, referring to FIG. 10D, third insulating layer 15 covering first lower wiring layer 41 and second lower wiring layer 42 is formed on wiring circuit forming layer 21. The third insulating layer 15 may be formed by a CVD (Chemical Vapor Deposition) method.

Next, referring to FIG. 10E, a first via hole 117 that exposes the first lower wiring layer 41 and a second via hole 118 that exposes the second lower wiring layer 42 are formed in the third insulating layer 15. . In this step, first, a mask 119 having a predetermined pattern is formed on the third insulating layer 15. The mask 119 has a plurality of openings 120 that expose regions in the third insulating layer 15 where the first via hole 117 and the second via hole 118 are to be formed.

Next, unnecessary portions of the third insulating layer 15 are removed by etching through the mask 119. As a result, a first via hole 117 and a second via hole 118 are formed in the third insulating layer 15. Mask 119 is then removed.
Next, referring to FIG. 10F, a base electrode layer 121 that becomes the base of the first via electrode 23 and the second via electrode 24 is formed on the third insulating layer 15. The step of forming the base electrode layer 121 includes the step of forming the barrier layer 122 and the main body layer 123 in this order from above the third insulating layer 15.

The step of forming the barrier layer 122 includes a step of forming a Ti layer and a TiN layer in this order from above the third insulating layer 15. The Ti layer and the TiN layer may each be formed by sputtering. The process of forming body layer 123 includes forming a tungsten layer on barrier layer 122 . The tungsten layer may be formed by CVD.
Next, referring to FIG. 10G, a step of removing base electrode layer 121 is performed. Base electrode layer 121 is removed until third insulating layer 15 is exposed. The step of removing base electrode layer 121 may include a step of removing base electrode layer 121 by grinding.

In this embodiment, the step of grinding the base electrode layer 121 is performed by a CMP (Chemical Mechanical Polishing) method using an abrasive (abrasive). The step of grinding the base electrode layer 121 may include a step of flattening the main insulating surface of the third insulating layer 15. As a result, the first via electrode 23 is formed within the first via hole 117. Further, a second via electrode 24 is formed within the second via hole 118.

Next, referring to FIG. 10H, the polishing agent (abrasive grains) adhering to the main insulating surface of third insulating layer 15 is removed by cleaning using a chemical solution. In this step, a part of the third insulating layer 15 is removed with a chemical solution together with the polishing agent (abrasive grains). As a result, a portion of the first via electrode 23 is formed as a first protrusion 23c that protrudes from the third insulating layer 15. Furthermore, a portion of the second via electrode 24 is formed as a second protrusion 24c that protrudes from the third insulating layer 15.

Next, referring to FIG. 10I, base resistance layer 124, which becomes the base of resistance layer 36, is formed on the main insulating surface of third insulating layer 15. Base resistance layer 124 includes chromium silicide. The base resistance layer 124 may include at least one of CrSi, CrSi ₂ , CrSiN, and CrSiO as an example of chromium silicide. In this form, the base resistance layer 124 is made of CrSi. Base resistance layer 124 may be formed by sputtering.

Next, a base protection layer 125 that becomes the base of the protection layer 40 is formed on the base resistance layer 124. Base protection layer 125 includes silicon oxide. The base protective layer 125 may be formed by a CVD method.
Next, the base resistance layer 124 (CrSi) is crystallized. The step of crystallizing the base resistance layer 124 includes an annealing process at a temperature and time such that the base resistance layer 124 (CrSi) is crystallized. The base resistance layer 124 may be heated at a temperature of 400° or more and 600° or less for 60 minutes or more and 120 minutes or less. The step of crystallizing the base resistance layer 124 may be performed after the step of forming the base resistance layer 124 and before the step of forming the protective layer 40.

Next, referring to FIG. 10J, a mask 126 having a predetermined pattern is formed on the base protective layer 125. The mask 126 has an opening 127 that covers a region of the base protective layer 125 where the protective layer 40 is to be formed and exposes the other region. Next, unnecessary portions of the base protective layer 125 are removed by etching through the mask 126. As a result, the protective layer 40 is formed.

Next, unnecessary portions of the base resistance layer 124 are removed by an etching method using the mask 126 and the protective layer 40 as masks. As a result, the resistance layer 36 is formed. Mask 126 is then removed. The mask 126 may be removed after the protective layer 40 is formed and before the resistive layer 36 is formed.
Next, referring to FIG. 10K, fourth insulating layer 16 covering protective layer 40 and thin film resistor 35 is formed on third insulating layer 15. The fourth insulating layer 16 may be formed by a CVD method.

Next, referring to FIG. 10L, the first via hole 128 that exposes the first lower wiring layer 41 and the second via hole 129 that exposes the second lower wiring layer 42 are connected to the third insulating layer 15 and the fourth insulating layer. Formed in layer 16.
In this step, first, a mask 130 having a predetermined pattern is formed on the fourth insulating layer 16. The mask 130 has a plurality of openings 131 that expose regions in the fourth insulating layer 16 where the first via hole 128 and the second via hole 129 are to be formed.

Next, unnecessary portions of the third insulating layer 15 and the fourth insulating layer 16 are removed by etching using the mask 130. As a result, a first via hole 128 and a second via hole 129 are formed in the third insulating layer 15 and the fourth insulating layer 16. Mask 130 is then removed.
Next, referring to FIG. 10M, a base electrode layer 132 that becomes the base of the first long via electrode 83 and the second long via electrode 84 is formed on the fourth insulating layer 16. The step of forming the base electrode layer 132 includes the step of forming a barrier layer 133 and a main body layer 134 in this order from above the fourth insulating layer 16.

The step of forming the barrier layer 133 includes a step of forming a Ti layer and a TiN layer in this order from above the fourth insulating layer 16. The Ti layer and the TiN layer may each be formed by sputtering. Forming the body layer 134 includes forming a tungsten layer on the barrier layer 133. The tungsten layer may be formed by CVD.
Next, referring to FIG. 10N, a step of removing base electrode layer 132 is performed. Base electrode layer 132 is removed until fourth insulating layer 16 is exposed. The step of removing base electrode layer 132 may include a step of removing base electrode layer 132 by grinding.

In this embodiment, the step of grinding the base electrode layer 132 is performed by a CMP method using an abrasive (abrasive). The step of grinding the base electrode layer 132 may include a step of planarizing the main insulating surface of the fourth insulating layer 16. As a result, the first long via electrode 83 and the second long via electrode 84 are formed in the first via hole 128 and the second via hole 129, respectively.

After the step of grinding the base electrode layer 132, the polishing agent (abrasive grains) attached to the main insulating surface of the fourth insulating layer 16 may be removed by cleaning using a chemical solution. A portion of the fourth insulating layer 16 may be removed together with a polishing agent (abrasive grains) using a chemical solution. In this case, a portion of the first long via electrode 83 may be formed as a protrusion that protrudes from the fourth insulating layer 16. Further, a portion of the second long via electrode 84 may be formed as a protrusion that protrudes from the fourth insulating layer 16.

Next, referring to FIG. 10O, a second base wiring layer 135 that becomes the base of the first upper wiring layer 61 and the second upper wiring layer 62 is formed on the fourth insulating layer 16. The step of forming the second base wiring layer 135 includes a step of forming a first barrier layer 136, a main body layer 137, and a second barrier layer 138 in this order from above the fourth insulating layer 16.
The step of forming the first barrier layer 136 includes a step of forming a Ti layer and a TiN layer in this order from above the fourth insulating layer 16. The Ti layer and the TiN layer may each be formed by sputtering. The process of forming the main body layer 137 includes forming an AlCu alloy layer on the first barrier layer 136. The AlCu alloy layer may be formed by sputtering.

The step of forming the second barrier layer 138 includes the step of forming a Ti layer and a TiN layer in this order from above the main body layer 137. The Ti layer and the TiN layer may each be formed by sputtering.
Next, referring to FIG. 10P, a mask 139 having a predetermined pattern is formed on the second base wiring layer 135. The mask 139 has an opening 140 in the outer region 7 that covers the region in the second base wiring layer 135 where the first upper wiring layer 61 and the second upper wiring layer 62 are to be formed, and exposes the other region. There is.

Next, unnecessary portions of the second base wiring layer 135 are removed by etching through the mask 139. As a result, the second base wiring layer 135 is divided into the first upper wiring layer 61 and the second upper wiring layer 62. Moreover, thereby, the insulating laminated structure 12 including the wiring circuit formation layer 21 and the resistance circuit formation layer 22 is formed on the first main surface 3 of the semiconductor layer 2. Mask 139 is then removed.

Next, referring to FIG. 10Q, a passivation layer 106 is formed over the insulating stack structure 12. Passivation layer 106 includes silicon nitride. Passivation layer 106 may be formed by a CVD method.
Next, referring to FIG. 10R, trimming marks 38 are formed in predetermined regions of the resistive layer 36 (see FIGS. 5, 6, and 8). In this step, a laser light irradiation step of irradiating the resistance layer 36 with laser light is performed. In this step, the resistive layer 36 is irradiated with a laser beam having energy enough to block the resistive layer 36, with the resistive layer 36 being focused.

The energy of the laser beam is adjusted to such an extent that the chromium silicide in the portion irradiated with the laser beam disappears and a plurality of conductive residues 39a detached from the resistance layer 36 are formed. As a result, trimming marks 38 are formed on the resistance layer 36. Further, in this step, an insulator 39b is formed to cover the plurality of conductive residues 39a.
Insulator 39b is interposed between resistance layer 36 and conductive residue 39a. The insulator 39b is interposed between the plurality of conductive residues 39a. The insulator 39b may include SiO ₂ formed from silicon of chromium silicide, or may include a melted portion of the protective layer 40. The insulator 39b increases the insulation between the resistive layer 36 and the plurality of conductive residues 39a.

The step of forming the trimming marks 38 includes the step of adjusting the resistance value of the resistance layer 36 in an increasing direction. Thereby, the resistance value of the resistance layer 36 is adjusted to a desired value. The resistance value of the resistance layer 36 is adjusted in an increasing direction depending on the number, shape, length, arrangement, etc. of the trimming marks 38.
Also, referring to FIG. 10S, chromium aggregates 37 are formed in predetermined regions of the resistance layer 36 (see FIGS. 5 to 7). In this step, a laser light irradiation step of irradiating the resistance layer 36 with laser light is performed. In the portion of the resistance layer 36 irradiated with the laser beam, the chromium silicide is melted, and the chromium contained in the chromium silicide aggregates into agglomerates. As a result, chromium aggregates 37 are formed in the resistance layer 36. The chromium aggregate 37 may contain a trace amount of silicon. A plurality of chromium aggregates 37 are formed in the portion irradiated with the laser beam.

The energy of the laser beam is adjusted to such an extent that the resistive layer 36 (chromium silicide) and the chromium aggregate 37 remain in a connected state without all of the chromium silicide in the laser beam irradiated area disappearing. In this step, a laser beam having energy capable of blocking the resistance layer 36 is irradiated onto the resistance layer 36 with its focus shifted from the resistance layer 36 .
Thereby, the chromium aggregate 37 can be formed using the same laser irradiation device as used in the process of forming the trimming marks 38. In other words, the step of forming the chromium aggregate 37 can be performed without using a new laser irradiation device.

The focus of the laser beam may be shifted downward with respect to the resistance layer 36 (toward the semiconductor layer 2 side), or may be shifted upward with respect to the resistance layer 36 (toward the fourth insulating layer 16 side). As a result, a plurality of chromium aggregates 37 are formed in the resistance layer 36.
The step of forming the chromium aggregate 37 includes the step of adjusting the resistance value of the resistance layer 36 in a decreasing direction. Thereby, the resistance value of the resistance layer 36 is adjusted to a desired value. The resistance value of the resistance layer 36 is adjusted to decrease depending on the proportion of the chromium aggregates 37 in the resistance layer 36. The proportion of the chromium aggregates 37 in the resistance layer 36 can be adjusted by moving the part of the resistance layer 36 irradiated with laser light.

By increasing the proportion of the chromium aggregates 37 in the resistance layer 36, the resistance value of the resistance layer 36 can be brought closer to the resistance value of chromium. On the contrary, by reducing the proportion of chromium aggregates 37 in the resistance layer 36, the resistance value of the resistance layer 36 can be brought closer to the resistance value of chromium silicide.
Before and after laser light irradiation, the planar area and thickness TR of the resistance layer 36 hardly change. Therefore, according to the laser irradiation method, the chromium aggregate 37 can be formed while suppressing the increase in size and thickness of the resistance layer 36. Moreover, according to the laser irradiation method, the proportion of the chromium aggregates 37 in the resistance layer 36 can be appropriately controlled. Thereby, the resistance value of the resistance layer 36 can be flexibly adjusted in the decreasing direction.

The plurality of chromium aggregates 37 may be formed over the entire area of the resistance layer 36, or may be formed in a partial region of the resistance layer 36. However, when forming a plurality of chromium aggregates 37 over the entire area of the resistance layer 36, it is necessary to irradiate the entire area of the resistance layer 36 with laser light, which increases manufacturing time. Furthermore, when forming a plurality of chromium aggregates 37 over the entire area of the resistance layer 36, it is more rational to form the thin film resistance 35 made of chromium. Therefore, the chromium aggregate 37 is preferably formed in such a manner that a portion of the resistance layer 36 remains.

The process order of the process of forming the trimming marks 38 (see FIG. 10R) and the process of forming the chromium aggregates 37 (see FIG. 10S) is arbitrary. After the step of forming the trimming marks 38, the step of forming the chromium aggregates 37 may be performed. In this case, the step of forming the chromium aggregate 37 may include a step of adjusting (finely adjusting) the resistance value increased in the step of forming the trimming marks 38 in a direction of decreasing it.

After the step of forming the chromium aggregates 37, a step of forming the trimming marks 38 may be performed. In this case, the step of forming the trimming marks 38 may include the step of adjusting (finely adjusting) the resistance value decreased in the step of forming the chromium aggregate 37 in the direction of increasing it.
The step of forming the trimming marks 38 and the step of forming the chromium aggregates 37 may be performed alternately multiple times in any order. After performing the step of forming the trimming marks 38 multiple times, the step of forming the chromium aggregates 37 may be performed multiple times. After performing the step of forming the chromium aggregate 37 multiple times, the step of forming the trimming marks 38 may be performed multiple times.

Next, referring to FIG. 10T, a photosensitive resin that will become resin layer 107 is applied onto passivation layer 106. The photosensitive resin may contain at least one of polyimide, polyamide, and polybenzoxazole. The photosensitive resin is preferably made of polyimide or polybenzoxazole. The photosensitive resin is then selectively exposed and developed. As a result, a resin layer 107 having a plurality of openings 141 serving as the bases of the first pad opening 102 and the second pad opening 103 is formed.

Next, referring to FIG. 10U, unnecessary portions of passivation layer 106 are removed by etching through resin layer 107. As a result, a first pad opening 102 and a second pad opening 103 are formed which expose the first upper wiring layer 61 and the second upper wiring layer 62, respectively. The electronic component 1 is manufactured through the steps including the above.
FIG. 11 is a schematic plan view showing an electronic component 151 according to the second embodiment of the present invention, in which the thin film resistor 35 according to the first embodiment is incorporated. Hereinafter, structures corresponding to those described for the electronic component 1 will be given the same reference numerals and their explanation will be omitted.

Electronic component 1 includes one resistance circuit 10 (thin film resistor 35) formed in outer region 7. On the other hand, referring to FIG. 11, electronic component 151 includes a plurality (two or more, in this embodiment, four) of resistor circuits 10 (thin film resistors 35) formed in outer region 7. The number of resistor circuits 10 (thin film resistors 35) is arbitrary, and five or more may be formed depending on the form of the functional device.

The plurality of resistance circuits 10 (thin film resistors 35) are each electrically connected to the device region 6 (functional device) via the wiring circuit formation layer 21. The plurality of resistance circuits 10 (thin film resistors 35) may be electrically connected to the device region 6 independently. At least two of the plurality of resistance circuits 10 (thin film resistors 35) may be connected to each other in parallel or in series.

In this embodiment, each of the plurality of resistance circuits 10 includes the thin film resistor 35 according to the first embodiment. However, each of the plurality of resistance circuits 10 may include any one of the thin film resistors 35 according to the first to seventh embodiments.
At least two of the plurality of resistance circuits 10 may include thin film resistors 35 having the same configuration. The plurality of resistance circuits 10 may include thin film resistors 35 according to different embodiments. The plurality of resistance circuits 10 may include a thin film resistor 35 having a configuration in which at least two of the features of the thin film resistor 35 according to the first to seventh embodiments are combined.

As described above, the electronic component 151 can also provide the same effects as those described for the electronic component 1.
Although embodiments of the invention have been described, embodiments of the invention may be implemented in other forms.
In each of the above-described embodiments, an example has been described in which one or more resistance circuits 10 (thin film resistors 35) are formed in the outer region 7. However, in each of the embodiments described above, one or more resistance circuits 10 (thin film resistors 35) may be formed in the device region 6.

Further, in each of the embodiments described above, one or more resistance circuits 10 (thin film resistors 35) may be formed in the device region 6 and the outer region 7, respectively. Furthermore, one or more resistance circuits 10 (thin film resistors 35) may be formed only in the device region 6 instead of in the outer region 7.
In each of the embodiments described above, an example was described in which the first upper wiring layer 61 and the second upper wiring layer 62 form the uppermost wiring layer of the insulating layered structure 12. However, the first upper wiring layer 61 and the second upper wiring layer 62 do not have to be the uppermost wiring layer of the insulating laminated structure 12. In this case, an insulating layer having a structure similar to that of the first to fourth insulating layers 13 to 16, the first lower wiring layer 41 (second lower wiring layer 42) and the first upper wiring layer 61 (second upper wiring layer 42), A wiring layer having a structure similar to layer 62) may be laminated on fourth insulating layer 16 in any manner and with any period.

In each of the above-described embodiments, an example has been described in which the thin film resistor 35 occupies the main insulating surface of the third insulating layer 15. However, in each of the embodiments described above, the wiring layer having the same structure as the first lower wiring layer 41 (second lower wiring layer 42) and the first upper wiring layer 61 (second upper wiring layer 62) is It may be formed on the main insulating surface of the third insulating layer 15. However, since such a structure may increase the number of manufacturing steps and make it difficult to ensure flatness, a structure in which the thin film resistor 35 occupies the main insulating surface of the third insulating layer 15 is preferable.

The electronic component 1 according to the first embodiment and the electronic component 151 according to the second embodiment may have the electrical structure shown in FIG. 12. FIG. 12 is a circuit diagram showing an electrical structure according to a first example of the electronic component 1 according to the first embodiment and the electronic component 151 according to the second embodiment.
Referring to FIG. 12, electronic component 1, 151 includes an operational amplifier circuit 201. The operational amplifier circuit 201 includes a positive power terminal 202, a negative power terminal 203, a non-inverting positive power terminal 204, an inverting positive power terminal 205, an output terminal 206, transistors TrA1 to TrA14 (semiconductor switching devices), and resistors RA1 to RA1. Includes RA4 (passive device).

A power supply voltage VDD is input to the positive power supply terminal 202 . A reference voltage VSS is input to the negative power supply terminal 203. The reference voltage VSS may be a ground voltage. A non-inverting voltage VIN+ is input to the non-inverting positive power supply terminal 204 . An inverted voltage VIN- is input to the inverted positive side power supply terminal 205. Operational amplifier circuit 201 amplifies the difference voltage between non-inverted voltage VIN+ and inverted voltage VIN-, and outputs it from output terminal 206. In other words, the operational amplifier circuit 201 is a differential operational amplifier circuit.

The transistors TrA1 to TrA14 are formed in the device region 6 of the semiconductor layer 2, respectively. That is, the functional device formed in device region 6 includes a circuit network formed by transistors TrA1 to TrA14. Each of the transistors TrA1 to TrA3 and TrA7 to TrA10 is a p-type MISFET. Each of the transistors TrA4 to TrA6 and TrA11 to TrA14 is an n-type MISFET.

On the other hand, the resistors RA1 to RA4 are formed in the outer region 7 of the semiconductor layer 2. At least one or all of the resistors RA1 to RA4 are formed by a thin film resistor 35. The resistors RA1 to RA4 form current value setting resistors and determine the current amplification factor. The resistors RA1 to RA4 are selectively connected to the circuit network formed by the transistors TrA1 to TrA14 via the wiring circuit formation layer 21 (the connection wiring layer 96 and the connection via electrode 97).

A bias voltage Vb1 is input to the gate of the transistor TrA1. The drain of the transistor TrA1 is connected to the positive power supply terminal 202. The source of the transistor TrA1 is connected to the source of the transistor TrA2 and the source of the transistor TrA3. The gate of the transistor TrA2 is connected to the non-inverting positive power supply terminal 204. The gate of the transistor TrA3 is connected to the inverted positive power supply terminal 205.

Bias voltage Vb2 is input to the gate of transistor TrA4. The drain of the transistor TrA4 is connected to the source of the transistor TrA5 and the source of the transistor TrA6.
The source of the transistor TrA4 is connected to the negative power supply terminal 203. The gate of the transistor TrA5 is connected to the non-inverting positive power supply terminal 204. The gate of the transistor TrA6 is connected to the inverted positive power supply terminal 205.

The gate of transistor TrA7 is connected to the gate of transistor TrA8. Bias voltage Vb3 is input to the gate of transistor TrA7 and the gate of transistor TrA8. The source of the transistor TrA7 is connected to the positive power supply terminal 202 via the resistor RA1.
The drain of the transistor TrA7 is connected to the source of the transistor TrA9. The source of the transistor TrA8 is connected to the positive power supply terminal 202 via a resistor RA2. The drain of the transistor TrA8 is connected to the source of the transistor TrA10.

The gate of transistor TrA9 is connected to the gate of transistor TrA10. A bias voltage Vb4 is input to the gate of the transistor TrA9 and the gate of the transistor TrA10.
The drain of the transistor TrA9 is connected to the drain of the transistor TrA11. The drain of the transistor TrA10 is connected to the drain of the transistor TrA12.

The drain of the transistor TrA6 is connected to the connection between the drain of the transistor TrA7 and the source of the transistor TrA9. The drain of the transistor TrA5 is connected to the connection between the drain of the transistor TrA8 and the source of the transistor TrA10.
The gate of the transistor TrA11 is connected to the gate of the transistor TrA12. A bias voltage Vb5 is input to the gate of the transistor TrA11 and the gate of the transistor TrA12.

The source of the transistor TrA11 is connected to the drain of the transistor TrA13. The source of the transistor TrA12 is connected to the drain of the transistor TrA14.
The gate of the transistor TrA13 is connected to the gate of the transistor TrA14. The gate of the transistor TrA13 and the gate of the transistor TrA14 are connected to the drain of the transistor TrA11.

The source of the transistor TrA13 is connected to the negative power supply terminal 203 via a resistor RA3. The source of the transistor TrA14 is connected to the negative power supply terminal 203 via a resistor RA4.
In this embodiment, an example has been described in which the operational amplifier circuit 201 includes transistors TrA1 to TrA6. However, the operational amplifier circuit 201 without the transistors TrA1 to TrA3 may be employed, or the operational amplifier circuit 201 without the transistors TrA4 to TrA6 may be employed.

The electronic component 1 according to the first embodiment and the electronic component 151 according to the second embodiment may have the electrical structure shown in FIG. 13. FIG. 13 is a circuit diagram showing an electrical structure according to a second example of the electronic component 1 according to the first embodiment and the electronic component 151 according to the second embodiment.
Referring to FIG. 13, electronic component 1, 151 includes a current amplification type constant current regulator 211. Constant current regulator 211 includes a positive power terminal 212, a negative power terminal 213, an output terminal 214, transistors TrB1 to TrB12 (semiconductor switching devices), resistors RB1 to RB3 (passive devices), and a capacitor C (passive device).

A power supply voltage VDD is input to the positive power supply terminal 212 . A reference voltage VSS is input to the negative power supply terminal 213. The reference voltage VSS may be a ground voltage. Constant current regulator 211 outputs a constant current from output terminal 214 according to the potential difference between power supply voltage VDD and reference voltage VSS.
Transistors TrB1 to TrB12, resistors RB1 and RB3, and capacitor C are each formed in device region 6 in semiconductor layer 2. That is, the functional device formed in device region 6 includes a circuit network formed by transistors TrB1 to TrB12, resistors RB1 and RB3, and capacitor C.

Each of the transistors TrB1 to TrB4 and TrB7 is an n-type MISFET. The transistors TrB5 and TrB6 each consist of an npn type BJT. Each of the transistors TrB8 to TrB12 is a p-type MISFET. The resistors RB1 and RB3 may each be formed of a polysilicon resistor.
The resistor RB2 is formed in the outer region 7 of the semiconductor layer 2. The resistor RB2 is formed by a thin film resistor 35. The resistor RB2 forms a current value setting resistor and determines the current amplification factor. Resistor RB2 is selectively connected to a circuit network formed by transistors TrB1 to TrB12, resistors RB1, RB3, and capacitor C via wiring circuit formation layer 21 (connection wiring layer 96 and connection via electrode 97).

The gate of the transistor TrB1 is connected to the gate of the transistor TrB2. The gate of the transistor TrB1 and the gate of the transistor TrB2 are connected to the drain of the transistor TrB1.
The drain of the transistor TrB1 is connected to the positive power supply terminal 212 via the resistor RB1. The source of the transistor TrB1 is connected to the negative power supply terminal 213. The source of the transistor TrB2 is connected to the source of the transistor TrB1.

The gate of transistor TrB3 is connected to the gate of transistor TrB4. The gate of transistor TrB3 and the gate of transistor TrB4 are connected to the drain of transistor TrB3.
The source of the transistor TrB3 is connected to the negative power supply terminal 213. The drain of the transistor TrB2 is connected to the gate of the transistor TrB1 and the gate of the transistor TrB2. The source of the transistor TrB4 is connected to the negative power supply terminal 213.

The base of transistor TrB5 is connected to the base of transistor TrB6. The base of the transistor TrB5 and the base of the transistor TrB6 are connected to the collector of the transistor TrB5. The emitter of transistor TrB5 is connected to negative power supply terminal 213 via resistor RB2. The emitter of the transistor TrB6 is connected to the negative power supply terminal 213.

The gate of transistor TrB7 is connected to the collector of transistor TrB6. The drain of the transistor TrB7 is connected to the drain of the transistor TrB2. The source of the transistor TrB7 is connected to the negative power supply terminal 213.
The resistor RB3 forms an RC series circuit 215 with the capacitor C. RC series circuit 215 is connected between the gate of transistor TrB7 and negative power supply terminal 213.

The gates of transistors TrB8 to TrB12 are connected to each other. The gates of transistors TrB8 to TrB12 are each connected to the gate of transistor TrB7. The drains of the transistors TrB8 to TrB12 are connected to the positive power supply terminal 212, respectively.
The source of the transistor TrB8 is connected to the drain of the transistor TrB3. The source of the transistor TrB9 is connected to the collector of the transistor TrB5. The source of the transistor TrB10 is connected to the collector of the transistor TrB6.

The source of the transistor TrB11 is connected to the gates of the transistors TrB8, TrB9, TrB10, and TrB12 and the drain of the transistor TrB7. The source of the transistor TrB12 is connected to the output terminal 214.
In addition, various design changes can be made within the scope of the claims.

1 Electronic component 2 Semiconductor layer 3 First main surface 6 Device region 7 Outer region 12 Insulating laminated structure 15 Third insulating layer 35 Thin film resistor 36 Resistance layer 37 Chromium aggregate 38 Trimming trace 151 Electronic component TR Thickness WC Width

Claims (13)

providing a resistive layer containing chromium silicide;
By irradiating a partial region of the resistive layer with a laser beam and causing chromium to aggregate in the portion of the resistive layer irradiated with the laser beam, a chromium agglomerate consisting of agglomerates of chromium is formed in a partial region of the resistive layer. A method of manufacturing a thin film resistor, comprising: forming a thin film resistor in a region. The step of forming the chromium aggregate includes using a laser beam having an energy capable of blocking the resistive layer, and irradiating the resistive layer with the laser beam from a direction crossing the resistive layer and with a shifted focus. The method for manufacturing a thin film resistor according to claim 1, which is carried out by: 3. The method of manufacturing a thin film resistor according to claim 1, wherein the step of forming the chromium aggregate includes forming a plurality of the chromium aggregates on the resistance layer by irradiating the resistor layer with the laser beam. The thin film resistor according to any one of claims 1 to 3, wherein the step of forming the chromium aggregates includes forming the chromium aggregates into particles or layers by irradiating the laser beam. Production method. Any one of claims 1 to 4, wherein the step of forming the chromium aggregate includes forming a chromium aggregate having a width exceeding the thickness of the resistance layer by irradiating the laser beam. The method for manufacturing a thin film resistor described in . 6. The method for manufacturing a thin film resistor according to claim 1, wherein in the step of preparing the resistance layer, a resistance layer having a thickness of 1 μm or less is prepared. The step of forming the chromium aggregate includes adjusting the irradiation area of the laser beam,
The method for manufacturing a thin film resistor according to any one of claims 1 to 6, comprising the step of adjusting the resistance value of the resistance layer in a direction of decreasing. The method for manufacturing the thin film resistor includes:
A laser beam having an energy capable of blocking the resistive layer is used, and the laser beam is focused on the resistive layer from a direction crossing the resistive layer to form trimming marks on the resistive layer. The method for manufacturing a thin film resistor according to any one of claims 1 to 7, comprising the step of adjusting the resistance value of the resistance layer in a direction of increasing it. a semiconductor layer;
a thin film resistor disposed on the semiconductor layer,
The thin film resistor is
a conductive resistance region containing chromium silicide and having a first resistance;
a conductive low-resistance region connected to the resistance region and having a second resistance less than the first resistance, the conductive low-resistance region including a chromium agglomerate consisting of an agglomerate of chromium and a chromium silicide; the low resistance region having a higher proportion of chromium aggregates than the resistance region. The semiconductor layer includes a device region including a functional device and an outer region outside the device region,
The electronic component according to claim 9, wherein the thin film resistor is formed in the outer region. further comprising an insulating layer formed on the semiconductor layer and having an insulating main surface,
The electronic component according to claim 9 or 10, wherein the thin film resistor is formed on the insulating main surface. formed on the semiconductor layer , having an insulating stacked structure in which a plurality of insulating layers are stacked;
The electronic component according to claim 9, wherein the thin film resistor is formed within the insulating layered structure. a first wiring on the high voltage side formed within the insulating layered structure;
further comprising a second wiring on the low voltage side formed in the insulating laminate structure,
The electronic component according to claim 12, wherein the thin film resistor is connected between the first wiring and the second wiring.

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