CN116783689A - Electronic component - Google Patents

Abstract

The electronic component includes: a chip having a main surface; an insulating layer laminated on the main surface with a thickness exceeding 2200nm, and having a first end on the chip side and a second end on the opposite side of the chip; and a resistive film which is disposed within the insulating layer so as not to be located within a thickness range of less than 2200nm with respect to the first end, and which includes an alloy crystal composed of a metal element and a non-metal element.

Description

Electronic component

Technical Field

The present application corresponds to Japanese patent application No. 2021-002263 filed on 1/8/2021 and Japanese patent application No. 2021-073596 filed on 4/2021, the disclosures of which are incorporated herein by reference in their entirety. The present application relates to an electronic component.

Background

Patent document 1 discloses an integrated SiCr metal thin film resistor including a dielectric substrate and a SiCr film formed on the dielectric substrate.

Prior art literature

Patent literature

Patent document 1: international publication No. 2006/035377

Disclosure of Invention

Problems to be solved by the application

An embodiment provides an electronic component capable of improving reliability of a resistive film including an alloy crystal composed of a metal element and a non-metal element.

Means for solving the problems

One embodiment provides an electronic component comprising: a chip having a main surface; an insulating layer laminated on the main surface; a resistive film disposed within the insulating layer and including an alloy crystal composed of a metal element and a non-metal element, the resistive film having a first end portion on one side and a second end portion on the other side; a first wiring interposed between the main surface and the first end portion within the insulating layer; a second wiring interposed between the main surface and the second end portion in the insulating layer so as to be separated from the first wiring; and an insulating region which is divided in the insulating layer into a region between the first wiring and the second wiring and is formed only of an insulator portion in the insulating layer in a thickness range between the main surface and the resistive film.

One embodiment provides an electronic component comprising: a chip having a main surface; an insulating layer laminated on the main surface; a resistive film disposed within the insulating layer and including an alloy crystal composed of a metal element and a non-metal element; and a plurality of top wirings which are arranged on the insulating layer at intervals from the periphery of the resistor film to a region outside the resistor film so as not to overlap the resistor film in a plan view.

One embodiment provides an electronic component comprising: a chip having a main surface; an insulating layer laminated on the main surface with a thickness exceeding 2200nm, and having a first end on the chip side and a second end on the opposite side of the chip; and a resistive film which is disposed within the insulating layer so as not to be located within a thickness range of less than 2200nm with respect to the first end, and which includes an alloy crystal composed of a metal element and a non-metal element.

One embodiment provides an electronic component comprising: a chip having a main surface; an insulating layer laminated on the main surface with a thickness exceeding 2200nm, and having a first end on the chip side and a second end on the opposite side of the chip; an insulating region having only an insulator in a thickness direction of the insulating layer and formed within the insulating layer with a thickness of 2200nm or more; and a resistive film that is disposed in the insulating layer in a region between the second end and the insulating region so as to directly cover the insulating region, and that includes an alloy crystal composed of a metal element and a non-metal element.

The above and other objects, features and effects of the present invention will become apparent from the embodiments described with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic plan view showing an electronic component according to a first embodiment.

Fig. 2 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with the resistive film according to the first embodiment.

Fig. 3 is an enlarged view of the region III shown in fig. 2.

Fig. 4 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with a resistive film according to a second embodiment.

Fig. 5 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with a resistive film according to a third embodiment.

Fig. 6 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with a resistive film of a fourth embodiment.

Fig. 7 is a graph showing sheet resistance of the resistive film.

Fig. 8 is a graph showing the coefficient of temperature resistance coefficient of the resistor film 1 st order.

Fig. 9 is a graph showing the coefficient of temperature resistance of the resistor film by the factor of 2.

Fig. 10 is a cross-sectional view showing an electronic component (=a mode in which the arrangement position and connection form of the resistive film are changed in the electronic component of the first embodiment) of the second embodiment, corresponding to fig. 2.

Fig. 11 is a cross-sectional view showing an electronic component (=a mode in which the connection mode of the resistive film is changed in the electronic component of the first embodiment) of the third embodiment, corresponding to fig. 2.

Fig. 12 is a cross-sectional view showing an electronic component (=a mode in which the arrangement position and connection form of the resistive film are changed in the electronic component of the third embodiment) of the fourth embodiment, corresponding to fig. 2.

Fig. 13 is a cross-sectional view showing an electronic component according to a fifth embodiment (=an embodiment in which the form of an insulating region is changed in the electronic component according to the first embodiment) corresponding to fig. 2.

Fig. 14 is a schematic plan view showing an electronic component according to a sixth embodiment.

Fig. 15 is an enlarged view showing the region XV shown in fig. 14 together with the resistive film of the first pattern.

Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in fig. 15.

Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in fig. 15.

Fig. 18A is an enlarged view showing the region XV shown in fig. 14 together with the resistive film of the second pattern.

Fig. 18B is an enlarged view showing the region XV shown in fig. 14 together with the third pattern of the resistive film.

Fig. 18C is an enlarged view showing the region XV shown in fig. 14 together with the resistance film of the fourth pattern.

Fig. 19 is a graph showing sheet resistance of the resistive film shown in fig. 15.

Fig. 20 is a graph showing the coefficient of resistance temperature coefficient of the resistive film shown in fig. 15, 1 st order.

Fig. 21 is a graph showing the coefficient of resistance temperature coefficient of the resistive film shown in fig. 15 by the factor of 2.

Detailed Description

The drawings are schematic and are not necessarily to scale, nor do they necessarily correspond to scale. Fig. 1 is a schematic plan view showing an electronic component 1 according to a first embodiment. Fig. 2 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with the resistive film 8 according to the first embodiment. Fig. 3 is an enlarged view of the region III shown in fig. 2.

Referring to fig. 1 to 3, in the present embodiment, an electronic component 1 is a semiconductor device including various functional devices utilizing semiconductor properties. The electronic component 1 includes a semiconductor chip 2 (chip) formed in a rectangular parallelepiped shape. The semiconductor chip 2 has a relatively high first thermal conductivity K1. The semiconductor chip 2 may be constituted by a Si (silicon) chip or a WBG (wide band gap) semiconductor chip. WBG semiconductors are semiconductors having a bandgap exceeding the Si bandgap.

The WBG semiconductor chip may be composed of a SiC chip, a GaN chip, or a GaAs chip. In the present embodiment, the semiconductor chip 2 is constituted by a Si chip, and has a first thermal conductivity K1 (≡160wm·k) caused by Si. The semiconductor chip 2 includes: a first main surface 2a on one side, a second main surface 2b on the other side, and a side surface 2c connecting the first main surface 2a and the second main surface 2 b. The first main surface 2a and the second main surface 2b are formed in a quadrangular shape in plan view as viewed from the normal direction thereof.

The electronic component 1 comprises a device region 3 arranged on the first main face 2 a. The device region 3 is divided in the interior of the first main surface 2a at a distance from the side surface 2c in a plan view. The number, arrangement, and shape of the device regions 3 are arbitrary, and are not limited to a specific number, arrangement, and shape. The electronic component 1 includes a functional device formed in the device region 3. The functional device may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device.

The semiconductor switching device may include at least one of JFET (Junction Field Effect Transistor), MISFET (Metal Insulator Semiconductor Field Effect Transistor), BJT (Bipolar Junction Transistor), and IGBT (Insulated Gate Bipolar Junction Transistor).

The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a zener diode, a schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse. The functional device may include a circuit network (for example, an integrated circuit such as an LSI) formed by selectively combining at least two devices among a semiconductor switching device, a semiconductor rectifying device, and a passive device.

The electronic component 1 comprises an outer region 4 arranged on the first main surface 2 a. The outer region 4 is an outer region of the device region 3. The outer region 4 is a region that does not include a functional device on the first main surface 2a, and is divided into any shape and any number at any position on the first main surface 2 a. In this embodiment, the outer region 4 is divided on the first main surface 2a into a region between the side surface 2c and the device region 3. When the plurality of device regions 3 are divided in the first main surface 2a, the outer region 4 may also be divided in a region between the plurality of device regions 3.

The electronic component 1 includes an insulating layer 5 laminated on the first main surface 2 a. The insulating layer 5 covers the device region 3 and the outside region 4. That is, the insulating layer 5 has a region covering the functional device and a region not covering the functional device. The insulating layer 5 has a second thermal conductivity K2 (K1 < K2) smaller than the first thermal conductivity K1 of the semiconductor chip 2. That is, the insulating layer 5 has higher heat storage than the semiconductor chip 2.

The insulating layer 5 contains at least one of silicon oxide and silicon nitride. That is, the insulating layer 5 has at least one of a thermal conductivity (1.3 wm·k) due to silicon oxide and a thermal conductivity (29.3 wm·k) due to silicon nitride, and a second thermal conductivity K2. In this embodiment, the insulating layer 5 is made of silicon oxide, and has a second thermal conductivity K2 (≡1.3wm·k) due to silicon oxide.

The insulating layer 5 has: a first end 5a on one side in the thickness direction (the semiconductor chip 2 side), a second end 5b on the other side in the thickness direction (the opposite side to the semiconductor chip 2), and an insulating side surface 5c connecting the first end 5a and the second end 5 b. The first end 5a is connected to the semiconductor chip 2 (first main surface 2 a). The second end 5b is formed flat so as to extend substantially parallel to the first main surface 2a, and is formed in a quadrangular shape that matches the first main surface 2a in plan view. The insulating side surface 5c extends from the periphery of the second end 5b toward the semiconductor chip 2 side, and is connected to the side surface 2c of the semiconductor chip 2.

The insulating layer 5 has a predetermined thickness TA. The thickness TA is the distance between the first end 5a and the second end 5 b. The thickness TA exceeds 2200nm. The upper limit value of the thickness TA is adjusted according to the specifications of the functional device, and is set to a value that does not interfere with the formation process time of the insulating layer 5. The thickness TA may have any one of an upper limit value of 30000nm or less, 25000nm or less, 20000nm or less, 15000nm or less, 10000nm or less, and 5000nm or less. The thickness TA is preferably set to 3000nm to 10000 nm. In this embodiment, the thickness TA is 4500nm.

The insulating layer 5 has: a laminated structure including a plurality of interlayer insulating films 6 laminated on the first main surface 2 a. A plurality of interlayer insulating films 6 are laminated on the first main surface 2a by CVD (chemical vapor deposition) method. The number of layers of the interlayer insulating film 6 is arbitrary and is not limited to a specific number of layers, as long as the insulating layer 5 has the above thickness TA (2200 nm < TA). The number of layers of the interlayer insulating film 6 is set to a general value that does not interfere with the formation process time of the insulating layer 5. As an example, the number of layers of the interlayer insulating film 6 may be 2 or more and 25 or less. The number of layers of the interlayer insulating film 6 is preferably 2 or more and 10 or less.

The insulating layer 5 preferably has: a laminated structure including 3 or more interlayer insulating films 6. The insulating layer 5 particularly preferably has: a laminated structure including 4 or more interlayer insulating films 6. In this embodiment, the insulating layer 5 includes: comprises a laminated structure of 6 layers of insulating films 6. The 6-layer laminated insulating film 6 includes, in order from the first main surface 2a side: a first interlayer insulating film 6A, a second interlayer insulating film 6B, a third interlayer insulating film 6C, a fourth interlayer insulating film 6D, a fifth interlayer insulating film 6E, and a sixth interlayer insulating film 6F.

The plurality of interlayer insulating films 6 may each include at least one of a silicon oxide film and a silicon nitride film. In this embodiment, each of the plurality of interlayer insulating films 6 has a single-layer structure composed of a silicon oxide film. Thereby, the insulating layer 5 made of silicon oxide is formed. The plurality of interlayer insulating films 6 may have a thickness of 100nm or more and 3000nm or less, respectively. The plurality of interlayer insulating films 6 preferably have a thickness of 300nm or more and 1500nm or less, respectively. The plurality of interlayer insulating films 6 may have different thicknesses from each other or may have equal thicknesses from each other.

The electronic component 1 includes an insulating region 7 formed in an arbitrary region within the insulating layer 5. The insulating region 7 is a region having no conductor film (metal film or the like) but only an insulator in the thickness direction of the insulating layer 5. In this embodiment, the insulating region 7 is formed in the insulating layer 5 at a portion covering the outer region 4. That is, the insulating region 7 covers the outside region 4 outside the device region 3, and does not cover the functional device. In other words, the functional device is not formed under the insulating region 7.

In the present embodiment, the insulating region 7 is formed to a thickness direction intermediate portion of the insulating layer 5 toward the second end 5b with reference to the first end 5a (first main surface 2 a) (zero point). In the present embodiment, the insulating region 7 has a laminated structure including a part of the plurality of interlayer insulating films 6 (first to fifth interlayer insulating films 6A to 6E in the present embodiment).

The insulating region 7 has a prescribed insulating thickness TB in the thickness direction of the insulating layer 5. The insulation thickness TB is set to 2200nm or more. The upper limit value of the insulating thickness TB is smaller than the thickness TA of the insulating layer 5 (TB < TA). The insulation thickness TB may have any upper limit value of less than 30000nm, 25000nm or less, 20000nm or less, 15000nm or less, 10000nm or less, and 5000nm or less. When the thickness TA of the insulating layer 5 exceeds 3100nm, the insulating thickness TB is preferably set to 3100nm or more. In this embodiment, the insulation thickness TB is set to 3900nm.

The electronic component 1 includes a resistive film 8 disposed within the insulating layer 5. The resistive film 8 is a so-called sheet resistor. The resistive film 8 contains an alloy crystal composed of a metal element and a non-metal element. The resistive film 8 is formed through a sputtering process and a crystallization process. In the sputtering step, an alloy containing a metal element and a non-metal element is scattered on the interlayer insulating film 6 to be film-formed by a sputtering method. Thereby, a base alloy film serving as a base of the resistor film 8 is formed on the interlayer insulating film 6 to be formed. The base alloy film after film formation is in an amorphous state.

In the crystallization process, the base alloy film is heated at a temperature (for example, a temperature of 300 ℃ or higher and 500 ℃ or lower) and for a time period at which the base alloy film is crystallized. Thereby, the resistive film 8 composed of the alloy crystal film is formed. The crystallization temperature and crystallization time of the base alloy film are set to a temperature and time that do not interfere with the electrical characteristics of the functional device. The sheet resistance Rs of the resistive film 8 is determined by the sheet resistance Rs of the alloy crystal film produced through the crystallization step.

The type of alloy crystal constituting the resistive film 8 is arbitrary as long as the crystallization step can be performed. As an example, the resistor film 8 may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the resistor film 8 has a single-layer structure made of a CrSi film. The resistive film 8 may also be referred to as a "CrSi resistive film". The content of the metal (Cr) with respect to the total weight of the resistive film 8 (CrSi film) may be 5wt% or more and 50wt% or less.

The resistive film 8 may have a thickness of 0.1nm or more and 100nm or less. The lower limit of the thickness of the resistive film 8 is preferably 0.5nm or more. The lower limit of the thickness of the resistive film 8 is most preferably 1nm or more. The upper limit of the thickness of the resistive film 8 is preferably 10nm or less. The upper limit of the thickness of the resistive film 8 is most preferably 5nm or less. The sheet resistance Rs of the resistive film 8 may be 100 Ω/∈s or more and 50000 Ω/∈s or less. The sheet resistance Rs is preferably 1000 Ω/≡or more and 10000 Ω/≡or less. The sheet resistance Rs is adjusted by adjusting the thickness of the resistive film 8, the planar area of the resistive film 8, the content of metal, and the like.

The resistor film 8 is preferably disposed on the interlayer insulating film 6 (any one of the third to fifth interlayer insulating films 6C to 6E) of the third layer or more, but is not disposed on the interlayer insulating film 6 (the first to second interlayer insulating films 6A to 6B) smaller than the third layer. The resistor film 8 is particularly preferably disposed on the interlayer insulating film 6 (any one of the fourth to fifth interlayer insulating films 6D to 6E) of the fourth layer or more, but not on the interlayer insulating film 6 (the first to third interlayer insulating films 6A to 6C) smaller than the fourth layer.

In this embodiment, the resistor film 8 is disposed on the fifth interlayer insulating film 6E and covered with the sixth interlayer insulating film 6F. The resistor film 8 is preferably an interlayer insulating film 6 (fifth interlayer insulating film 6E in this embodiment) which is an object of film formation exclusively. That is, the conductor film (metal film) other than the resistive film 8 is preferably not disposed in the same layer as the resistive film 8.

The resistor film 8 is disposed in the insulating layer 5 in a region between the second end 5b and the insulating region 7, and covers the insulating region 7. The resistive film 8 preferably directly covers the insulating region 7. That is, the resistive film 8 is preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 2200nm with respect to the first end 5a (first main surface 2 a). The resistive film 8 is particularly preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 3100nm with respect to the first end 5a (first main surface 2 a).

In this embodiment, the resistive film 8 is disposed in the insulating layer 5 so as not to be located in a thickness range of less than 3900nm with respect to the first end 5a (first main surface 2 a). The thickness (insulation thickness TB) between the first end 5a (first main surface 2 a) and the resistive film 8 in the insulating layer 5 is preferably equal to or greater than the thickness between the second end 5b and the resistive film 8 in the insulating layer 5. In this embodiment, the insulation thickness TB exceeds the thickness between the second end 5b and the resistive film 8.

The resistive film 8 faces the first main surface 2a through the insulating region 7. That is, the resistive film 8 includes the following portions: a portion of the insulating layer 5 facing the first main surface 2a is located between the regions where the conductor film (metal film) is not disposed. In addition, the resistive film 8 includes the following portions: a portion facing the outer region 4 via the insulating region 7 and not facing the functional device. In this embodiment, the resistive film 8 is not opposed to the functional device in the thickness direction of the insulating layer 5. The planar shape of the resistive film 8 is arbitrary. The resistive film 8 may have a square shape, a rectangular shape (a strip shape), a polygonal shape, a zigzag shape (a zigzag shape), or a shape in which they are selectively combined in plan view.

The electronic component 1 includes: an inorganic insulating film 9 covering the resistive film 8 in the insulating layer 5. The inorganic insulating film 9 is disposed in a region between the resistive film 8 and the interlayer insulating film 6 (in this embodiment, the sixth interlayer insulating film 6F), and faces the insulating region 7 through the resistive film 8. The inorganic insulating film 9 preferably covers the entire area of the resistive film 8. In this embodiment, the inorganic insulating film 9 has a planar shape matching the planar shape of the resistive film 8. The inorganic insulating film 9 may contain at least one of a silicon oxide film and a silicon nitride film. In this embodiment, the inorganic insulating film 9 has a single-layer structure made of a silicon oxide film.

The electronic component 1 includes: a plurality of interlayer wires 10 are stacked in the insulating layer 5 within a thickness range of the first end 5a and the second end 5 b. The plurality of interlayer wirings 10 are electrically connected to the corresponding functional device and/or the resistive film 8, respectively. The plurality of interlayer wirings 10 may electrically connect the plurality of functional devices to each other. The plurality of interlayer wirings 10 may electrically connect the resistive film 8 to any functional device. The arrangement and routing pattern of the plurality of interlayer wirings 10 are arbitrary.

In this embodiment, the plurality of interlayer wires 10 are stacked in the insulating layer 5 within a thickness range between the first end 5a and the resistive film 8, and are not stacked in the insulating layer 5 within a thickness range between the second end 5b and the resistive film 8. The plurality of interlayer wirings 10 are disposed on the corresponding interlayer insulating film 6, respectively. That is, the plurality of interlayer wirings 10, the plurality of interlayer insulating films 6, and the resistor film 8 form a multilayer wiring structure. The number of layers of the plurality of interlayer wirings 10 is adjusted according to the number of layers of the interlayer insulating film 6. In this embodiment, the plurality of interlayer wirings 10 includes: at least one first interlayer wiring 10A, at least one second interlayer wiring 10B, at least one third interlayer wiring 10C, and at least one fourth interlayer wiring 10D.

The first interlayer wiring 10A is disposed on the first interlayer insulating film 6A and covered with the second interlayer insulating film 6B. The second interlayer wiring 10B is disposed on the second interlayer insulating film 6B and covered with the third interlayer insulating film 6C. The third interlayer wiring 10C is disposed on the third interlayer insulating film 6C and covered with the fourth interlayer insulating film 6D. The fourth interlayer wiring 10D is disposed on the fourth interlayer insulating film 6D and covered with the fifth interlayer insulating film 6E. The plurality of interlayer wirings 10 are not disposed on the interlayer insulating film 6 (the fifth interlayer insulating film 6E in this embodiment) on which the resistive film 8 is disposed.

The plurality of interlayer wirings 10 includes a first lower wiring 11 and a second lower wiring 12 for the resistive film 8. The first lower wiring 11 is disposed directly under one end of the resistive film 8. One end of the resistive film 8 is referred to as an electrical connection. In this embodiment, the first lower wiring 11 is constituted by one of the fourth interlayer wirings 10D. The first lower wiring 11 is arranged along the insulating region 7 so as to divide the insulating region 7 in a plan view.

The second lower wiring 12 is arranged directly below the other end of the resistive film 8. The other end of the resistive film 8 is referred to as an electrical connection terminal. The second lower wiring 12 is arranged on the same layer as the first lower wiring 11 with a space from the first lower wiring 11. In this embodiment, the second lower wiring 12 is constituted by one of the fourth interlayer wirings 10D. The second lower wiring 12 is arranged along the insulating region 7 in a manner to divide the insulating region 7 in a plan view. The second lower wiring 12 is opposed to the first lower wiring 11 across the insulating region 7 in a plan view. In such a structure, the resistive film 8 covers the insulating region 7 and is disposed in the insulating layer 5 so as to overlap the first lower wiring 11 and the second lower wiring 12 in a plan view.

The plurality of interlayer wirings 10 each have a thickness exceeding the thickness of the resistive film 8. The plurality of interlayer wirings 10 each have: the semiconductor device includes a laminated structure including a first barrier film 13, a main body film 14, and a second barrier film 15 laminated in this order from the semiconductor chip 2 side. The first barrier film 13 is made of a Ti-based metal film. The first barrier film 13 may also have: a laminated structure including a Ti film 16 and a TiN film 17 laminated in this order from the semiconductor chip 2 side.

The main body film 14 is made of an Al-based metal film or a Cu-based metal film, and has a thickness exceeding the thickness of the first barrier film 13. The body film 14 may include at least one of a pure Al film (an Al film having a purity of 99% or more), a pure Cu film (an Al film having a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The second barrier film 15 is made of a Ti-based metal film, and has a thickness smaller than that of the main body film 14. The second barrier film 15 may have: a laminated structure including a Ti film 18 and a TiN film 19 laminated in this order from the main body film 14 side.

The electronic component 1 includes a plurality of via electrodes 20 disposed in an insulating layer 5. The plurality of via electrodes 20 are electrically connected to any two interlayer wirings 10 facing each other in the thickness direction. The plurality of via electrodes 20 includes a first via electrode 21 and a second via electrode 22 for the resistive film 8. The first via electrode 21 is interposed between one end of the resistive film 8 and the first lower wiring 11, and is electrically connected to one end of the resistive film 8 and the first lower wiring 11. The second via electrode 22 is interposed between the other end of the resistive film 8 and the second lower wiring 12, and is electrically connected to the other end of the resistive film 8 and the second lower wiring 12.

The upper end portions of the first via electrodes 21 and the upper end portions of the second via electrodes 22 may protrude from the main surface of the corresponding interlayer insulating film 6 (the main surface of the fifth interlayer insulating film 6E in this embodiment). In this case, the resistive film 8 may be formed in a film shape along the upper end portions (a part of the main surface and the side wall) of the first via electrode 21 and the upper end portions (a part of the main surface and the side wall) of the second via electrode 22, and may have a ridge portion caused by the upper end portions of the first via electrode 21 and the upper end portions of the second via electrode 22.

The plurality of via electrodes 20 each have: comprises a laminated structure of a through hole barrier film 24 and a through hole main body 25 laminated in this order from the inner wall of a through hole 23 formed in a corresponding interlayer insulating film 6. The through-hole blocking film 24 is formed in a film shape along the inner wall of the through-hole 23, and a groove is defined in the through-hole 23. The via blocking film 24 is made of a Ti-based metal film. The via blocking film 24 may have: a laminated structure including a Ti film 26 and a TiN film 27 laminated in this order from the inner wall of the through hole 23. The through-hole main body 25 is embedded in the through-hole 23 via the through-hole blocking film 24. The via main body 25 includes W (tungsten) or Cu (copper) embedded in the through hole 23 as a single body (integrated member).

The electronic component 1 includes a plurality of top wirings 30 arranged on the second end 5b of the insulating layer 5. The plurality of top wirings 30 are electrically connected to the corresponding functional devices and/or the resistive film 8, respectively. The plurality of top wirings 30 are terminal electrodes connected to wires (e.g., bonding wires). The plurality of top wirings 30 transfer an input signal from the outside to each functional device or transfer an output signal from each functional device to the outside.

The plurality of top wirings 30 include a first upper wiring 31 and a second upper wiring 32 for the resistive film 8. The first upper wiring 31 is arranged directly above the first lower wiring 11. The second upper wiring 32 is arranged directly above the second lower wiring 12. The plurality of top wirings 30 have a thickness exceeding that of the plurality of interlayer wirings 10. The plurality of top wirings 30, like the plurality of interlayer wirings 10, each have: comprises a laminated structure of a first barrier film 13, a main body film 14, and a second barrier film 15 laminated in this order from the side of the semiconductor chip 2 (the side of the insulating layer 5).

The electronic component 1 includes a plurality of long via electrodes 40 arranged in an insulating layer 5. The plurality of long via electrodes 40 are electrically connected to the arbitrary interlayer wiring 10 and the arbitrary top wiring 30 which are opposed in the thickness direction. The long via electrode 40 is a via electrode 20 across at least two interlayer insulating films 6 among the via electrodes 20.

The plurality of long via electrodes 40 includes a first long via electrode 41 and a second long via electrode 42 for the resistive film 8. The first long via electrode 41 is electrically connected to the first lower wiring 11 and the first upper wiring 31 in a region between the first lower wiring 11 and the first upper wiring 31. The first long via electrode 41 is arranged at a distance from the resistive film 8, and extends from the second end 5b toward the first end 5a so as to traverse the resistive film 8.

The second long via electrode 42 is electrically connected to the second lower wiring 12 and the second upper wiring 32 in a region between the second lower wiring 12 and the second upper wiring 32. The second long via electrode 42 is arranged at a distance from the resistive film 8, and extends from the second end 5b side toward the first end 5a side so as to traverse the resistive film 8. The plurality of long via electrodes 40, like the plurality of via electrodes 20, each have: comprises a laminated structure of a through hole barrier film 24 and a through hole main body 25 laminated in this order from the inner wall of a through hole 23 formed in a corresponding interlayer insulating film 6.

The electronic component 1 includes: a top insulating layer 50 partially covering the plurality of top wirings 30 on the second end 5b of the insulating layer 5. The top insulating layer 50 may be referred to as a "passivation layer". The top insulating layer 50 has a plurality of pad openings 50a partially exposing the inside of the plurality of top wirings 30, and covers the peripheral edge portions of the plurality of top wirings 30.

In this embodiment, the top insulating layer 50 has: comprises a laminated structure of a first insulating film 51 and a second insulating film 52 laminated in this order from the insulating layer 5 side. The first insulating film 51 may include a silicon oxide film. The second insulating film 52 includes an insulator different from the first insulating film 51. The second insulating film 52 may also include a silicon nitride film. The top insulating layer 50 may have a single-layer structure composed of the first insulating film 51 or the second insulating film 52.

Fig. 4 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with a resistive film 8 according to a second embodiment. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in fig. 1 to 3, and their descriptions are omitted.

Referring to fig. 4, in the present embodiment, the insulating layer 5 includes first to fifth interlayer insulating films 6A to 6E stacked in this order from the first main surface 2a side, and has a thickness TA of 3600 nm. The insulating region 7 includes a laminated structure constituted by a part of the first to fourth interlayer insulating films 6A to 6D, and has an insulating thickness TB of 3100 nm. The resistive film 8 is disposed in the insulating layer 5 so as not to be located in a thickness range of less than 3100nm with respect to the first end 5a (first main surface 2 a). The plurality of interlayer wirings 10 includes first to third interlayer wirings 10A to 10C. In this embodiment, the first lower wiring 11 and the second lower wiring 12 for the resistor film 8 are each constituted by one of the third interlayer wirings 10C with respect to the plurality of interlayer wirings 10.

Fig. 5 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with a resistive film 8 according to a third embodiment. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in fig. 1 to 3, and their descriptions are omitted.

Referring to fig. 5, in the present embodiment, the insulating layer 5 includes first to fourth interlayer insulating films 6A to 6D stacked in this order from the first main surface 2a side, and has a thickness TA of 2700 nm. The insulating region 7 includes a laminated structure constituted by a part of the first to third interlayer insulating films 6A to 6C, and has an insulating thickness TB of 2200 nm. The resistive film 8 is disposed in the insulating layer 5 so as not to be located in a thickness range of less than 2200nm with respect to the first end 5a (first main surface 2 a). The plurality of interlayer wirings 10 includes first to second interlayer wirings 10A to 10B. In this embodiment, each of the first lower wiring 11 and the second lower wiring 12 for the resistor film 8 is constituted by one of the second interlayer wirings 10B.

Fig. 6 is a cross-sectional view showing a sectional structure along the line II-II shown in fig. 1 together with a resistive film 8 of the fourth embodiment. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in fig. 1 to 3, and their descriptions are omitted.

Referring to fig. 6, in this embodiment, the insulating layer 5 includes first to third interlayer insulating films 6A to 6C stacked in this order from the first main surface 2a side, and has a thickness TA of 1900 nm. The insulating region 7 has a laminated structure including a part of the first to second interlayer insulating films 6A to 6B, and has an insulating thickness TB of 1400 nm. The resistive film 8 is disposed in the insulating layer 5 so as not to be located in a thickness range of less than 1400nm with respect to the first end 5a (first main surface 2 a). The plurality of interlayer wirings 10 includes a first interlayer wiring 10A. The first lower wiring 11 and the second lower wiring 12 for the resistor film 8 are each constituted by one of the first interlayer wirings 10A.

The electrical characteristics of the resistor film 8 according to the first to fourth embodiments will be described below with reference to fig. 7 to 9. Hereinafter, as the electrical characteristics of the resistive film 8, sheet resistance Rs, coefficient of resistance temperature coefficient (TCR: temperature Coefficient Resistance) coefficient 1 TCR1 and coefficient 2 TCR2 of TCR are described. The number of samples of the resistive film 8 of the first to fourth examples used in obtaining the graphs of fig. 7 to 9 was 68.

Fig. 7 is a graph showing sheet resistance Rs of the resistive film 8. In fig. 7, the vertical axis represents the cumulative probability [% ], and the horizontal axis represents the sheet resistance Rs [ Ω/≡of the resistive film 8 ]. Fig. 7 shows a first characteristic S1, a second characteristic S2, a third characteristic S3, and a fourth characteristic S4.

The first characteristic S1 represents the characteristic of the resistive film 8 (insulation thickness tb=3900 nm) of the first embodiment. The second characteristic S2 represents the characteristic of the resistive film 8 (insulation thickness tb=3100 nm) of the second embodiment example. The third characteristic S3 represents the characteristic of the resistive film 8 (insulation thickness tb=2200 nm) of the third embodiment example. The fourth characteristic S4 represents the characteristic of the resistive film 8 (insulation thickness tb=1400 nm) of the fourth embodiment. The design value of the sheet resistance Rs is 1700 Ω/≡and 2300 Ω/≡.

Referring to the first characteristic S1, in the case of the resistive film 8 of the first embodiment, the sheet resistance Rs is converged in a range of 1970Ω/∈and 2110Ω/∈and less, and the central value M1 (50%) of the sheet resistance Rs is about 2050Ω/∈. Referring to the second characteristic S2, in the case of the resistive film 8 of the second embodiment, the sheet resistance Rs is converged in a range of 1930Ω/∈and 2120Ω/∈and falls below, and the central value M1 (50%) of the sheet resistance Rs is about 2050Ω/∈.

Referring to the third characteristic S3, in the case of the resistive film 8 of the third embodiment, the sheet resistance Rs is converged to a range of 2140Ω/∈and 2230Ω/∈and less, and the central value M1 (50%) of the sheet resistance Rs is about 2150Ω/∈. Referring to the fourth characteristic S4, in the case of the resistive film 8 of the fourth embodiment, the sheet resistance Rs is converged in the range of 2130Ω/∈and 2390Ω/∈and is equal to or lower, and the central value M1 (50%) of the sheet resistance Rs is about 2270Ω/∈.

The sheet resistance Rs depends on the configuration of the resistive film 8, and the greater the distance between the first end 5a of the insulating layer 5 and the resistive film 8, the greater the accuracy of the sheet resistance Rs with respect to the design value. Specifically, the accuracy of the sheet resistance Rs with respect to the design value is improved in the order of the fourth embodiment example, the third embodiment example, the second embodiment example, and the first embodiment example. Since the first characteristic S1 and the second characteristic S2 are substantially uniform, the sheet resistance Rs tends to converge toward the design value without diverging due to the increase in the distance between the first end 5a and the resistive film 8.

From the above results, the resistive film 8 is preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 2200nm with respect to the first end 5a of the insulating layer 5. According to this configuration, the accuracy of the sheet resistance Rs with respect to the design value can be improved. In this case, the resistive film 8 preferably covers the insulating region 7 having an insulating thickness TB of 2200nm or more.

The resistive film 8 is particularly preferably covered with an insulating region 7 having a thickness of 3100nm or more. According to this configuration, the accuracy of the sheet resistance Rs with respect to the design value can be further improved. In this case, the resistive film 8 is preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 3100nm with respect to the first end 5a of the insulating layer 5.

Fig. 8 is a graph showing the coefficient TCR1 of the TCR of the resistive film 8. In FIG. 8, the vertical axis represents the cumulative probability [% ], and the horizontal axis represents the coefficient TCR1[ ppm/. Degree.C ] of TCR 1. Fig. 8 shows a first characteristic S11, a second characteristic S12, a third characteristic S13, and a fourth characteristic S14.

The first characteristic S11 represents the characteristic of the resistive film 8 of the first embodiment. The second characteristic S12 represents the characteristic of the resistive film 8 of the second embodiment. The third characteristic S13 represents the characteristic of the resistive film 8 of the third embodiment. The fourth characteristic S14 represents the characteristic of the resistive film 8 of the fourth embodiment. The design values of the coefficient TCR1 of the 1 st order are all-100 ppm/DEG C or more and +100 ppm/DEG C or less. The optimum value of coefficient 1 TCR1 is 0 ppm/DEG C.

Referring to first characteristic S11, in the case of resistive film 8 of the first embodiment, coefficient 1 TCR1 converges in the range of-20 ppm/°c or more and +25ppm/°c or less, and central value M2 (50%) is substantially 0ppm/°c. The coefficient TCR1 of the first characteristic S11 converges within a range of +20% to-10 ppm/. Degree.C.and +10 ppm/. Degree.C.or more based on the central value M1 (50%).

Referring to the second characteristic S12, in the case of the resistive film 8 of the second embodiment, the coefficient 1 TCR1 is converged to a range of-20 ppm/°c or more and +25ppm/°c or less, and the central value M2 (50%) is substantially 0ppm/°c. The coefficient TCR1 of the second characteristic S12 is converged within a range of-10 ppm/DEG C or more and +10 ppm/DEG C or less within a range of + -20% based on the central value M1 (50%).

Referring to the third characteristic S13, in the case of the resistive film 8 of the third embodiment, the coefficient 1 TCR1 is converged to a range of +5ppm/°c or more and +60ppm/°c or less, and the central value M2 (50%) is about +21ppm/°c. Referring to fourth characteristic S14, in the case of resistive film 8 of the fourth embodiment, coefficient 1 TCR1 is converged to a range of +34ppm/°c or more and +84ppm/°c or less, and central value M2 (50%) is about +52ppm/°c.

The 1 st order coefficient TCR1 depends on the arrangement of the resistive film 8, and increases the distance between the first end 5a of the insulating layer 5 and the resistive film 8. Specifically, the 1 st coefficient TCR1 is increased in the order of the fourth embodiment example, the third embodiment example, the second embodiment example, and the first embodiment example. The first characteristic S11 substantially coincides with the second characteristic S12, and therefore, the 1 st-order coefficient TCR1 tends to converge toward the design value without diverging due to an increase in the distance between the first end 5a and the resistive film 8.

From the above results, the resistive film 8 is preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 2200nm with respect to the first end 5a of the insulating layer 5. According to this constitution, the resistive film 8 having the coefficient TCR1 of 1 degree can be formed in a range of-20 ppm/DEG C or more and +60 ppm/DEG C or less. In this case, the resistive film 8 preferably covers the insulating region 7 having an insulating thickness TB of 2200nm or more.

The resistive film 8 is particularly preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 3100nm with respect to the first end 5a of the insulating layer 5. In this case, the resistive film 8 having the coefficient TCR1 of 1 degree can be formed in a range of-20 ppm/DEG C or more and +25 ppm/DEG C or less. In this case, the resistive film 8 is particularly preferably covered with the insulating region 7 having a thickness of 3100nm or more.

Fig. 9 is a graph showing the coefficient 2 TCR2 of the TCR of the resistive film 8. In fig. 9, the vertical axis represents the cumulative probability [%]The horizontal axis represents the coefficient 2 TCR2[ ppm/. Degree.C ] of TCR of the resistive film 8 ² ]. Fig. 9 shows a first characteristic S21, a second characteristic S22, a third characteristic S23, and a fourth characteristic S24.

The first characteristic S21 represents the characteristic of the resistive film 8 of the first embodiment. The second characteristic S22 represents the characteristic of the resistive film 8 of the second embodiment. The third characteristic S23 represents the characteristic of the resistive film 8 of the third embodiment. The fourth characteristic S24 represents the characteristic of the resistive film 8 of the fourth embodiment. Design values of the coefficient 2 TCR2 are-0.5 ppm/DEG C ² Above and 0.5 ppm/DEG C ² The following is given. The optimum value of coefficient 2 TCR2 is 0 ppm/. Degree.C ² 。

Referring to the first characteristic S21, in the case of the resistive film 8 of the first embodiment, the coefficient 2 TCR2 converges to-0.16 ppm/. Degree.C ² Above and-0.08 ppm/DEG C ² The following are the followingThe median value M3 (50%) was 0.13 ppm/. Degree.C ² Left and right. The coefficient 2 TCR2 of the first characteristic S21 converges to-0.15 ppm/. Degree.C.within a range of + -20% based on the median value M3 (50%) ² Above and-0.1 ppm/DEG C ² The following ranges.

Referring to the second characteristic S22, in the case of the resistive film 8 of the second embodiment, the coefficient 2 TCR2 converged to-0.16 ppm/. Degree.C ² Above and-0.10 ppm/DEG C ² The central value M3 (50%) was 0.13 ppm/. Degree.C.within the following range ² Left and right. The coefficient 2 TCR2 of the second characteristic S22 converges to-0.15 ppm/. Degree.C.within a range of + -20% based on the median value M3 (50%) ² Above and-0.1 ppm/DEG C ² The following ranges.

Referring to the third characteristic S23, in the case of the resistive film 8 of the third embodiment, the coefficient 2 TCR2 converges to-0.23 ppm/. Degree.C ² Above and-0.14 ppm/DEG C ² The central value M3 (50%) was 0.17 ppm/. Degree.C.within the following range ² Left and right. Referring to the fourth characteristic S24, in the case of the resistive film 8 of the fourth embodiment, the coefficient 2 TCR2 converges to-0.32 ppm/. Degree.C ² Above and-0.19 ppm/DEG C ² The central value M3 (50%) was 0.22 ppm/. Degree.C.within the following range ² Left and right.

The 2 nd order coefficient TCR2 depends on the arrangement of the resistive film 8, and increases the distance between the first end 5a of the insulating layer 5 and the resistive film 8. Specifically, the 2 nd order coefficient TCR2 is increased in the order of the fourth embodiment example, the third embodiment example, the second embodiment example, and the first embodiment example. The first characteristic S21 substantially coincides with the second characteristic S22, and therefore, the 2 nd order coefficient TCR2 has a tendency to converge toward the design value without diverging due to an increase in the distance between the first end 5a and the resistive film 8.

From the above results, the resistive film 8 is preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 2200nm with respect to the first end 5a of the insulating layer 5. According to this constitution, it is possible to form a composition of-0.23 ppm/. Degree.C ² Above and-0.08 ppm/DEG C ² The following range has a 2-degree coefficient TCR2 of the resistive film 8. In this case, the resistive film 8 preferably covers the insulating region 7 having an insulating thickness TB of 2200nm or more.

ResistorThe film 8 particularly preferably covers the insulating region 7 having a thickness of 3100nm or more. According to this constitution, it can be formed at-0.16 ppm/. Degree.C ² Above and-0.08 ppm/DEG C ² The following range has a 2-degree coefficient TCR2 of the resistive film 8. In this case, the resistive film 8 is preferably disposed in the insulating layer 5 so as not to be located in a thickness range of less than 3100nm with respect to the first end 5a of the insulating layer 5.

As is clear from the results of fig. 7 to 9, the electrical characteristics of the resistive film 8 depend on the distance between the first end 5a (semiconductor chip 2) of the insulating layer 5 and the resistive film 8. This is because the electrical characteristics of the resistive film 8 are substantially determined in the crystallization process performed in the formation process of the resistive film 8. That is, in the crystallization process, the base alloy film that becomes the base of the resistive film 8 is heated at the crystallization temperature. At this time, the larger the distance between the first end 5a and the base alloy film within the insulating layer 5, the greater the heat storage effect in the region between the first end 5a and the base alloy film.

Thereby, the heat applied to the base alloy film increases, and crystallization of the base alloy film is promoted. As a result, the resistor film 8 is formed with high accuracy. This effect is due to the heat storage effect of the insulating layer 5, and therefore, it is not necessary to increase the crystallization temperature in the chamber or to lengthen the crystallization time of the base alloy film. Therefore, in the case where the functional device is formed on the semiconductor chip 2, it is possible to avoid an excessive heat load from being generated on the functional device.

In addition, by providing the insulating region 7 in the insulating layer 5 and forming the base alloy film directly covering the insulating region 7, the resistor film 8 can be efficiently crystallized by the temperature rise of the insulating region 7. That is, the insulating region 7 becomes a heat storage region in the manufacturing process. The insulating region 7 is preferably provided on the outer side of the device region 3 on the outer side of the region 4. According to this configuration, thermal interference of the insulating region 7 with the functional device can be suppressed. In addition, the electrical interference between the resistive film 8 and the functional device can also be suppressed.

The insulating layer 5 preferably has a second thermal conductivity K2 that is smaller than the first thermal conductivity K1 of the semiconductor chip 2. According to this structure, the heat storage effect of the region between the base alloy film and the semiconductor chip 2 (specifically, the semiconductor wafer serving as the base of the semiconductor chip 2) can be improved in the insulating layer 5. In other words, when the distance between the semiconductor chip 2 and the resistive film 8 becomes small, the temperature rise of the base alloy film and the insulating layer 5 is hindered by the heat radiation through the semiconductor chip 2, and crystallization of the base alloy film is suppressed. Therefore, the distance between the first end 5a in the insulating layer 5 and the resistive film 8 needs to be set to be equal to or greater than a predetermined distance.

The electric characteristics of the resistive film 8 have a tendency to converge toward the design value without diverging due to the increase in the distance between the first end 5a and the resistive film 8. This is considered to be because the base alloy film approaches the crystallization limit due to the heat storage effect. Referring to the evaluation results of the first embodiment and the second embodiment shown in fig. 7 to 9, it is apparent that the resistor film 8 having high-precision electrical characteristics can be stably formed when the distance between the first end 5a and the base alloy film is at least 3100 nm. Therefore, it can be said that the distance between the first end 5a and the resistive film 8 is preferably 2200nm or more, particularly preferably 3100nm or more.

The electrical characteristics of the resistor film 8 hardly vary due to the thickness of the insulator covering the resistor film 8 (i.e., the number of layers and the thickness of the interlayer insulating film 6 positioned above the resistor film 8). This is because, after the formation process of the resistive film 8, an insulator covering the resistive film 8 is laminated. Therefore, if the thickness position of the resistive film 8 (base alloy film) is to be arranged to be determined, the upper limit value of the thickness TA of the insulating layer 5 is arbitrary.

The electronic component 1 includes: a semiconductor chip 2 (chip), an insulating layer 5, and a resistive film 8. The semiconductor chip 2 has a first main surface 2a (main surface). The insulating layer 5 is laminated on the first main surface 2a with a thickness exceeding 2200 nm. The insulating layer 5 has a first end 5a on the semiconductor chip 2 side and a second end 5b on the opposite side of the semiconductor chip 2. The resistive film 8 contains an alloy crystal composed of a metal element and a non-metal element. The resistive film 8 is disposed in the insulating layer 5 so as not to be located in a thickness range of less than 2200nm with respect to the first end 5 a. According to this structure, the reliability of the resistive film 8 can be improved.

Fig. 10 is a cross-sectional view showing an electronic component 61 according to the second embodiment (=the electronic component 1 according to the first embodiment is modified in the arrangement and connection of the resistive film 8). Hereinafter, structures corresponding to those described for the electronic component 1 are denoted by the same reference numerals, and their description is omitted.

Referring to fig. 10, the electronic component 61 includes, like the electronic component 1: the semiconductor chip 2, the device region 3, the outer region 4, the insulating layer 5, the insulating region 7, the resistive film 8, the inorganic insulating film 9, the plurality of interlayer wirings 10, the plurality of via electrodes 20, the plurality of top wirings 30, the plurality of long via electrodes 40, and the top insulating layer 50. The insulating layer 5 includes, as in the case of the first embodiment, first to sixth interlayer insulating films 6A to 6F laminated in this order from the first main surface 2a side. In the present embodiment, the insulating region 7 has a laminated structure including a part of the first to fourth interlayer insulating films 6A to 6D, and has an insulating thickness TB of 2200nm or more. The insulating thickness TB is preferably 3100nm or more.

In this embodiment, the resistive film 8 is disposed in the insulating layer 5 so as to be covered with a laminated film of two or more interlayer insulating films 6. In this embodiment, the resistor film 8 is disposed on the fourth interlayer insulating film 6D and covered with the fifth to sixth interlayer insulating films 6E to 6F. The resistor film 8 is exclusive to the fourth interlayer insulating film 6D. The number of layers of the interlayer insulating film 6 covering the resistor film 8 may be 3 or more.

In this embodiment, the plurality of interlayer wires 10 are disposed in the insulating layer 5 in a thickness range between the second end 5b and the resistive film 8 in addition to the thickness range of the first end 5a and the resistive film 8 in the insulating layer 5. In this embodiment, the plurality of interlayer wirings 10 include a plurality of upper interlayer wirings 62 in addition to the first to third interlayer wirings 10A to 10C. The first to third interlayer wirings 10A to 10C are stacked and arranged within the thickness range of the first terminal 5a and the resistive film 8, respectively, in the insulating layer 5. Specifically, the first to third interlayer wirings 10A to 10C are stacked and arranged on the first to third interlayer insulating films 6A to 6C, respectively.

The plurality of upper interlayer wirings 62 are arranged within the insulating layer 5 within a thickness range between the second end 5b and the resistive film 8. In this embodiment, the upper interlayer wiring 62 is disposed on the fifth interlayer insulating film 6E and covered with the sixth interlayer insulating film 6F. In the case where 3 or more interlayer insulating films 6 are stacked on the resistive film 8, the plurality of upper interlayer wirings 62 may be stacked within the insulating layer 5 within a thickness range between the second end 5b and the resistive film 8.

The plurality of interlayer wirings 10 include: a first lower wiring 11, a second lower wiring 12, a first upper wiring 31, and a second upper wiring 32 for the resistor film 8. In this embodiment, each of the first lower wiring 11 and the second lower wiring 12 is constituted by one of the third interlayer wirings 10C. Each of the first upper wiring 31 and the second upper wiring 32 is constituted by one of the upper interlayer wirings 62. That is, in the electronic component 61, the first upper wiring 31 and the second upper wiring 32 are constituted by the interlayer wiring 10 instead of the top wiring 30.

The plurality of via electrodes 20 includes a first via electrode 21 and a second via electrode 22 for the resistive film 8. The first via electrode 21 is electrically connected to one end of the resistive film 8 and the first lower wiring 11 in a region between one end of the resistive film 8 and the first lower wiring 11. The second via electrode 22 is electrically connected to the other end of the resistive film 8 and the second lower wiring 12 in a region between the one end of the resistive film 8 and the second lower wiring 12.

In this embodiment, the plurality of long via electrodes 40 are electrically connected to the arbitrary interlayer wiring 10 and the arbitrary upper interlayer wiring 62 which are opposed in the thickness direction. Includes a first long via electrode 41 and a second long via electrode 42 for the resistive film 8. The first long via electrode 41 is electrically connected to the first lower wiring 11 and the first upper wiring 31 in a region between the first lower wiring 11 and the first upper wiring 31 (upper interlayer wiring 62). The second long via electrode 42 is electrically connected to the second lower wiring 12 and the second upper wiring 32 in a region between the first lower wiring 11 and the second upper wiring 32 (the upper interlayer wiring 62).

The electronic component 61 includes a plurality of top via electrodes 63. The plurality of top via electrodes 63 are electrically connected to the arbitrary interlayer wiring 10 (the upper interlayer wiring 62) and the arbitrary top wiring 30 which are opposed in the thickness direction. The plurality of top via electrodes 63, like the plurality of via electrodes 20, each have: comprises a laminated structure of a through hole barrier film 24 and a through hole main body 25 laminated in this order from the inner wall of a through hole 23 formed in a corresponding interlayer insulating film 6.

As described above, the same effects as those described for the electronic component 1 can be obtained also by the electronic component 61.

Fig. 11 is a cross-sectional view showing an electronic component 71 according to the third embodiment (=the electronic component 1 according to the first embodiment is modified in the connection mode of the resistive film 8). Hereinafter, structures corresponding to those described for the electronic component 1 are denoted by the same reference numerals, and their description is omitted.

Referring to fig. 11, the electronic component 71 includes, as with the electronic component 1: the semiconductor chip 2, the device region 3, the outer region 4, the insulating layer 5, the insulating region 7, the resistive film 8, the inorganic insulating film 9, the plurality of interlayer wirings 10, the plurality of via electrodes 20, the plurality of top wirings 30, the plurality of long via electrodes 40, and the top insulating layer 50. The insulating layer 5 includes, as in the case of the first embodiment, first to sixth interlayer insulating films 6A to 6F laminated in this order from the first main surface 2a side. In the present embodiment, the insulating region 7 has a laminated structure including a part of the first to fifth interlayer insulating films 6A to 6E, and has an insulating thickness TB of 2200nm or more. The insulating thickness TB is preferably 3100nm or more.

The resistor film 8 is disposed on the fifth interlayer insulating film 6E and covered with the sixth interlayer insulating film 6F as in the case of the first embodiment. The resistor film 8 is disposed in the insulating layer 5 in a region between the second end 5b and the insulating region 7, and directly covers the insulating region 7. In this embodiment, the resistive film 8 is opposed to the semiconductor chip 2 (the first main surface 2 a) through only the insulating region 7 in the insulating layer 5. That is, the resistive film 8 is not opposed to the conductor film (metal film) in the region between the first end 5 a.

As in the case of the first embodiment, the plurality of interlayer wires 10 are stacked in the insulating layer 5 within the thickness range of the first end 5a and the resistive film 8, and are not stacked in the insulating layer 5 within the thickness range of the second end 5b and the resistive film 8. The plurality of interlayer wirings 10 includes first to fourth interlayer wirings 10A to 10D. In this embodiment, the plurality of interlayer wirings 10 do not include the first lower wiring 11 and the second lower wiring 12 for the resistive film 8. As in the case of the first embodiment, the plurality of via electrodes 20 are electrically connected to any 2 interlayer wirings 10 facing each other in the thickness direction.

The plurality of top wirings 30 include a first upper wiring 31 and a second upper wiring 32 for the resistive film 8. The first upper wiring 31 faces one end of the resistive film 8 through a part of the insulating layer 5, and the second upper wiring 32 is not enough to face the other end of the resistive film 8 through a part of the insulating layer 5. That is, the resistor film 8 is disposed in the insulating layer 5 so as to cover the insulating region 7 and overlap the first upper wiring 31 and the second upper wiring 32 in a plan view. As in the case of the first embodiment, the plurality of long via electrodes 40 are electrically connected to the arbitrary interlayer wiring 10 and the arbitrary top wiring 30 which face each other in the thickness direction.

The electronic component 71 includes a first pad electrode 72 and a second pad electrode 73 disposed in the insulating layer 5. The first pad electrode 72 penetrates the inorganic insulating film 9 in the insulating layer 5 (in the sixth interlayer insulating film 6F in this embodiment) and is electrically connected to one end portion of the resistive film 8. The second pad electrode 73 penetrates the inorganic insulating film 9 in the insulating layer 5 (in the sixth interlayer insulating film 6F in this embodiment) and is electrically connected to the other end portion of the resistive film 8.

The electronic component 71 includes a first pad via electrode 74 and a second pad via electrode 75 disposed in the insulating layer 5. The first pad via electrode 74 is interposed in a region between the first pad electrode 72 and the first upper wiring 31, and is electrically connected to the first pad electrode 72 and the first upper wiring 31. The second pad via electrode 75 is interposed in a region between the second pad electrode 73 and the second upper wiring 32, and is electrically connected to the second pad electrode 73 and the second upper wiring 32. The first pad via electrode 74 and the second pad via electrode 75 have, like the plurality of via electrodes 20, respectively: comprises a laminated structure of a through hole barrier film 24 and a through hole main body 25 laminated in this order from the inner wall of a through hole 23 formed in a corresponding interlayer insulating film 6.

As described above, the same effects as those described for the electronic component 1 can be obtained also by the electronic component 71. In this embodiment, an example is described in which the resistive film 8 faces the semiconductor chip 2 through only the insulating region 7 in the thickness direction of the insulating layer 5. However, a part of the interlayer wiring 10 may be interposed between the first end 5a and the resistive film 8. That is, the resistive film 8 may be opposed to the insulating region 7 and a part of the conductor film (metal film) in the thickness direction of the insulating layer 5.

Fig. 12 is a cross-sectional view showing an electronic component 81 according to a fourth embodiment (=a mode in which the arrangement and connection form of the resistive film 8 are changed in the electronic component 71 according to the third embodiment) corresponding to fig. 2. Hereinafter, structures corresponding to those described for the electronic component 71 are denoted by the same reference numerals, and their description is omitted.

Referring to fig. 12, the electronic component 81 includes, like the electronic component 71: the semiconductor chip 2, the device region 3, the outer region 4, the insulating layer 5, the insulating region 7, the resistive film 8, the inorganic insulating film 9, the plurality of interlayer wirings 10, the plurality of via electrodes 20, the plurality of top wirings 30, the plurality of long via electrodes 40, the top insulating layer 50, the first pad electrode 72, the second pad electrode 73, the first pad via electrode 74, and the second pad via electrode 75. As in the case of the electronic component 71, the insulating layer 5 includes first to sixth interlayer insulating films 6A to 6F laminated in this order from the first main surface 2a side. In the present embodiment, the insulating region 7 has a laminated structure including a part of the first to fourth interlayer insulating films 6A to 6D, and has an insulating thickness TB of 2200nm or more. The insulating thickness TB is preferably 3100nm or more.

In this embodiment, the resistive film 8 is disposed in the insulating layer 5 so as to be covered with a laminated film of two or more interlayer insulating films 6. In this embodiment, the resistor film 8 is disposed on the fourth interlayer insulating film 6D and covered with the fifth to sixth interlayer insulating films 6E to 6F. The resistor film 8 is exclusive to the fourth interlayer insulating film 6D. The number of layers of the interlayer insulating film 6 covering the resistor film 8 may be at least 3.

In this embodiment, the plurality of interlayer wires 10 are disposed in the insulating layer 5 in a thickness range between the second end 5b and the resistive film 8 in addition to the thickness range of the first end 5a and the resistive film 8 in the insulating layer 5. In this embodiment, the plurality of interlayer wirings 10 include upper interlayer wirings 62 in addition to the first to third interlayer wirings 10A to 10C. The first to third interlayer wirings 10A to 10C are stacked and arranged within the thickness range of the first terminal 5a and the resistive film 8, respectively, in the insulating layer 5. Specifically, the first to third interlayer wirings 10A to 10C are stacked and arranged on the first to third interlayer insulating films 6A to 6C, respectively.

The plurality of upper interlayer wirings 62 are arranged within the insulating layer 5 within a thickness range between the second end 5b and the resistive film 8. In this embodiment, the upper interlayer wiring 62 is disposed on the fifth interlayer insulating film 6E and covered with the sixth interlayer insulating film 6F. In the case where 3 or more interlayer insulating films 6 are stacked on the resistive film 8, the plurality of upper interlayer wirings 62 may be stacked in the insulating layer 5 within a thickness range between the second end 5b and the resistive film 8.

The plurality of interlayer wirings 10 includes a first upper wiring 31 and a second upper wiring 32 for the resistive film 8. In this embodiment, each of the first upper wiring 31 and the second upper wiring 32 is constituted by one of the upper interlayer wirings 62. In this embodiment, the plurality of long via electrodes 40 are electrically connected to the arbitrary interlayer wiring 10 and the arbitrary upper interlayer wiring 62 which are opposed in the thickness direction. The plurality of long via electrodes 40 includes a first long via electrode 41 and a second long via electrode 42. The first long via electrode 41 is interposed between any of the interlayer wiring 10 and the first upper wiring 31 (upper interlayer wiring 62), and is electrically connected to any of the interlayer wiring 10 and the first upper wiring 31. The second long via electrode 42 is interposed between the arbitrary interlayer wiring 10 and the second upper wiring 32 (upper interlayer wiring 62), and is electrically connected to the arbitrary interlayer wiring 10 and the second upper wiring 32.

The first pad electrode 72 penetrates the inorganic insulating film 9 in the insulating layer 5 (in the fifth interlayer insulating film 6E in this embodiment) and is electrically connected to one end portion of the resistive film 8. The second pad electrode 73 penetrates the inorganic insulating film 9 in the insulating layer 5 (in the fifth interlayer insulating film 6E in this embodiment) and is electrically connected to the other end portion of the resistive film 8. The first pad via electrode 74 is interposed in a region between the first pad electrode 72 and the first upper wiring 31 (upper interlayer wiring 62), and is electrically connected to the first pad electrode 72 and the first upper wiring 31. The second pad via electrode 75 is interposed in a region between the second pad electrode 73 and the second upper wiring 32 (upper interlayer wiring 62), and is electrically connected to the second pad electrode 73 and the second upper wiring 32.

The electronic component 81 includes a first top via electrode 82 and a second top via electrode 83 disposed within the insulating layer 5. The first top via electrode 82 is interposed between the first upper wiring 31 (upper interlayer wiring 62) and any of the top wirings 30, and is electrically connected to the first upper wiring 31 and any of the top wirings 30. The second top via electrode 83 is interposed between the second upper wiring 32 (upper interlayer wiring 62) and any of the top wirings 30, and is electrically connected to the second upper wiring 32 and any of the top wirings 30. The first top via electrode 82 and the second top via electrode 83 have, like the plurality of via electrodes 20, respectively: comprises a laminated structure of a through hole barrier film 24 and a through hole body 25 laminated in order from the inner wall of a through hole 23 formed in a corresponding interlayer insulating film 6.

As described above, the same effects as those described for the electronic component 1 can be obtained by the electronic component 81.

Fig. 13 is a cross-sectional view showing an electronic component 91 according to the fifth embodiment (=the embodiment in which the insulating region 7 is modified in the electronic component 1 according to the first embodiment) corresponding to fig. 2. Hereinafter, structures corresponding to those described for the electronic component 1 are denoted by the same reference numerals, and their description is omitted.

In the electronic component 1, an example in which the insulating region 7 has the insulating thickness TB with the first end 5a as a reference (zero point) is described. In contrast, referring to fig. 13, in the electronic component 91, the insulating region 7 has an insulating thickness TB with respect to any interlayer wiring 10 disposed on the first end 5a side in the insulating layer 5 (zero point). In fig. 13, as an example, the insulating region 7 has an insulating thickness TB with the first interlayer wiring 10A as a reference (zero point). In this case, the insulation thickness TB is also preferably 2200nm or more. The insulating thickness TB is particularly preferably 3100nm or more.

The same effects as those described for the electronic component 1 can be obtained by the electronic component 91 as described above. The insulating region 7 of the fifth embodiment can be applied to the second to fourth embodiments as well as the first embodiment.

Fig. 14 is a schematic plan view showing an electronic component 101 according to a sixth embodiment. Fig. 15 is an enlarged view showing the region XV shown in fig. 14 together with the first pattern of the resistive film 8. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in fig. 15. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in fig. 15. Hereinafter, the same reference numerals are given to structures corresponding to those shown in fig. 1 to 13, and a part of the structures will be described in detail using different viewpoints and definitions from those of the first embodiment and the like, and the description of other structures will be omitted or simplified.

The electronic component 101 includes, as in the case of the first embodiment: a semiconductor chip 2, a device region 3 and an outside region 4. In the present embodiment, the electronic component 101 includes a plurality of device regions 3 provided on the first main surface 2a and at least one outside region 4. The plurality of device regions 3 are each divided inside the first main surface 2a with a space from the side surface 2c in a plan view.

The number, arrangement, and shape of the device regions 3 are arbitrary, and are not limited to a specific number, arrangement, and shape. Of course, the electronic component 101 may have a single device region 3 as in the case of the first embodiment. At least 1 outer region 4 is provided in the first main face 2a in a region between at least 2 device regions 3. In the present embodiment, at least one outer region 4 is provided in a region divided from four directions by four device regions 3 inside the first main surface 2 a.

The electronic component 101 includes the insulating layer 5 laminated on the first main surface 2a, as in the case of the first embodiment. The insulating layer 5 includes a plurality of interlayer insulating films 6 (first to sixth interlayer insulating films 6A to 6F in this embodiment) and has the thickness TA (2200 nm < TA) described above. In this mode, the insulating layer 5 covers the plurality of device regions 3 and the outside region 4. In this embodiment, the plurality of interlayer insulating films 6 each have a flat outer surface. The outer surface of each interlayer insulating film 6 was planarized by CMP (Chemical Mechanical Polishing) method.

The electronic component 101 includes, as in the case of the first embodiment: a resistor film 8, an inorganic insulating film 9, a plurality of interlayer wirings 10 (first to fourth interlayer wirings 10A to 10D), a first lower wiring 11, a second lower wiring 12, and an insulating region 7. As in the case of the first embodiment, the plurality of interlayer wirings 10 each include: a laminated structure including a first barrier film 13, a main body film 14, and a second barrier film 15.

The resistive film 8 is disposed in the insulating layer 5 as in the case of the first embodiment. The resistor film 8 is disposed in the insulating layer 5 at a portion covering the outer region 4. That is, in the present embodiment, the resistive film 8 is provided in a region between at least two device regions 3 in a plan view. Specifically, the resistive film 8 is provided in a region divided from 4 directions by 4 device regions 3 in a plan view. The resistive film 8 includes: a first end 8a on one side, a second end 8b on the other side, and a resistor main body 8c between the first end 8a and the second end 8 b. Hereinafter, the direction in which the straight line connecting the first end portion 8a and the second end portion 8b extends will be referred to as a first direction X, and the intersecting direction (specifically, the orthogonal direction) of the first direction X will be referred to as a second direction Y.

The first end portion 8a and the second end portion 8b are electrical connection terminals, and are portions facing other members in the thickness direction of the insulating layer 5. The resistor main body portion 8c is located outside the first end portion 8a and the second end portion 8b, and is a portion connecting the first end portion 8a and the second end portion 8 b. The resistor main body portion 8c extends in a band shape between the first end portion 8a and the second end portion 8 b. In this embodiment, the resistor main body portion 8c extends in a linear band shape (rectangular shape) along the first direction X. The width of the resistor main body 8c may be 1 μm or more and 200 μm or less. The width of the resistor main body 8c is a width in a direction (second direction Y) orthogonal to the direction in which the resistor main body 8c extends (first direction X).

The first lower wiring 11 is disposed between the first main surface 2a and the first end 8a of the resistive film 8 in the insulating layer 5. In this embodiment, the first lower wiring 11 is constituted by one of the fourth interlayer wirings 10D. The first lower wiring 11 is led out of the resistive film 8 from a region below the first end portion 8a of the resistive film 8 toward a region opposite to the second end portion 8b of the resistive film 8 in a plan view. The first lower wiring 11 has one end portion located below the first end portion 8a of the resistive film 8, and the other end portion located in a region outside the resistive film 8. In this embodiment, the first lower wiring 11 (one end portion) is formed wider in the second direction Y than the resistor main body portion 8c of the resistor film 8.

The second lower wiring 12 is arranged between the first main surface 2a and the second end portion 8b of the resistive film 8 with a space from the first lower wiring 11 in the first direction X. In this embodiment, the second lower wiring 12 is constituted by one of the fourth interlayer wirings 10D. The second lower wiring 12 is led out from a region below the second end portion 8b of the resistive film 8 toward a region outside the resistive film 8 in a direction opposite to the first end portion 8a of the resistive film 8 in a plan view. The second lower wiring 12 is opposed to the first lower wiring 11 through a part of the insulating layer 5. The second lower wiring 12 has one end portion located below the second end portion 8b of the resistive film 8 and the other end portion located in the region outside the resistive film 8. In the present embodiment, the second lower wiring 12 (one end portion) is formed wider than the resistive film 8 (the resistive body portion 8 c) in the second direction Y.

The insulating region 7 is divided into regions between the first lower wiring 11 and the second lower wiring 12 in the insulating layer 5 as in the case of the first embodiment. The insulating region 7 has the above-described insulating thickness TB (=2200 nm or more: TB < TA) in the thickness direction of the insulating layer 5. The insulating region 7 is formed only by the insulator portion 7a in the insulating layer 5 in the thickness range between the first main face 2a and the resistive film 8. The insulator portion 7a is a portion having no conductor film (metal film or the like) but only an insulator in the thickness direction of the insulating layer 5. The insulator portion 7a has a laminated structure constituted by a part of a plurality of interlayer insulating films 6 (first to fifth interlayer insulating films 6A to 6E in this embodiment) located in a thickness range between the first main surface 2a and the resistive film 8.

The insulating region 7 (insulator portion 7 a) is formed in the insulating layer 5 over the entire area of the opposing region between the first lower wiring 11 and the second lower wiring 12 in plan view and in cross-section. The insulating region 7 is formed over the entire region of the portion where the entire region of the resistor main body portion 8c overlaps the first main surface 2a in plan view and in cross section. In this embodiment, the insulator portion 7a is formed in a quadrangular shape including the entire resistor main body portion 8c with reference to the outermost portion of the peripheral edges of the resistor main body portion 8c in the second direction Y in plan view.

The electronic component 101 includes a forbidden region 102 that extends the insulating region 7 to a range outside the resistive film 8. The forbidden region 102 is a region in which the arrangement of a conductor film (metal film or the like) is forbidden within the insulating layer 5. The forbidden region 102 may also be referred to as an "insulation extension region". The forbidden zone 102 includes an insulation extension 102a that extends the insulator portion 7a of the insulating zone 7 from the periphery of the resistive film 8 to a range outside the resistive film 8. Specifically, the insulation extension 102a extends the insulator portion 7a from the region between the first lower wiring 11 and the second lower wiring 12 in a plan view in a direction (second direction Y) orthogonal to the opposing direction (first direction X) of the first lower wiring 11 and the second lower wiring 12.

In this embodiment, the forbidden region 102 expands the insulating region 7 into a quadrilateral shape in plan view. The insulation extension 102a covers the outer region 4. The insulating extension 102a preferably covers the outer region 4 with a space from the plurality of device regions 3. Of course, the insulating extension 102a may also cover the at least one device region 3 across the outer region 4.

The inhibition region 102 forms a heat storage region for the resistive film 8, as with the insulating region 7. The width W of the forbidden region 102 is preferably 2200nm or more (2200 nm < W, TB) as the insulating thickness TB of the insulating region 7. The expanded width W is a width of the forbidden region 102 along the second direction Y when the peripheral edge of the resistive film 8 is a reference (zero point) in plan view. In this case, the forbidden region 102 obtains the same action and effect as the action and effect of the insulating region 7 in the lateral direction along the second end 5b of the insulating layer 5. When the insulating thickness TB of the insulating region 7 is 3100nm or more, the width W may be 3100nm or more (3100 nm < W, TB).

The width W may be equal to or greater than the insulation thickness TB of the insulation region 7 (TB. Ltoreq.W), or may be smaller than the insulation thickness TB (TB > W). The width W may be equal to or larger than the thickness TA of the insulating layer 5 (TA.ltoreq.W), or may be smaller than the thickness TA (TA > W). The upper limit value of the expansion width W is arbitrary. In view of the size of the semiconductor chip 2, the layout of the plurality of interlayer wirings 10, and the like, the upper limit value of the expanded width W is preferably 10 times or less (w.ltoreq.10×tb) of the insulating thickness TB. The width W of the extension is particularly preferably 3.5 μm or more and 20 μm or less. That is, the forbidden region 102 (insulation extension 102 a) preferably extends the insulation region 7 (insulator portion 7 a) from the periphery of the resistive film 8 to a range of 3.5 μm or more and 20 μm or less in plan view.

The electronic component 101 includes a plurality of third wirings 103 arranged in the insulating layer 5. The plurality of third wirings 103 are each constituted by the interlayer wiring 10 other than the first lower wiring 11 and the second lower wiring 12. The plurality of third wirings 103 are arranged in layers (first to fourth interlayer insulating films 6A to 6D) other than the layer (fifth interlayer insulating film 6E) in which the resistive film 8 is arranged. The plurality of third wirings 103 are disposed in the insulating layer 5 separately from the resistive film 8, the first lower wirings 11, and the second lower wirings 12.

The plurality of third wirings 103 are arranged in the insulating layer 5 at intervals from the peripheral edge of the resistive film 8 to the region outside the resistive film 8 so as not to overlap the resistive film 8 in a plan view. Specifically, the plurality of third wirings 103 are arranged in a region outside the insulating region 7 and the forbidden region 102 in plan view, and do not face the resistive film 8, the insulating region 7, and the forbidden region 102 through a part of the insulating layer 5.

At least one third wiring 103 among the plurality of third wirings 103 is arranged on the same layer as the first lower wiring 11 and the second lower wiring 12, separately from the first lower wiring 11 and the second lower wiring 12. At least one third wiring 103 among the plurality of third wirings 103 is arranged in a layer (first to third interlayer insulating films 6A to 6C) different from the layer (fourth interlayer insulating film 6D) in which the first lower wiring 11 and the second lower wiring 12 are arranged. At least one third wiring 103 may be provided in a layer different from the first lower wiring 11 and the second lower wiring 12, and may be provided so as to face either one or both of the first lower wiring 11 and the second lower wiring 12 in the thickness direction of the insulating layer 5.

The plurality of third wirings 103 include at least one (in this embodiment, a plurality of) connection wirings 103a electrically connected to one or both of the semiconductor chip 2 (specifically, a functional device) and the resistive film 8. The plurality of third wirings 103 include at least one (in this embodiment, a plurality of) dummy wirings 103b electrically disconnected from the semiconductor chip 2 (specifically, the functional device) and the resistive film 8. Specifically, the dummy wiring 103b is formed in an electrically floating state.

The plurality of dummy wirings 103b protect the plurality of interlayer wirings 10 from undesired corrosion in the etching process for the plurality of interlayer wirings 10. The plurality of dummy wirings 103b protect the interlayer insulating film 6 from unwanted undulation in the process of forming the interlayer insulating film 6. The interlayer insulating film 6 whose undulation is suppressed is properly planarized by the CMP method.

In this embodiment, a plurality of connection wirings 103a and a plurality of dummy wirings 103b are formed on the first to fourth interlayer insulating films 6A to 6D, respectively. The plurality of connection wirings 103a and the plurality of dummy wirings 103b are arranged in the same layer as the first lower wirings 11 and the second lower wirings 12 at intervals in the lateral direction along the second end 5b of the insulating layer 5 from the first lower wirings 11 and the second lower wirings 12. Fig. 15 and 16 show examples in which the connection wiring 103a is arranged on one side (left side of the drawing) and the dummy wiring 103b is arranged on the other side (right side of the drawing) in the same layer as the first lower wiring 11 and the second lower wiring 12.

The plurality of dummy wirings 103b are arranged on the first to fourth interlayer insulating films 6A to 6D so that the total planar area of the plurality of interlayer wirings 10 (electrode films) is 20% or more and 80% or less of the outer surface of the interlayer insulating film 6 to be formed in a plan view. The proportion of the total planar area is preferably 25% or more and 65% or less. At least one third wiring 103 (interlayer wiring 10) is arranged in a range of 1.5 to 4 times the width of the resistive film 8 with respect to the peripheral edge (zero point) of the resistive film 8 in a region outside the insulating region 7 and the forbidden region 102.

The plurality of third wirings 103 are preferably arranged so as to be separated from the peripheral edge of the resistive film 8 by 2200nm or more in plan view according to the expanded width W of the forbidden region 102. The plurality of third wirings 103 are preferably arranged so as to be separated from the peripheral edge of the resistive film 8 by 3100nm or more. The plurality of third wirings 103 are particularly preferably arranged so as to be separated from the peripheral edge of the resistive film 8 by 3.5 μm or more. The plurality of third wirings 103 are preferably arranged so as not to be separated from the peripheral edge of the resistive film 8 by a distance of 20 μm or more in plan view. That is, the plurality of third wirings 103 are particularly preferably arranged in a range of 3.5 μm or more and 20 μm or less from the peripheral edge of the resistive film 8 in plan view.

The electronic component 101 includes, as in the case of the first embodiment: a plurality of via electrodes 20 (first via electrode 21 and second via electrode 22), a plurality of top wirings 30 (first upper wiring 31 and second upper wiring 32), a plurality of long via electrodes 40 (first long via electrode 41 and second long via electrode 42), and a top insulating layer 50.

As in the case of the first embodiment, the plurality of via electrodes 20 each include: comprises a laminated structure of a through hole barrier film 24 and a through hole main body 25 laminated in this order from the inner wall of a through hole 23 formed in a corresponding interlayer insulating film 6. As in the case of the first embodiment, the plurality of via electrodes 20 are electrically connected to any 2 interlayer wirings 10 facing each other in the thickness direction, and include a first via electrode 21 and a second via electrode 22 for the resistive film 8.

The first via electrode 21 is interposed between the first end 8a of the resistive film 8 and one end of the first lower wiring 11, and is electrically connected to the first end 8a of the resistive film 8 and one end of the first lower wiring 11, as in the case of the first embodiment. In this embodiment, the plurality of first via electrodes 21 are interposed between the first end 8a of the resistive film 8 and one end of the first lower wiring 11. In this embodiment, the plurality of first via electrodes 21 are arranged in a row at intervals in the second direction Y in a plan view.

The plurality of first via electrodes 21 may be arranged in a matrix or a rack shape at intervals in the first direction X and the second direction Y in a plan view. Each of the first via electrodes 21 may be formed in a circular shape or a polygonal shape (for example, a quadrangular shape) in a plan view. The number of the first via electrodes 21 is arbitrary, and a single first via electrode 21 may be disposed.

The second via electrode 22 is interposed between the second end portion 8b of the resistive film 8 and one end portion of the second lower wiring 12, and is electrically connected to the second end portion 8b of the resistive film 8 and one end portion of the second lower wiring 12, as in the case of the first embodiment. In this embodiment, the plurality of second via electrodes 22 are interposed between the second end 8b of the resistive film 8 and one end of the second lower wiring 12. In this embodiment, the plurality of second via electrodes 22 are arranged in a row at intervals in the second direction Y in a plan view. The plurality of second via electrodes 22 are opposed to the plurality of first via electrodes 21 across the insulating region 7 in the first direction X in a plan view.

The plurality of second via electrodes 22 may be arranged in a matrix or a rack shape with a space therebetween in the first direction X and the second direction Y in a plan view. Each of the second via electrodes 22 may be formed in a circular shape or a polygonal shape (for example, a quadrangular shape) in plan view. The number of the second via electrodes 22 is arbitrary, and a single second via electrode 22 may be disposed.

As in the case of the first embodiment, the plurality of top wirings 30 each include: comprises a laminated structure of a first barrier film 13, a main body film 14, and a second barrier film 15 laminated in this order from the side of the semiconductor chip 2 (the side of the insulating layer 5). In this embodiment, the plurality of top wirings 30 are arranged on the second end 5b of the insulating layer 5 at intervals from the peripheral edge of the resistive film 8 to the region outside the resistive film 8 so as not to overlap the resistive film 8 in a plan view. Specifically, the plurality of top wirings 30 are arranged in a region outside the insulating region 7 and the forbidden region 102 in plan view, and do not face the resistive film 8, the insulating region 7, and the forbidden region 102 through a part of the insulating layer 5. The plurality of top wirings 30 are opposed to any interlayer wiring 10 in the thickness direction of the insulating layer 5.

The plurality of top wirings 30 include a first upper wiring 31 and a second upper wiring 32 for the resistive film 8 as in the case of the first embodiment. The first upper wiring 31 is arranged in a region outside the insulating region 7 and the forbidden region 102 in plan view, and faces the first lower wiring 11 of the lower layer through a part of the insulating layer 5. The first upper wiring 31 is not opposed to the resistive film 8 in plan view and cross-sectional view. The second upper wiring 32 is arranged in a region outside the insulating region 7 and the forbidden region 102 in plan view, and faces the second lower wiring 12 through a part of the insulating layer 5. The second upper wiring 32 is not opposed to the resistive film 8 in plan view and cross-sectional view.

In this embodiment, the plurality of top wirings 30 include at least one (in this embodiment, a plurality of) dummy top wirings 104 electrically disconnected from the semiconductor chip 2 (specifically, the functional device) and the resistive film 8. In fig. 17, an example in which a plurality of dummy top wirings 104 are arranged is shown. Specifically, the dummy top wiring 104 is formed in an electrically floating state. The plurality of dummy top wirings 104 protect the plurality of top wirings 30 from undesired corrosion during the etching process for the plurality of top wirings 30.

The plurality of dummy top wirings 104 are arranged on the uppermost interlayer insulating film 6 so that the ratio of the total planar area of the plurality of top wirings 30 (electrode films) to the outer surface of the uppermost interlayer insulating film 6 (sixth interlayer insulating film 6F in this embodiment) to be formed is 20% or more and 80% or less in plan view. The proportion of the total planar area is preferably 25% or more and 65% or less.

The plurality of top wirings 30 are preferably arranged so as to be separated from the peripheral edge of the resistive film 8 by 2200nm or more in plan view according to the expanded width W of the forbidden region 102. The plurality of top wirings 30 are preferably arranged so as to be separated from the peripheral edge of the resistive film 8 by 3100nm or more. The plurality of top wirings 30 are particularly preferably arranged so as to be separated from the peripheral edge of the resistive film 8 by 3.5 μm or more. The plurality of top wirings 30 are preferably arranged so as not to be spaced apart from the peripheral edge of the resistive film 8 by a distance of 20 μm or more in plan view. That is, the plurality of top wirings 30 are particularly preferably arranged in a range of 3.5 μm or more and 20 μm or less from the peripheral edge of the resistive film 8 in plan view.

As in the case of the first embodiment, the plurality of long via electrodes 40 each include: comprises a laminated structure of a through hole barrier film 24 and a through hole main body 25 laminated in this order from the inner wall of a through hole 23 formed in a corresponding interlayer insulating film 6. As in the case of the first embodiment, the plurality of long via electrodes 40 are electrically connected to the arbitrary interlayer wiring 10 and the arbitrary top wiring 30 facing each other in the thickness direction, and include the first long via electrode 41 and the second long via electrode 42 for the resistive film 8.

The first long via electrode 41 is electrically connected to the first lower wiring 11 and the first upper wiring 31 in a region interposed between the first lower wiring 11 and the first upper wiring 31 as in the case of the first embodiment. The second long via electrode 42 is electrically connected to the second lower wiring 12 and the second upper wiring 32 in a region interposed between the second lower wiring 12 and the second upper wiring 32 as in the case of the first embodiment.

The first lower wiring 11 may be electrically connected to the lower interlayer wiring 10 (third wiring 103) via the via electrode 20. In this case, the first upper wiring 31 does not necessarily need to be electrically connected to the first lower wiring 11, but may be electrically connected to any interlayer wiring 10 (third wiring 103) located at a lower layer via the first long via electrode 41. The second lower wiring 12 may be electrically connected to the lower interlayer wiring 10 (third wiring 103) via the via electrode 20. In this case, the second upper wiring 32 does not necessarily have to be electrically connected to the second lower wiring 12, but may be electrically connected to any interlayer wiring 10 (third wiring 103) located at the lower layer via the second long via electrode 42.

The electronic component 101 includes the top insulating layer 50 partially covering the plurality of top wirings 30 on the second end 5b of the insulating layer 5 as in the case of the first embodiment. The top insulating layer 50 has, as in the case of the first embodiment: a laminated structure including a first insulating film 51 and a second insulating film 52. The top insulating layer 50 covers the resistive film 8, the insulating region 7, and the forbidden region 102 with a portion of the insulating layer 5 interposed therebetween in a region outside the plurality of top wirings 30. The top insulating layer 50 may cover the entire area of the area outside the plurality of top wirings 30 at the second end 5b of the insulating layer 5.

The resistive film 8 may have various patterns shown in fig. 18A to 18C. Fig. 18A to 18C are enlarged views showing the region XV shown in fig. 14 together with the resistor films 8 of the second to fourth patterns. Hereinafter, the same reference numerals are given to the structures corresponding to those shown in fig. 14 to 17, and their descriptions are omitted.

Referring to fig. 18A, in this embodiment, the resistor film 8 is formed wider than the first lower wiring 11 and the second lower wiring 12. That is, the first lower wiring 11 and the second lower wiring 12 are formed narrower than the resistive film 8.

Referring to fig. 18B, in this embodiment, the resistive film 8 includes: the resistor main body portion 8c extends in a zigzag shape in the first direction X so as to meander to one side and the other side in the second direction Y in a region between the first end portion 8a and the second end portion 8b in a plan view. In this embodiment, the first lower wiring 11 and the second lower wiring 12 are formed to have a width exceeding the meandering width of the resistive film 8. The meandering width of the resistive film 8 is the meandering range of the resistive film 8 along the second direction Y. That is, the first lower wiring 11 and the second lower wiring 12 are formed such that the resistive film 8 is included in the entire area of the opposing area between the first lower wiring 11 and the second lower wiring 12 in a plan view.

Referring to fig. 18C, in this embodiment, the resistive film 8 includes: the resistor main body portion 8c extends in a zigzag shape in the first direction X so as to meander to one side and the other side in the second direction Y in a region between the first end portion 8a and the second end portion 8b in a plan view. In this embodiment, the first lower wiring 11 and the second lower wiring 12 are formed to have a width smaller than the meandering width of the resistive film 8. The meandering width of the resistive film 8 is the meandering range of the resistive film 8 along the second direction Y. That is, the first lower wiring 11 and the second lower wiring 12 are formed such that a part of the resistive film 8 protrudes from the opposing region between the first lower wiring 11 and the second lower wiring 12 in a plan view.

Referring to fig. 18A to 18C, in these embodiments, the insulating region 7 (insulator portion 7 a) is formed in the insulating layer 5 over the entire region of the opposing region between the first lower wiring 11 and the second lower wiring 12 in plan view and in cross-section. The insulating region 7 is formed over the entire region of the portion where the entire region of the resistor main body portion 8c overlaps the first main surface 2a in plan view and in cross section. The insulating region 7 is formed in a quadrangular shape including the entire resistor main body 8c with reference to the outermost portion of the peripheral edge of the resistor main body 8c in the second direction Y in plan view and in cross section.

In these embodiments, the forbidden region 102 also expands the insulator portion 7a in a direction (second direction Y) orthogonal to the opposing direction (first direction X) of the first lower wiring 11 and the second lower wiring 12, and has the aforementioned expansion width W with the peripheral edge (zero point) of the resistive film 8 as a reference. In this embodiment, the forbidden region 102 expands the insulating region 7 into a quadrilateral shape in plan view.

Fig. 19 is a graph showing sheet resistance Rs of the resistive film 8 shown in fig. 15. In fig. 19, the vertical axis represents sheet resistance Rs [ Ω/≡ ], and the horizontal axis represents the expansion width W [ μm ] of the forbidden region 102. Fig. 19 shows a design value line L of sheet resistance characteristics SR and sheet resistance Rs in the case where the extension width W is changed.

Here, the sheet resistance characteristic SR when the width W is varied in a range of-5 μm or more and 20 μm or less is shown. The zero point of the expanded width W is the peripheral edge of the resistive film 8, the positive expanded width W is the third wiring 103 disposed apart from the peripheral edge of the resistive film 8, and the negative expanded width W is the third wiring 103 facing the resistive film 8 in the up-down direction. Here, characteristics when one third wiring 103 is arranged on the interlayer insulating film 6 (third interlayer insulating film 6C) located below the resistor film 8 are shown.

Referring to the sheet resistance characteristic SR, it was confirmed that the sheet resistance Rs varied by the expansion width W. Specifically, the sheet resistance Rs increases with a decrease in the extension width W, and decreases with an increase in the extension width W. In addition, it was confirmed that the sheet resistance characteristic SR had a tendency to saturate in the vicinity of the design value line L.

When the width W is set to the negative range, the sheet resistance Rs represents a sharp rate of change of the rate of change with respect to the width W from the design value line L. The absolute value of the slope of the tangent to the sheet resistance characteristic SR takes a maximum value in the range where the expanded width W is negative (-5 μm.ltoreq.W < 0 μm). On the other hand, when the width W is set to the positive range, the sheet resistance Rs represents a slow rate of change with respect to the rate of change of the width W in the vicinity of the design value line L. The absolute value of the slope of the tangent line of the sheet resistance characteristic SR takes the minimum value in the range where the width W of expansion is positive (0 μm.ltoreq.W.ltoreq.20 μm).

Specifically, the absolute value of the slope of the tangent to the sheet resistance characteristic SR is changed from increasing to decreasing with an expansion width W of 3.5 μm as a boundary. When the width W is 3.5 μm or more, the sheet resistance characteristic SR (sheet resistance Rs) shows a tendency to converge toward the design value line L without diverging with an increase in the width W.

Fig. 20 is a graph showing the coefficient TCR1 of the TCR of the resistive film 8 shown in fig. 15. In FIG. 20, the vertical axis represents coefficient TCR1[ ppm/. Degree.C ] of degree 1, and the horizontal axis represents the width W [ μm ] of the forbidden region 102. Fig. 20 shows the first-order characteristic ST1 and the design range R1 of the first-order characteristic ST 1. The design range R1 is-25 ppm/DEG C or more and 0 ppm/DEG C or less. The measurement conditions were the same as those in the case of the sheet resistance characteristic SR of fig. 19.

Referring to the first order characteristic ST1, it was confirmed that the 1 ST order coefficient TCR1 varies due to the expansion width W. Specifically, the coefficient 1 TCR1 increases as the width W increases, and decreases as the width W increases. In addition, it was confirmed that the 1 ST order characteristic ST1 has a tendency to saturate in the design range R1.

When the expansion width W is set to the negative range, the 1 st coefficient TCR1 indicates a rapid rate of change of the rate of change with respect to the expansion width W from the design range R1. The absolute value of the slope of the tangent line of the 1 ST order characteristic ST1 takes the maximum value in the range where the expanded width W is negative (-5 μm.ltoreq.w < 0 μm). On the other hand, when the width W is set to the positive range, the 1 st coefficient TCR1 indicates a slow rate of change with respect to the rate of change of the width W in the vicinity of the design range R1. The absolute value of the slope of the tangent line of the 1 ST order characteristic ST1 takes the minimum value in the range where the width W of expansion is positive (0 μm.ltoreq.w.ltoreq.20μm).

Specifically, the absolute value of the slope of the tangent to the 1 ST order characteristic ST1 is changed from increasing to decreasing with an expansion width W of 3.5 μm as a boundary. When the width W is 3.5 μm or more, the 1 ST order characteristic ST1 (1 ST order coefficient TCR 1) shows a tendency to converge toward the design range R1 without diverging with an increase in the width W. When the width W is 3.5 μm or more, the coefficient TCR1 of the resistive film 8 is-25 ppm/DEG C or more and 0 ppm/DEG C or less.

Fig. 21 is a graph showing the coefficient 2 TCR2 of the TCR of the resistive film 8 shown in fig. 15. In FIG. 20, the vertical axis represents the coefficient 2 TCR2[ ppm/. Degree.C ] ² ]The horizontal axis represents the expanded width W [ mu ] m of the forbidden region 102]. Fig. 21 shows the design range R2 of the 2-step characteristic ST2 and the 2-step characteristic ST 2. The design range R2 is-0.15 ppm/DEG C ² Above and 0 ppm/. Degree.C ² The following is given. The measurement conditions were the same as those in the case of the sheet resistance characteristic SR of fig. 19.

Referring to the second order characteristic ST2, it was confirmed that the 2 nd order coefficient TCR2 fluctuates due to the expansion width W. Specifically, the 2 nd coefficient TCR2 decreases with decreasing expansion width W, and increases with increasing expansion width W. In addition, it was confirmed that the 2 nd order coefficient TCR2 has a tendency to saturate in the design range R2.

When the expansion width W is set to the negative range, the 2 nd coefficient TCR2 indicates a rapid change rate from the design range R2 with respect to the change rate of the expansion width W. The absolute value of the slope of the tangent line of the 2 nd order characteristic ST2 takes the maximum value in the range (-5 μm.ltoreq.W < 0 μm) where the expanded width W is negative. On the other hand, when the width W is set to the positive range, the 2 nd coefficient TCR2 indicates a slow rate of change with respect to the rate of change of the width W in the vicinity of the design range R2. The absolute value of the slope of the tangent line of the 2 nd order characteristic ST2 is minimized in the range where the width W of the expansion is positive (0 μm.ltoreq.W.ltoreq.20μm).

Specifically, the absolute value of the slope of the tangent to the 2 nd order characteristic ST2 is changed from increasing to decreasing with an expansion width W of 3.5 μm as a boundary. When the width W is 3.5 μm or more, the second order characteristic ST2 (2 nd order coefficient TCR 2) shows a tendency to converge toward the design range R2 without diverging with an increase in the width W. When the width W is 3.5 μm or more, the coefficient 2 TCR2 of the resistor film 8 is-0.15 ppm/DEG C ² Above and 0 ppm/. Degree.C ² The following is given.

As is clear from the results of fig. 19 to 21, the electrical characteristics of the resistive film 8 depend on the width W of the forbidden region 102 (the insulating extension 102 a) disposed between the resistive film 8 and the third wiring 103. This is because the electrical characteristics of the resistive film 8 are substantially determined in the crystallization process performed in the formation process of the resistive film 8. That is, in the crystallization process, the base alloy film that becomes the base of the resistive film 8 is heated at the crystallization temperature. At this time, the larger the expansion width W in the insulating layer 5, the smaller the heat transferred from the insulating region 7 and the forbidden region 102 to the third wiring 103, and the larger the heat storage effect in the insulating region 7 and the forbidden region 102.

Thereby, the heat applied to the base alloy film increases, and crystallization of the base alloy film is promoted. As a result, the resistor film 8 is formed with high accuracy. This effect is due to the heat storage effect of the insulating region 7 and the forbidden region 102, and therefore, it is not necessary to raise the crystallization temperature in the chamber or to lengthen the crystallization time of the base alloy film. Therefore, when the functional device is formed on the semiconductor chip 2, it is possible to avoid an excessive heat load from being generated on the functional device.

The electronic component 101 includes: the semiconductor chip 2, the insulating layer 5, the resistive film 8, the first lower wiring 11, the second lower wiring 12, and the insulating region 7. The semiconductor chip 2 has a first main surface 2a. An insulating layer 5 is laminated on the first main surface 2a. The resistive film 8 is disposed in the insulating layer 5, and includes an alloy crystal composed of a metal element and a non-metal element, and has a first end 8a on one side and a second end 8b on the other side.

The first lower wiring 11 is interposed between the first main surface 2a and the first end 8a of the resistive film 8 in the insulating layer 5. The second lower wiring 12 is interposed between the first main surface 2a and the second end portion 8b of the resistive film 8 in the insulating layer 5, separately from the first lower wiring 11 in the insulating layer 5. The insulating region 7 is defined in the insulating layer 5 between the first lower wiring 11 and the second lower wiring 12, and is formed in the insulating layer 5 only by the insulator portion 7a located in the thickness range between the first main surface 2a and the resistive film 8. According to this structure, the reliability of the resistive film 8 can be improved.

The electronic component 101 preferably includes: the insulating region 7 is extended within the insulating layer 5 to a forbidden region 102 of a range outside the resistive film 8. The exclusion zone 102 contains: the insulator portion 7a of the insulating region 7 is extended from the periphery of the resistive film 8 to an insulation extension 102a of a range outside the resistive film 8. In this case, the electronic component 101 includes: a plurality of third wirings 103 disposed in the insulating layer 5. The plurality of third wirings 103 are disposed in the insulating layer 5 so as not to be located in the insulating region 7 and the forbidden region 102, and are separated from the resistive film 8, the first lower wirings 11, and the second lower wirings 12. According to this structure, in the structure in which the resistive film 8, the first lower wiring 11, the second lower wiring 12, and the plurality of third wirings 103 are arranged in the insulating layer 5, the reliability of the resistive film 8 can be improved.

In other aspects, the electronic component 101 comprises: a semiconductor chip 2, an insulating layer 5, and a plurality of top wirings 30. The semiconductor chip 2 has a first main surface 2a. An insulating layer 5 is laminated on the first main surface 2a. The resistive film 8 is disposed in the insulating layer 5 and includes an alloy crystal composed of a metal element and a nonmetallic element. The plurality of top wirings 30 are arranged on the insulating layer 5 at intervals from the peripheral edge of the resistive film 8 to the region outside the resistive film 8 so as not to overlap the resistive film 8 in a plan view. According to this structure, stress generated in the resistor film 8 by the plurality of top wirings 30 can be relaxed. This can suppress the variation in the electrical characteristics of the resistive film 8 caused by the plurality of top wirings 30. Therefore, the reliability of the resistive film 8 can be improved.

In this configuration, the electronic component 101 may also include: first lower wiring 11, second lower wiring 12, and insulating region 7. The first lower wiring 11 is interposed between the first main surface 2a and the first end 8a of the resistive film 8 in the insulating layer 5. The second lower wiring 12 is interposed between the first main surface 2a and the second end portion 8b of the resistive film 8 in the insulating layer 5, separately from the first lower wiring 11 in the insulating layer 5.

The insulating region 7 is defined in the insulating layer 5 between the first lower wiring 11 and the second lower wiring 12, and is formed in the insulating layer 5 only by the insulator portion 7a located in the thickness range between the first main surface 2a and the resistive film 8. In this case, the plurality of top wirings 30 are preferably arranged in a region outside the insulating region 7 in a plan view. According to this structure, in the structure in which the resistive film 8, the first lower wiring 11, the second lower wiring 12, and the plurality of top wirings 30 are arranged, the reliability of the resistive film 8 can be improved.

The electronic component 101 preferably includes: the insulating region 7 is extended within the insulating layer 5 to a forbidden region 102 of a range outside the resistive film 8. The exclusion zone 102 contains: the insulator portion 7a of the insulating region 7 is extended from the periphery of the resistive film 8 to an insulation extension 102a of a range outside the resistive film 8. In this case, the plurality of top wirings 30 are preferably arranged in a region outside the insulating region 7 and the forbidden region 102 in a plan view. According to this structure, the variation in the electrical characteristics of the resistive film 8 caused by the plurality of top wirings 30 can be appropriately suppressed.

In this configuration, the electronic component 101 may also include: at least one third wiring 103 disposed in the insulating layer 5 separately from the resistive film 8, the first lower wiring 11, and the second lower wiring 12. According to this structure, in the structure in which the resistive film 8, the first lower wiring 11, the second lower wiring 12, the third wiring 103, and the plurality of top wirings 30 are arranged, the reliability of the resistive film 8 can be improved. The electronic component 101 may also comprise a top insulating layer 50 covering the insulating layer 5. The top insulating layer 50 preferably partially covers the top wiring 30 on the insulating layer 5, and covers the resistive film 8 through a part of the insulating layer 5.

The at least one top wiring 30 is preferably electrically connected to either one or both of the semiconductor chip 2 (specifically, the functional device) and the resistive film 8. At least one top wiring 30 is preferably formed as a dummy top wiring 104 in an electrically floating state.

The manner of the exclusion area 102, the plurality of third wirings 103, and the plurality of top wirings 30 of the sixth embodiment can be applied to any of the electronic components 101 of the second to fifth embodiments in addition to the first embodiment. In this case, the electronic components 1, 61, 71, 81, 91 according to the second to fifth embodiments include: the insulating region 7, the forbidden region 102, the plurality of third wirings 103, and the plurality of top wirings 30 can obtain the same operational effects as those of the sixth embodiment.

The embodiments described above can also be implemented in other ways. In the above embodiments, the case where the single resistive film 8 is disposed in the insulating layer 5 has been described. However, a plurality of resistor films 8 may be disposed in the insulating layer 5. In this case, the plurality of resistive films 8 are preferably arranged on the same layer with a gap therebetween. The plurality of resistor films 8 are particularly preferably exclusively disposed on the main surface of any one of the interlayer insulating films 6. The plurality of resistive films 8 may also be arranged in a portion of the insulating layer 5 covering the outer region 4. The plurality of resistive films 8 may be disposed in the same outer region 4 in a plan view, or may be disposed in different outer regions 4. In this case, it is preferable to provide the insulating region 7 and the forbidden region 102 for each of the plurality of resistive films 8.

In the above embodiments, the example in which the resistive film 8 is disposed in the portion of the insulating layer 5 covering the outer region 4 has been described. However, the resistive film 8 may be disposed in a portion of the insulating layer 5 covering the device region 3. In the case where the plurality of resistive films 8 are formed, the plurality of resistive films 8 may include the resistive film 8 disposed in the portion of the insulating layer 5 covering the outside region 4, and other resistive films 8 in the portion of the insulating layer 5 covering the device region 3. In this case, it is preferable that the insulating region 7 and the inhibit region 102 are provided in the device region 3, respectively.

In the above embodiments, the device region 3 may not be provided. That is, the electronic components 1, 61, 71, 81, 91, 101 may be contact members including only one or a plurality of resistor films 8.

In the above embodiments, instead of the semiconductor chip 2, an insulator chip made of glass or ceramic may be used. The resistor film 8 of each of the above embodiments may be a fuse resistor film that fuses when a rated or higher current flows. In this case, the specific embodiment is obtained by replacing the "resistor film 8" with the "fuse resistor film (8)" in each of the above embodiments.

The features of the first to sixth embodiments described above may be combined in any form therebetween, and an electronic component having at least two of the features of the first to sixth embodiments at the same time may be used. That is, the features of the second embodiment may also be combined with the features of the first embodiment. The features of the third embodiment may be combined with any of the features of the first to second embodiments. The features of the fourth embodiment may be combined with any of the features of the first to third embodiments. The features of the fifth embodiment may be combined with any of the features of the first to fourth embodiments. The features of the sixth embodiment may be combined with any of the features of the first to fifth embodiments.

Hereinafter, examples of features extracted from the present specification and drawings are shown. The following [ A1] to [ A29] and [ B1] to [ B22] provide an electronic component capable of improving the reliability of a resistive film containing an alloy crystal composed of a metal element and a nonmetal element.

[A1] An electronic component, comprising:

a chip having a main surface;

an insulating layer laminated on the main surface with a thickness exceeding 2200nm, and having a first end on the chip side and a second end on the opposite side of the chip; and

And a resistive film which is disposed within the insulating layer so as not to be located within a thickness range of less than 2200nm with respect to the first end, and which includes an alloy crystal composed of a metal element and a non-metal element.

[A2] The electronic component according to A1, wherein,

the resistive film has a thickness of 0.1nm or more and 100nm or less.

[A3] The electronic component according to A1 or A2, wherein,

the electronic component further includes: an insulating region having only an insulator in a thickness direction of the insulating layer and formed in the insulating layer at a thickness of 2200nm or more,

the resistive film is disposed within the insulating layer so as to cover the insulating region.

[A4] The electronic component according to any one of A1 to A3, wherein,

the electronic component further includes: and a plurality of wirings stacked in a thickness direction of the insulating layer within a thickness range between the main surface and the resistive film in the insulating layer.

[A5] The electronic component according to A4, wherein,

the wiring is not arranged within the insulating layer in a thickness range between the second end and the resistive film.

[A6] The electronic component according to any one of A1 to A5, wherein,

The thickness between the first end and the resistive film in the insulating layer is greater than the thickness between the second end and the resistive film in the insulating layer.

[A7] The electronic component according to any one of A1 to A6, wherein,

the insulating layer has a thickness exceeding 3100nm,

the resistive film is disposed within the insulating layer so as not to be located within a thickness range of less than 3100nm with respect to the first end.

[A8] The electronic component according to any one of A1 to A7, wherein,

the insulating layer has: a laminated structure comprising 3 or more interlayer insulating films,

the resistor film is disposed on the interlayer insulating film of the third layer or more.

[A9] The electronic component according to A8, wherein,

the insulating layer includes 4 or more layers of the interlayer insulating film,

the resistor film is disposed on the interlayer insulating film above the fourth layer.

[A10] The electronic component according to A8 or A9, wherein,

each of the interlayer insulating films has a thickness of 100nm to 3000 nm.

[A11] The electronic component according to any one of A1 to A10, wherein,

the electronic component further includes: and a top wiring disposed on the second end.

[A12] The electronic component according to A11, wherein,

the electronic component further includes: a top insulating layer partially covering the top wiring.

[A13] The electronic component according to any one of A1 to A12, wherein,

the coefficient of resistance temperature of the resistive film is-20 ppm/DEG C or more and +60 ppm/DEG C or less.

[A14] The electronic component according to a13, wherein,

the coefficient 1 is +25 ppm/DEG C or less.

[A15] The electronic component according to any one of A1 to A14, wherein,

the coefficient of temperature coefficient of resistance of the resistive film is-0.23 ppm/DEG C2 ² Above and-0.08 ppm/DEG C ² The following is given.

[A16] The electronic component according to a15, wherein,

the coefficient 2 is-0.16 ppm/DEG C ² The above.

[A17] The electronic component according to any one of A1 to A16, wherein,

the resistive film includes at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.

[A18] An electronic component, comprising:

a chip having a main surface;

an insulating layer laminated on the main surface with a thickness exceeding 2200nm, and having a first end on the chip side and a second end on the opposite side of the chip;

an insulating region having only an insulator in a thickness direction of the insulating layer and formed within the insulating layer with a thickness of 2200nm or more; and

And a resistive film which is disposed in the insulating layer in a region between the second end and the insulating region so as to directly cover the insulating region, and which contains an alloy crystal composed of a metal element and a nonmetallic element.

[A19] The electronic component according to A18, wherein,

the electronic component further includes:

a first wiring disposed in the insulating layer; and

a second wiring disposed in the insulating layer at a distance from the first wiring in a plan view,

the insulating region is divided into a region between the first wiring and the second wiring in a plan view,

the resistor film is disposed in the insulating layer so as to directly cover the insulating region and overlap the first wiring and the second wiring in a plan view.

[A20] The electronic component according to A19, wherein,

the electronic component further includes:

a first via electrode disposed within the insulating layer between the resistive film and the first wiring; and

and a second via electrode disposed between the resistive film and the second wiring within the insulating layer.

[A21] A semiconductor device, comprising:

a semiconductor chip including a main surface and having a first thermal conductivity;

An insulating layer laminated on the main surface with a thickness exceeding 3100nm and including a first end on the semiconductor chip side and a second end on the opposite side of the semiconductor chip, the insulating layer having a second thermal conductivity smaller than the first thermal conductivity;

an insulating region having only an insulator in a thickness direction of the insulating layer and formed in an arbitrary region within the insulating layer at a thickness of 3100nm or more; and

and a CrSi resistor film which is disposed in the insulating layer so as to directly cover the insulating region and has a thickness of 0.1nm or more and 10nm or less in a region between the second end and the insulating region.

[A22] The semiconductor device according to A21, wherein,

the CrSi resistive film has a thickness of 5nm or less.

[A23] The semiconductor device according to A21 or A22, wherein,

the CrSi resistive film has a thickness of 1nm or more.

[A24] The semiconductor device according to any one of A21 to A23, wherein,

the insulating layer has: a laminated structure comprising 3 or more interlayer insulating films,

the CrSi resistor film is disposed on the interlayer insulating film of the third layer or more.

[A25] The semiconductor device according to A24, wherein,

The insulating layer includes 4 or more layers of the interlayer insulating film,

the CrSi resistor film is disposed on the interlayer insulating film above the fourth layer.

[A26] The semiconductor device according to any one of A21 to A25, wherein,

the semiconductor device further includes: and a plurality of wirings which are stacked in the thickness direction of the insulating layer within a thickness range between the first end in the insulating layer and the CrSi resistor film.

[A27] The semiconductor device according to A26, wherein,

the wiring is not arranged within the insulating layer in a thickness range between the second end and the CrSi resistive film.

[A28] The semiconductor device according to A26, wherein,

the wiring is disposed within the insulating layer within a thickness range between the second end and the CrSi resistive film.

[A29] The semiconductor device according to any one of A21 to A28, wherein,

the thickness between the first end and the CrSi resistive film in the insulating layer is equal to or greater than the thickness between the second end and the CrSi resistive film in the insulating layer.

[B1] An electronic component, comprising:

a chip having a main surface;

an insulating layer laminated on the main surface;

A resistive film disposed within the insulating layer and including an alloy crystal composed of a metal element and a non-metal element, the resistive film having a first end portion on one side and a second end portion on the other side;

a first wiring interposed between the main surface and the first end portion within the insulating layer;

a second wiring interposed between the main surface and the second end portion in the insulating layer so as to be separated from the first wiring; and

an insulating region which is divided in the insulating layer into a region between the first wiring and the second wiring and is formed only of an insulator portion of the insulating layer in a thickness range between the main surface and the resistive film.

[B2] The electronic component according to B1, wherein,

the electronic component further includes:

a forbidden zone including an insulation extension extending the insulator portion from a periphery of the resistive film to a range outside the resistive film, the insulation zone extending to a range outside the resistive film; and

and a plurality of third wirings disposed in the insulating layer so as not to be located in the insulating region and the forbidden region, the third wirings being separated from the resistive film, the first wirings, and the second wirings.

[B3] The electronic component according to B2, wherein,

the forbidden region has an extended width of 2200nm or more with respect to a peripheral edge of the resistive film in a plan view,

the plurality of third wirings are arranged so as to be separated from the peripheral edge of the resistive film by 2200nm or more in a plan view.

[B4] The electronic component according to B3, wherein,

the insulating layer has a thickness exceeding 2200nm,

the insulating region has a thickness of 2200nm or more.

[B5] The electronic component according to B3 or B4, wherein,

the width of the expansion is more than 3.5 mu m,

the plurality of third wirings are arranged to be separated from the peripheral edge of the resistive film by 3.5 μm or more in a plan view.

[B6] The electronic component according to any one of B3 to B5, wherein,

the width of the expansion is 20 μm or less,

at least one of the third wirings is disposed within 20 μm from the peripheral edge of the resistive film in a plan view.

[B7] The electronic component according to any one of B2 to B6, wherein,

at least one of the third wirings is disposed separately from the first wiring in the same layer as the first wiring,

at least one of the third wirings is arranged in a layer different from the first wiring.

[B8] The electronic component according to any one of B2 to B7, wherein,

At least one of the third wirings is electrically connected to one or both of the chip and the resistive film.

[B9] The electronic component according to any one of B2 to B8, wherein,

at least one of the third wirings is formed as a dummy wiring in an electrically floating state.

[B10] The electronic component according to any one of B2 to B9, wherein,

the plurality of third wirings are not arranged in a layer in which the resistive film is arranged.

[B11] The electronic component according to any one of B1 to B10, wherein,

the second wiring is arranged on the same layer as the first wiring.

[B12] The electronic component according to any one of B1 to B11, wherein,

the insulating layer has: a laminated structure in which a plurality of interlayer insulating films are laminated,

the insulator portion has: a laminated structure constituted by a plurality of portions of the interlayer insulating films.

[B13] The electronic component according to B12, wherein,

the insulating layer has: a laminated structure comprising 3 or more layers of the interlayer insulating film,

the resistor film is disposed on the interlayer insulating film of the third layer or more.

[B14] The electronic component according to any one of B1 to B13, wherein,

the electronic component further includes:

A first via hole connected to the first end portion and the first wiring within the insulating layer; and

and a second via hole connected to the second end portion and the second wiring within the insulating layer.

[B15] The electronic component according to any one of B1 to B14, wherein,

the electronic component further includes:

a plurality of top wirings disposed on the insulating layer; and

a top insulating layer partially covering the top wiring.

[B16] An electronic component, comprising:

a chip having a main surface;

an insulating layer laminated on the main surface;

a resistive film disposed within the insulating layer and including an alloy crystal composed of a metal element and a non-metal element; and

and a plurality of top wirings which are arranged on the insulating layer at intervals from the periphery of the resistive film to a region outside the resistive film so as not to overlap the resistive film in a plan view.

[B17] The electronic component according to B16, wherein,

the electronic component further includes:

a first wiring interposed between the main surface and one end of the resistive film in the insulating layer;

a second wiring interposed between the main surface and the other end portion of the resistive film, in the insulating layer, separately from the first wiring; and

An insulating region which is divided in the insulating layer into a region between the first wiring and the second wiring and is formed of only an insulator portion in the insulating layer in a thickness range between the main surface and the resistive film,

the plurality of top wirings are arranged in a region outside the insulating region in a plan view.

[B18] The electronic component according to B17, wherein,

the electronic component further includes: a forbidden zone including an insulation extension extending the insulator portion from a periphery of the resistive film to a range outside the resistive film, extending the insulation zone to a range outside the resistive film,

the plurality of top wirings are arranged in a region outside the insulating region and the forbidden region in a plan view.

[B19] The electronic component according to B18, wherein,

the electronic component further includes: and a third wiring that is disposed in the insulating layer so as not to be located in the insulating region and the forbidden region, and is separated from the resistive film, the first wiring, and the second wiring.

[B20] The electronic component according to any one of B16 to B19, wherein,

the electronic component further includes: and a top insulating film that partially covers the top wiring on the insulating layer and covers the resistor film with a portion of the insulating layer interposed therebetween.

[B21] The electronic component according to any one of B16 to B20, wherein,

at least one of the top wirings is electrically connected to either one or both of the chip and the resistive film.

[B22] The electronic component according to any one of B16 to B21, wherein,

at least one of the top wirings is formed as a dummy top wiring in an electrically floating state.

The [ A1] to [ A29] and the [ B1] to [ B22] may be combined in any manner therebetween, or an electronic component having at least two of the [ A1] to [ A29] and the [ B1] to [ B22] may be used.

The embodiments have been described in detail, but these are only specific examples used for the purpose of clarifying the technical content, and the present invention should not be construed as being limited to these specific examples, but the scope of the present invention is defined by the appended claims.

Symbol description

1. Electronic component

2. Semiconductor chip

2a first main face

5. Insulating layer

5a first end

5b second end

6. Interlayer insulating film

7. Insulating region

7a insulator portion

8. Resistor film

10. Interlayer wiring

11. First lower wiring

12. Second lower wiring

21. First via electrode

22. Second through hole electrode

30. Top wiring

50. Top insulating layer

61. Electronic component

71. Electronic component

81. Electronic component

91. Electronic component

101. Electronic component

102. Forbidden zone

102a insulation extension

103. Third wiring

103b dummy wiring

TCR1 1 coefficient

TCR 22 coefficient

Thickness of TA insulation layer

Thickness of TB insulation region

The extended width of the W exclusion zone.

Claims (20)

1. An electronic component, comprising:

a chip having a main surface;

an insulating layer laminated on the main surface with a thickness exceeding 2200nm, and having a first end on the chip side and a second end on the opposite side of the chip; and

and a resistive film which is disposed within the insulating layer so as not to be located within a thickness range of less than 2200nm with respect to the first end, and which includes an alloy crystal composed of a metal element and a non-metal element.

2. The electronic component according to claim 1, wherein,

the resistive film has a thickness of 0.1nm or more and 100nm or less.

3. The electronic component according to claim 1 or 2, wherein,

the electronic component further includes: an insulating region having only an insulator in a thickness direction of the insulating layer and formed in the insulating layer at a thickness of 2200nm or more,

The resistive film is disposed within the insulating layer so as to cover the insulating region.

4. The electronic component according to any one of claim 1 to 3, wherein,

the electronic component further includes: and a plurality of wirings stacked in a thickness direction of the insulating layer within a thickness range between the main surface and the resistive film in the insulating layer.

5. The electronic component according to claim 4, wherein,

the wiring is not arranged within the insulating layer in a thickness range between the second end and the resistive film.

6. The electronic component according to any one of claims 1 to 5, wherein,

the thickness between the first end and the resistive film in the insulating layer is greater than the thickness between the second end and the resistive film in the insulating layer.

7. The electronic component according to any one of claims 1 to 6, wherein,

the insulating layer has a thickness exceeding 3100nm,

the resistive film is disposed within the insulating layer so as not to be located within a thickness range of less than 3100nm with respect to the first end.

8. The electronic component according to any one of claims 1 to 7, wherein,

The insulating layer has: a laminated structure comprising 3 or more interlayer insulating films,

the resistor film is disposed on the interlayer insulating film of the third layer or more.

9. The electronic component according to claim 8, wherein,

the insulating layer includes 4 or more layers of the interlayer insulating film,

the resistor film is disposed on the interlayer insulating film above the fourth layer.

10. An electronic component according to claim 8 or 9, characterized in that,

each of the interlayer insulating films has a thickness of 100nm to 3000 nm.

11. The electronic component according to any one of claims 1 to 10, wherein,

the electronic component further includes: and a top wiring disposed on the second end.

12. The electronic component according to claim 11, wherein,

the electronic component further includes: a top insulating layer partially covering the top wiring.

13. The electronic component according to any one of claims 1 to 12, wherein,

the coefficient of resistance temperature of the resistive film is-20 ppm/DEG C or more and +60 ppm/DEG C or less.

14. The electronic component according to claim 13, wherein,

The coefficient 1 is +25 ppm/DEG C or less.

15. The electronic component according to any one of claims 1 to 14, wherein,

the coefficient of temperature coefficient of resistance of the resistive film is-0.23 ppm/DEG C2 ² Above and-0.08 ppm/DEG C ² The following is given.

16. The electronic component of claim 15, wherein the electronic component comprises a plurality of electronic components,

the coefficient 2 is-0.16 ppm/DEG C ² The above.

17. The electronic component according to any one of claims 1 to 16, wherein,

the resistive film includes at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.

18. An electronic component, comprising:

a chip having a main surface;

an insulating layer laminated on the main surface with a thickness exceeding 2200nm, and having a first end on the chip side and a second end on the opposite side of the chip;

an insulating region having only an insulator in a thickness direction of the insulating layer and formed within the insulating layer with a thickness of 2200nm or more; and

and a resistive film which is disposed in the insulating layer in a region between the second end and the insulating region so as to directly cover the insulating region, and which contains an alloy crystal composed of a metal element and a nonmetallic element.

19. The electronic component of claim 18, wherein the electronic component comprises a plurality of electronic components,

the electronic component further includes:

a first wiring disposed in the insulating layer; and

a second wiring disposed in the insulating layer at a distance from the first wiring in a plan view,

the insulating region is divided into a region between the first wiring and the second wiring in a plan view,

the resistor film is disposed in the insulating layer so as to directly cover the insulating region and overlap the first wiring and the second wiring in a plan view.

20. The electronic component of claim 19, wherein the electronic component comprises a plurality of electronic components,

the electronic component further includes:

a first via electrode disposed within the insulating layer between the resistive film and the first wiring; and

and a second via electrode disposed between the resistive film and the second wiring within the insulating layer.