JP2020043120A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2020043120A
JP2020043120A JP2018166985A JP2018166985A JP2020043120A JP 2020043120 A JP2020043120 A JP 2020043120A JP 2018166985 A JP2018166985 A JP 2018166985A JP 2018166985 A JP2018166985 A JP 2018166985A JP 2020043120 A JP2020043120 A JP 2020043120A
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JP6903612B2 (en
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一道 津村
Kazumichi Tsumura
一道 津村
東　和幸
Kazuyuki Azuma
和幸 東
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

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Abstract

To provide a semiconductor device having excellent interface characteristics between substrates.SOLUTION: A semiconductor device 1 comprises a substrate 10, a substrate 20, a first interface layer 41, and a second interface layer 42. The substrate 10 includes: a metal electrode 12 containing a first metal element; and an insulation layer 13 containing a first element and oxygen (O). The substrate 20 includes: a metal electrode 22 containing a second metal element; and an insulation layer 23 containing a second element and oxygen (O). The first interface layer 41, provided at an interface between the metal electrode 12 and the metal electrode 22, contains at least one of the first and second metal elements as well as a third metal element, and has conductivity. The second interface layer 42, provided at an interface between the insulation layer 13 and the insulation layer 23, contains at least one of the first and second elements, the third metal element, and oxygen (O), and has an insulation property.SELECTED DRAWING: Figure 1

Description

本発明の実施形態は、半導体装置に関する。   Embodiments of the present invention relate to a semiconductor device.

表面に金属電極パターンを有する２枚の基板（ウェハ）同士を貼り合わせる技術（Wafer-to-Wafer(W2W)/Hybrid bonding）が開発されている。この技術では、各基板の主面側に金属電極及び絶縁層を形成し、２枚の基板同士を貼り合わせて金属電極同士を接合している。   A technology (Wafer-to-Wafer (W2W) / Hybrid bonding) for bonding two substrates (wafers) each having a metal electrode pattern on the surface has been developed. In this technique, a metal electrode and an insulating layer are formed on the main surface side of each substrate, and the two substrates are bonded to each other to bond the metal electrodes.

しかしながら、２枚の基板同士を接合する界面の特性は必ずしも十分なものではなかった。   However, the characteristics of the interface joining the two substrates are not always sufficient.

特開２０１３−３３９００号公報JP 2013-33900 A

基板間の良好な界面特性を有する半導体装置を提供する。   Provided is a semiconductor device having good interface characteristics between substrates.

実施形態に係る半導体装置は、第１の基板と、第２の基板と、第１の界面層と、第２の界面層とを備える。前記第１の基板は、第１の金属元素を含有する第１の金属層と、第１の元素及び酸素（Ｏ）を含有する第１の絶縁層とを含む。前記第２の基板は、第２の金属元素を含有する第２の金属層と、第２の元素及び酸素（Ｏ）を含有する第２の絶縁層とを含む。前記第１の界面層は、第１の金属層と前記第２の金属層との界面に設けられ、前記第１の金属元素及び前記第２の金属元素の少なくとも一方と第３の金属元素とを含有し、導電性を有する。前記第２の界面層は、前記第１の絶縁層と前記第２の絶縁層との界面に設けられ、前記第１の元素及び前記第２の元素の少なくとも一方と前記第３の金属元素と酸素（Ｏ）とを含有し、絶縁性を有する。   A semiconductor device according to an embodiment includes a first substrate, a second substrate, a first interface layer, and a second interface layer. The first substrate includes a first metal layer containing a first metal element, and a first insulating layer containing the first element and oxygen (O). The second substrate includes a second metal layer containing a second metal element, and a second insulating layer containing a second element and oxygen (O). The first interface layer is provided at an interface between a first metal layer and the second metal layer, and includes at least one of the first metal element and the second metal element and a third metal element. And has conductivity. The second interface layer is provided at an interface between the first insulating layer and the second insulating layer, and includes at least one of the first element and the second element and the third metal element. It contains oxygen (O) and has insulating properties.

実施形態に係る半導体装置の構成を模式的に示した断面図である。FIG. 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to an embodiment. 実施形態に係る半導体装置の製法方法の一部を示した断面図である。FIG. 4 is a cross-sectional view illustrating a part of the method for manufacturing a semiconductor device according to the embodiment. 実施形態に係る半導体装置の製法方法の一部を示した断面図である。FIG. 4 is a cross-sectional view illustrating a part of the method for manufacturing a semiconductor device according to the embodiment.

以下、図面を参照して実施形態を説明する。
図１は、実施形態に係る半導体装置１の構成を模式的に示した断面図である。
半導体装置１は、基板１０（第１の基板）、基板２０（第２の基板）、第１の界面層４１、第２の界面層４２、第３の界面層４３、及び第４の界面層４４を備える。 Hereinafter, embodiments will be described with reference to the drawings.
FIG. 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor device 1 according to the embodiment.
The semiconductor device 1 includes a substrate 10 (first substrate), a substrate 20 (second substrate), a first interface layer 41, a second interface layer 42, a third interface layer 43, and a fourth interface layer. 44.

基板１０は、下部構造１１、金属電極１２（第１の金属層）、バリアメタル層１２ａ（第１のバリアメタル層）、及び絶縁層１３（第１の絶縁層）を有する。
下部構造１１は、例えば、半導体基板とトランジスタ等を含む回路とを有する。
金属電極１２は、基板１０の主面側表面に所定のパターンで形成されている。金属電極１２は第１の金属元素を主成分として含有する。例えば、第１の金属元素は銅（Ｃｕ）である。以下の説明においては、第１の金属元素は銅（Ｃｕ）であるとして説明する。 The substrate 10 has a lower structure 11, a metal electrode 12 (first metal layer), a barrier metal layer 12a (first barrier metal layer), and an insulating layer 13 (first insulating layer).
The lower structure 11 has, for example, a semiconductor substrate and a circuit including a transistor and the like.
The metal electrode 12 is formed on the main surface of the substrate 10 in a predetermined pattern. The metal electrode 12 contains a first metal element as a main component. For example, the first metal element is copper (Cu). In the following description, it is assumed that the first metal element is copper (Cu).

バリアメタル層１２ａは、金属電極１２と絶縁層１３の間に形成されており、金属電極１２に含まれる金属元素（銅（Ｃｕ））が絶縁層１３に拡散するのを防止するために設けられている。バリアメタル層１２ａは、例えば、チタン（Ｔｉ）、タンタル（Ｔａ）、ルテニウム（Ｒｕ）又はそれらの窒化物（窒化チタン（ＴｉＮ）、窒化タンタル（ＴａＮ）、窒化ルテニウム（ＲｕＮ））で形成される。また、金属電極１２は、基板１０中の図示せぬ配線と接続している。   The barrier metal layer 12a is formed between the metal electrode 12 and the insulating layer 13, and is provided to prevent a metal element (copper (Cu)) contained in the metal electrode 12 from diffusing into the insulating layer 13. ing. The barrier metal layer 12a is formed of, for example, titanium (Ti), tantalum (Ta), ruthenium (Ru) or a nitride thereof (titanium nitride (TiN), tantalum nitride (TaN), ruthenium nitride (RuN)). . The metal electrode 12 is connected to a wiring (not shown) in the substrate 10.

絶縁層１３は、金属電極１２同士を絶縁するための層間絶縁膜として機能する。絶縁層１３は少なくとも第１の元素及び酸素（Ｏ）を含有する。例えば、第１の元素は、シリコン（Ｓｉ）である。絶縁層１３は、酸化膜であり、例えば、シリコン酸化物（ＳｉＯ２）、又はシリコン炭素酸化物（ＳｉＯＣ）などを主成分とする。以下の説明では、第１の元素は、シリコン（Ｓｉ）であり、絶縁層１３は、シリコン酸化物（ＳｉＯ２）で形成されているとして説明する。 The insulating layer 13 functions as an interlayer insulating film for insulating the metal electrodes 12 from each other. The insulating layer 13 contains at least a first element and oxygen (O). For example, the first element is silicon (Si). The insulating layer 13 is an oxide film, and has, for example, silicon oxide (SiO 2 ) or silicon carbon oxide (SiOC) as a main component. In the following description, it is assumed that the first element is silicon (Si) and the insulating layer 13 is formed of silicon oxide (SiO 2 ).

基板２０は、下部構造２１、金属電極２２（第２の金属層）、バリアメタル層２２ａ（第２のバリアメタル層）、及び絶縁層２３（第２の絶縁層）を有する。
下部構造２１は、例えば、半導体基板とセンサ等とを含む。
金属電極２２は、基板２０の主面側表面に所定のパターンで形成される。金属電極２２は第２の金属元素を主成分として含有する。例えば、第２の金属元素は、第１の金属元素と同様、銅（Ｃｕ）である。以下の説明においては、第２の金属元素は、第１の金属元素と同様、銅（Ｃｕ）であるとして説明する。 The substrate 20 has a lower structure 21, a metal electrode 22 (second metal layer), a barrier metal layer 22a (second barrier metal layer), and an insulating layer 23 (second insulating layer).
The lower structure 21 includes, for example, a semiconductor substrate and a sensor.
The metal electrode 22 is formed in a predetermined pattern on the main surface of the substrate 20. The metal electrode 22 contains a second metal element as a main component. For example, the second metal element is copper (Cu), like the first metal element. In the following description, it is assumed that the second metal element is copper (Cu), similarly to the first metal element.

バリアメタル層２２ａは、金属電極２２と絶縁層２３の間に形成されている。バリアメタル層２２ａは、金属電極２２に含まれる金属元素（銅（Ｃｕ））が絶縁層２３に拡散するのを防止するために設けられている。バリアメタル層２２ａの主成分はバリアメタル層１２ａと同様である。また、金属電極２２は、基板２０中の図示せぬ配線と接続している。   The barrier metal layer 22a is formed between the metal electrode 22 and the insulating layer 23. The barrier metal layer 22 a is provided for preventing a metal element (copper (Cu)) contained in the metal electrode 22 from diffusing into the insulating layer 23. The main components of the barrier metal layer 22a are the same as those of the barrier metal layer 12a. The metal electrode 22 is connected to a wiring (not shown) in the substrate 20.

絶縁層２３は金属電極２２同士を絶縁するための層間絶縁膜として機能する。絶縁層２３は少なくとも第２の元素及び酸素（Ｏ）を含有する。例えば、第２の元素は第１の元素と同様、シリコン（Ｓｉ）である。絶縁層２３は酸化膜であり、例えば、シリコン酸化物（ＳｉＯ２）、又はシリコン炭素酸化物（ＳｉＯＣ）などを主成分とする。以下の説明では、第２の元素は、シリコン（Ｓｉ）であり、絶縁層２３は、シリコン酸化物（ＳｉＯ２）で形成されているとして説明する。 The insulating layer 23 functions as an interlayer insulating film for insulating the metal electrodes 22 from each other. The insulating layer 23 contains at least a second element and oxygen (O). For example, the second element is silicon (Si), like the first element. The insulating layer 23 is an oxide film, and has, for example, silicon oxide (SiO 2 ) or silicon carbon oxide (SiOC) as a main component. In the following description, it is assumed that the second element is silicon (Si) and the insulating layer 23 is formed of silicon oxide (SiO 2 ).

基板１０及び基板２０は、金属電極１２、２２同士が対向するように、主面同士を向い合せて貼り合わされている。基板１０及び基板２０の間には、第１の界面層４１、第２の界面層４２、第３の界面層４３、及び第４の界面層４４が形成されている。
第１の界面層４１は、金属電極１２と金属電極２２との界面に設けられている。第１の界面層４１は、第１の金属元素及び第２の金属元素の少なくとも一方と第３の金属元素とを含有する。第３の金属元素は、例えばマンガン（Ｍｎ）である。また、上述したように、第１の金属元素及び第２の金属元素が銅（Ｃｕ）である場合、第１の界面層４１には、Ｃｕ（銅）及びＭｎ（マンガン）が含有されている。また、第１の界面層４１は導電性を有しており、第１の界面層４１を介した金属電極１２、２２間の導通を実現できる。 The substrate 10 and the substrate 20 are bonded together with their main surfaces facing each other such that the metal electrodes 12 and 22 face each other. Between the substrate 10 and the substrate 20, a first interface layer 41, a second interface layer 42, a third interface layer 43, and a fourth interface layer 44 are formed.
The first interface layer 41 is provided at the interface between the metal electrode 12 and the metal electrode 22. The first interface layer 41 contains at least one of a first metal element and a second metal element and a third metal element. The third metal element is, for example, manganese (Mn). Further, as described above, when the first metal element and the second metal element are copper (Cu), the first interface layer 41 contains Cu (copper) and Mn (manganese). . Further, the first interface layer 41 has conductivity, and electrical conduction between the metal electrodes 12 and 22 via the first interface layer 41 can be realized.

第２の界面層４２は、絶縁層１３と絶縁層２３との界面に設けられている。第２の界面層４２は、第１の元素及び第２の元素の少なくとも一方と第３の金属元素と酸素（Ｏ）とを含有する。上述したように、第１の元素及び第２の元素はシリコン（Ｓｉ）であり、第３の金属元素は、マンガン（Ｍｎ）であることから、第２の界面層４２は、マンガン（Ｍｎ）、及びシリコン（Ｓｉ）が含有された酸化物で形成されている。   The second interface layer 42 is provided at the interface between the insulating layer 13 and the insulating layer 23. The second interface layer 42 contains at least one of the first element and the second element, a third metal element, and oxygen (O). As described above, since the first element and the second element are silicon (Si) and the third metal element is manganese (Mn), the second interface layer 42 is made of manganese (Mn). And an oxide containing silicon (Si).

第２の界面層４２は絶縁性を有する。また、第２の界面層４２により、金属電極１２、金属電極２２、第１の界面層４１、後述する第３の界面層４３及び第４の界面層４４に含まれる第１及び第２の金属元素（ここでは、銅（Ｃｕ））が、互いに隣り合う金属電極１２間、及び互いに隣り合う金属電極２２間で拡散することを抑制することができる。   The second interface layer 42 has an insulating property. Further, the second interface layer 42 allows the first and second metals included in the metal electrode 12, the metal electrode 22, the first interface layer 41, the third interface layer 43 and the fourth interface layer 44 described later. The element (here, copper (Cu)) can be suppressed from diffusing between the metal electrodes 12 adjacent to each other and between the metal electrodes 22 adjacent to each other.

このように、第２の界面層４２により、基板１０内の金属電極１２同士の間、及び基板２０内の金属電極２２同士の間の漏れ電流を抑制することができる。
基板１０の金属電極１２の位置は基板２０の金属電極２２の位置と一致することが理想である。しかしながら、基板１０と基板２０とを貼り合わせる場合、基板１０の金属電極１２の位置と基板２０の金属電極２２の位置とがずれてしまう場合がある。このような場合、それらの界面には、第３の界面層４３、及び第４の界面層４４が形成される。 As described above, the second interface layer 42 can suppress the leakage current between the metal electrodes 12 in the substrate 10 and between the metal electrodes 22 in the substrate 20.
Ideally, the position of the metal electrode 12 on the substrate 10 coincides with the position of the metal electrode 22 on the substrate 20. However, when the substrate 10 and the substrate 20 are bonded to each other, the position of the metal electrode 12 of the substrate 10 and the position of the metal electrode 22 of the substrate 20 may be shifted. In such a case, a third interface layer 43 and a fourth interface layer 44 are formed at those interfaces.

第３の界面層４３は、基板１０の金属電極１２と基板２０の絶縁層２３との界面に設けられている。第３の界面層４３は、第１の部分４３ａと第２の部分４３ｂとを有する。第１の部分４３ａは、第１の金属元素（銅（Ｃｕ））と第３の金属元素（マンガン（Ｍｎ））とを含有する。第１の部分４３ａは、第３の界面層４３における金属電極１２側に設けられている。第２の部分４３ｂは、第２の元素（シリコン（Ｓｉ））と第３の金属元素（マンガン（Ｍｎ））と酸素（Ｏ）とを含有する。また、第２の部分４３ｂは、第３の界面層４３における絶縁層２３側に設けられている。   The third interface layer 43 is provided at the interface between the metal electrode 12 of the substrate 10 and the insulating layer 23 of the substrate 20. The third interface layer 43 has a first portion 43a and a second portion 43b. The first portion 43a contains a first metal element (copper (Cu)) and a third metal element (manganese (Mn)). The first portion 43a is provided on the third interface layer 43 on the metal electrode 12 side. The second portion 43b contains a second element (silicon (Si)), a third metal element (manganese (Mn)), and oxygen (O). The second portion 43b is provided on the third interface layer 43 on the insulating layer 23 side.

第４の界面層４４は、基板１０の絶縁層１３と基板２０の金属電極２２との界面に設けられている。第４の界面層４４は、第１の部分４４ａと第２の部分４４ｂとを有している。
第１の部分４４ａは、第２の金属元素（銅（Ｃｕ））と第３の金属元素（Ｍｎ（マンガン））とを含有する。また、第１の部分４４ａは、第４の界面層４４における金属電極２２側に設けられている。第２の部分４４ｂは、第１の元素（シリコン（Ｓｉ））と第３の金属元素（マンガン（Ｍｎ））と酸素（Ｏ）とを含有する。また、第２の部分４４ｂは、第４の界面層４４における絶縁層１３側に設けられている。 The fourth interface layer 44 is provided at the interface between the insulating layer 13 of the substrate 10 and the metal electrode 22 of the substrate 20. The fourth interface layer 44 has a first portion 44a and a second portion 44b.
The first portion 44a contains a second metal element (copper (Cu)) and a third metal element (Mn (manganese)). Further, the first portion 44a is provided on the metal electrode 22 side in the fourth interface layer 44. The second portion 44b contains a first element (silicon (Si)), a third metal element (manganese (Mn)), and oxygen (O). Further, the second portion 44b is provided on the insulating layer 13 side of the fourth interface layer 44.

第３の界面層４３の第２の部分４３ｂは、基板１０の金属電極１２、第１の界面層４１及び第３の界面層４３の第１の部分４３ａから銅（Ｃｕ）が基板２０の絶縁層２３に拡散することを抑制できる。同様に、第４の界面層４４の第２の部分４４ｂは、基板２０の金属電極２２、第１の界面層４１及び第４の界面層４４の第１の部分４４ａから銅（Ｃｕ）が基板１０の絶縁層１３に拡散することを抑制できる。   The second portion 43b of the third interface layer 43 is formed by insulating the substrate 20 from copper (Cu) from the metal electrode 12, the first interface layer 41, and the first portion 43a of the third interface layer 43. Diffusion into the layer 23 can be suppressed. Similarly, the second portion 44b of the fourth interface layer 44 is formed by a copper (Cu) substrate from the metal electrode 22, the first interface layer 41, and the first portion 44a of the fourth interface layer 44. Diffusion into the ten insulating layers 13 can be suppressed.

次に、実施形態に係る半導体装置１の製法方法を図２及び図３を用いて説明する。
まず、図２に示すような構造を形成する。なお、以下の説明では、便宜上、基板１０の工程と基板２０の工程とを並列に記述しているが、基板１０の工程と基板２０の工程とはそれぞれ独立して行われる。 Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described with reference to FIGS.
First, a structure as shown in FIG. 2 is formed. In the following description, for convenience, the process of the substrate 10 and the process of the substrate 20 are described in parallel, but the process of the substrate 10 and the process of the substrate 20 are performed independently.

図２に示すように、基板１０においては下部構造１１を形成し、基板２０においては下部構造２１を形成する。
次に、基板１０の下部構造１１上に絶縁層１３を、基板２０の下部構造２１上に絶縁層２３を形成する。絶縁層１３及び絶縁層２３は、ＣＶＤ法等を用いて形成される。 As shown in FIG. 2, a lower structure 11 is formed on the substrate 10 and a lower structure 21 is formed on the substrate 20.
Next, the insulating layer 13 is formed on the lower structure 11 of the substrate 10, and the insulating layer 23 is formed on the lower structure 21 of the substrate 20. The insulating layers 13 and 23 are formed using a CVD method or the like.

次に、基板１０においてはバリアメタル層１２ａを、基板２０においてはバリアメタル層２２ａを形成する。ここでは、基板１０の絶縁層１３上にレジスト膜を形成し、そのレジスト膜をマスクとしてドライエッチング処理を行うことで、絶縁層１３に溝を形成し、その形成された溝の側面及び底面と絶縁層１３表面にバリアメタル層１２ａを形成する。バリアメタル層１２ａは、チタン（Ｔｉ）、タリウム（Ｔａ）、ルテニウム（Ｒｕ）、又はそれらの窒化物（窒化チタン（ＴｉＮ）、ＴａＮ（窒化タリウム）、窒化ルテニウム（ＲｕＮ））などをＡｒ／Ｎ２雰囲気中でスパッタリングすることで生成される。バリアメタル層２２ａも同様にして、基板２０に形成される。 Next, a barrier metal layer 12a is formed on the substrate 10, and a barrier metal layer 22a is formed on the substrate 20. Here, a groove is formed in the insulating layer 13 by forming a resist film on the insulating layer 13 of the substrate 10 and performing dry etching using the resist film as a mask, and forming a groove on the side and bottom surfaces of the formed groove. The barrier metal layer 12a is formed on the surface of the insulating layer 13. The barrier metal layer 12a is made of titanium (Ti), thallium (Ta), ruthenium (Ru), or a nitride thereof (titanium nitride (TiN), TaN (thallium nitride), ruthenium nitride (RuN)) or the like. It is generated by sputtering in two atmospheres. The barrier metal layer 22a is similarly formed on the substrate 20.

次に、基板１０においてはバリアメタル層１２ａが形成された溝に金属電極１２を形成し、基板２０においてはバリアメタル層２２ａが形成された溝に金属電極２２を形成する。金属電極１２及び金属電極２２は電解メッキ法により、銅（Ｃｕ）で形成される。   Next, in the substrate 10, the metal electrode 12 is formed in the groove where the barrier metal layer 12a is formed, and in the substrate 20, the metal electrode 22 is formed in the groove where the barrier metal layer 22a is formed. The metal electrode 12 and the metal electrode 22 are formed of copper (Cu) by an electrolytic plating method.

さらに、基板１０においては金属電極１２及びバリアメタル層１２ａを、基板２０においては金属電極２２及びバリアメタル層２２ａをＣＭＰ等によって研磨して平坦化することで図２に示す状態になる。即ち、基板１０の表面に金属電極１２、バリアメタル層１２ａ、及び絶縁層１３が露出した状態になる。同様に、基板２０の表面に金属電極２２、バリアメタル層２２ａ、及び絶縁層２３が露出した状態になる。   Further, the metal electrode 12 and the barrier metal layer 12a in the substrate 10 and the metal electrode 22 and the barrier metal layer 22a in the substrate 20 are polished and flattened by CMP or the like, so that a state shown in FIG. 2 is obtained. That is, the metal electrode 12, the barrier metal layer 12a, and the insulating layer 13 are exposed on the surface of the substrate 10. Similarly, the metal electrode 22, the barrier metal layer 22a, and the insulating layer 23 are exposed on the surface of the substrate 20.

次に、図３に示すように、スパッタ法を用いて、基板１０においては金属電極１２上及び絶縁層１３上にＭｎ層３０ａを形成し、基板２０においては金属電極２２上及び絶縁層２３上にＭｎ層３０ｂを形成する。この際のＭｎ層３０ａ及びＭｎ層３０ｂの厚さは、例えば２ｎｍである。   Next, as shown in FIG. 3, an Mn layer 30a is formed on the metal electrode 12 and the insulating layer 13 on the substrate 10 by using a sputtering method, and on the metal electrode 22 and the insulating layer 23 on the substrate 20. Then, a Mn layer 30b is formed. At this time, the thickness of the Mn layer 30a and the Mn layer 30b is, for example, 2 nm.

次に、基板１０及び基板２０の表面に対して、１分程度Ｎ２プラズマ処理を行う。このＮ２プラズマ処理は、例えば、高周波電源の出力が２５０Ｗ、高周波電源の周波数が３５０ｋＨｚ、Ｎ２の流量が３５ｓｃｃｍ、時間が１分（６０秒）間という条件で行われる。ここでは、Ｎ２プラズマ処理を行うとしたが、Ｍｎ層３０ａ、３０ｂ表面の不純物等を取り除くために追加で水洗処理を行ってもよい。水洗処理に限らず、薬液を用いた処理を行ってもよい。 Next, N 2 plasma treatment is performed on the surfaces of the substrate 10 and the substrate 20 for about one minute. This N 2 plasma processing is performed, for example, under the conditions that the output of the high frequency power supply is 250 W, the frequency of the high frequency power supply is 350 kHz, the flow rate of N 2 is 35 sccm, and the time is 1 minute (60 seconds). Here, the N 2 plasma processing is performed, but an additional water washing processing may be performed to remove impurities and the like on the surfaces of the Mn layers 30a and 30b. Not only the washing process but also a process using a chemical solution may be performed.

次に、図１に示すように、基板１０の主面と基板２０の主面とを向い合せて、金属電極１２の位置と金属電極２２の位置とが対応するように基板１０と基板２０とを貼り合わせる。このとき、金属電極１２の位置と金属電極２２の位置とが完全に一致せず、金属電極１２の一部に対向する位置に絶縁層２３が位置し、金属電極２２の一部に対向する位置に絶縁層１３が位置する場合がある。図１は、このような場合について示している。   Next, as shown in FIG. 1, the main surface of the substrate 10 and the main surface of the substrate 20 face each other, and the substrate 10 and the substrate 20 are positioned so that the position of the metal electrode 12 and the position of the metal electrode 22 correspond to each other. Paste. At this time, the position of the metal electrode 12 does not completely match the position of the metal electrode 22, and the insulating layer 23 is located at a position facing a part of the metal electrode 12, and is located at a position facing the part of the metal electrode 22. There is a case where the insulating layer 13 is located at the bottom. FIG. 1 shows such a case.

基板１０及び基板２０を貼り合わせた後、基板１０と基板２０とに熱処理を行う。このとき、例えば、基板１０及び基板２０は、Ｎ２雰囲気、大気圧で、１時間、２５０℃で加熱される。
Ｎ２プラズマ処理及び熱処理を行うことで、金属電極１２及び金属電極２２に含まれる銅（Ｃｕ）が拡散し、Ｍｎ層３０ａ及びＭｎ層３０ｂ中に導入される。そして、金属電極１２及び金属電極２２の界面には、マンガン（Ｍｎ）と銅（Ｃｕ）とを含む第１の界面層４１が形成される。 After the substrates 10 and 20 are bonded to each other, heat treatment is performed on the substrates 10 and 20. At this time, for example, the substrate 10 and the substrate 20 are heated at 250 ° C. for 1 hour in an N 2 atmosphere at atmospheric pressure.
By performing the N 2 plasma treatment and the heat treatment, copper (Cu) contained in the metal electrodes 12 and 22 diffuses and is introduced into the Mn layers 30a and 30b. Then, a first interface layer 41 containing manganese (Mn) and copper (Cu) is formed at the interface between the metal electrode 12 and the metal electrode 22.

また、Ｎ２プラズマ処理及び熱処理を行うことで、絶縁層１３及び絶縁層２３に含まれるシリコン（Ｓｉ）及び酸素（Ｏ）がＭｎ層３０ａ及びＭｎ層３０ｂ中に導入される。これにより、絶縁層１３及び絶縁層２３の界面には、マンガン（Ｍｎ）、シリコン（Ｓｉ）及び酸素（Ｏ）を含む第２の界面層４２が形成される。 Further, by performing the N 2 plasma treatment and the heat treatment, silicon (Si) and oxygen (O) included in the insulating layers 13 and 23 are introduced into the Mn layers 30a and 30b. Thus, a second interface layer 42 containing manganese (Mn), silicon (Si), and oxygen (O) is formed at the interface between the insulating layers 13 and 23.

なお、第２の界面層４２に含まれる酸素（Ｏ）は、絶縁層１３及び絶縁層２３から導入されたもの、基板１０、２０同士の貼り合わせ前にＭｎ層３０ａ及びＭｎ層３０ｂ表面の酸化よってＭｎ層３０ａ及びＭｎ層３０ａに含まれるに至ったもの、Ｍｎ層３０ａ及びＭｎ層３０ｂの成膜以降の熱工程中に、基板１０及び基板２０上の絶縁層１３及び絶縁層２３に含有された水分によってＭｎ層３０ａ及びＭｎ層３０ｂが酸化されることで導入されたものがある。   Note that oxygen (O) contained in the second interface layer 42 is introduced from the insulating layers 13 and 23, and oxidizes the surfaces of the Mn layers 30a and 30b before the substrates 10 and 20 are bonded to each other. Therefore, those included in the Mn layer 30a and the Mn layer 30a and contained in the insulating layer 13 and the insulating layer 23 on the substrate 10 and the substrate 20 during the heating process after the formation of the Mn layer 30a and the Mn layer 30b. Some are introduced by oxidizing the Mn layer 30a and the Mn layer 30b by the moisture.

また、上述した貼り合わせ工程により、金属電極１２の位置と、金属電極２２の位置とが一致していない部分には、第３の界面層及び第４の界面層が形成される。
基板１０及び基板２０表面にＭｎ層を形成しないで、基板１０及び基板２０を貼り合わせる場合、即ち、基板１０の金属電極１２と基板２０の金属電極２２とを直接を接合する場合、貼り合わせずれが生じることで以下の問題が生じる。貼り合わせずれとは、基板１０の金属電極１２と基板２０の絶縁層２３とが接触する部分、基板２０の金属電極２２と基板１０の絶縁層１３とが接触する部分が生じることである。 Further, by the above-described bonding step, a third interface layer and a fourth interface layer are formed in a portion where the position of the metal electrode 12 does not match the position of the metal electrode 22.
When the substrate 10 and the substrate 20 are bonded without forming the Mn layer on the surfaces of the substrate 10 and the substrate 20, that is, when the metal electrode 12 of the substrate 10 is directly bonded to the metal electrode 22 of the substrate 20, the bonding misalignment occurs. Causes the following problems. The misalignment means that a portion where the metal electrode 12 of the substrate 10 contacts the insulating layer 23 of the substrate 20 and a portion where the metal electrode 22 of the substrate 20 contacts the insulating layer 13 of the substrate 10 occur.

貼り合わせずれの部分では、一方の基板の金属電極を構成する銅（Ｃｕ）が、他方の基板の絶縁層中に拡散してしまう。これにより、半導体装置１の電気特性、信頼性が低下するおそれがある。また、絶縁層１３及び絶縁層２３同士の接合界面はバルクの絶縁層と異なり微小な欠陥が存在すると、金属電極１２及び２２を構成する銅（Ｃｕ）が拡散しやすいため、金属電極１２及び金属電極２２を構成する銅（Ｃｕ）が界面を拡散し得る。この場合、同じ基板内の金属電極間でショートしたり、金属電極間のＴＤＤＢ劣化が生じる。   In the part where the bonding is displaced, copper (Cu) constituting the metal electrode of one substrate diffuses into the insulating layer of the other substrate. As a result, the electrical characteristics and reliability of the semiconductor device 1 may be reduced. In addition, unlike a bulk insulating layer, when a minute defect exists at the bonding interface between the insulating layers 13 and 23, copper (Cu) forming the metal electrodes 12 and 22 is easily diffused. Copper (Cu) constituting the electrode 22 may diffuse at the interface. In this case, a short circuit occurs between the metal electrodes in the same substrate, and TDDB deterioration between the metal electrodes occurs.

また、基板１０の表面は、金属電極（銅（Ｃｕ））１２と絶縁層（シリコン酸化物（ＳｉＯ２））１３とバリアメタル層１２ａとで構成されている。即ち、基板１０表面は異なる材料で構成された複数の層が露出している。このため、基板１０及び基板２０を接合する前の処理を最適化することが難しい。例えば、絶縁層１３を接合に適した状態にするためにプラズマ処理、洗浄などを実行した場合、金属電極１２表面が酸化してしまう。基板２０についても同様である。 The surface of the substrate 10 includes a metal electrode (copper (Cu)) 12, an insulating layer (silicon oxide (SiO 2 )) 13, and a barrier metal layer 12a. That is, a plurality of layers made of different materials are exposed on the surface of the substrate 10. For this reason, it is difficult to optimize the processing before joining the substrate 10 and the substrate 20. For example, when plasma treatment, cleaning, or the like is performed to make the insulating layer 13 suitable for bonding, the surface of the metal electrode 12 is oxidized. The same applies to the substrate 20.

また、基板１０及び基板２０表面にＭｎ層を形成しない場合、基板１０及び基板２０の表面の金属電極部分に凹みを有する状態で基板１０及び基板２０を貼り合わせ、熱処理を行うことで、金属電極１２、２２を膨張させて基板１０の金属電極１２と基板２０の金属電極２２とを接合していた。この場合、貼り合わせずれ部分において隙間が生じることがあり、基板１０、２０同士を強固に貼り付けることが難しい。   When the Mn layer is not formed on the surfaces of the substrate 10 and the substrate 20, the substrate 10 and the substrate 20 are attached to each other in a state where the metal electrode portion on the surface of the substrate 10 and the substrate 20 has a depression, and heat treatment is performed. The metal electrodes 12 of the substrate 10 and the metal electrode 22 of the substrate 20 were joined by expanding the metal electrodes 12 and 22. In this case, a gap may be formed in a bonding displacement portion, and it is difficult to firmly bond the substrates 10 and 20 to each other.

これに対して、本実施形態における半導体装置１は、基板１０及び基板２０の表面にそれぞれＭｎ層３０ａ、３０ｂを形成した後、基板１０、２０同士の接合前処理（Ｎ２プラズマ処理）、基板１０、２０同士の貼り合わせ、接合後処理（熱処理）を行うことで、上述したように、基板１０及び基板２０の界面に、絶縁性を有し、金属元素（銅（Ｃｕ））の拡散を抑制する性質を有する第２の界面層４２が形成される。このため、基板１０及び基板２０を接合した後において、同一基板内の金属電極間における漏れ電流を抑制することができる。よって、同一基板内での金属電極間でのショート、金属電極間のＴＤＤＢ劣化を抑制できる。 In contrast, the semiconductor device 1 in the present embodiment, after forming Mn layer 30a, and 30b respectively on the surface of the substrate 10 and the substrate 20, before bonding between the substrates 10 and 20 treated (N 2 plasma treatment), the substrate As described above, the bonding between the substrates 10 and 20 and the post-bonding treatment (heat treatment) are performed, and as described above, the interface between the substrate 10 and the substrate 20 has an insulating property and prevents diffusion of the metal element (copper (Cu)). The second interface layer 42 having the property of suppressing is formed. For this reason, after joining the substrate 10 and the substrate 20, the leakage current between the metal electrodes in the same substrate can be suppressed. Therefore, short-circuit between metal electrodes and TDDB deterioration between metal electrodes in the same substrate can be suppressed.

また、基板１０及び基板２０の界面には、導電性を有する第１の界面層４１が形成されるため、基板１０の金属電極１２と基板２０の金属電極２２間の導通を確保できる。
さらに基板１０と基板２０との貼り合わせずれの部分には、第３の界面層４３と第４の界面層４４が形成されるため、金属電極１２、２２を構成する金属元素（Ｃｕ）が、他方の基板の絶縁層中へ拡散することを抑制できる。 In addition, since the first interface layer 41 having conductivity is formed at the interface between the substrate 10 and the substrate 20, conduction between the metal electrode 12 of the substrate 10 and the metal electrode 22 of the substrate 20 can be secured.
Further, since the third interface layer 43 and the fourth interface layer 44 are formed at the portion where the substrates 10 and 20 are bonded to each other, the metal element (Cu) forming the metal electrodes 12 and 22 is Diffusion into the insulating layer of the other substrate can be suppressed.

また、基板１０及び基板２０の接合界面全面がマンガン（Ｍｎ）を主成分とする層から構成されるため、接合前処理の最適化が容易となる。例えば、Ｎ２プラズマ処理、水洗処理による金属電極の酸化を防止できる。
また、第１〜第４の界面層４１、４２、４３、４４は、高い密着性を有しており、基板１０と基板２０とを強固に接合することが可能である。 Further, since the entire bonding interface between the substrate 10 and the substrate 20 is composed of a layer containing manganese (Mn) as a main component, optimization of pre-bonding processing is facilitated. Eg, N 2 plasma treatment, oxidation of the metal electrode due to water washing treatment can be prevented.
Further, the first to fourth interface layers 41, 42, 43, and 44 have high adhesiveness, and can firmly join the substrate 10 and the substrate 20.

したがって、上述した基板１０の金属電極１２と基板２０の金属電極２２との貼り合わせずれが生じる場合の問題点を改善できる。
なお、金属電極１２に含まれる第１の金属元素として、銅（Ｃｕ）の代わりにタングステン（Ｗ）が用いられてもよい。金属電極２２に含まれる第２の金属元素についても同様、銅（Ｃｕ）の代わりにタングステン（Ｗ）が用いられてもよい。 Therefore, it is possible to improve the problem in the case where the bonding displacement between the metal electrode 12 of the substrate 10 and the metal electrode 22 of the substrate 20 occurs.
Note that as the first metal element included in the metal electrode 12, tungsten (W) may be used instead of copper (Cu). Similarly, for the second metal element included in the metal electrode 22, tungsten (W) may be used instead of copper (Cu).

また、第１〜第４の界面層４１、４２、４３、４４の主成分である第３の金属元素はマンガン（Ｍｎ）であるとして説明したが、第１〜第４の界面層４１、４２、４３、４４には主成分として、Ｍｎ（マンガン）、アルミニウム（Ａｌ）、バナジウム（Ｖ）、亜鉛（Ｚｎ）、ニオブ（Ｎｂ）、ジルコニウム（Ｚｒ）、クロム（Ｃｒ）、イットリウム（Ｙ）、テクネチウム（Ｔｃ）及びレニウム（Ｒｅ）から選択された金属元素が含まれればよい。   In addition, although the third metal element that is a main component of the first to fourth interface layers 41, 42, 43, and 44 is described as being manganese (Mn), the first to fourth interface layers 41 and 42 are described. , 43, and 44 have, as main components, Mn (manganese), aluminum (Al), vanadium (V), zinc (Zn), niobium (Nb), zirconium (Zr), chromium (Cr), yttrium (Y), It suffices that a metal element selected from technetium (Tc) and rhenium (Re) is included.

なお、上述した説明において、図３に示すＭｎ層を形成する工程において、基板１０及び基板２０にそれぞれＭｎ層３０ａ，３０ｂを形成するとしたが、一方の基板のみにＭｎ層を形成し、基板１０と基板２０とを貼り合わせてもよい。
また、第１の界面層４１にはさらに酸素（Ｏ）が含有されていてもよい。即ち、図３に示す、基板１０及び基板２０それぞれにＭｎ層３０ａ及びＭｎ層３０ｂを形成することに替えて、マンガン酸化物（ＭｎＯ２）層を形成してもよい。 In the above description, in the step of forming the Mn layer shown in FIG. 3, the Mn layers 30a and 30b are formed on the substrate 10 and the substrate 20, respectively. And the substrate 20 may be bonded.
Further, the first interface layer 41 may further contain oxygen (O). That is, a manganese oxide (MnO 2 ) layer may be formed instead of forming the Mn layer 30a and the Mn layer 30b on the substrate 10 and the substrate 20, respectively, as shown in FIG.

以上、本実施形態によれば、基板間の良好な界面特性を有する複数の基板同士が接合された半導体装置を提供できる。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 As described above, according to the present embodiment, it is possible to provide a semiconductor device in which a plurality of substrates having good interface characteristics between the substrates are joined.
Although several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

１…半導体装置 １０…基板 １１…下部構造 １２…金属電極
１２ａ…バリアメタル層 １３…絶縁層 ２０…基板 ２１…下部構造
２２…金属電極 ２２ａ…バリアメタル層 ２３…絶縁層
３０ａ，３０ｂ…Ｍｎ層 ４１…第１の界面層 ４２…第２の界面層
４３…第３の界面層 ４３ａ…第１の部分 ４３ｂ…第２の部分
４４…第４の界面層 ４４ａ…第１の部分 ４４ｂ…第２の部分 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Substrate 11 ... Lower structure 12 ... Metal electrode 12a ... Barrier metal layer 13 ... Insulating layer 20 ... Substrate 21 ... Lower structure
22 metal electrode 22a barrier metal layer 23 insulating layer
30a, 30b: Mn layer 41: first interface layer 42: second interface layer
43: third interface layer 43a: first portion 43b: second portion
44: fourth interface layer 44a: first portion 44b: second portion

Claims (9)

第１の金属元素を含有する第１の金属層と、第１の元素及び酸素（Ｏ）を含有する第１の絶縁層とを含む第１の基板と、
第２の金属元素を含有する第２の金属層と、第２の元素及び酸素（Ｏ）を含有する第２の絶縁層とを含む第２の基板と、
前記第１の金属層と前記第２の金属層との界面に設けられ、前記第１の金属元素及び前記第２の金属元素の少なくとも一方と第３の金属元素とを含有し、導電性を有する第１の界面層と、
前記第１の絶縁層と前記第２の絶縁層との界面に設けられ、前記第１の元素及び前記第２の元素の少なくとも一方と前記第３の金属元素と酸素（Ｏ）とを含有し、絶縁性を有する第２の界面層と
を備えることを特徴とする半導体装置。 A first substrate including a first metal layer containing a first metal element, and a first insulating layer containing the first element and oxygen (O);
A second substrate including a second metal layer containing a second metal element and a second insulating layer containing a second element and oxygen (O);
An interface is provided at an interface between the first metal layer and the second metal layer and contains at least one of the first metal element and the second metal element and a third metal element, and has conductivity. A first interface layer having
The semiconductor device is provided at an interface between the first insulating layer and the second insulating layer and contains at least one of the first element and the second element, the third metal element, and oxygen (O). And a second interface layer having an insulating property. 前記第１の金属層と前記第２の絶縁層との界面に設けられ、前記第１の金属元素と前記第３の金属元素とを含有し且つ前記第１の金属層側に設けられた第１の部分と、前記第２の元素と前記第３の金属元素と酸素（Ｏ）とを含有し且つ前記第２の絶縁層側に設けられた第２の部分とを含む第３の界面層をさらに備えることを特徴とする請求項１記載の半導体装置。   A first metal layer provided at an interface between the first metal layer and the second insulating layer, containing the first metal element and the third metal element, and provided at a side of the first metal layer; A third interface layer including a first portion and a second portion including the second element, the third metal element, and oxygen (O) and provided on the second insulating layer side; The semiconductor device according to claim 1, further comprising: 前記第２の金属層と前記第１の絶縁層との界面に設けられ、前記第２の金属元素と前記第３の金属元素とを含有し且つ前記第２の金属層側に設けられた第１の部分と、前記第１の元素と前記第３の金属元素と酸素（Ｏ）とを含有し且つ前記第１の絶縁層側に設けられた第２の部分とを含む第４の界面層をさらに備えることを特徴とする請求項１記載の半導体装置。   A second metal layer provided at an interface between the second metal layer and the first insulating layer, the second metal layer containing the second metal element and the third metal element, and a second metal layer provided on the side of the second metal layer; A fourth interface layer including a first portion, a second portion including the first element, the third metal element, and oxygen (O) and provided on the first insulating layer side; The semiconductor device according to claim 1, further comprising: 前記第１の金属元素は、銅（Ｃｕ）及びタングステン（Ｗ）から選択され、
前記第２の金属元素は、銅（Ｃｕ）及びタングステン（Ｗ）から選択されることを特徴とする請求項１記載の半導体装置。 The first metal element is selected from copper (Cu) and tungsten (W);
2. The semiconductor device according to claim 1, wherein the second metal element is selected from copper (Cu) and tungsten (W). 前記第１の元素及び前記第２の元素はシリコン（Ｓｉ）であることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the first element and the second element are silicon (Si). 前記第３の金属元素は、マンガン（Ｍｎ）、アルミニウム（Ａｌ）、バナジウム（Ｖ）、亜鉛（Ｚｎ）、ニオブ（Ｎｂ）、ジルコニウム（Ｚｒ）、クロム（Ｃｒ）、イットリウム（Ｙ）、テクネチウム（Ｔｃ）及びレニウム（Ｒｅ）から選択されることを特徴とする請求項１記載の半導体装置。   The third metal element is manganese (Mn), aluminum (Al), vanadium (V), zinc (Zn), niobium (Nb), zirconium (Zr), chromium (Cr), yttrium (Y), technetium ( 2. The semiconductor device according to claim 1, wherein the semiconductor device is selected from Tc) and rhenium (Re). 前記第１の界面層は、銅（Ｃｕ）及びＭｎ（マンガン）を含有することを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the first interface layer contains copper (Cu) and Mn (manganese). 前記第１の界面層にはさらに酸素（Ｏ）が含有されることを特徴とする請求項７記載の半導体装置。   The semiconductor device according to claim 7, wherein the first interface layer further contains oxygen (O). 前記第２の界面層は、シリコン（Ｓｉ）、酸素（Ｏ）及びマンガン（Ｍｎ）を含有することを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the second interface layer contains silicon (Si), oxygen (O), and manganese (Mn).
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