CN110880452A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN110880452A
CN110880452A CN201910137521.4A CN201910137521A CN110880452A CN 110880452 A CN110880452 A CN 110880452A CN 201910137521 A CN201910137521 A CN 201910137521A CN 110880452 A CN110880452 A CN 110880452A
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layer
metal
substrate
interface
insulating layer
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津村一道
东和幸
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Abstract

Embodiments relate to a semiconductor device. A semiconductor device having excellent interface characteristics between substrates is provided. A semiconductor device according to an embodiment includes a 1 st substrate, a 2 nd substrate, a conductive 1 st interface layer, and an insulating 2 nd interface layer. The 1 st substrate includes a 1 st metal layer containing a 1 st metal element, and a 1 st insulating layer containing a 1 st element and oxygen. The 2 nd substrate includes a 2 nd metal layer containing a 2 nd metal element, and a 2 nd insulating layer containing a 2 nd element and oxygen. The 1 st interface layer is disposed on an interface of the 1 st metal layer and the 2 nd metal layer, and includes a 3 rd metal element and at least one of a 1 st metal element and a 2 nd metal element. The 2 nd interface layer is disposed on an interface between the 1 st insulating layer and the 2 nd insulating layer, and includes at least one of the 1 st element and the 2 nd element, a 3 rd metal element, and oxygen.

Description

Semiconductor device with a plurality of semiconductor chips
The present application is based on Japanese patent application 2018-. This application is incorporated by reference into this application in its entirety.
Technical Field
Embodiments of the present invention relate to a semiconductor device.
Background
A technique (Wafer-to-Wafer (W2W)/Hybrid bonding) for bonding 2 substrates (wafers) having a metal electrode pattern on the surface thereof was developed. In this technique, a metal electrode and an insulating layer are formed on the main surface side of each substrate, and 2 substrates are bonded to each other to bond the metal electrodes to each other.
Disclosure of Invention
The problems to be solved by the present invention are: a semiconductor device having excellent interface characteristics between substrates is provided.
Means for solving the problems
A semiconductor device according to an embodiment includes a 1 st substrate, a 2 nd substrate, a 1 st interface layer, and a 2 nd interface layer. The 1 st substrate includes a 1 st metal layer containing a 1 st metal element and a 1 st insulating layer containing a 1 st element and oxygen (O). The 2 nd substrate includes a 2 nd metal layer containing a 2 nd metal element and a 2 nd insulating layer containing a 2 nd element and oxygen (O). The 1 st interface layer is provided at an interface between the 1 st metal layer and the 2 nd metal layer, contains at least one of the 1 st metal element and the 2 nd metal element, and a 3 rd metal element, and has conductivity. The 2 nd interface layer is provided at an interface between the 1 st insulating layer and the 2 nd insulating layer, contains at least one of the 1 st element and the 2 nd element, the 3 rd metal element, and oxygen (O), and has insulating properties.
According to the semiconductor device having the above configuration, the interface characteristics between the substrates can be improved.
Drawings
Fig. 1 is a cross-sectional view schematically showing the structure of a semiconductor device according to an embodiment.
Fig. 2 is a cross-sectional view showing a part of a method for manufacturing a semiconductor device according to an embodiment.
Fig. 3 is a cross-sectional view showing a part of a method for manufacturing a semiconductor device according to an embodiment.
Description of the symbols
1 … semiconductor device, 10 … substrate, 11 … lower structure, 12 … metal electrode, 12a … barrier metal layer, 13 … insulating layer, 20 … substrate, 21 … lower structure, 22 … metal electrode, 22a … barrier metal layer, 23 … insulating layer, 30a, 30b … Mn layer, 41 … 1 st interface layer, 42 … 2 nd interface layer, 43 … 3 rd interface layer, 43a … 1 st part, 43b … 2 nd part, 44 … 4 th interface layer, 44a … 1 st part, 44b … nd part.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual views, and the dimensions, ratios, and the like of the drawings are not necessarily limited to the actual dimensions and ratios. In the drawings, the same or corresponding portions are denoted by the same reference numerals (including ones having different subscripts), and repeated descriptions are given as necessary.
Fig. 1 is a cross-sectional view schematically showing the structure of a semiconductor device 1 according to the embodiment.
The semiconductor device 1 includes a substrate 10 (1 st substrate), a substrate 20 (2 nd substrate), a 1 st interface layer 41, a 2 nd interface layer 42, a 3 rd interface layer 43, and a 4 th interface layer 44.
The substrate 10 has a lower structure 11, a metal electrode 12 (1 st metal layer), a barrier metal layer 12a (1 st barrier metal layer), and an insulating layer 13 (1 st insulating layer).
The lower structure 11 has, for example, a semiconductor substrate and a circuit including a transistor and the like.
The metal electrodes 12 are formed in a predetermined pattern on the main surface side surface of the substrate 10. The metal electrode 12 contains the 1 st metal element as a main component. For example, the 1 st metal element is copper (Cu). In the following description, the case where the 1 st metal element is copper (Cu) will be described.
The barrier metal layer 12a is formed between the metal electrode 12 and the insulating layer 13, and is provided to prevent a metal element (copper (Cu)) contained in the metal electrode 12 from diffusing into the insulating layer 13. The barrier metal layer 12a is formed of, for example, titanium (Ti), tantalum (Ta), ruthenium (Ru), or a nitride thereof (titanium nitride (TiN), tantalum nitride (TaN), ruthenium nitride (RuN)). The metal electrode 12 is connected to a wiring, not shown, on the substrate 10.
The insulating layer 13 functions as an interlayer insulating film for insulating the metal electrodes 12 from each other. The insulating layer 13 contains at least the 1 st element andoxygen (O). For example, the 1 st element is silicon (Si). The insulating layer 13 is an oxide film, for example, silicon oxide (SiO)2) Or silicon oxycarbide (SiOC) or the like as a main component. In the following description, the 1 st element is silicon (Si), and the insulating layer 13 is silicon oxide (SiO)2) The case of formation will be described.
The substrate 20 has a lower structure 21, a metal electrode 22 (2 nd metal layer), a barrier metal layer 22a (2 nd barrier metal layer), and an insulating layer 23 (2 nd insulating layer).
The lower structure 21 includes, for example, a semiconductor substrate, a sensor, and the like.
The metal electrodes 22 are formed in a predetermined pattern on the main surface side surface of the substrate 20. The metal electrode 22 contains the 2 nd metal element as a main component. For example, the 2 nd metal element is copper (Cu) as in the 1 st metal element. In the following description, a case where the 2 nd metal element is copper (Cu) as in the 1 st metal element will be described.
The barrier metal layer 22a is formed between the metal electrode 22 and the insulating layer 23. The barrier metal layer 22a is provided to prevent a metal element (copper (Cu)) contained in the metal electrode 22 from diffusing into the insulating layer 23. The main component of the barrier metal layer 22a is the same as that of the barrier metal layer 12 a. The metal electrode 22 is connected to a wiring, not shown, on the substrate 20.
The insulating layer 23 functions as an interlayer insulating film for insulating the metal electrodes 22 from each other. The insulating layer 23 contains at least the 2 nd element and oxygen (O). For example, the 2 nd element is silicon (Si) as in the 1 st element. The insulating layer 23 is an oxide film, for example, silicon oxide (SiO)2) Or silicon oxycarbide (SiOC) or the like as a main component. In the following description, the 2 nd element is silicon (Si), and the insulating layer 23 is made of silicon oxide (SiO)2) The case of formation will be described.
The substrate 10 and the substrate 20 are bonded with their main surfaces facing each other so that the metal electrodes 12 and 22 face each other. Between the substrate 10 and the substrate 20, a 1 st interface layer 41, a 2 nd interface layer 42, a 3 rd interface layer 43, and a 4 th interface layer 44 are formed.
The 1 st interface layer 41 is provided on the interface between the metal electrode 12 and the metal electrode 22. The 1 st interface layer 41 contains the 3 rd metal element and at least one of the 1 st metal element and the 2 nd metal element. The 3 rd metallic element is, for example, manganese (Mn). As described above, when the 1 st metal element and the 2 nd metal element are copper (Cu), Cu (copper) and Mn (manganese) are contained in the 1 st interface layer 41. The 1 st interface layer 41 has conductivity, and conduction between the metal electrodes 12 and 22 via the 1 st interface layer 41 can be achieved.
The 2 nd interface layer 42 is provided on the interface between the insulating layer 13 and the insulating layer 23. The 2 nd interface layer 42 contains at least one of the 1 st element and the 2 nd element, the 3 rd metal element, and oxygen (O). As described above, since the 1 st and 2 nd elements are silicon (Si) and the 3 rd metal element is manganese (Mn), the 2 nd interface layer 42 is formed of an oxide containing manganese (Mn) and silicon (Si).
The 2 nd interface layer 42 has insulation properties. Further, the diffusion of the 1 st and 2 nd metal elements (copper (Cu) in this case) contained in the metal electrodes 12, the metal electrodes 22, the 1 st interface layer 41, and the 3 rd and 4 th interface layers 43 and 44 described later into the metal electrodes 12 adjacent to each other and the metal electrodes 22 adjacent to each other can be suppressed by the 2 nd interface layer 42.
In this manner, the 2 nd interface layer 42 can suppress leakage currents between the metal electrodes 12 in the substrate 10 and between the metal electrodes 22 in the substrate 20.
It is desirable that the position of the metal electrode 12 of the substrate 10 coincides with the position of the metal electrode 22 of the substrate 20. However, when the substrate 10 and the substrate 20 are bonded to each other, the position of the metal electrode 12 of the substrate 10 may be shifted from the position of the metal electrode 22 of the substrate 20. In this case, the 3 rd interface layer 43 and the 4 th interface layer 44 are formed at their interfaces.
The 3 rd interface layer 43 is provided on the interface between the metal electrode 12 of the substrate 10 and the insulating layer 23 of the substrate 20. The 3 rd interfacial layer 43 has a 1 st portion 43a and a 2 nd portion 43 b. The 1 st portion 43a contains a 1 st metal element (copper (Cu)) and a 3 rd metal element (manganese (Mn)). The 1 st portion 43a is provided on the metal electrode 12 side in the 3 rd interface layer 43. The 2 nd portion 43b contains the 2 nd element (silicon (Si)), the 3 rd metallic element (manganese (Mn)), and oxygen (O). In addition, the 2 nd portion 43b is provided on the insulating layer 23 side in the 3 rd interface layer 43.
The 4 th interface layer 44 is provided on the interface between the insulating layer 13 of the substrate 10 and the metal electrode 22 of the substrate 20. The 4 th interface layer 44 has a 1 st portion 44a and a 2 nd portion 44 b.
The 1 st portion 44a contains a 2 nd metallic element (copper (Cu)) and a 3 rd metallic element (Mn (manganese)). In addition, the 1 st portion 44a is provided on the metal electrode 22 side in the 4 th interface layer 44. The 2 nd portion 44b contains the 1 st element (silicon (Si)), the 3 rd metallic element (manganese (Mn)), and oxygen (O). In addition, the 2 nd portion 44b is provided on the insulating layer 13 side in the 4 th interface layer 44.
The 2 nd portion 43b of the 3 rd interface layer 43 can suppress copper (Cu) from diffusing from the metal electrode 12 of the substrate 10, the 1 st interface layer 41, and the 1 st portion 43a of the 3 rd interface layer 43 into the insulating layer 23 of the substrate 20. Similarly, the 2 nd portion 44b of the 4 th interface layer 44 can suppress copper (Cu) from diffusing from the metal electrode 22 of the substrate 20, the 1 st interface layer 41, and the 1 st portion 44a of the 4 th interface layer 44 into the insulating layer 13 of the substrate 10.
Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described with reference to fig. 2 and 3.
First, a structure as shown in fig. 2 is formed. In the following description, the steps of the substrate 10 and the steps of the substrate 20 are described in parallel for convenience, but the steps of the substrate 10 and the steps of the substrate 20 are performed independently of each other.
As shown in fig. 2, a lower structure 11 is formed in the substrate 10, and a lower structure 21 is formed in the substrate 20.
Next, an insulating layer 13 is formed on the lower structure 11 of the substrate 10, and an insulating layer 23 is formed on the lower structure 21 of the substrate 20. The insulating layer 13 and the insulating layer 23 are formed by CVD or the like.
Next, the barrier metal layer 12a is formed in the substrate 10, and the barrier metal layer 22a is formed in the substrate 20. Here, a resist film is formed on the insulating layer 13 of the substrate 10, a groove is formed in the insulating layer 13 by dry etching using the resist film as a mask, and the barrier metal layer 12a is formed on the side surface and the bottom surface of the groove and the surface of the insulating layer 13. Barrier metal layer 12a throughTitanium (Ti), thallium (Ta), ruthenium (Ru), or their nitrides (titanium nitride (TiN), TaN (thallium nitride), ruthenium nitride (RuN)), etc. were put on Ar/N2Sputtering is performed in an atmosphere. The barrier metal layer 22a is formed on the substrate 20 in the same manner.
Next, the metal electrode 12 is formed in the groove in which the barrier metal layer 12a is formed in the substrate 10, and the metal electrode 22 is formed in the groove in which the barrier metal layer 22a is formed in the substrate 20. The metal electrode 12 and the metal electrode 22 are formed of copper (Cu) by an electrolytic plating method.
Further, the metal electrode 12 and the barrier metal layer 12a are polished and planarized by CMP or the like in the substrate 10, and the metal electrode 22 and the barrier metal layer 22a are polished and planarized by CMP or the like in the substrate 20, so that the state shown in fig. 2 is achieved. That is, the metal electrode 12, the barrier metal layer 12a, and the insulating layer 13 are exposed on the surface of the substrate 10. Similarly, the metal electrode 22, the barrier metal layer 22a, and the insulating layer 23 are exposed on the surface of the substrate 20.
Next, as shown in fig. 3, using a sputtering method, an Mn layer 30a is formed on the metal electrode 12 and the insulating layer 13 in the substrate 10, and an Mn layer 30b is formed on the metal electrode 22 and the insulating layer 23 in the substrate 20. The thickness of the Mn layer 30a and the Mn layer 30b in this case is, for example, 2 nm.
Subsequently, the surfaces of the substrates 10 and 20 are subjected to N for about 1 minute2And (4) carrying out plasma treatment. The N is2The plasma treatment is carried out, for example, at an output of 250W from a high-frequency power supply and at a frequency of 350kHz, N from the high-frequency power supply2The flow rate of (3) was 35sccm, and the time was 1 minute (60 seconds). Here, it is set to carry out N2The plasma treatment may be performed in order to remove impurities and the like on the surface of the Mn layers 30a and 30 b. The treatment using the chemical liquid may be performed without being limited to the water washing treatment.
Next, as shown in fig. 1, the substrate 10 and the substrate 20 are bonded so that the main surface of the substrate 10 and the main surface of the substrate 20 face each other and the position of the metal electrode 12 corresponds to the position of the metal electrode 22. In this case, the position of the metal electrode 12 and the position of the metal electrode 22 do not completely coincide with each other, and the insulating layer 23 and the insulating layer 13 may be located at positions facing the metal electrode 12 and the metal electrode 22, respectively. Fig. 1 illustrates this case.
After the substrates 10 and 20 are bonded, the substrates 10 and 20 are heat-treated. At this time, for example, the substrates 10 and 20 are at N2The mixture was heated under atmospheric pressure for 1 hour at 250 ℃.
By carrying out N2The plasma treatment and the heat treatment diffuse copper (Cu) contained in the metal electrodes 12 and 22, and the copper is introduced into the Mn layer 30a and the Mn layer 30 b. Further, a 1 st interface layer 41 containing manganese (Mn) and copper (Cu) is formed on the interface between the metal electrode 12 and the metal electrode 22.
In addition, by carrying out N2The plasma treatment and the heat treatment introduce silicon (Si) and oxygen (O) contained in the insulating layer 13 and the insulating layer 23 into the Mn layer 30a and the Mn layer 30 b. As a result, the 2 nd interface layer 42 containing manganese (Mn), silicon (Si), and oxygen (O) is formed at the interface between the insulating layer 13 and the insulating layer 23.
The oxygen (O) contained in the 2 nd interface layer 42 includes oxygen introduced from the insulating layer 13 and the insulating layer 23, oxygen contained in the Mn layer 30a and the Mn layer 30a due to oxidation of the surface of the Mn layer 30a and the Mn layer 30b before the substrates 10 and 20 are bonded to each other, and oxygen introduced by oxidation of the Mn layer 30a and the Mn layer 30b by moisture contained in the insulating layer 13 and the insulating layer 23 on the substrates 10 and 20 in the thermal process after the formation of the Mn layer 30a and the Mn layer 30 b.
In addition, in the bonding step, the 3 rd interface layer and the 4 th interface layer are formed in the portions where the position of the metal electrode 12 does not coincide with the position of the metal electrode 22.
When the substrates 10 and 20 are bonded without forming the Mn layer on the surfaces of the substrates 10 and 20, that is, when the metal electrode 12 of the substrate 10 and the metal electrode 22 of the substrate 20 are directly bonded, the following problem occurs due to bonding misalignment. The bonding misalignment is a portion where the metal electrode 12 of the substrate 10 contacts the insulating layer 23 of the substrate 20, and a portion where the metal electrode 22 of the substrate 20 contacts the insulating layer 13 of the substrate 10.
In the portion where the bonding misalignment occurs, copper (Cu) constituting a metal electrode of one substrate diffuses into an insulating layer of the other substrate. This may reduce the electrical characteristics and reliability of the semiconductor device 1. In addition, if the bonding interface between the insulating layer 13 and the insulating layer 23 is different from the insulating layer of the body (bulk) and has a minute defect, copper (Cu) constituting the metal electrodes 12 and 22 is easily diffused, so that copper (Cu) constituting the metal electrodes 12 and 22 can be diffused in the interface. In this case, a short circuit occurs between metal electrodes in the same substrate, or TDDB between metal electrodes deteriorates.
The surface of the substrate 10 is composed of a metal electrode (copper (Cu))12 and an insulating layer (silicon oxide (SiO)) 122) 13) and a barrier metal layer 12 a. That is, a plurality of layers made of different materials are exposed on the surface of the substrate 10. Therefore, it is difficult to optimize the process before bonding the substrates 10 and 20. For example, when plasma treatment, cleaning, or the like is performed to bring the insulating layer 13 into a state suitable for bonding, oxidation occurs on the surface of the metal electrode 12. The same applies to the substrate 20.
When no Mn layer is formed on the surfaces of the substrates 10 and 20, the substrates 10 and 20 are bonded to each other with the metal electrode portions on the surfaces of the substrates 10 and 20 having depressions, and heat treatment is performed, whereby the metal electrodes 12 and 22 are expanded to bond the metal electrode 12 of the substrate 10 and the metal electrode 22 of the substrate 20. In this case, a gap may be generated in the bonding misalignment portion, and it may be difficult to firmly bond the substrates 10 and 20 to each other.
In contrast, in the semiconductor device 1 of the present embodiment, after the Mn layers 30a and 30b are formed on the surfaces of the substrate 10 and the substrate 20, respectively, the substrates 10 and 20 are subjected to a bonding pretreatment (N)2Plasma treatment), bonding of the substrates 10 and 20 to each other, and post-bonding treatment (heat treatment), thereby forming the 2 nd interface layer 42 having insulation properties and having a property of suppressing diffusion of a metal element (copper (Cu)) on the interface between the substrate 10 and the substrate 20 as described above. Therefore, after the substrate 10 and the substrate 20 are bonded, the metal electrodes in the same substrate can be prevented from being interposedAnd (7) leakage current. Therefore, short-circuiting between metal electrodes in the same substrate and deterioration of TDDB between metal electrodes can be suppressed.
Further, since the 1 st interface layer 41 having conductivity is formed on the interface between the substrate 10 and the substrate 20, electrical conduction between the metal electrode 12 of the substrate 10 and the metal electrode 22 of the substrate 20 can be ensured.
Further, since the 3 rd interface layer 43 and the 4 th interface layer 44 are formed in the portion where the bonding misalignment between the substrate 10 and the substrate 20 occurs, the diffusion of the metal element (Cu) constituting the metal electrodes 12 and 22 into the insulating layer of the other substrate can be suppressed.
Further, since the entire bonding interface between the substrate 10 and the substrate 20 is composed of a layer containing manganese (Mn) as a main component, optimization of the pre-bonding treatment is facilitated. For example, N can be prevented2Oxidation of the metal electrode by plasma treatment or water washing treatment.
The 1 st to 4 th interface layers 41, 42, 43 and 44 have high adhesion, and can firmly bond the substrate 10 and the substrate 20.
Therefore, the problem of the occurrence of the bonding misalignment between the metal electrode 12 of the substrate 10 and the metal electrode 22 of the substrate 20 can be improved.
As the 1 st metal element included in the metal electrode 12, tungsten (W) may be used instead of copper (Cu). Tungsten (W) may be used instead of copper (Cu) for the metal element 2 included in the metal electrode 22.
In addition, although the case where the 3 rd metal element that is the main component of the 1 st to 4 th interface layers 41, 42, 43, and 44 is manganese (Mn) has been described, the 1 st to 4 th interface layers 41, 42, 43, and 44 may contain a metal element selected from the group consisting of Mn (manganese), aluminum (Al), vanadium (V), zinc (Zn), niobium (Nb), zirconium (Zr), chromium (Cr), yttrium (Y), technetium (Tc), and rhenium (Re) as the main component.
In the above description, although the Mn layers 30a and 30b are formed on the substrate 10 and the substrate 20, respectively, in the step of forming the Mn layer shown in fig. 3, the Mn layer may be formed on only one substrate and the substrate 10 and the substrate 20 may be bonded to each other.
The 1 st interface layer 41 may further contain oxygen (O). That is, manganese oxide (MnO) may be formed2) Instead of forming the Mn layer 30a and the Mn layer 30b on the substrate 10 and the substrate 20, respectively, as shown in fig. 3.
As described above, according to the present embodiment, a semiconductor device in which a plurality of substrates having excellent interface characteristics between the substrates are bonded to each other can be provided.
Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.
The above embodiments may be summarized as follows.
Technical solution 1
A semiconductor device is characterized by comprising:
a 1 st substrate including a 1 st metal layer containing a 1 st metal element and a 1 st insulating layer containing a 1 st element and oxygen (O);
a 2 nd substrate including a 2 nd metal layer containing a 2 nd metal element and a 2 nd insulating layer containing a 2 nd element and oxygen (O);
a 1 st interface layer provided at an interface between the 1 st metal layer and the 2 nd metal layer, containing a 3 rd metal element and at least one of the 1 st metal element and the 2 nd metal element, and having conductivity; and
and a 2 nd interface layer which is provided at an interface between the 1 st insulating layer and the 2 nd insulating layer, contains at least one of the 1 st element and the 2 nd element, the 3 rd metal element, and oxygen (O), and has an insulating property.
Technical solution 2
The semiconductor device according to claim 1, further comprising a 3 rd interface layer provided at an interface between the 1 st metal layer and the 2 nd insulating layer, the 3 rd interface layer including a 1 st portion containing the 1 st metal element and the 3 rd metal element and provided on the 1 st metal layer side, and a 2 nd portion containing the 2 nd element, the 3 rd metal element, and oxygen (O) and provided on the 2 nd insulating layer side.
Technical solution 3
The semiconductor device according to claim 1, further comprising a 4 th interface layer provided at an interface between the 2 nd metal layer and the 1 st insulating layer, the 4 th interface layer including a 1 st portion containing the 2 nd metal element and the 3 rd metal element and provided on the 2 nd metal layer side, and a 2 nd portion containing the 1 st element, the 3 rd metal element, and oxygen (O) and provided on the 1 st insulating layer side.
Technical solution 4
The semiconductor device according to claim 1, wherein the 1 st metal element is selected from the group consisting of copper (Cu) and tungsten (W),
the 2 nd metal element is selected from copper (Cu) and tungsten (W).
Technical solution 5
The semiconductor device according to claim 1, wherein the 1 st element and the 2 nd element are silicon (Si).
Technical scheme 6
The semiconductor device according to claim 1, wherein the 3 rd metal element is selected from manganese (Mn), aluminum (Al), vanadium (V), zinc (Zn), niobium (Nb), zirconium (Zr), chromium (Cr), yttrium (Y), technetium (Tc), and rhenium (Re).
Technical scheme 7
The semiconductor device according to claim 1, wherein the 1 st interface layer contains copper (Cu) and Mn (manganese).
Technical solution 8
The semiconductor device according to claim 7, wherein the 1 st interface layer further contains oxygen (O).
Technical solution 9
The semiconductor device according to claim 1, wherein the 2 nd interface layer contains silicon (Si), oxygen (O), and manganese (Mn).

Claims (9)

1. A semiconductor device is characterized by comprising:
a 1 st substrate including a 1 st metal layer containing a 1 st metal element, and a 1 st insulating layer containing a 1 st element and oxygen (O);
a 2 nd substrate including a 2 nd metal layer containing a 2 nd metal element, and a 2 nd insulating layer containing a 2 nd element and oxygen (O);
a 1 st interface layer provided at an interface between the 1 st metal layer and the 2 nd metal layer, containing a 3 rd metal element and at least one of the 1 st metal element and the 2 nd metal element, and having conductivity; and
and a 2 nd interface layer which is provided at an interface between the 1 st insulating layer and the 2 nd insulating layer, contains at least one of the 1 st element and the 2 nd element, the 3 rd metal element, and oxygen (O), and has an insulating property.
2. The semiconductor device according to claim 1, further comprising a 3 rd interface layer, wherein the 3 rd interface layer is provided at an interface between the 1 st metal layer and the 2 nd insulating layer, and includes a 1 st portion that contains the 1 st metal element and the 3 rd metal element and is provided on the 1 st metal layer side, and a 2 nd portion that contains the 2 nd element, the 3 rd metal element, and oxygen (O) and is provided on the 2 nd insulating layer side.
3. The semiconductor device according to claim 1, further comprising a 4 th interface layer provided at an interface between the 2 nd metal layer and the 1 st insulating layer, the 4 th interface layer including a 1 st portion containing the 2 nd metal element and the 3 rd metal element and provided on the 2 nd metal layer side, and a 2 nd portion containing the 1 st element, the 3 rd metal element, and oxygen (O) and provided on the 1 st insulating layer side.
4. The semiconductor device according to claim 1, wherein the 1 st metal element is selected from copper (Cu) and tungsten (W),
the 2 nd metal element is selected from copper (Cu) and tungsten (W).
5. The semiconductor device according to claim 1, wherein the 1 st element and the 2 nd element are silicon (Si).
6. The semiconductor device according to claim 1, wherein the 3 rd metal element is selected from manganese (Mn), aluminum (Al), vanadium (V), zinc (Zn), niobium (Nb), zirconium (Zr), chromium (Cr), yttrium (Y), technetium (Tc), and rhenium (Re).
7. The semiconductor device according to claim 1, wherein the 1 st interface layer contains copper (Cu) and manganese (Mn).
8. The semiconductor device according to claim 7, wherein oxygen (O) is further contained in the 1 st interface layer.
9. The semiconductor device according to claim 1, wherein the 2 nd interface layer contains silicon (Si), oxygen (O), and manganese (Mn).
CN201910137521.4A 2018-09-06 2019-02-25 Semiconductor device with a plurality of semiconductor chips Pending CN110880452A (en)

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