JP2015002219A - Deposition method on semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a deposition method on a semiconductor wafer which prevents peel-off of a SiOfilm and preserves an adhesion property, regardless of a film thickness of the SiOfilm when the SiOfilm is deposited on a low dielectric constant film on the semiconductor wafer, thereby improving the reliability.SOLUTION: According to a deposition method on a semiconductor wafer, an adhesion property to a low dielectric constant film in an interlayer insulating film 14 of a SiOfilm, can be secured regardless of a film thickness of the SiOfilm as far as a warpage amount of the SiOfilm is a certain value or less. In addition, the warpage amount of the interlayer insulating film 14 of the SiOfilm with any film thickness can be controlled by a film stress value. Further, the film stress value is determined by an output ratio of a high-frequency RF power (e.g., 13.56 MHz) and a low-frequency RF power (e.g., 400 KHz) used for the deposition by a parallel plate type plasma enhanced CVD. Thus, when the interlayer insulating film 14 of the SiOfilm is deposited by the parallel plate type plasma enhanced CVD by using TEOS, for example, the warpage amount of the interlayer insulating film 14 can be controlled to a certain value (e.g., 46 μm) or less by controlling the high-frequency RF power and the low-frequency RF power to proper values.

Description

  The present invention relates to a film forming method for a semiconductor wafer.

  A semiconductor wafer typically includes a semiconductor substrate, an element layer formed on the main surface of the semiconductor substrate, and a multilayer wiring layer stacked on the element layer. In the element layer, semiconductor elements such as element isolation structures, MOS transistors, and capacitors are formed. The multilayer wiring layer is a wiring of the semiconductor element included in the element layer.

  FIG. 4 is a diagram illustrating an example of a multilayer wiring layer. The multilayer wiring layer shown in FIG. 1 includes a plurality of interlayer insulating films 11, 12, 13, and 14, interlayer barrier films 21, 22, and 23 stacked therebetween, interlayer insulating films 11 to 14, and It comprises a plurality of metal wiring portions 31 that penetrate the interlayer barrier films 21 to 23 in the stacking direction.

  As shown in FIG. 4, the metal wiring portion 31 includes, for example, a first wiring portion 31 a embedded in the interlayer insulating films 11 and 12, and a second wiring portion 31 b and a third wiring portion embedded in the interlayer insulating film 13. 31c. Each of the first to third wiring portions 31 a to 31 c is composed of a wiring metal 311. The wiring metal 311 is preferably excellent in conductivity, for example, copper Cu. Further, a metal barrier film 32 is formed between the wiring metal 311 and the interlayer insulating films 11 to 13.

  A metal layer 41 is laminated in the element region of the uppermost interlayer insulating film 14 among the interlayer insulating films constituting the multilayer wiring layer. The metal layer 41 serves as both a bonding pad and an inspection terminal of the semiconductor chip, and is preferably made of a metal that is less susceptible to wet etching than the wiring portion 31. For example, aluminum (Al) having etching resistance to nitric acid. Is good. Further, the metal layer 41 is connected to a third wiring part 31 c constituting the wiring part 31 through a contact plug 42 provided in the interlayer insulating film 14. The contact plug 42 functions as a metal wiring part by being connected to the third wiring part 31c.

A passivation film 51 is stacked on the metal layer 41.
Here, conventionally, silicon oxide SiO ₂ and silicon nitride SiN have been used as materials for the interlayer insulating films 11 to 14 and the interlayer barrier films 21 to 23, respectively, but as the miniaturization progresses, the wiring interval becomes narrower. The parasitic capacitance that occurs there is no longer negligible.

  As means for solving this problem, recently, instead of these materials, SiOC and SiCN are employed to reduce the dielectric constant of these films.

However, for example, in the configuration shown in FIG. 4, the interlayer insulating film 14 as a cap film is an SiO ₂ film as it is. In such a case, there is a problem in that the adhesion between the SiO ₂ film and the underlying SiOC film (a SiCN film when there is a SiCN film) is insufficient. As a result, there is a problem that the SiO ₂ film is peeled off and becomes a defect, or a problem occurs that peeling occurs due to the force applied by the bonding during bonding, which hinders assembly.

As shown in FIG. 5, the problem of peeling off of the upper SiO ₂ film generally appears more prominently as the film thickness increases if the film quality is the same. That is, in this figure, only the thickness of 400 nm → 800 nm of the upper SiO ₂ film at the end portion of the wafer as an exception, the number of peeled squares of 100 in the mass in each region, 180 nm → 400 nm → 800 nm and an upper SiO ₂ film The film thickness increases as the film thickness increases.

In order to solve the above-described problems, there is a technique in which a special layer is provided between the SiOC film and the upper SiO ₂ film to improve the adhesion thereof (see, for example, Patent Document 1). That is, Patent Document 1 aims at improving the adhesion between the SiOC film (low-k film) and the SiO ₂ film (cap film), and the relationship between the SiOC film (reference numeral 2) and the SiO ₂ film (4). It discloses disposing a modified layer (3) in between.

JP 2004-207604 A

  However, as in Patent Document 1, providing a special layer such as a modified layer has a problem of increasing the number of processes.

A film forming method for a semiconductor wafer according to the present invention is a film forming method for forming a SiO ₂ film on a low dielectric constant film in a multilayer wiring layer of a semiconductor wafer, and the amount of warpage of the SiO ₂ film is set to a predetermined value. The gist is to keep it below.

According to the film forming method for a semiconductor wafer of the present invention, when a SiO ₂ film is formed on a low dielectric constant film, the adhesion can be maintained without causing the peeling regardless of the thickness of the SiO ₂ film. . As a result, it is possible to improve general troubles caused by peeling. In particular, since peeling during bonding can be prevented, reliability is improved.

It is a figure for demonstrating one Embodiment of the film-forming method in the semiconductor wafer of this invention. Upper SiO ₂ film thickness, film stress values, and is a diagram showing results of an experiment examining the presence or absence of peeling in each condition of the warp amount. It is a figure which shows the relationship between high frequency RF power and low frequency RF power, and a film | membrane stress value. It is sectional drawing which shows the structure of the multilayer wiring layer in a semiconductor wafer. Is a diagram showing the relationship between the thickness of the upper SiO ₂ film formed with its peeling.

Hereinafter, an example of a film forming method on a semiconductor wafer to which the present invention is applied will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .

FIG. 1 is a diagram for explaining an embodiment of a film forming method on a semiconductor wafer of the present invention. The manufacturing process up to the state shown in FIG. 1 (a) is as follows.
That is, the interlayer insulating film 11, the interlayer barrier film 21, and the interlayer insulating film 12 are sequentially stacked, a concave portion penetrating them is provided, the metal barrier film 32 is stacked, and the wiring metal 311 is formed thereon by plating. Thus, the first wiring part 31a is formed.

  Next, an interlayer barrier film 22 and an interlayer insulating film 13 are sequentially stacked on the interlayer insulating film 12, a recess is formed through them, and a metal barrier film 32 is stacked. By forming 311, the second wiring portion 31 b and the third wiring portion 31 c are formed.

  Here, the interlayer insulating films 11 to 13 are preferably SiOC, and the interlayer barrier films 21 and 22 are preferably SiCN.

  Next, referring to FIG. 1B, next, an interlayer barrier film 23 which is a SiCN film is laminated on the interlayer insulating film 13.

Then, although to laminate the SiO ₂ film serving as the interlayer insulating film 14, the present inventors have adhesion to the low dielectric constant film of the SiO ₂ film may be any warpage of the SiO ₂ film is constant less, the It was found that it can be secured regardless of the film thickness. Further, it has been found that the warpage amount of the interlayer insulating film 14 which is a SiO ₂ film can be controlled by the film stress value. Further, it is understood that the film stress value is determined by the output ratio related to the high frequency RF power (for example, 13.56 MHz) and the low frequency RF power (for example, 400 KHz) used for film formation by parallel plate type plasma CVD (Chemical Vapor Deposition). ing. Specifically, the film stress value is proportional to low frequency RF power / (high frequency RF power + low frequency RF power).

Therefore, when the interlayer insulating film 14 as a SiO ₂ film is formed by parallel plate plasma CVD using, for example, TEOS (Tetraethyl orthosilicate), high frequency RF power (for example, 13.56 MHz) and low frequency RF power (for example, 400 KHz). ) To an appropriate value, the warpage amount of the interlayer insulating film 14 is made constant (for example, 46 μm) or less. As a result, the interlayer insulating film 14 is ensured in adhesion without being peeled regardless of its thickness.

Here, the interlayer barrier film 23 which is a SiCN film is provided, and the interlayer insulating film 14 which is a SiO ₂ film is laminated thereon. However, the interlayer barrier film 23 is not provided, and the interlayer insulating film 13 which is a SiOC film is provided on the interlayer insulating film 13. The interlayer insulating film 14 may be directly laminated.

Example 1
The present inventor has found that the adhesion of the upper SiO ₂ film to the lower SiOC film can be ensured regardless of the thickness of the upper SiO ₂ film as long as the warpage (Bow) of the upper SiO ₂ film is not more than a certain value.

  FIG. 2 is a diagram showing an experimental result indicating the grounds. That is, in FIG. 2, the upper, middle, and lower stages are the experimental results with different conditions. The thickness of the lower SiOC film is common (1100 nm) in each stage. Each column shows the experimental results at the center (Center), middle (Middle), and end (Edge) of the wafer.

Therefore, the upper stage is a case where the upper SiO ₂ film has a thickness of 180 nm and a stress of 150 MPa is applied to cause a warpage amount of 46 μm, and the upper stage is an upper SiO ₂ film having a thickness of 400 nm and 150 MPa. The lower stage is a case where the thickness of the upper SiO ₂ film is 400 nm and a stress of 60 MPa is applied to cause a warp quantity of 46 μm. .

Therefore, the relationship between the upper stage and the middle stage is the same as that shown in FIG. 5, and the amount of warpage increases as the film thickness of the upper SiO ₂ film increases even under the same stress. In other words, peeling occurred in the middle stage.

Further, the relationship between the middle stage and the lower stage shows that even if the film thickness of the upper SiO ₂ film is the same, if the stress is reduced and, for example, the same warp amount of 46 μm as the upper stage is suppressed, peeling does not occur. ing.

Therefore, the adhesion of the upper SiO ₂ film to the lower SiOC film does not depend on the film thickness of the upper SiO ₂ film, but depends on the warpage amount. It can be concluded that no peeling occurs regardless of the thickness. Specifically, if the amount of warpage is suppressed to about 46 μm or less, peeling does not occur.

The reason why the adhesion of the upper SiO ₂ film does not depend on the film thickness and depends on the warpage amount is that the stress applied to the interface between the lower dielectric constant film and the upper SiO ₂ film when the warpage amount exceeds a certain value. This is considered to be because peeling occurs at the interface between the lower low dielectric constant film and the upper SiO ₂ film, which originally exceeded the limit and has poor adhesion.

Therefore, the following three relationships are considered.
(1) regardless of the thickness of the upper SiO ₂ film, if Osaere warpage amount constant less, there is no peeling of the upper SiO ₂ film.
(2) The amount of warpage of the upper SiO ₂ film at an arbitrary film thickness can be controlled by the film stress value.
(3) The film stress value is determined by the output ratio of the high frequency RF power (13.56 MHz) and the low frequency RF power (400 KHz) used for film formation by parallel plate type plasma CVD. Specifically, as shown in FIG. 3, the film stress value is proportional to low frequency RF power / (high frequency RF power + low frequency RF power).

  Here, the relationship (1) is the relationship derived so far. The relations (2) and (3) are known facts.

From these three relations, by controlling the high frequency RF power (13.56 MHz) and the low frequency RF power (400 KHz), the warpage amount at an arbitrary thickness of the upper SiO ₂ film can be controlled. By controlling, peeling of the upper SiO ₂ film does not occur, and the adhesion can be ensured.

An example of conditions for forming the upper SiO ₂ film by parallel plate type plasma CVD is shown in Table 1.

According to the embodiment described above, when the upper SiO ₂ film is formed on the lower SiOC film, the adhesion can be maintained without causing the peeling regardless of the thickness of the upper SiO ₂ film. As a result, it is possible to improve general troubles caused by peeling. In particular, since peeling during bonding can be prevented, reliability is improved.

The present invention can be employed when a semiconductor wafer manufacturing process includes a step of forming a SiO ₂ film on a low dielectric constant film.

11-14 ... Interlayer insulating films 21-23 ... Interlayer barrier films 31a-31c ... 1st-3rd wiring part 311 ... Wiring metal 32 ... Metal barrier film 41 ... Metal layer 42 ... Contact plug 51 ... Passivation film

Claims (5)

A film forming method for forming a SiO ₂ film on a low dielectric constant film in a multilayer wiring layer of a semiconductor wafer,
A film forming method characterized in that the amount of warping of the SiO ₂ film is suppressed to a predetermined value or less.   The film forming method according to claim 1, wherein the predetermined value is 46 μm.   The film formation method according to claim 1, wherein the warpage amount is controlled by a film stress value at the time of film formation.   4. The film forming method according to claim 3, wherein the film stress value is controlled by a high frequency RF power and a low frequency RF power used for film formation by parallel plate type plasma CVD.   The film formation method according to claim 1, wherein the low dielectric constant film is a SiOC film.