JP2006165054A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2006165054A
JP2006165054A JP2004350157A JP2004350157A JP2006165054A JP 2006165054 A JP2006165054 A JP 2006165054A JP 2004350157 A JP2004350157 A JP 2004350157A JP 2004350157 A JP2004350157 A JP 2004350157A JP 2006165054 A JP2006165054 A JP 2006165054A
Authority
JP
Japan
Prior art keywords
conductive pad
pad
conductive
insulating layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004350157A
Other languages
Japanese (ja)
Other versions
JP4422004B2 (en
Inventor
Takao Nishimura
隆雄 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2004350157A priority Critical patent/JP4422004B2/en
Publication of JP2006165054A publication Critical patent/JP2006165054A/en
Application granted granted Critical
Publication of JP4422004B2 publication Critical patent/JP4422004B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a crack from being generated on a multilayered wiring layer formed on a lower layer by permitting external stress applied to an electrode pad to be directly propagated to a further lower layer of the electrode pad, in a semiconductor device having a multilayered structure electrode pad. <P>SOLUTION: In the semiconductor device where the upper layer conductive pad of the electrode pad of the multilayered structure and a lower layer conductive pad are stacked via an interlayer insulating layer, and the upper layer conductive pad and the lower layer conductive pad are electrically connected by a plurality of conductive plugs penetrating the interlayer insulating layer. A conductive plug is slantingly formed with respect to the perpendicular direction of the upper layer conductive pad or the lower layer conductive pad. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置に関し、特に、層間絶縁層を介して導電性パッドが積層した電極パッドを有する半導体装置に係わる。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an electrode pad in which conductive pads are stacked via an interlayer insulating layer.

近年、ＩＣデバイスの高速化要求に伴い、高速動作時の配線遅延を回避するために、配線材料として銅を用いて低抵抗化し、層間絶縁層として低誘電率材（Ｌｏｗ−ｋ材）を用いて低配線容量化したＩＣデバイスの実用化が進められている。Ｌｏｗ−ｋ材の例としては、ＳｉＯ２をベースとしてフッ素をドープしたものや、ＳｉＯ２をベースに骨格の末端をＨやＣＨ３で終端した無機系材料や有機系材料を用いたもの、多孔質（ポーラス）構造のもの等がある。しかし、これらの絶縁層は、Ｔｅｔｒａ−Ｅｔｈｏｘｙｓｉｌａｎｅ（ＴＥＯＳ）−ＣＶＤ層や、Ｓｐｉｎ−ｏｎ Ｄｉｅｌｅｃｔｒｉｃｓ（ＳＯＤ）層といった従来のＳｉＯ２系の層間絶縁層に比べて機械的強度が低いことが課題となっており、とりわけ、多孔質構造のＬｏｗ−ｋ材を用いた層間絶縁層では顕著である。 In recent years, with the demand for higher speed IC devices, in order to avoid wiring delay during high-speed operation, resistance is reduced using copper as a wiring material, and a low dielectric constant material (Low-k material) is used as an interlayer insulating layer. IC devices with reduced wiring capacity are being put to practical use. Examples of the Low-k material, those used doped with fluorine of SiO 2 as a base and the inorganic material or organic material which the ends of the skeleton of SiO 2 based terminated with H or CH 3, porous There is a quality (porous) structure. However, it is a problem that these insulating layers have lower mechanical strength than conventional SiO 2 -based interlayer insulating layers such as Tetra-Ethoxysilane (TEOS) -CVD layer and Spin-on Dielectrics (SOD) layer. This is particularly noticeable in an interlayer insulating layer using a low-k material having a porous structure.

一方、従来、電極パッド部での局所的衝撃・応力によって、下部の層間絶縁層に剥れやクラック等の損傷が発生するので、それを軽減するために、導電性プラグを有する積層した電極パッド構造が用いられている。   On the other hand, conventionally, a layered electrode pad having a conductive plug has been used to reduce damages such as peeling and cracks caused by local impact / stress in the electrode pad portion. Structure is used.

図５及び図６は、従来の積層電極パッドの要部断面構造と付加される外部応力の例を示す。多層配線層４、中間絶縁層５、層間絶縁層６が交互に積層され、最上層絶縁層７の窓領域に上層導電性パッド８と下層導電性パッド９が上下に対向して配置され、間にある層間絶縁層６を貫通する複数のタングステン（Ｗ）プラグ２０１又は２０２によって、上層導電性パッド８と下層導電性パッド９が接続され、更に、図示されてないが、下層導電性パッド９は多層配線層４に電気的に接続されている。これらのＷプラグを用いた電極パッド構造においても、図５に示すように、金製のボンディングワイヤ２０をボンディングキャピラリ４０を介して、上層導電性パッド８の表面に、加熱と超音波振動とによって圧着するか、或いは、図６に示すように、各種電気的試験用にＷ製プローブ３０を上層導電性パッド８の表面に、圧接摺動する際には、その局所的衝撃・応力によって、下部の層間絶縁層、配線や回路素子等に剥れやクラック等の損傷が発生することがある。これら損傷の発生を低減する方法も提案されている（例えば、特許文献１）が、下層部の層間絶縁層として機械的強度が低いＬｏｗ−ｋ材を用いた場合には、下層部の層間絶縁層、配線や回路素子等の剥れやクラック等の損傷の発生を十分抑制することは困難である。
特開２００１−３５８１６９号公報（第４頁、第１図) 5 and 6 show an example of a cross-sectional structure of a main part of a conventional laminated electrode pad and external stress applied. The multilayer wiring layer 4, the intermediate insulating layer 5, and the interlayer insulating layer 6 are alternately stacked, and the upper conductive pad 8 and the lower conductive pad 9 are disposed in the window region of the uppermost insulating layer 7 so as to face each other vertically. The upper conductive pad 8 and the lower conductive pad 9 are connected by a plurality of tungsten (W) plugs 201 or 202 penetrating the interlayer insulating layer 6, and further, although not shown, the lower conductive pad 9 It is electrically connected to the multilayer wiring layer 4. Also in the electrode pad structure using these W plugs, as shown in FIG. 5, the gold bonding wire 20 is applied to the surface of the upper conductive pad 8 through the bonding capillary 40 by heating and ultrasonic vibration. As shown in FIG. 6, when the W probe 30 is slid on the surface of the upper conductive pad 8 for various electrical tests, the lower impact is caused by the local impact and stress. In some cases, the interlayer insulating layer, the wiring, the circuit element, etc. may be damaged such as peeling or cracking. A method for reducing the occurrence of these damages has also been proposed (for example, Patent Document 1). However, when a low-k material having low mechanical strength is used as an interlayer insulating layer in the lower layer, the interlayer insulation in the lower layer is used. It is difficult to sufficiently suppress the occurrence of damage such as peeling and cracking of layers, wirings, circuit elements, and the like.
JP 2001-358169 A (page 4, FIG. 1)

本発明の目的は、半導体装置の製造工程における、プロービング、ワイヤボンディング、スタッドバンプボンディング、フリップチップボンディングの場合等に電極パッドに付与されるストレスによって、下層の層間絶縁層、配線や回路素子等に剥れやクラック等の損傷が発生することを防止する電極構造を提供することにある。   An object of the present invention is to apply a stress to an electrode pad in the case of probing, wire bonding, stud bump bonding, flip chip bonding, etc. in a manufacturing process of a semiconductor device, to a lower interlayer insulating layer, wiring, circuit element, etc. An object of the present invention is to provide an electrode structure that prevents the occurrence of damage such as peeling or cracking.

上記の目的を達成するために、上層導電性パッドと下層導電性パッドとが、層間絶縁層を介して積層され、該上層導電性パッドと該下層導電性パッドとは、該層間絶縁層を貫通する複数の導電性プラグによって電気的に接続されている半導体装置において、該導電性プラグは、該上層導電性パッドと該下層導電性パッド間において、傾斜して形成されていることを特徴とする半導体装置。   In order to achieve the above object, an upper conductive pad and a lower conductive pad are laminated via an interlayer insulating layer, and the upper conductive pad and the lower conductive pad penetrate through the interlayer insulating layer. In the semiconductor device electrically connected by the plurality of conductive plugs, the conductive plug is formed to be inclined between the upper conductive pad and the lower conductive pad. Semiconductor device.

本発明の効果として、複数の導電性プラグにより上下パッドを接続する構造のため、引張応力に対して耐性が向上し、層間絶縁層部での剥離やクラックの発生が抑制されることに加えて、導電体が垂直でなく、斜めに形成されているので、垂直方向に印加される圧縮応力が層間絶縁層中に分散され、下層パッド及びその下層に伝播する荷重が軽減され、下層の層間絶縁層及びその下層の層間絶縁層部でのクラック発生が抑制される。   As an effect of the present invention, the structure in which the upper and lower pads are connected by a plurality of conductive plugs improves resistance to tensile stress and suppresses the occurrence of peeling and cracks in the interlayer insulating layer. Since the conductor is not vertical but formed obliquely, the compressive stress applied in the vertical direction is dispersed in the interlayer insulating layer, the load propagated to the lower layer pad and its lower layer is reduced, and the lower layer interlayer insulation The generation of cracks in the layer and the underlying interlayer insulating layer is suppressed.

図１は、本発明による実施例１の電極パッド構造を有する半導体装置要部の断面図である。 半導体基板１の表面部のフィールド酸化層３の窓領域に拡散層２とゲート電極を含む素子領域が形成され、その上に、多層配線層４、中間絶縁層５、層間絶縁層６が交互に積層され、最上層絶縁層７の窓領域に上層導電性パッド８と下層導電性パッド９とが上下に対向して配置されている。また、図示されてないが、上層導電性パッド８と下層導電性パッド９の少なくとも一方は多層配線層４に電気的に接続されている。従来の積層電極パッドと異なり、上層導電性パッド８と下層導電性パッド９との間にある層間絶縁層６を貫通する複数本の円柱又は角柱の導電性プラグ１０が、上層導電性パッド８或いは下層導電性パッド９の垂直方向に対して、傾斜して形成されている。図１の実施例では、個々の導電性プラグ１０が、上下導電性パッドの平面に垂直な方向に対して一定角度をなし伸延しているので、上層導電性パッド８と接続する部位と下層導電性パッド９に接続する部位とが、平面的に見てずれた位置に配置されている。   FIG. 1 is a cross-sectional view of a main part of a semiconductor device having an electrode pad structure of Example 1 according to the present invention. An element region including the diffusion layer 2 and the gate electrode is formed in the window region of the field oxide layer 3 on the surface portion of the semiconductor substrate 1, and the multilayer wiring layer 4, the intermediate insulating layer 5, and the interlayer insulating layer 6 are alternately formed thereon. The upper conductive pad 8 and the lower conductive pad 9 are disposed in the window region of the uppermost insulating layer 7 so as to face each other in the vertical direction. Although not shown, at least one of the upper conductive pad 8 and the lower conductive pad 9 is electrically connected to the multilayer wiring layer 4. Unlike the conventional laminated electrode pad, a plurality of cylindrical or prismatic conductive plugs 10 penetrating the interlayer insulating layer 6 between the upper conductive pad 8 and the lower conductive pad 9 are connected to the upper conductive pad 8 or The lower conductive pad 9 is formed to be inclined with respect to the vertical direction. In the embodiment of FIG. 1, the individual conductive plugs 10 extend at a certain angle with respect to the direction perpendicular to the plane of the upper and lower conductive pads, so that the portion connected to the upper conductive pad 8 and the lower conductive layer are connected. The portion connected to the conductive pad 9 is disposed at a position shifted from the plan view.

図２（ａ）は、傾斜を有する導電性プラグの形成方法を示すための電極パッド要部断面図である。図示省略された半導体基板上にシリコン酸化層等の層間絶縁層６０を形成した後、スパッタリング法等により下層導電性パッド９となる金属層（アルミニウム合金または銅合金等）を形成し、その後フォトリソグラフィ及びエッチングにより加工して導電性パッド９を形成する。その後プラズマＣＶＤ法等により層間絶縁層６３を堆積し、ＣＭＰ法等により表面を平坦化し、その後フォトリソグラフィおよびエッチングにより導電性プラグを形成のためのビアホールを形成する。このビアホール内に、ＣＶＤ法等によってタングステン（Ｗ）や銅等の高融点金属を埋め込み、導電性プラグ１０１を形成する。このプラグ形成を、少しずつ位置をずらし、下段プラグと一部が重なるようにして、繰り返し行うことで、徐々に位置がずれた導電性プラグ１０２を有する層間絶縁層６２、更に、導電性プラグ１０１を有する層間絶縁層６１を順次形成する。その後、スパッタリング法等により、上層パッド層となる金属層（アルミニウム合金または銅合金等）を形成し、フォトリソグラフィ及びエッチングにより加工して、上層導電性パッド８を形成する。その後、ＣＶＤ法等により、シリコン酸化層、シリコン窒化層やポリイミド等からなるパッシベーション層である最上層絶縁層７を形成し、フォトリソグラフィ及びエッチングにより上層導電性パッドの開口部を形成する。   FIG. 2A is a sectional view of the main part of the electrode pad for illustrating a method of forming a conductive plug having an inclination. After an interlayer insulating layer 60 such as a silicon oxide layer is formed on a semiconductor substrate (not shown), a metal layer (such as an aluminum alloy or a copper alloy) to be the lower conductive pad 9 is formed by sputtering or the like, and then photolithography is performed. Then, the conductive pad 9 is formed by processing by etching. Thereafter, an interlayer insulating layer 63 is deposited by plasma CVD or the like, the surface is planarized by CMP or the like, and then a via hole for forming a conductive plug is formed by photolithography and etching. A refractory metal such as tungsten (W) or copper is buried in the via hole by a CVD method or the like to form a conductive plug 101. This plug formation is repeated little by little so that it partially overlaps the lower plug, whereby the interlayer insulating layer 62 having the conductive plug 102 gradually shifted in position, and further the conductive plug 101 Are sequentially formed. Thereafter, a metal layer (such as an aluminum alloy or a copper alloy) serving as an upper pad layer is formed by sputtering or the like, and processed by photolithography and etching to form the upper conductive pad 8. Thereafter, the uppermost insulating layer 7 which is a passivation layer made of a silicon oxide layer, a silicon nitride layer, polyimide, or the like is formed by a CVD method or the like, and an opening of the upper conductive pad is formed by photolithography and etching.

図２（ａ）に示した例では導電性プラグは３段で形成したが、層間絶縁層の層の厚みを薄くして、このプラグ形成の段数を増やすことで、図１のように、擬似的に連続的な傾斜を有する導電性プラグを形成することもできる。尚、図２（ａ）においては省略したが、図１に示したシリコン酸化層等の層間絶縁層６を積層する際に、中間絶縁層５を介在させているが、これらは層間絶縁層６のエッチングの際のストッパー膜の働きをし、シリコン酸化層のエッチングガスに対してエッチング速度の遅いシリコン窒化層等が用いられる。   In the example shown in FIG. 2A, the conductive plug is formed in three stages. However, by reducing the thickness of the interlayer insulating layer and increasing the number of stages of plug formation, as shown in FIG. It is also possible to form a conductive plug having a continuous slope. Although omitted in FIG. 2A, the intermediate insulating layer 5 is interposed when the interlayer insulating layer 6 such as the silicon oxide layer shown in FIG. A silicon nitride layer or the like that functions as a stopper film during the etching and has a slow etching rate relative to the etching gas of the silicon oxide layer is used.

このような電極構造において、上層導電性パッド８に引張り又は圧縮応力が印加された場合、従来の構造では、全応力が垂直方向のみに直接伝達されるのに対して、導電性プラグ１０が傾斜しているので、図２（ｂ）に示すように、引張り又は圧縮応力Ｔは、上層導電性パッド８との界面で、導電性プラグ１０の中心軸１１に平行な応力成分Ｔ１とそれに垂直な応力成分Ｔ２とに分解され、更に、中心軸に平行な応力成分Ｔ１は、下層導電性パッド９との界面で、界面に垂直な応力成分Ｔ３と界面に平行な応力成分Ｔ４とに分解されるので、応力が途中で層間絶縁層中に分散され、下層パッド及びその下層に伝播する垂直荷重応力が軽減され、下層の層間絶縁層、更にその下層の層間絶縁層でのクラック発生が抑制される効果が生じる。 In such an electrode structure, when a tensile or compressive stress is applied to the upper conductive pad 8, in the conventional structure, the total stress is directly transmitted only in the vertical direction, whereas the conductive plug 10 is inclined. Therefore, as shown in FIG. 2B, the tensile or compressive stress T is a stress component T 1 parallel to the central axis 11 of the conductive plug 10 at the interface with the upper conductive pad 8 and perpendicular thereto. are decomposed into a stress component T 2, further stress components T 1 parallel to the central axis, at the interface between the lower conductive pad 9, the vertical stress component at the interface T 3 and stress parallel to the interface component T 4 Therefore, the stress is dispersed in the interlayer insulating layer in the middle, the vertical load stress propagated to the lower layer pad and the lower layer is reduced, and the crack in the lower interlayer insulating layer and further the lower interlayer insulating layer is reduced. The effect that generation | occurrence | production is suppressed arises.

図３は、屈曲した導電性プラグを有する積層電極パッド要部断面図である。
図２（ａ）で述べた製造方法により、Ｗプラグを少しずつずらす方向を中間で１８０度変換させれば、“く”の字状の導電性プラグが形成できる。この場合は、実施例１と異なり、個々の導電性プラグ１０が、上層導電性パッド８と接続する部位と下層導電性パッド９に接続する部位とが、平面的に見て一致した位置に配置することが可能である。更に、導電性プラグを少しずつずらす方向を、上層導電性パッド８と接続する部位の中心を通り、パッド平面に垂直な軸の周りに、少しずつ回転させると、この垂直軸に沿ったコイル状の導電性プラグが形成できる。この場合、導電性プラグの中心線は、螺旋を描き、中心線の接線方向は場所により変化し、先のパッド平面に垂直な垂直軸に対し、常にある角度を持つ。応力に対しては、実施例１と同様な効果が期待できる。 FIG. 3 is a cross-sectional view of an essential part of a laminated electrode pad having a bent conductive plug.
If the direction in which the W plug is gradually shifted is changed by 180 degrees in the middle by the manufacturing method described with reference to FIG. 2A, a "<"-shaped conductive plug can be formed. In this case, unlike the first embodiment, each conductive plug 10 is disposed at a position where a portion connected to the upper conductive pad 8 and a portion connected to the lower conductive pad 9 coincide in plan view. Is possible. Further, when the direction in which the conductive plug is gradually shifted passes through the center of the portion connected to the upper conductive pad 8 and is rotated little by little around an axis perpendicular to the pad plane, a coil shape along the vertical axis is formed. The conductive plug can be formed. In this case, the center line of the conductive plug draws a spiral, and the tangential direction of the center line changes depending on the location, and always has an angle with respect to the vertical axis perpendicular to the previous pad plane. The effect similar to Example 1 can be expected with respect to the stress.

図４は、本発明による実施例３の半導体装置要部の断面図である。実施例１と異なる点は、下層導電性パッドは、多層配線層４が兼ねており、それが、分割されていることである。表現を変えれば、分割された下層導電性パッドが、多層配線層に電気的に接続されていると見ることもできる。ところで、多層配線層に電気的に接続されるのは、下層導電性パッドに限らず、下層導電性パッドであってもよい。更なる特徴としては、本発明では、応力は上層の層間絶縁層中に分散され、下層の層間絶縁層中への伝達は軽減されるので、下層の層間絶縁層には、電気的特性の優れた例えば多孔質（ポーラス）構造等を有するような各種低誘電率（Ｌｏｗ−ｋ）材からなる層間絶縁層６６を用いて低配線容量化することが可能になることである。また、更に、導電性パッド直下に相当する部位に多層配線層４及び入出力回路素子３０１が配置されている。これにより、半導体装置の高密度化が可能になる。   FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. The difference from the first embodiment is that the lower conductive pad is also used as the multilayer wiring layer 4 and is divided. In other words, it can be seen that the divided lower conductive pads are electrically connected to the multilayer wiring layer. By the way, what is electrically connected to the multilayer wiring layer is not limited to the lower conductive pad but may be a lower conductive pad. As a further feature, in the present invention, stress is dispersed in the upper interlayer insulating layer and transmission to the lower interlayer insulating layer is reduced, so that the lower interlayer insulating layer has excellent electrical characteristics. For example, it is possible to reduce the wiring capacitance by using the interlayer insulating layer 66 made of various low dielectric constant (Low-k) materials having a porous structure. Furthermore, the multilayer wiring layer 4 and the input / output circuit element 301 are disposed in a portion corresponding to the portion immediately below the conductive pad. Thereby, the density of the semiconductor device can be increased.

上記の例では、導電性パッドは２層構成としたが、３層以上で構成し、それぞれの導電性パッド間を斜めの導電性プラグで接続した構成としてもよい。この場合はパッドの下層の層間絶縁層に対してより緩衝効果が高まることは言うまでもない。
（付記１）上層導電性パッドと下層導電性パッドとが、層間絶縁層を介して積層され、該上層導電性パッドと該下層導電性パッドとは、該層間絶縁層を貫通する複数の導電性プラグによって電気的に接続されている半導体装置において、該導電性プラグは、該上層導電性パッドと該下層導電性パッド間において、傾斜して形成されていることを特徴とする半導体装置。
（付記２）前記導電性プラグの傾斜方向が変化していることを特徴とする付記１記載の半導体装置。
（付記３）前記層間絶縁層は、複数の絶縁層の積層からなり、前記導電性プラグは各々の該絶縁層に位置をずらして形成された貫通口に充填された導電物を積層したものからなることを特徴とする付記１記載の半導体装置。
（付記４）前記下層導電性パッドのさらに下層に、前記上層導電性パッドと該下層導電性パッド間の層間絶縁層よりも、低誘電率の絶縁層が形成されていることを特徴とする付記１記載の半導体装置。
（付記５）前記上層導電性パッド又は前記下層導電性パッドの少なくとも一方は、複数の分割領域を有し、該分割領域の各々に前記導電性プラグが形成されていることを特徴とする付記１記載の半導体装置。
（付記６）前記導電性プラグが少なくとも一つの折れ曲がり領域を有することを特徴とする付記１記載の半導体装置。
（付記７）前記導電性プラグがコイルスプリング状の領域を有することを特徴とする付記１記載の半導体装置。
（付記８）前記上層導電性パッド又は前記下層導電性パッドの少なくとも一方は、下層の多層配線層と電気的に接続されていることを特徴とする付記１記載の半導体装置。
（付記９）前記上層導電性パッドの一つに対応する前記下層導電性パッドが複数に分割されていることを特徴とする付記５記載の半導体装置。
（付記１０）前記低誘電率の絶縁層は、フッ素含有シリコンオキサイド又は多孔質材であることを特徴とする付記４記載の半導体装置。
（付記１１）前記下層導電性パッドの下層であって、直下に相当する部位に入出力回路素子が形成されていることを特徴とする付記１記載の半導体装置。 In the above example, the conductive pad has a two-layer structure. However, the conductive pad may be formed of three or more layers, and each conductive pad may be connected by an oblique conductive plug. In this case, it goes without saying that the buffering effect is further enhanced with respect to the interlayer insulating layer below the pad.
(Appendix 1) An upper conductive pad and a lower conductive pad are stacked via an interlayer insulating layer, and the upper conductive pad and the lower conductive pad are a plurality of conductive layers that penetrate the interlayer insulating layer. In the semiconductor device electrically connected by a plug, the conductive plug is formed to be inclined between the upper conductive pad and the lower conductive pad.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein an inclination direction of the conductive plug is changed.
(Additional remark 3) The said interlayer insulation layer consists of lamination | stacking of several insulation layers, and the said electroconductive plug is what laminated | stacked the electrically conductive substance with which the through-hole formed in the position which shifted each said insulation layer was laminated | stacked. The semiconductor device as set forth in appendix 1, wherein:
(Additional remark 4) The insulating layer of low dielectric constant is formed in the lower layer of the said lower conductive pad further than the interlayer insulating layer between the said upper conductive pad and this lower conductive pad 1. The semiconductor device according to 1.
(Appendix 5) At least one of the upper conductive pad or the lower conductive pad has a plurality of divided regions, and the conductive plug is formed in each of the divided regions. The semiconductor device described.
(Supplementary note 6) The semiconductor device according to supplementary note 1, wherein the conductive plug has at least one bent region.
(Supplementary note 7) The semiconductor device according to supplementary note 1, wherein the conductive plug has a coil spring-like region.
(Supplementary note 8) The semiconductor device according to supplementary note 1, wherein at least one of the upper conductive pad and the lower conductive pad is electrically connected to a lower multilayer wiring layer.
(Supplementary note 9) The semiconductor device according to supplementary note 5, wherein the lower conductive pad corresponding to one of the upper conductive pads is divided into a plurality of parts.
(Supplementary note 10) The semiconductor device according to supplementary note 4, wherein the low dielectric constant insulating layer is fluorine-containing silicon oxide or a porous material.
(Supplementary note 11) The semiconductor device according to supplementary note 1, wherein an input / output circuit element is formed in a lower layer of the lower conductive pad and corresponding to a portion immediately below.

実施例１の積層電極パッド構造を有する半導体装置要部の断面図Sectional drawing of the principal part of the semiconductor device which has the laminated electrode pad structure of Example 1. （ａ）実施例１の傾斜した導電性プラグの形成方法を説明するための積層電極パッド要部断面図、（ｂ）実施例１の傾斜した導電性プラグに印加された応力の伝播を説明するための積層電極パッド要部断面図(A) Cross-sectional view of the main part of the laminated electrode pad for explaining the method of forming the inclined conductive plug of Example 1, (b) Propagation of stress applied to the inclined conductive plug of Example 1 is explained. Cross-sectional view of main parts of laminated electrode pad for 実施例２の屈曲した導電性プラグを有する積層電極パッド要部断面図Cross-sectional view of the main part of the laminated electrode pad having the bent conductive plug of Example 2 実施例３の半導体装置要部の断面図Sectional drawing of the principal part of the semiconductor device of Example 3. ワイヤボンディング時の従来の導電性プラグを有する積層電極パッド部要部断面図Cross-sectional view of the main part of a laminated electrode pad having a conventional conductive plug at the time of wire bonding 試験プロービング時の従来の導電性プラグを有する積層電極パッド部要部断面図Cross-sectional view of the main part of a laminated electrode pad having a conventional conductive plug during test probing

符号の説明Explanation of symbols

１ 半導体基板
２ 拡散層
３ フィールド酸化層
４ 多層配線層
５ 中間絶縁層
６、６０ 層間絶縁層
７ 最上層絶縁層
８ 上層導電性パッド
９ 下層導電性パッド
１０ 導電性プラグ
１１ 導電性プラグの中心線の接線
２０ ボンディングワイヤ
３０ プローブ
４０ ボンディングキャピラリ
６１ 導電性プラグ１０１を有する層間絶縁層
６２ 導電性プラグ１０２を有する層間絶縁層
６３ 導電性プラグ１０３を有する層間絶縁層
６６ Ｌｏｗ−ｋ材からなる層間絶縁層
１０１、１０２、１０３ タングステンプラグ
１０４ 屈曲を有する導電性プラグ
２０１、２０２ 垂直な導電性プラグ
３０１ 入出力回路素子 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Diffusion layer 3 Field oxide layer 4 Multilayer wiring layer 5 Intermediate insulating layer 6, 60 Interlayer insulating layer 7 Uppermost layer insulating layer 8 Upper layer conductive pad 9 Lower layer conductive pad 10 Conductive plug 11 Center line of conductive plug Tangent line 20 bonding wire 30 probe 40 bonding capillary 61 interlayer insulating layer 62 having conductive plug 101 interlayer insulating layer 63 having conductive plug 102 interlayer insulating layer 66 having conductive plug 103 interlayer insulating layer made of Low-k material 101, 102, 103 Tungsten plug 104 Conductive plugs 201, 202 having a bend Vertical conductive plug 301 Input / output circuit element

Claims (5)

上層導電性パッドと下層導電性パッドとが、層間絶縁層を介して積層され、該上層導電性パッドと該下層導電性パッドとは、該層間絶縁層を貫通する複数の導電性プラグによって電気的に接続されている半導体装置において、該導電性プラグは、該上層導電性パッドと該下層導電性パッド間において、傾斜して形成されていることを特徴とする半導体装置。   An upper conductive pad and a lower conductive pad are stacked via an interlayer insulating layer, and the upper conductive pad and the lower conductive pad are electrically connected by a plurality of conductive plugs penetrating the interlayer insulating layer. In the semiconductor device connected to the semiconductor device, the conductive plug is formed to be inclined between the upper conductive pad and the lower conductive pad. 前記導電性プラグの傾斜方向が変化していることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein an inclination direction of the conductive plug is changed. 前記層間絶縁層は、複数の絶縁層の積層からなり、前記導電性プラグは各々の該絶縁層に位置をずらして形成された貫通口に充填された導電物を積層したものからなることを特徴とする請求項１記載の半導体装置。   The interlayer insulating layer is formed by stacking a plurality of insulating layers, and the conductive plug is formed by stacking conductive materials filled in through holes formed in the insulating layers at different positions. The semiconductor device according to claim 1. 前記下層導電性パッドのさらに下層に、前記上層導電性パッドと該下層導電性パッド間の層間絶縁層よりも、低誘電率の絶縁層が形成されていることを特徴とする請求項１記載の半導体装置。   The insulating layer having a lower dielectric constant than the interlayer conductive layer between the upper conductive pad and the lower conductive pad is formed in a lower layer of the lower conductive pad. Semiconductor device. 前記上層導電性パッド又は前記下層導電性パッドの少なくとも一方は、複数の分割領域を有し、該分割領域の各々に前記導電性プラグが形成されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor according to claim 1, wherein at least one of the upper conductive pad or the lower conductive pad has a plurality of divided regions, and the conductive plug is formed in each of the divided regions. apparatus.
JP2004350157A 2004-12-02 2004-12-02 Semiconductor device Expired - Fee Related JP4422004B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004350157A JP4422004B2 (en) 2004-12-02 2004-12-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004350157A JP4422004B2 (en) 2004-12-02 2004-12-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006165054A true JP2006165054A (en) 2006-06-22
JP4422004B2 JP4422004B2 (en) 2010-02-24

Family

ID=36666751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004350157A Expired - Fee Related JP4422004B2 (en) 2004-12-02 2004-12-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4422004B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531373B2 (en) 2007-09-19 2009-05-12 Micron Technology, Inc. Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry
US7679109B2 (en) 2006-12-08 2010-03-16 Seiko Epson Corporation Semiconductor device, layout design method thereof, and layout design device using the same
KR101067358B1 (en) * 2007-07-23 2011-09-23 내셔널 세미콘덕터 코포레이션 Bond pad stacks for ESD under pad and active under pad bonding
CN102054818B (en) * 2009-11-10 2012-08-22 中芯国际集成电路制造(上海)有限公司 Interconnection structure and manufacture method thereof
JP2015173284A (en) * 2012-09-28 2015-10-01 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． pad structure
TWI567868B (en) * 2012-05-04 2017-01-21 台灣積體電路製造股份有限公司 Semiconductor interconnect structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210039744A (en) 2019-10-02 2021-04-12 삼성전자주식회사 Semiconductor devices including a thick metal layer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7679109B2 (en) 2006-12-08 2010-03-16 Seiko Epson Corporation Semiconductor device, layout design method thereof, and layout design device using the same
KR101067358B1 (en) * 2007-07-23 2011-09-23 내셔널 세미콘덕터 코포레이션 Bond pad stacks for ESD under pad and active under pad bonding
US7531373B2 (en) 2007-09-19 2009-05-12 Micron Technology, Inc. Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry
US7741210B2 (en) 2007-09-19 2010-06-22 Aptina Imaging Corporation Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry
CN102054818B (en) * 2009-11-10 2012-08-22 中芯国际集成电路制造(上海)有限公司 Interconnection structure and manufacture method thereof
TWI567868B (en) * 2012-05-04 2017-01-21 台灣積體電路製造股份有限公司 Semiconductor interconnect structure
JP2015173284A (en) * 2012-09-28 2015-10-01 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． pad structure

Also Published As

Publication number Publication date
JP4422004B2 (en) 2010-02-24

Similar Documents

Publication Publication Date Title
JP6614212B2 (en) Wiring structure
US11145564B2 (en) Multi-layer passivation structure and method
JP2004235416A (en) Semiconductor device and manufacturing method thereof
US7459792B2 (en) Via layout with via groups placed in interlocked arrangement
JP5205066B2 (en) Semiconductor device and manufacturing method thereof
JP2001267323A (en) Semiconductor device and its manufacturing method
US7626268B2 (en) Support structures for semiconductor devices
KR100812731B1 (en) Interconnects with harmonized stress and methods for fabricating the same
JP2009147218A (en) Semiconductor device, and method for manufacturing the same
JP2005243907A (en) Semiconductor device
CN102130094B (en) Integrated circuit chip
JP5383446B2 (en) Semiconductor device
JP2011146563A (en) Semiconductor device
JP2009295733A (en) Semiconductor apparatus and method of manufacturing the same
US20100090344A1 (en) Semiconductor device
JP4422004B2 (en) Semiconductor device
JP2005142351A (en) Semiconductor device and its manufacturing method
JP4663510B2 (en) Semiconductor device
JP2003218114A (en) Semiconductor device and its manufacturing method
JP3725527B2 (en) Semiconductor device
JP4021376B2 (en) Pad structure
JP2015053371A (en) Semiconductor device and method of manufacturing the same
JP4701264B2 (en) Semiconductor device and manufacturing method of semiconductor device
KR100607363B1 (en) Inter-Metal-Dielectric Layer Using Low-k Dielectric Material And Method for Same
JP2004235586A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071004

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20080731

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090828

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090901

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091015

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091110

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091203

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4422004

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121211

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131211

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees