JP2020028118A - Ad converter and solid-state image sensor - Google Patents

Abstract

To provide an AD converter applicable to a solid-state image sensor and capable of achieving high throughput capacity.SOLUTION: An AD converter (130) includes: an analog circuit (131) for outputting a synthetic potential which is a difference between a reset potential and a signal potential from a pixel (120) on the basis of a reference potential; an AD conversion circuit (132). The AD conversion circuit digital-outputs a difference between the synthetic potential and the reference potential.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an AD converter and a solid-state imaging device using the AD converter.

  2. Description of the Related Art In recent years, image sensors have become widespread, and their applications are widespread. Above all, a CMOS (Complementary Metal Oxide Semiconductor) image sensor is widely used as a solid-state imaging device because it can be produced by a general-purpose semiconductor forming process.

  In a CMOS image sensor, noise removal processing by correlated double sampling (CDS) is performed to remove noise during a reset operation. As such a technique, an AD converter provided for each column performs two A / D conversions of a reset potential and a signal potential of a pixel, and performs a noise removal process by taking a difference between the two. Digital CDS is used.

JP 2011-229120 A (released on November 10, 2011)

  However, further enhancement of the performance of the CMOS image sensor is desired, and therefore, further improvement of the processing capability of the AD converter used therein is desired.

  An object of one embodiment of the present invention is to realize an AD converter with improved processing capability that can be applied to a solid-state imaging device.

(1) One embodiment of the present invention is an AD converter that receives a reset potential and a signal potential from a plurality of pixels and performs column AD conversion, wherein the reset potential and the reset potential are referenced to a reference potential. An analog circuit that outputs a composite potential that is a difference from a signal potential, and an AD conversion circuit that receives the composite potential and the reference potential, and digitally outputs a difference between the composite potential and the reference potential. An AD converter characterized by the following.
(2) An embodiment of the present invention is an A / D converter characterized in that the A / D conversion circuit is a single-slope A / D conversion circuit in addition to the configuration of (1).
(3) One embodiment of the present invention is an AD converter including a plurality of the analog circuits in addition to any one of the above (1) and (2).
(4) One embodiment of the present invention is a unit AD converter capable of receiving a reset potential and a signal potential from a plurality of pixels and performing column AD conversion, wherein the unit AD converter is based on a reference potential. An analog circuit capable of outputting a composite potential that is a difference between a reset potential and the signal potential; and an AD conversion circuit capable of inputting the composite potential and the reference potential, wherein a difference between the composite potential and the reference potential is digitally calculated. A plurality of unit A / D converters that can be output, and a potential obtained by adding the combined potential of the other unit A / D converter to the combined potential of the unit A / D converter is input to the A / D conversion circuit. An AD converter characterized in that the AD converter can be used.
(5) An embodiment of the present invention is an AD converter, characterized in that the unit AD converter includes a plurality of the analog circuits in addition to the configuration of the above (4).
(6) In one embodiment of the present invention, in addition to the configuration of any one of the above (3) to (5), the AD converter is a single slope type AD converter. It is.
(7) In one embodiment of the present invention, in addition to the configuration of any one of (1) to (6), the composite potential is obtained by subtracting the reset potential from the reference potential and adding the signal potential. An AD converter characterized by being a potential.
(8) In one embodiment of the present invention, in addition to the configuration of any one of (1) to (7), the analog circuit includes a first capacitor that holds a potential difference between a reference potential and the reset potential; A second capacitor for holding the signal potential, wherein the analog circuit outputs the composite potential by connecting the first capacitor and the second capacitor in series. , AD converters.
(9) One embodiment of the present invention is a solid-state imaging device including a plurality of pixels arranged in a matrix and a plurality of AD converters according to any one of (1) to (8).

  According to one embodiment of the present invention, an AD converter with improved processing capability, which can be applied to a solid-state imaging device, can be realized.

FIG. 1 is a diagram illustrating a solid-state imaging device according to a first embodiment. FIG. 2 is a schematic circuit diagram illustrating a configuration of a pixel of the solid-state imaging device according to Embodiment 1. FIG. 2 is a schematic circuit diagram illustrating a configuration of an AD converter according to the first embodiment. 5 is a timing chart illustrating an operation of the AD converter according to the first embodiment. 5 is a timing chart illustrating an operation of the AD converter according to the first embodiment. FIG. 6 is a schematic circuit diagram illustrating a configuration of an AD converter according to a second embodiment. 9 is a timing chart illustrating an operation of the AD converter according to the second embodiment. FIG. 9 is a schematic circuit diagram illustrating a configuration of an AD converter according to a third embodiment. FIG. 13 is a schematic circuit diagram illustrating a state of the AD converter according to Embodiment 3 in a predetermined period. FIG. 9 is a schematic circuit diagram illustrating a configuration of an AD converter according to a comparative example. 9 is a timing chart illustrating the operation of the AD converter of the comparative example. FIG. 2 is a schematic circuit diagram illustrating a configuration of a comparator of the solid-state imaging device according to the first embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the configuration, relative arrangement, operation, and the like of the configuration described in this embodiment are merely examples, and the scope of the present invention should not be limitedly interpreted by these. Further, the drawings are schematic, and dimensional ratios, shapes, and magnitudes and ratios of numerical values are different from actual ones. In each drawing, the same or corresponding components may be denoted by the same reference numerals.

[Embodiment 1]
Hereinafter, an embodiment of the present invention will be described in detail.

(Configuration of solid-state imaging device)
FIG. 1 is a diagram illustrating a solid-state imaging device 1 according to the first embodiment. In the solid-state imaging device 1, a plurality of pixels 120 are arranged in a matrix on a plane, and each of the pixels 120 is connected to a row selection signal line 111 and a readout signal line 112. The vertical scanning circuit 110 selects a row of the pixel 120 through the row selection signal line 111 of each row. The pixel 120 selected in the row outputs a signal to the readout signal line 112 of each column. The AD converter 130 is connected to the read signal line 112 of each column, and the memory 142 is further connected. The AD converter 130 obtains a pixel output signal from the pixel 120 in the column, performs a column AD conversion for sequentially converting the pixel output signal into a digital signal and outputting the digital signal. The horizontal scanning circuit 140 selects a column of the memory 142 through a column selection signal line 141 of each column. The selected memory 142 sequentially outputs digital signals through the horizontal output line 143. The solid-state imaging device 1 is a CMOS image sensor in the first embodiment, but may be another imaging device.

(Pixel configuration)
FIG. 2 is a circuit diagram schematically illustrating a configuration example of the pixel 120 of the solid-state imaging device 1. The pixel 120 includes a photodiode PD, a transfer transistor Ttr, a reset transistor Rtr, a selection transistor Str, an amplification transistor Atr, and a signal charge storage unit FD. Further, the pixel 120 supplies a readout signal line 112, a transfer signal line for transmitting a transfer signal TX, a reset signal line for transmitting a reset signal RST, a row selection signal line 111 for transmitting a row selection signal SEL, and a power supply voltage Vdd. Connected to the power line. Note that, in FIG. 1, for simplicity, reset signal lines, selection signal lines, and the like are omitted, but these are signal lines arranged for each row similarly to the row selection signal lines 111. It is.

  The reset transistor Rtr turns on in accordance with the reset signal RST, thereby discharging the signal charges stored in the signal charge storage unit FD, and resetting the potential of the signal charge storage unit FD to a high potential. The photodiode PD (sensor element) performs photoelectric conversion and generates signal charges corresponding to the amount of received light (incident light). The pixel 120 may include another type of light receiving element, sensor element, or the like, instead of the photodiode PD. The transfer transistor Ttr transfers the signal charge generated by the photodiode PD to the signal charge storage unit FD by being turned on in accordance with the transfer signal TX. The signal charge storage section FD is a floating diffusion region where signal charges are stored. Therefore, the potential of the signal charge storage section FD decreases according to the amount of the stored signal charge.

  In the selection transistor Str, the gate is connected to the row selection signal line 111, the drain is connected to the source of the amplification transistor Atr, and the source is connected to the read signal line 112. When the selection transistor Str is turned on in accordance with the row selection signal SEL, only the pixels 120 in the selected row among the plurality of pixels 120 arranged in the solid-state imaging device 1 output a pixel output signal to the readout signal line 112. .

  The amplification transistor Atr operates as a source follower transistor in which the source voltage (output voltage) changes so as to follow the gate voltage (input voltage) with a constant voltage gain. In the amplification transistor Atr, the gate is connected to the signal charge storage unit FD, and the drain is connected to the power supply line. Thus, the amplification transistor Atr outputs a signal voltage obtained by amplifying the potential of the signal charge storage unit FD to the read signal line 112 via the selection transistor Str.

  The voltage value (reset potential) of the pixel output signal VSIG when the potential of the signal charge storage unit FD is reset is set to VSIG (RST). In addition, the voltage value (signal potential) of the pixel output signal VSIG when the potential of the signal charge storage unit FD decreases according to the amount of signal charge stored in the PD is set to VSIG (SIG).

(Configuration of AD converter)
FIG. 3 is a schematic circuit diagram showing the configuration of the AD converter 130. The pixel output signal VSIG is input to the AD converter 130. The pixel output signal VSIG is an output of the pixel 120 whose row is selected by the vertical scanning circuit 110. The AD converter 130 reads out (samples) the reset potential VSIG (RST) generated in the pixel 120 and the signal potential VSIG (SIG) corresponding to the amount of signal charge accumulated in the PD, and performs a CDS operation for obtaining a difference. Execute. The AD converter 130 outputs the difference as a digital signal.

  The AD converter 130 includes an analog circuit 131 at a preceding stage and an AD converter 132 at a subsequent stage. In the following description, the side closer to the input end of the AD converter 130 will be referred to as the input side, and the side closer to the digital output end will be referred to as the output side.

  First, the configuration of the analog circuit 131 will be described. A switch SIG_SMP1 and a switch RST_SMP1 are connected to each of two branches from an input terminal to which the pixel output signal VSIG is input. The analog circuit 131 also receives a reference potential VCDS_REF and is connected to the switch CDS_REF_SMP1. A capacitor CS (second capacitor) is provided between the output side (voltage label VC_SIG) of the switch SIG_SMP1 and the ground. The switch ACDS_EN1 is provided between the output side of the switch SIG_SMP1 and the output side (voltage label VC_RST) of the switch RST_SMP1. A capacitor CR (first capacitor) is provided between the output side of the switch RST_SMP1 and the output side (voltage label VACDS) of the switch CDS_REF_SMP1. A switch CMP_CCNT1 is provided between the output side of the switch CDS_REF_SMP1 (one end of the capacitor CR) and the output of the analog circuit 131 (voltage label VAD_SIGIN).

  Next, the configuration of the AD conversion circuit 132 will be described. The AD conversion circuit 132 is a single slope type AD conversion circuit. The input terminal of the AD conversion circuit 132 is connected to the output terminal of the analog circuit 131. The input terminal (voltage label VAD_SIGIN) of the AD conversion circuit 132 is connected to the comparator 133 through the coupling capacitor CIN. Further, the clip voltage VAZCLP can be introduced to the input terminal of the AD conversion circuit 132 via the switch CMP_AZCLP. The ramp signal VRAMP is introduced to the other input terminal of the comparator 133 through the coupling capacitor CIN. The output of the comparator 133 (voltage label XCMPO: 1-bit signal) is input to the counter 134. The counter 134 outputs the count number of the pulse of the clock signal CLK in a predetermined period as the output digital signal D_OUT of the AD converter 130. A single-slope A / D conversion circuit performs an A / D conversion by comparing an analog input signal and a ramp signal with a comparator, and digitally outputting a pulse count number of a clock signal required until the magnitude relationship is inverted. Refers to a circuit.

  An example circuit diagram of the comparator 133 is shown in FIG. FIG. 12 shows the input capacitor CIN of the signal VAD_SIGIN and the ramp signal VRAMP in addition to the comparator 133.

  In FIG. 12, AVDD, CVDD, CGND, and AGND represent an analog power supply voltage, a comparator regulator voltage, a first comparator ground, and an analog ground, respectively. CMP_REG_VG1, CMP_REG_VG2, and XAZ are a gate input voltage of the first comparator section regulator voltage generation Tr, a gate input voltage of the second comparator section regulator voltage generation Tr, and an input / output short (auto zero) control signal, respectively. CMP1ST_VB1, CMP1ST_VB0, and CMP1ST_EN are a tail bias current control voltage of the first 1st comparator, a tail bias current control voltage of the second 1st comparator, and a tail bias current ON / OFF control signal of the 1st comparator, respectively. CMP2ND_VB1, CMP2ND_VB0, and CMP2ND_EN are a tail bias current control voltage of the first 2nd comparator, a tail bias current control voltage of the second 2nd comparator, and a tail bias current ON / OFF control signal of the 2nd comparator, respectively.

(Operation of AD converter)
FIG. 4 is a timing chart showing the on / off operation of each switch, and FIG. 5 is a timing chart showing the voltage waveform at each point. The operation of the AD converter 130 will be described with reference to these.

  Period T1 (auto-zero period): First, the switch CDS_REF_SMP1 and the switch CMP_AZCLP are turned on. Other switches are off. The clip voltage VAZCLIP is applied to the input terminal of the comparator 133, and at the same time, the input and output of the comparator 133 are short-circuited (input / output short control signal XAZ is turned on), thereby performing auto-zero. At the end of the period, the switch CMP_AZCLP is turned off (the input / output short control signal XAZ signal is also turned off).

  Period T2 (AD conversion period of reference potential): The switch CMP_CCNT1 is turned on. Then, the input voltage VAD_SIGIN of the comparator 133 becomes equal to the reference potential VCDS_REF. Then, the counting of the number of clocks by the counter 134 and the voltage change of the ramp signal VRAMP are started (single slope AD conversion is started). Here, the ramp signal VRAMP is a constant value VRAMP (ST) having a slightly higher potential than the reference potential VCDS_REF in a normal state, but is a signal that falls linearly with a constant gradient with time when the voltage change starts. It should be noted that the voltage change may be configured not only in the falling direction but also in the rising direction. When the voltage change ends, the voltage returns to the initial constant value. At the start of the voltage change, the ramp signal VRAMP has a higher potential than the input voltage VAD_SIGIN to the comparator 133. When the magnitude relationship is reversed with a decrease in the potential of the ramp signal VRAMP, the comparator output XCMPO is inverted. When the inversion of the comparator output XCMPO is detected, the counter 134 stops counting. (Single slope type AD conversion is completed). Therefore, here, the reference potential VRAMP (ST) -VCDS_REF based on VRAMP (ST) is converted into a count number. In the AD conversion of the reference potential (period T2), the count is down-counted. When the counting stops, the switch CMP_CCNT1 is turned off, and the period T2 ends.

  Period T3 (reset potential sampling period): The AD converter 130 operates so as to adapt the period T3 to a period in which the pixel 120 outputs the reset potential VSIG (RST) as the output signal VSIG. Turn on the switch RST_SMP1. Then, the potentials at both ends of the capacitor CR are VACDS = VCDS_REF and VC_RST = VSIG (RST), respectively. At the end of the period T3, the switches RST_SMP1 and CDS_REF_SMP1 are turned off.

  Period T4 (sampling period of signal potential): The AD converter 130 operates so as to adapt the period T4 to a period during which the pixel 120 outputs the signal potential VSIG (SIG) as the output signal VSIG. Turn on the switch SIG_SMP1. Then, the potential VC_SIG of the terminal on the output side of the capacitor CS becomes VSIG (SIG). The potential of the other terminal of the capacitor CS is always 0 because it is grounded. At the end of the period T4, the switch SIG_SMP1 is turned off.

  Period T5 (CDS period): The switch ACDS_EN1 is turned on. Generally, a capacitor tries to maintain a potential difference between both ends unless electric charges enter and exit. The potential VC_SIG of the terminal on the output side of the capacitor CS does not change from the period T4 and is VSIG (SIG). The capacitor CR is charged so that the potential difference between both ends becomes VCDS_REF-VSIG (RST) during the period T3. During the subsequent period T4, all switches connected to the capacitor CR are off. Therefore, even in the period 5, the capacitor CR operates to keep the potential difference VACDS-VC_RST between both ends at VCDS_REF-VSIG (RST). Therefore, by turning on the switch ACDS_EN1, the capacitors CR and CS are connected in series. As a result, the respective potential differences are combined, and the potential VACDS of the terminal on the output side of the capacitor CR becomes the combined potential VSIG (SIG) + VCDS_REF-VSIG ( RST) = VC. That is, the composite potential VC is obtained by subtracting the reset potential VSIG (RST) from the reference potential VCDS_REF and further adding the signal potential VSIG (SIG). The combined potential is a difference VSIG (SIG) -VSIG (RST) between the reset potential and the signal potential with reference to the reference potential. Next, when the switch CMP_CCNT1 is turned on, the input voltage VAD_SIGIN of the comparator is set to the main composite potential VC.

Period T6 (A / D conversion period of composite potential):
The clock count by the counter 134 and the voltage change of the ramp signal VRAMP are executed, and the single slope AD conversion is performed in the same manner as in the above-described period T2. Then, here, the combined potential VC based on VRAMP (ST) is converted into the count number. Further, in the A / D conversion of the composite potential (period T6), the count is taken over from the end of the down-count in the A / D conversion of the reference potential (period T2), and the up-count is performed. Therefore, when the AD conversion of the composite potential VC (period T6) is completed, the count number corresponds to the difference between the AD conversion value of the composite potential and the AD conversion value of the reference potential. That is, VSIG (RST) -VSIG (SIG) corresponds to the final count number, and is output from the AD converter 130 as a digital output D_OUT. At the end of the period T6, the switches ACDS_EN1 and CMP_CCNT1 are turned off.

  As described above, in the periods T1 to T6, the reading of one pixel by the AD converter 130 and the AD conversion processing are completed. Therefore, in the first embodiment, the unit H time (unit horizontal time), which is the cycle in which the AD converter 130 reads out one pixel and also performs the digital output for one pixel, is the period T1 to T6. Period.

(Advantages of AD converter)
As described above, VSIG (RST) -VSIG (SIG) is obtained as a final output from the AD converter 130 for each pixel 120, and the CDS operation is being performed. A threshold variation (hereinafter, pixel variation) due to a threshold characteristic of a transistor or the like for each pixel 120 is canceled by calculating a difference between two pixel outputs of a reset potential VSIG (RST) and a signal potential VSIG (SIG). . This is realized by effectively generating the composite potential VC by the analog circuit 131 in the period T5. Further, the variation in the characteristics for each column (hereinafter, column variation) such as the variation in the characteristics for each AD conversion circuit 132 is calculated by comparing the AD conversion results of the reference potential (digital value) and the combined potential (digital value) twice. Canceled by taking the difference. This is realized by a counter (up-down counter) in which a count for AD conversion of the reference potential VCDS_REF is set to a down-count, and then a count for AD conversion of the composite potential VC is an up-count. However, the method for obtaining the difference between the two AD conversion results is not limited to this, and may be replaced with another known method. For example, it is realized by a counter (up-up counter) in which a count for AD conversion of the reference potential VCDS_REF is set as an up-count, the count value is inverted for all bits, and then a count for AD conversion of the composite potential VC is an up-count. May be.

  As described above, according to the AD converter 130 of the first embodiment, a final output in which both the pixel variation and the column variation are canceled is obtained.

(Comparison with comparative example)
An AD converter 930 of a comparative example that performs a general digital CDS operation will be described for comparison with the AD converter 130 of the first embodiment. FIG. 10 is a diagram illustrating an AD converter 930 of a comparative example. The AD converter 930 is different from the AD converter 130 in that the analog circuit 131 is not provided, and the pixel output signal VSIG is directly input to the comparator 933. Further, unlike the AD converter 130, the AD converter 930 does not use the reference potential VCDS_REF. The AD conversion method in the AD converter 930 is a single slope type using a counter 934, and is similar to the AD converter 130.

  FIG. 11 is a diagram showing the operation of the AD converter 930 of the comparative example, and shows voltage waveforms of the ramp signal VRAMP and the pixel output signal VSIG. In the operation of the AD converter 930 that performs general digital CDS, for a certain pixel 120, AD conversion of the reset potential VSIG (RST) is performed as the first AD conversion, and signal potential VSIG (SIG) is performed as the next AD conversion. A / D conversion is performed. By counting down and counting up by the counter 934, VSIG (RST) -VSIG (SIG) is obtained as a digital output D_OUT. Pixel variation is canceled by taking the difference between the reset potentials VSIG (RST) and VSIG (SIG). Column variation is also canceled by taking the difference between the two AD conversions. As described above, also in the AD converter 930 of the comparative example that performs a general digital CDS operation, a final output in which pixel variations and column variations are canceled can be obtained.

  In the single-slope AD conversion, counting is performed by reversing the magnitude relationship between two inputs to the comparator. Therefore, AD conversion cannot be performed unless there is an input signal within the range of the voltage change width of the ramp signal VRAMP. In the AD converter 930 of the comparative example, the reset potential VSIG (RST), which is the target of the first AD conversion, has a pixel variation. It needs to be large. Then, a long period of AD conversion of the reset potential VSIG (RST) is required. Similarly, the signal potential VSIG (SIG) to be subjected to the next A / D conversion also includes a pixel variation, so that the necessary voltage change period is also long here. In this period, the slope of the voltage change waveform, which is the ratio of the conversion from the voltage to the count (time), is reduced (higher analog gain), and the accuracy of the count is improved. Become. Therefore, there is a limit in improving the AD conversion processing speed.

  On the other hand, the first A / D conversion (period T2) for a certain pixel 120 in the operation of the A / D converter 130 is for a constant reference potential VCDS_REF, and the variation is very small. Therefore, the period of the first AD conversion may be very short. Similarly, in the second AD conversion (period T2) in which the AD conversion of the composite potential VC is performed, the pixel variation is already canceled by the analog circuit 131 and is not included. Good. Furthermore, there is no problem that saturation is likely to occur in AD conversion due to the inclusion of pixel variation, and high gradation can be achieved.

(effect)
As described above, according to the AD converter 130 according to the first embodiment, it is possible to obtain an output signal in which pixel variation and column variation are canceled. The period required for AD conversion is short, and the processing capability can be improved. Higher sensitivity can be achieved by allocating processing power to sensitivity improvement. Further, high saturation can be achieved with little saturation.

  According to the solid-state imaging device 1 according to the first embodiment, it is possible to obtain a high-quality captured image with reduced pixel variation and column variation. Further, it is possible to obtain a captured image with a higher frame rate. In addition, it is possible to obtain a high-quality captured image with higher sensitivity and higher gradation.

[Embodiment 2]
Embodiment 2 of the present invention will be described below. For convenience of description, members having the same functions as those described in the above embodiment are denoted by the same reference numerals, and description thereof will not be repeated.

(Configuration of AD converter 230)
FIG. 6 is a schematic circuit diagram illustrating a configuration of the AD converter 230 according to the second embodiment.

  The AD converter 230 has a configuration in which two analog circuits (231 and 281) are connected in parallel to the analog circuit 131 of the AD converter 130 according to the first embodiment. An input terminal to which the pixel output signal VSIG is input and an input terminal to which the reference potential VCDS_REF is introduced are branched and connected to the analog circuits 231 and 281 respectively. The outputs of the respective analog circuits 231 and 281 are merged and input to the AD conversion circuit 132. The AD conversion circuit 132 is the same as the AD conversion circuit of the AD converter 130 according to the first embodiment. The AD conversion circuit 132 has a comparator 133 and a counter 134. The sign of each switch in the analog circuit 231 is the same as the sign of the corresponding switch in the analog circuit 131. The sign of each switch in the analog circuit 281 is obtained by changing the last one character of the sign of the corresponding switch in the analog circuit 131 to 2. The signs of the capacitors in the analog circuits 231 and 281 are obtained by adding characters 1 and 2 to the end of the signs of the corresponding capacitors in the analog circuit 131, respectively.

(Operation of AD converter 230)
The AD converter 230 performs an operation of alternately reading the set of the reset potential and the signal potential for each pixel 120 sequentially sent by the pixel output signal VSIG by the two analog circuits 231 and 281. In addition, the voltage signal for each pixel 120 processed by the two analog circuits 231 and 281 is input to the AD conversion circuit 132 to perform AD conversion processing. The reading (sampling) process and the AD conversion process proceed simultaneously and in parallel. One analog circuit 231 performs the reading process of the pixels 120 in the k-th row within the first unit H time, and performs the AD conversion process in the next unit H time. The other analog circuit 281 reads out the pixels 120 in the (k + 1) th row in the next unit H time. As for ON / OFF of each switch, this two-unit H time is one cycle. In the following description, the processing for one pixel will be described over two units of H time, and the operation of each switch will be described for ON / OFF of each switch.

  Period T11: First, the switch CDS_REF_SMP2 is on and the other switches are off. At the beginning of the period, the switch CDS_REF_SMP1 and the switch CMP_AZCLP are turned on, and at the end of the period, the switch CMP_AZCLP is turned off.

  Period T12 (sampling period of reset potential): The AD converter 230 operates so as to adapt the period T12 to a period during which the pixels 120 in the k-th row output the reset potential VSIG (RST) as the pixel output signal VSIG. . The switch RST_SMP1 is turned on at the beginning of the period, and turned off at the end of the period. At the beginning of the period, the switch SIG_SMP1 and the switch ACDS_EN1 are turned on, and are immediately turned off. The switch RST_SMP1, the switch SIG_SMP1, and the switch ACDS_EN1 are all turned on for a very short period of time, so that the reset potential VSIG (RST) is applied to the connection between the capacitor CS1 and the capacitor CR1. As a result, initialization is performed to keep the states of the capacitors CS1 and CR1 constant regardless of the magnitude of the previous signal. The period T12 is a period in which the reset potential is sampled in the capacitor CR1 (similar to the period T3 in the first embodiment). The switch CMP_CCNT2 is turned on at the beginning of the period, and is turned off together with the switch CDS_REF_SMP2 by the end of the period. At this time, CMP_AZCLP is turned on.

  Period T13 (sampling period of signal potential): The AD converter 230 operates so as to adapt the period T13 to a period during which the pixel 120 outputs the signal potential VSIG (SIG) as the pixel output signal VSIG. At the beginning of the period, the switch CMP_AZCLP is turned off, and the switch SIG_SMP1 is turned on. This is a period during which the signal potential is sampled by the capacitor CS1 (similar to the period T4). At the end of the period, the switch SIG_SMP1 is turned off. When the switch CMP_AZCLP is turned off at the beginning of the period, the switches ACDS_EN2 and CMP_CCNT2 are turned on, and turned off at the end of the period.

  The first unit H time ends in the periods T11 to T13, and the reading from the pixels 120 in the k-th row is completed. The on / off operation of the switch in the next unit H time is the one in which the on / off operation of the switch in the first unit H time (T11 to T13) is replaced by the analog circuits 231 and 281.

  Period T21 (auto-zero period): The switches CDS_REF_SMP2 and the switch CMP_AZCLP are turned on at the beginning of the period, and the switch CMP_AZCLP is turned off at the end of the period. During the period, the clip voltage VAZCLIP is applied to the input of the comparator 133 and is auto-zeroed (similar to the period T1).

  Period T22 (AD conversion period of reference potential): At the beginning of the period T22, the CMP_CCNT1 is turned on. When the switches CDS_REF_SMP1 and the switch CMP_CCNT1 are on, the reference potential VCDS_REF is input to the comparator 133. During this time, the AD conversion circuit 132 performs AD conversion of the reference potential VCDS_REF (similar to the period T2). By the end of the period, the CMP_CCNT1 and the switch CDS_REF_SMP1 are turned off. At this time, CMP_AZCLP is turned on. Then, the clip voltage VAZCLIP is applied to the input of the comparator 133 and is auto-zeroed. In addition, the AD converter 230 operates so that the period T22 is adapted to a period in which the pixel 120 outputs the reset potential VSIG (RST) as the pixel output signal VSIG. The switch RST_SMP2 is turned on at the beginning of the period and turned off at the end. At the beginning of the period, the switch SIG_SMP2 and the switch ACDS_EN2 are turned on, and are immediately turned off.

  Period T23 (combination operation of potential and AD conversion period of combined potential): At the beginning of the period, the switch CMP_AZCLP is turned off to end the auto-zero. Then, when the switches ACDS_EN1 and CMP_CCNT1 are turned on, the voltages held in the capacitors CR1 and CS1 are combined (similar to the period T5). Further, the combined potential VC is supplied to the comparator 133 to perform AD conversion (similar to the period T6). At the end of the period, the switches ACDS_EN1 and CMP_CCNT1 are turned off. In addition, the AD converter 230 operates so as to adapt the period T23 to a period during which the pixel 120 outputs the signal potential VSIG (SIG) as the pixel output signal VSIG. The switch SIG_SMP2 is turned on at the beginning of the period and turned off at the end.

  In the above periods T21 to T23, the next unit H time ends, and two AD conversions are completed. The on / off operation of the switch in the first unit H time (T11 to T13) is replaced by the analog circuits 231 and 281 in the next unit H time (T21 to T23). Therefore, the analog circuit 281 starts the process for the pixels 120 in the (k + 1) th row during the periods T21 to T23, and completes the reading operation.

(Effect of Embodiment 2)
By the operations in the above periods T11 to T23, the same processing as that in the first embodiment is performed on the pixel output signal. Therefore, also in the second embodiment, it is possible to obtain an output signal in which the pixel variation and the column variation are canceled. Further, the period required for AD conversion is short, and the processing capability can be improved. Higher sensitivity can be achieved by allocating processing power to sensitivity improvement. In addition, high gradation can be achieved with little saturation.

  Furthermore, according to the AD converter 230 according to the second embodiment, the readout from the pixel 120 and the AD conversion are performed simultaneously and in parallel by including the plurality of analog circuits 231 and 281. Therefore, the processing capability of AD conversion can be further greatly improved.

  Further, in the solid-state imaging device using the AD converter 230, it is possible to obtain a high-quality captured image with reduced pixel variation and column variation. Further, it is possible to obtain a photographed image having a significantly higher frame rate. In addition, it is possible to obtain a high-quality captured image with higher sensitivity and higher gradation.

[Embodiment 3]
Embodiment 3 of the present invention will be described below.

(Configuration of AD converter 330)
FIG. 8 is a schematic circuit diagram illustrating a configuration of the AD converter 330 according to the third embodiment.

  The AD converter 330 includes the same circuit as the AD converter 230 according to the second embodiment as unit AD converters 330a and 330b. In the solid-state imaging device according to the third embodiment, the AD converter 330 is provided over two rows. The unit AD converter 330a includes analog circuits 331a and 381a and an AD converter 332a, and the AD converter 332a includes a comparator 333a and a counter 334a. The unit AD converter 330b includes analog circuits 331b and 381b and an AD conversion circuit 332b, and the AD conversion circuit 332b includes a comparator 333b and a counter 334b. The signs of the switches of the unit AD converters 330a and 330b are respectively obtained by adding _A and _B to the signs of the corresponding switches in the AD converter 230, respectively. The signs of the capacitors of the unit A / D converters 330a and 330b are obtained by adding a and b to the end of the signs of the corresponding capacitors in the A / D converter 230, respectively.

  However, as a point different from the AD converter 230, in the unit AD converter 330a, the ground-side terminal of the capacitor CS1a is branched into two. One of the branches is grounded via switch CB_ASE_EN1. The other is connected to the output terminal of the capacitor CR1b of the unit AD converter 330b via the switch HB_INNING_EN1. The same applies to the capacitor CS2a. One of the branches from the ground terminal of the capacitor CS2a is grounded via the switch CB_ASE_EN2. The other is connected to the output terminal of the capacitor CR2b of the unit AD converter 330b via the switch HB_INNING_EN2.

(Operation of AD converter 330)
Normal operation mode: Each of the unit AD converters 330a and 330b can operate exactly the same as the AD converter 230 of the second embodiment. In the normal operation mode, the switches CB_ASE_EN1 and CB_ASE_EN2 are always on, and the switches HB_INNING_EN1 and HB_INNING_EN2 are always off. Therefore, the unit AD converters 330a and 330b are separated, and each has the same circuit configuration as the AD converter 230 of the second embodiment. The unit AD converter 330a performs column AD conversion of the n-th column, and the unit AD converter 330b performs column AD conversion of the (n + 1) -th column.

  Horizontal addition operation mode: Also, the unit AD converters 330a and 330b can execute the horizontal addition operation in cooperation with each other. This operation mode will be described in detail below.

  In the horizontal addition operation mode, the AD conversion circuit 332b of the unit AD converter 330b does not operate. The switches CMP_CCNT1_B and CMP_CCNT2_B input to the AD conversion circuit 332b are always off. Therefore, at this time, the number of columns in the solid-state imaging device according to the third embodiment including the AD converter 330 is half that in the normal operation mode.

  Also in the horizontal addition operation mode, normally, the switches CB_ASE_EN1 and CB_ASE_EN2 are on, and the switches HB_INNING_EN1 and HB_INNING_EN2 are off. Thus, the analog circuits 331a, 381a, 331b, and 381b of the unit AD converters 330a and 330b normally operate in the same manner as the AD converter 230 of the second embodiment.

  However, the operation differs in the operation of synthesizing the potential difference held in the capacitor during the period T23 in the second embodiment. In the AD converter 330, the potential differences held in the capacitors CR1a, CS1a, CR1b, and CS1b are combined. FIG. 9 shows the on / off state of the switch during the combining operation. In this period, as shown in FIG. 9, the switches CB_ASE_EN1_A in the unit AD converter 330a are turned off and the switches HB_INNING_EN1 are turned on in accordance with the turning on of the switches ACDS_EN1_A and ACDS_EN1_B. Then, the capacitors CR1a, CS1a, CR1b, and CS1b are connected in series. By this operation, the potential differences held in the capacitors CR1a, CS1a, CR1b, and CS1b are combined and input to the AD conversion circuit 332a. Further, in the period T13, the operation of synthesizing the potential difference held in the capacitors CR2a, CS2a, CR2b, and CS2b is similarly performed. Since the signals of the pixels in the n-th column and the (n + 1) -th column received by the analog circuits 331a and 331b are added and A / D-converted, the output voltage is approximately twice as large as that in the second embodiment.

(Effect of Embodiment 3)
With the above operation, the unit AD converters 330a and 330b have substantially the same circuit configuration as the AD converter 230 of the second embodiment in the normal operation mode, and the same processing is performed on the pixel output signal VSIG in each column. Is performed. Therefore, the same effect as the AD converter 230 of the second embodiment can be obtained in the AD converter 330. Further, also in the solid-state imaging device according to the third embodiment using the AD converter 330, the same effect as the solid-state imaging device according to the second embodiment can be obtained.

  Further, in the horizontal addition operation mode, the AD converter 330 can add and output signals from a plurality of columns of pixels, and can significantly improve sensitivity. Therefore, in the solid-state imaging device according to the third embodiment, it is possible to obtain a captured image with significantly increased sensitivity.

  Further, in the solid-state imaging device and the AD converter 330 according to the third embodiment, the normal operation mode and the horizontal addition operation mode can be switched in this manner.

[Appendix]
The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 110 Vertical scanning circuit 111 Row selection signal line 112 Readout signal line 120 Pixel 130, 230, 330 AD converter 131, 231, 281, 331a, 331b, 381a, 381b Analog circuit 132, 332a, 332b AD conversion circuit 133, 333a, 333b Comparator 134, 334a, 224b Counter 140 Horizontal scanning circuit 141 Column selection signal line 142 Memory 143 Horizontal output line 330a, 330b Unit AD converter CR, CR1, CR1a, CR1b, CR2, CR2a, CR2b Capacitor (No. 1 capacitor)
CS, CS1, CS1a, CS1b, CS2, CS2a, CS2b Capacitor (second capacitor)

Claims (9)

An AD converter that receives a reset potential and a signal potential from a plurality of pixels and performs column AD conversion,
An analog circuit that outputs a composite potential that is a difference between the reset potential and the signal potential with reference to a reference potential,
An AD conversion circuit to which the combined potential and the reference potential are input,
The A / D converter, wherein the A / D conversion circuit digitally outputs a difference between the combined potential and the reference potential. The AD conversion circuit is a single slope type AD conversion circuit,
The AD converter according to claim 1.   The AD converter according to claim 1, comprising a plurality of the analog circuits. A unit AD converter capable of receiving a reset potential and a signal potential from a plurality of pixels and performing column AD conversion,
An analog circuit that can output a composite potential that is a difference between the reset potential and the signal potential with reference to a reference potential,
An AD conversion circuit capable of inputting the composite potential and the reference potential,
A plurality of unit AD converters that can digitally output a difference between the combined potential and the reference potential,
An A / D converter characterized in that a potential obtained by adding the combined potential of another unit A / D converter to the combined potential of the unit A / D converter can be input to the A / D conversion circuit. The unit AD converter includes a plurality of the analog circuits,
The AD converter according to claim 4. The AD conversion circuit is a single slope type AD conversion circuit,
The AD converter according to claim 3.   The A / D converter according to claim 1, wherein the combined potential is a potential obtained by subtracting the reset potential from the reference potential and adding the signal potential. The analog circuit includes:
A first capacitor for holding a potential difference between a reference potential and the reset potential;
A second capacitor for holding the signal potential,
The analog circuit outputs the composite potential by connecting the first capacitor and the second capacitor in series,
The A / D converter according to claim 1.   A solid-state imaging device comprising a plurality of pixels arranged in a matrix and a plurality of AD converters according to any one of claims 1 to 5.

Images