JP2009130828A - Solid imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress output image shading that is caused by difference in the gradient of a ramp signal of each row. <P>SOLUTION: A pixel portion 10 having a plurality of pixels 11 arranged in N rows, M columns outputs pixel signals to M row signal lines L2 corresponding to each column. A latch circuit 81 latches values counted by a counter 70 as the pixel signals with predetermined bits until a level of the ramp signal reaches that of the pixel signal. A control portion 300 in which the pixel signals with the predetermined bits are inputted carries out correction for reducing fluctuations of the pixel signals of each column that are caused after A/D conversion thereof is carried on the basis of a difference in the gradient of the ramp signal inputted in each comparator 50 due to the wiring length of the ramp signal line L1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a column parallel A / D conversion type solid-state imaging device.

  In recent years, in order to realize a high-speed operation of a CMOS image sensor, a CMOS image sensor of a column parallel A / D conversion type in which A / D conversion is performed in each column of the CMOS image sensor has been developed. The column parallel A / D conversion method is a method of converting into a digital signal while suppressing fixed pattern noise of a pixel by an A / D converter that performs parallel processing for each column (Non-patent Document 1, Patent Document 1). Specifically, a comparator is provided for each column signal line, a pixel signal and a ramp signal from a pixel corresponding to each comparator are input, and after the input of the ramp signal is started, the voltage level of the ramp signal is equal to that of the pixel signal. A / D conversion is performed by counting the time until the voltage level is reached.

Further, in Non-Patent Document 2 and Patent Document 2, after the reference component is counted in the down-count mode, a subtraction process is performed in which the signal component is counted in the up-count mode, and a reset component including variation for each unit pixel; An AD conversion method for removing an offset component for each column AD circuit is disclosed (paragraphs [0165] to [0169] in Patent Document 2).
Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publishing Company, p. 201-203 SONY CX-PAL71 http://www.sony.co.jp/Products/SC-HP/cx_pal/vol71/pdf/featuring71.pdf Japanese Patent Laid-Open No. 5-48460 JP 2005-323331 A

  However, in the above-described column parallel A / D conversion type image sensor, when the number of column signal lines increases, the ramp signal input to each comparator is the wiring length of the ramp signal line connecting the signal source and each comparator. The inclination becomes smaller due to the increase in the wiring load accompanying the increase in. As a result, even if the amount of incident light is the same, the pixel signal after A / D conversion in a column with a long wiring length of the lamp signal line has a larger value than the pixel signal in a short column. There is a problem in that the pixel signals after conversion vary and shading appears in the output image.

  An object of the present invention is to provide a solid-state imaging device capable of suppressing the appearance of shading in an output image due to a difference in slope of a ramp signal in each column.

  (1) A solid-state imaging device according to the present invention is a column-parallel A / D conversion type solid-state imaging device, and is arranged in N (N is an integer of 1 or more) rows × M (M is an integer of 2 or more) columns. A pixel unit that outputs a pixel signal to M column signal lines corresponding to each column, a ramp signal generation unit that generates a ramp signal and outputs the ramp signal to the column signal line, and the column signal line The pixel signal is input via the ramp signal line, the ramp signal is input via the ramp signal line, and a detection signal is output when the voltage level of the ramp signal reaches the voltage level of the pixel signal. By counting the time from the start of the output of the ramp signal by the M comparison units corresponding to the columns to the output of the detection signal by each comparison unit, the pixels A / to convert the signal from analog to digital Correction processing is performed to reduce variation in pixel signals after analog-to-digital conversion in each column based on a difference in slope of the ramp signal input to the conversion unit and each comparison unit due to the wiring length of the ramp signal line. And a correction unit.

  According to this configuration, correction for reducing variations in pixel signals after analog-to-digital conversion in each column based on a difference in slope of the ramp signal input to each comparison unit due to the length of the ramp signal line. Since the process is performed, it is possible to suppress the appearance of shading in the output image.

  (2) It is preferable that the correction unit performs the correction process on the basis of a column having the maximum or minimum slope of the ramp signal. According to this configuration, the correction process is performed based on the shortest column or the longest column of the lamp signal line, so that the process can be simplified.

  (3) It is preferable that the correction unit performs the correction process on the pixel signal after analog-digital conversion. According to this configuration, since the correction process is performed digitally, it is possible to accurately suppress the appearance of shading in the output image.

  (4) It is preferable that the correction unit performs the correction process by adjusting a gain of a pixel signal input to each comparison unit. According to this configuration, since the gain of the pixel signal is adjusted so as to reduce the variation in the pixel signal after A / D conversion of each column, it is possible to accurately suppress the occurrence of shading in the output image. .

  (5) The correction unit is preferably configured by M amplifier circuits connected in front of the comparison units in each column signal line. According to this configuration, since the gain adjustment of the pixel signal is performed by the amplifier circuit provided in each column, the gain adjustment can be adjusted with high accuracy.

  (6) The gain is preferably a different value for each column or for each of a plurality of columns. According to this configuration, it is possible to accurately suppress the occurrence of shading in the output image by setting a preferable gain for the amplifier circuit in each column. In addition, by setting a preferable gain of the amplifier circuit in advance for each of a plurality of columns, the processing can be simplified.

  (7) It is preferable that the correction unit performs the correction process by adjusting the gain of the ramp signal input to each comparison unit. According to this configuration, it is possible to reduce variation in the slope of the ramp signal input to each comparison unit, and it is possible to suppress the appearance of shading in the output image.

  (8) It is preferable that the correction unit is configured by an amplifier circuit connected between the ramp signal generation unit and the comparison unit. According to this configuration, since the gain adjustment of the ramp signal is performed by the amplifier circuit, the gain adjustment can be performed with high accuracy.

  (9) The amplifier circuit is preferably provided for each column or for each of a plurality of columns. According to this configuration, it is possible to reduce variation in pixel signals after A / D conversion by setting a gain that makes the slope of the ramp signal constant in the amplifier circuit of each column, and shading appears in the output image. This can be suppressed. In addition, it is possible to simplify the processing by setting in advance a preferable gain for making the slope of the ramp signal constant in the amplifier circuits for each of a plurality of columns.

  (10) It is preferable that the correction unit periodically detects an amount of change in inclination of each column of the ramp signal, and obtains a correction value to be used for the correction process based on a detection result. According to this configuration, the delay amount of each column of the ramp signal is periodically detected, and the correction value used for the correction process is obtained based on the detection result. Therefore, after the A / D conversion due to the change in the environmental temperature It is possible to flexibly cope with changes in the variation of the pixel signal.

  According to the present invention, it is possible to suppress the appearance of shading in the output image due to the difference in the slope of the ramp signal in each column.

(Embodiment 1)
The solid-state imaging device according to Embodiment 1 of the present invention will be described below. FIG. 1 shows a block diagram of a solid-state imaging device according to Embodiment 1 of the present invention. The solid-state imaging device shown in FIG. 1 is a solid-state imaging device including a column-parallel A / D (analog / digital) conversion type CMOS image sensor, and includes a pixel unit 10, a vertical scanning circuit 20, a ramp signal generation circuit 30, a GCA / CDS. Circuit 40, comparator (CMP) 50 (an example of a comparison unit), edge detection circuit (ED: Edge Detector: an example of a comparison unit) 60, counter 70 (an example of an A / D conversion unit), latch unit 80 (A / D) An example of a conversion unit), a sense amplifier (SA) 90, a horizontal scanning circuit 100, a timing generator (TG) 110, and a control unit 300 (an example of a correction unit). In the present embodiment, a CMOS image sensor in which each circuit other than the control unit 300 shown in FIG. Note that each circuit constituting the CMOS image sensor may be constituted by individual circuits without being integrated into one chip.

  The pixel unit 10 includes a plurality of pixels 11 arranged in N (N is an integer of 1 or more) rows × M (M is an integer of 2 or more) columns, and M column signal lines L2 corresponding to the respective columns are provided. A pixel signal is output. In FIG. 1, for convenience of explanation, only a total of six pixels 11 of 2 rows × 3 columns are shown. The pixel 11 includes a photodiode, an amplifier circuit, and the like. The signal charge photoelectrically converted by the photodiode is amplified by the amplifier circuit to be converted into an electric signal, and is output to the column signal line L2 as a pixel signal. In the present embodiment, the pixel 11 outputs a pixel signal with a small voltage level as the amount of incident light increases. However, the present invention is not limited to this, and outputs a pixel signal with a large voltage level as the amount of incident light increases. May be. There are M column signal lines L2 corresponding to each column, and each column signal line L2 is connected to each of N pixels arranged in each column.

  The vertical scanning circuit 20 is composed of, for example, a shift register, and cyclically selects the row signal line L3 in the row direction according to the clock signal CLK output from the timing generator 110, and outputs the pixel signal from the pixel 11.

  The ramp signal generation circuit 30 generates a ramp signal according to the clock signal CLK and outputs it to the ramp signal line L1. Here, the ramp signal generation circuit 30 outputs one ramp signal while the vertical scanning circuit 20 selects one row, so that the ramp signal is output in units of rows in synchronization with the vertical scanning circuit 20. Is output. In the present embodiment, the ramp signal employs a waveform that linearly decreases as time elapses. However, the present invention is not limited to this, and a waveform that increases linearly as time elapses may be employed. The GCA / CDS circuit 40 includes a GCA (Gain Control Amp) and a CDS (Correlated Double Sampling) circuit, and removes fixed pattern noise included in the pixel signal.

  There are M comparators 50 corresponding to the respective columns. A pixel signal is input via the column signal line L2, a ramp signal is input via the ramp signal line L1, and the voltage level of the ramp signal is set to the pixel. When the voltage level of the signal is reached, the output signal is changed from the high level to the low level or from the low level to the high level according to the clock signal CLK. Specifically, the comparator 50 has one input terminal connected to the ramp signal generation circuit 30 via the ramp signal line L1, the other input terminal connected to the column signal line L2, and an output terminal connected to the edge detection circuit 60. It is connected to the.

  There are M edge detection circuits 60 corresponding to each column, the edge of the signal output from the comparator 50 is detected according to the clock signal output from the timing generator 110, and the pulse-shaped detection signal is sent to the latch unit 80. Output.

  The counter 70 is composed of a 4-bit counter and performs a counting operation according to the clock signal CLK. Here, the counter 70 is connected to the latch unit 80 via four count signal lines CL1 to CL4 corresponding to the four bits from the least significant bit to the most significant bit. The count signal line CL1 outputs, for example, a count signal having the same cycle as that of the clock signal CLK, the count signal line CL2 outputs, for example, a count signal obtained by dividing the clock signal CLK by 2, and the count signal line CL3 includes, for example, a clock signal The count signal obtained by dividing CLK by 4 is output, and the count signal line CL4 outputs, for example, a count signal obtained by dividing the clock signal by 8.

  The latch unit 80 includes 4M latch circuits 81 arranged in a matrix of 4 rows × M columns corresponding to the four count signal lines CL1 to CL4 and the M column signal lines L2. The latch circuit 81 latches a 1 signal when the count signal output from the counter 70 is high level when the edge detection signal is output from the edge detection circuit 60, and a 0 signal when the count signal is low level. Latch. Accordingly, the 4-bit digital value of the pixel signal output from one pixel 11 in the corresponding column is latched by the four latch circuits 81 in each column. That is, the analog pixel signal output from each pixel 11 is A / D converted by the counter 70 and the latch unit 80 into a 4-bit digital pixel signal.

  There are four sense amplifiers 90 corresponding to each of the four count signal lines CL <b> 1 to CL <b> 4, amplify the signal output from the latch circuit 81, and output the amplified signal to the control unit 300. Here, since the latch circuit 81 outputs a signal having a small voltage amplitude from the viewpoint of energy saving, the sense amplifier 90 amplifies the signal having the small voltage amplitude to thereby obtain a signal of 0 and 1. The difference is obvious. As a result, the control unit 300 can clearly distinguish the 0 signal from the 1 signal.

  The horizontal scanning circuit 100 includes, for example, a shift register, and cyclically selects M column signal lines L2 in the column direction in synchronization with the clock signal CLK, and includes four latch circuits 81 that configure each column. The latched signal is output. The timing generator 110 generates a clock signal CLK and supplies it to the vertical scanning circuit 20, the ramp signal generation circuit 30, the comparator 50, the edge detection circuit 60, the counter 70, the horizontal scanning circuit 100, and the like, and the operation of each of these circuits. Synchronize.

  The control unit 300 includes a CPU, a ROM, a RAM, and the like, and governs overall control of the solid-state imaging device. Further, the control unit 300 corrects the variation in the pixel signal after A / D conversion of each column based on the difference in the slope of the ramp signal input to each comparator 50 due to the wiring length of the ramp signal line L1. I do. Here, the least significant bit of the A / D converted pixel signal input to the control unit 300 is represented as VS [0], the bit one digit higher than VS [0] is represented as VS [1], and VS [1]. 1] is represented by VS [2], and the most significant bit is represented by VS [3]. Details of the processing of the control unit 300 will be described later.

  In FIG. 1, for convenience of explanation, the counter 70 is a 4-bit counter. However, the present invention is not limited to this, and an arbitrary counter of 2 bits or more may be adopted. In this case, if the counter 70 is a 12-bit counter, the number of latch circuits 81 per column is 12, and if the counter 70 is an 8-bit counter, the number of latch circuits 81 per column is 8. As described above, the number of latch circuits in each column may be changed as appropriate according to the number of bits of the counter 70.

  Next, the operation of the solid-state imaging device shown in FIG. 1 will be described. When one row signal line L3 is selected by the vertical scanning circuit 20, each pixel 11 arranged in the selected row outputs a pixel signal to the column signal line L2. The pixel signal of each column output to the column signal line L2 is latched by the latch circuit 81 of each column to be a 4-bit digital pixel signal. Then, the column signal line L2 is sequentially selected by the horizontal scanning circuit 100, and a 4-bit digital pixel signal is sequentially output to the control unit 300 via the sense amplifier 90.

  FIG. 2 is a timing chart showing the operation of the solid-state imaging device when a 2-bit counter is adopted as the counter 70, (a) shows the ramp signal, (b) shows the clock signal CLK input to the comparator 50. (C) shows a signal output from the comparator 50, (d) shows a detection signal output from the edge detection circuit 60, and (e) shows a count value of the counter 70.

  A ramp signal is output from the ramp signal generation circuit 30 at time t0 in FIG. The ramp signal decreases linearly over time. At this time, as shown in FIG. 2E, the counter 70 starts counting the clock signal CLK. At time t1, when the voltage level of the ramp signal reaches the voltage level of the pixel signal output from the pixel 11 as shown in FIG. 2A, the voltage is output by the comparator 50 as shown in FIG. Signal falls from a high level to a low level.

  When the signal output from the comparator 50 falls, a detection signal is output by the edge detection circuit 60 as shown in FIG. Since the two latch circuits 81 corresponding to the columns to which the detection signals are output, as shown in FIG. 2E, the count signal “01” is output from the counter when the detection signals are received. The signal “01” is latched.

  Since the pixel 11 outputs a pixel signal having a lower voltage level as the amount of incident light increases, the time until the voltage level of the ramp signal reaches the voltage level of the pixel signal increases as the amount of incident light increases. The level of the digital pixel signal increases as the amount of incident light increases. In FIG. 2, a ramp signal that descends to the right is used, but a ramp signal that rises to the right may be used. In this case, the level of the digital pixel signal decreases as the amount of incident light increases.

  FIG. 3 is a diagram showing a change in the slope of the ramp signal, where (a) shows the ramp signal line L1, (b) shows the ramp signal, and (c) shows the pixel signal after A / D conversion. The photoelectric conversion characteristics are shown. As shown in FIG. 3A, the ramp signal line L1 has a wiring load composed of a parasitic resistance and a parasitic capacitance. Therefore, as shown by the dotted line in FIG. 3B, the slope and amplitude of the ramp signal decrease with distance from the ramp signal generation circuit 30 that is a signal source. Therefore, even if the amount of incident light is the same, the output timing of the detection signal output from the edge detection circuit 60 is delayed as the column is farther from the ramp signal generation circuit 30. As a result, the photoelectric conversion characteristic indicating the relationship between the level of the pixel signal after A / D conversion and the amount of light incident on the pixel 11 is a column separated from the ramp signal generation circuit 30 as indicated by the dotted line in FIG. As the slope increases, the slope increases. Further, when the amplitude of the ramp signal is reduced, the saturation level of the photoelectric conversion characteristics is also reduced as shown in FIG. Thus, if the waveform of the lamp signal is different, even if the incident light amount is the same, the pixel signal after A / D conversion in each column varies, and the brightness of the output image varies depending on the region. Shading occurs.

  Therefore, in this embodiment, shading appearing in the output image is suppressed by performing correction processing on the digital pixel signal that is the pixel signal after A / D conversion. Here, the control unit 300 detects the inclination (gain) of the ramp signal in each column, obtains a correction value for each column based on the detected inclination, and multiplies the digital pixel signal by this correction value to perform correction processing. I do.

  Specifically, the control unit 300 inputs two DC voltages V1 and V2 having different levels to each column signal line L2, and applies the DC voltages V1 and V2 to the CMOS image sensor in the same manner as when a pixel signal is captured. D conversion is performed to obtain digital DC voltages V1 ′ and V2 ′ in each column. Next, the control unit 300 obtains the slope of the ramp signal of each column by (V1−V2) / (V1′−V2 ′), obtains a correction value for reducing the variation of the pixel signal from these slopes, and stores it in the memory. Remember me. When a pixel signal is input from the CMOS image sensor, the control unit 300 corrects the pixel signal by multiplying the input pixel signal by a column correction value corresponding to the input pixel signal.

  Here, the control unit 300 uses the gradient of the ramp signal of each column as a reference and uses the gradient of the ramp signal of each column as a reference, and the correction value of each column so that the value becomes smaller as the row length is longer. You can ask for.

  Further, the control unit 300 may periodically perform a correction value calculation process. Accordingly, it is possible to flexibly cope with a change in the slope of the lamp signal due to a change in the environmental temperature or the like. Furthermore, the control unit 300 may store correction values for each column obtained in advance through experiments, and perform correction processing using the correction values. Furthermore, the digital pixel signal of each column may be corrected based on the gradient of the ramp signal of a predetermined column other than the maximum or minimum gradient of the ramp signal.

  As described above, according to the present solid-state imaging device, the pixel signals after analog-digital conversion in each column based on the difference in the slope of the ramp signal input to each comparator 50 due to the wiring length of the ramp signal line L1. Since the correction process for reducing the variation of the image is performed, it is possible to suppress the appearance of shading in the output image. In addition, since the correction process is performed digitally, it is possible to accurately suppress the appearance of shading in the output image.

(Embodiment 2)
Next, a solid-state imaging device according to Embodiment 2 of the present invention will be described. FIG. 4 is a block diagram of the solid-state imaging device according to the second embodiment. The solid-state imaging device according to the present embodiment is characterized in that an amplifier circuit 120 (an example of a correction unit) is connected between the comparator 50 and the ramp signal generation circuit 30. In the present embodiment, the same components as those in the first embodiment will not be described, and only differences will be described.

  There are M amplifier circuits 120 shown in FIG. 4 corresponding to the respective columns. Each of the amplifiers 120 is connected to the ramp signal line L1 before the input terminal of the comparator 50, and each comparator is caused by the wiring length of the ramp signal line L1. In order to reduce the variation in the pixel signal after A / D conversion of each column based on the difference in the slope of the ramp signal input to 50, the gain of the ramp signal input to the comparator 50 is adjusted.

  FIG. 5 is a diagram illustrating a connection relationship between the ramp signal generation circuit 30 and the amplifier circuit 120. The resistors and capacitors shown in FIG. 5 indicate the wiring load due to the ramp signal line L1. 5 indicates a point on the ramp signal line L1 closest to the output terminal of the ramp signal generation circuit 30. Further, points B to D indicate points on the ramp signal line L1 closest to the input terminals of the comparators 50 in the first to third columns counting from the left. In FIG. 5, for convenience of explanation, the third column is the final column, but there are actually M columns. Since the point A is located in the immediate vicinity of the output terminal of the ramp signal generation circuit 30, the ramp signal is not affected by the wiring load at the point A and draws a waveform indicated by RA. However, when the wiring lengths of the point B, the point C, the point D and the ramp signal line L1 are increased, the ramp signal at each of the points B to D draws a waveform indicated by RB to RD. It can be seen that the slope of the signal is small.

  Therefore, the amplifier circuit 120 performs a correction to increase the gain so that the ramp signal whose slope has decreased at each point of the ramp signal line L1 has the waveform of the first column indicated by RB, and the slope of the ramp signal of each column is thereby reduced. Keep it constant. Specifically, the amplifier circuit 120 is configured by an inverting amplifier circuit including resistors R1 and R2, and amplifies the ramp signal with a gain determined by the resistors R1 and R2. Here, the gain of the amplifier circuit 120 is based on the column having the maximum or minimum slope of the ramp signal, and a value such that the value becomes larger as the line length is longer using the slope of the ramp signal of each column is adopted. More specifically, the value of the ramp signal to be inputted can be a value that can be changed to a waveform indicated by RB, and a value obtained in advance by experiments may be employed. In FIG. 5, the ramp waveform at each of the points B ′ to D ′ is shown as a down waveform. Specifically, when an inverting amplifier circuit is employed as the amplifier circuit 120, these ramp waveforms become an up waveform. When the forward amplifier circuit is employed, these ramp waveforms are downward waveforms.

  Further, the amplifier circuit 120 employs an amplifier whose gain can be adjusted, and the control unit 300 periodically detects the slope of the ramp signal input to the comparator 50 in each column, and forms the slope in a waveform indicated by RB. Alternatively, the gain of the amplifier circuit 120 in each column may be obtained, and the obtained gain may be set as the gain of the amplifier circuit 120 in each column. In this case, the controller 300 may obtain the slope of the ramp signal in each column in the same manner as in the first embodiment. By periodically setting the gain, it is possible to flexibly cope with changes in pixel signal variations after A / D conversion due to environmental temperature changes.

  In addition, as the amplifying circuit 120 capable of adjusting the gain, a plurality of resistors are connected in parallel to the resistor R1 or R2, and a switch for connecting each resistor connected in parallel to the resistor R1 or R2 is connected to each resistor. In this case, the control unit 300 can adjust the gain of the amplifier circuit 120 by turning on and off these switches.

  As described above, the ramp signal having the RB waveform is output from the points B ′ to D ′ closest to the input terminals of the comparators 50 in the first to third columns, and the slope of the ramp signal input to the comparator 50 in each column is determined. Can be constant. As described above, according to the solid-state imaging device, since the amplifier circuit 120 is connected before the input terminal of the comparator 50 in each column, the variation in pixel signals after A / D conversion is reduced, and the output image is shaded. Appearance can be suppressed.

  In the above description, the ramp signal of each column is matched with the ramp signal of the first column having the maximum inclination. However, the present invention is not limited to this, and the ramp signal of the third column having the minimum inclination of the ramp signal is used. The ramp signals in each column may be combined. Further, the ramp signal of each column may be corrected so that the ramp signal of each column has a predetermined reference waveform. Further, the ramp signal of each column may be corrected so that the ramp signal has a gradient of a predetermined column other than the maximum or minimum.

  In this embodiment, the amplifier circuit 120 is provided for each column as shown in FIG. 4, but the present invention is not limited to this, and the amplifier circuit 120 may be provided for every plurality of columns as shown in FIG. Good. FIG. 6 is a diagram illustrating a connection relationship between the amplifier circuit 120 and the comparator 50 when the amplifier circuit 120 is provided for every two columns. As shown in FIG. 6, the output terminal of the amplifier circuit 120 in the first column is connected to the input terminal of the comparator 50 in the first column and the second column, and the output terminal of the amplifier circuit 120 in the third column is connected to the third column. It can be seen that they are connected to the input terminals of the comparators 50 in the fourth and fourth rows. By doing so, it is possible to reduce the circuit scale while suppressing shading appearing in the output image.

  In this embodiment, the gain of the amplifier circuit 120 shown in FIG. 4 is set to a different value for each column. However, the present invention is not limited to this, and the 1 to M columns are divided into a plurality of blocks. The gain of 120 may be set to the same value. Furthermore, the amplifier circuit 120 is not limited to an inverting amplifier circuit, and may be another amplifier circuit such as a normal amplifier circuit.

(Embodiment 3)
Next, a solid-state imaging device according to Embodiment 3 of the present invention will be described. FIG. 7 is a diagram illustrating a connection relationship between the column signal line L2 and the comparator 50 of the solid-state imaging device according to the third embodiment. The solid-state imaging device according to the present embodiment is characterized in that an amplifier circuit 130 (an example of a correction unit) is connected before the comparator 50 of the column signal line L2. In the present embodiment, the description of the same elements as those in the embodiment will be omitted, and only the differences will be described. Moreover, since the whole structure is the same as Embodiment 1, FIG. 1 is used.

  As shown in FIG. 7, the amplifier circuit 130 includes a switched capacitor amplifier included in the GCA / CDS circuit 40 connected to the upstream side of the comparator 50 in each column signal line.

  The gain of the switched capacitor amplifier is determined by the capacitance ratio of the two capacitors. In the amplifier circuit 130 in the first column from the left in FIG. 7, the gain is connected between the input and output terminals of the capacitor CB connected to the input terminal side. The value divided by the capacitor Co, ie, CB / Co. Therefore, the signal VBo output from the amplifier circuit 130 is represented by VBo = (CB / Co) · VBi, where the input signal is VBi. Further, the signals VCo and VDo output from the amplifier circuits 130 in the second and third columns are VCo = (CC / Co) · VCi, VDo = (CD / Co) · when the input signals are VCi and VDi. Represented as VDi.

  The ramp signal output from the ramp signal generation circuit 30 has a slope that decreases with the wiring load as the distance from the signal source increases as shown by the dotted line in FIG. The slope of becomes smaller. As a result, even when pixel signals of the same level are input to the comparators 50 in the first to third columns, the time until the level of the ramp signal reaches the level of the pixel signal is delayed toward the first to third columns. The output timing of the detection signal output from the edge detection circuit 60 is delayed, and the value of the pixel signal after A / D conversion increases. Therefore, the amplifier circuit 130 adjusts the gain of the input pixel signal so that the variation in the pixel signal after A / D conversion due to the difference in the slope of the ramp signal is reduced.

  Here, the gain of the amplifier circuit 130 is obtained in advance by experiment to obtain a value that reduces variation in pixel signals after A / D conversion in each column, with reference to the column having the maximum or minimum slope of the ramp signal. A value may be adopted.

  Further, the amplifier circuit 130 employs an amplifier whose gain can be adjusted, and the control unit 300 detects the slope of the ramp signal in each column in the same manner as in the first embodiment, and uses the detected slope to The gain of the amplifier circuit 130 in each column may be obtained so as to reduce variation in pixel signals after A / D conversion of the column. In this case, the control unit 300 may perform the gain setting process of the amplifier circuit 130 periodically. As a result, it is possible to flexibly cope with variations in pixel signal variations after A / D conversion due to changes in the slope of the ramp signal due to changes in the environmental temperature or the like.

  Specifically, since the slope of the ramp signal becomes smaller toward the first to third columns, the first to third columns are used in order to reduce variations in pixel signals after A / D conversion due to this slope. The values of CB, CC, and CD are set so that the gain of the amplifier circuit 130 decreases as it goes, that is, the values of CB, CC, and CD may be set so that CD <CC <CB.

  As an example of the amplifier circuit 130 whose gain can be adjusted, the amplifier circuit 130 in the first column will be described as an example. A plurality of capacitors are connected in parallel to the capacitor CB or the capacitor Co, and each capacitor connected in parallel is connected. What is necessary is just to employ | adopt what connected the switch for connecting in parallel with CB or Co to each capacitor, and in this case, the control part 300 adjusts the gain of the amplifier circuit 130 by turning on / off these switches. be able to.

  As described above, according to the solid-state imaging device, the gain of the pixel signal is adjusted by the amplifier circuit 130 so that the variation in the pixel signal after A / D conversion based on the difference in the slope of the ramp signal of each column is reduced. Output to the comparator 50, shading can be prevented from appearing in the output image.

  Although a switched capacitor amplifier is used as the amplifier circuit 130, the present invention is not limited to this, and an amplifier circuit made of a resistor as shown in the second embodiment may be used. Further, although the amplifier circuit 130 is included in the GCA / CDS circuit 40, it may be provided separately from the GCA / CDS circuit 40.

  In the first to third embodiments, one ramp signal generation circuit 30 is used. However, the present invention is not limited to this, and a plurality of ramp signal generation circuits 30 may be provided. In this case, a total of two ramp generation circuits, that is, a ramp signal generation circuit that outputs a ramp signal to an odd-numbered column and a ramp signal generation circuit that outputs a ramp signal to an even-numbered column may be provided. A total of two ramp signal generation circuits for generating a ramp signal may be provided in the right half column, or a plurality of ramp signal generation circuits for dividing each column into a plurality of blocks and generating a ramp signal in each block. May be provided.

1 is a block diagram of a solid-state imaging device according to Embodiment 1 of the present invention. It is a timing chart which shows operation | movement of a solid-state imaging device when a 2-bit counter is employ | adopted. It is the figure which showed the change of the inclination of a ramp signal. FIG. 3 shows a block diagram of a solid-state imaging device according to a second embodiment. It is the figure which showed the connection relation of a ramp signal generation circuit and an amplifier circuit. It is the figure which showed the connection relation of the amplifier circuit at the time of providing an amplifier circuit for every 2 columns, and a comparator. 6 is a diagram illustrating a connection relationship between a column signal line and a comparator of a solid-state imaging device according to Embodiment 3. FIG.

Explanation of symbols

10 pixel section 11 pixel 20 vertical scanning circuit 30 ramp signal generation circuit 40 GCA / CDS circuit 50 comparator 60 edge detection circuit 70 counter 80 latch section 81 latch circuit 90 sense amplifier 100 horizontal scanning circuit 110 timing generator 120 amplification circuit 130 amplification circuit 300 Controllers CL1 to CL4 Count signal line L1 Ramp signal line L2 Column signal line L3 Row signal line

Claims (10)

A solid-state imaging device of a column parallel A / D conversion method,
A pixel unit that includes a plurality of pixels arranged in N (N is an integer of 1 or more) rows × M (M is an integer of 2 or more) columns, and outputs pixel signals to M column signal lines corresponding to each column. When,
A ramp signal generation unit that generates a ramp signal and outputs the ramp signal to the ramp signal line;
The pixel signal is input via the column signal line, and the ramp signal is input via the ramp signal line, and a detection signal is output when the level of the ramp signal reaches the level of the pixel signal. M comparison units corresponding to each column to be
A / D conversion for analog-digital conversion of the pixel signal by counting the time from when the ramp signal generation unit starts outputting the ramp signal to when the detection signal is output by each comparison unit And
A correction unit that performs correction processing to reduce variations in pixel signals after analog-digital conversion in each column based on a difference in slope of the ramp signal input to each comparison unit due to the wiring length of the ramp signal line. A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the correction unit performs the correction processing with reference to a column having a maximum or minimum slope of the ramp signal.   The solid-state imaging device according to claim 1, wherein the correction unit performs the correction process on the pixel signal after analog-digital conversion.   The solid-state imaging device according to claim 1, wherein the correction unit performs the correction process by adjusting a gain of a pixel signal input to each comparison unit.   5. The solid-state imaging device according to claim 4, wherein the correction unit includes M amplifier circuits connected in front of each comparison unit in each column signal line.   The solid-state imaging device according to claim 5, wherein the gain has a different value for each column or for each of a plurality of columns.   The solid-state imaging apparatus according to claim 1, wherein the correction unit performs the correction process by adjusting a gain of a ramp signal input to each comparison unit.   The solid-state imaging device according to claim 7, wherein the correction unit includes an amplifier circuit connected between the ramp signal generation unit and the comparison unit.   The solid-state imaging device according to claim 8, wherein the amplifier circuit is provided for each column or for each of a plurality of columns.   The said correction | amendment part detects the variation | change_quantity of the inclination of each row | line | column of a ramp signal regularly, and calculates | requires the correction value used for the said correction process based on a detection result. The solid-state imaging device described in 1.

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