JP2011160046A - Solid-state imaging apparatus and method for driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide sunspot correction and voltage drop prevention during a row selection blank period without expanding a circuit scale as much as possible with a simple circuit configuration. <P>SOLUTION: One set of voltage output circuits as a sunspot correction/voltage drop prevention circuit is provided in an image sensor, and the voltage output circuits apply a prescribed voltage value to a column signal line. The application period of the prescribed voltage value is a period from timing that corresponds to the end of an output of a row selection signal for selecting a previous row to timing that corresponds to the end of a period for resetting a pixel during selecting the next row. Consequently, only one set of voltage output circuits achieves both the sunspot correction and the voltage drop prevention during the row selection blank period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a driving method thereof, and more particularly to a solid-state imaging device having a sunspot correction function and a function of preventing a voltage drop of a pixel signal during a row selection pause period and a driving method thereof.

  An imaging apparatus such as a digital still camera or a video camera includes an image sensor (solid-state imaging apparatus) that converts imaging light into an electrical signal. As such an image sensor, for example, a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor are known.

  In these image sensors, pixels arranged in a matrix are driven so as to scan in the row / column direction at appropriate timing, and signals corresponding to the amount of received light are sequentially read from the pixels, and video signals are read out. obtain.

  However, in the image sensor, due to the structure of the pixel circuit, when the pixel is irradiated with very strong light such as sunlight, on the contrary, the brightest part of the image changes to black. Is known to occur. Such a phenomenon is also referred to as a sunspot or the like because, for example, when the sun is photographed, the above-described portion that has turned black appears to be a sunspot. This sunspot is not supposed to be seen originally and leads to a reduction in the quality of the captured image. As a technique for avoiding the generation of such sunspots, for example, the following is known. That is, a potential obtained at a signal output node common to a plurality of pixel portions in a reset state is held, and a potential fed back to the signal output node based on the held potential is clipped to a predetermined potential (for example, (See Patent Document 1).

Japanese Patent Laying-Open No. 2005-57612 (FIG. 3)

  As a pixel of an image sensor, for example, a row selection transistor is omitted, and a so-called three-transistor configuration formed by including three transistors of a transfer transistor, a reset transistor, and an amplification transistor is known. In this three-transistor configuration, it is necessary to provide a pause period at the timing of switching the row to be selected for the row selection signal output for sequentially selecting the rows of pixels. However, the row selection signal is not applied to the pixels in any row during this pause period. For this reason, in the actual pause period, a voltage drop of the column signal line from which the pixel signal is read out is caused, which may cause a decrease in the frame rate, for example.

  Therefore, the present invention, for example, in addition to the previous sunspot correction, in order to improve the quality and performance as a solid-state imaging device by preventing the voltage drop that occurs in the pause period of the row selection signal output described above, The object is to realize this with the simplest possible configuration.

  The present invention has been made to solve the above problems, and a first aspect of the present invention is that a row selection is sequentially performed for a pixel array in which pixels are arranged in a matrix and for each row in the pixel array. A pause period of a predetermined time length is set between the output of the signal and the output of the row selection signal for selecting one row to the start of the output of the row selection signal for selecting the next row. Corresponding to each column of the pixel array, and connected in common to the pixels of the corresponding column, and the row selected by the row selection unit is connected among the connected pixels. A column signal line for outputting the potential obtained at the pixel, a reset means for resetting the potential output to the column signal line during the period in which the row selection signal is output, and the row selection signal being output During the After the reset of the potential by the gate means, the light receiving signal output means for outputting the potential obtained by receiving the pixel selected by the row selection signal to the column signal line, and the column signal line On the other hand, the voltage application means for applying a predetermined voltage value and the voltage application means during the period from the end of the output of the row selection signal for selecting one row to the end of the resetting of the potential. A solid-state imaging device comprising: timing control means for controlling the predetermined voltage value to be applied to the column signal line. As a result, the voltage is continuously applied to the column signal line from the rest period to the period when the potential is reset by the resetting means.

  In the first aspect, the voltage application unit performs an operation of applying the predetermined voltage value when a timing signal is output from the timing control unit, and the timing control unit The timing signal may be output in a period from the end of outputting the row selection signal for selecting a row to the end of the potential reset period. As a result, there is an effect that the timing control means sets the timing for applying the voltage to the column signal line by the output of the timing signal.

  Further, according to the first aspect, one set of voltage output means for outputting a predetermined voltage value and one set corresponding to each column signal line are provided, and according to the predetermined voltage value output from the voltage output means. Column corresponding voltage applying means for applying the amplified output to the corresponding column signal line. This brings about the effect that a voltage is simultaneously applied to a plurality of column signal lines from one voltage output means.

  In the first aspect, the voltage output means may be configured to change the predetermined voltage value to be output according to a setting. This brings about the effect that the potential clamped by the column signal line is changed by changing the predetermined voltage value according to the setting.

  According to the present invention, the sun drop correction and the voltage drop of the column signal line during the rest period of the row selection signal output are eliminated, and a higher quality and higher performance solid-state imaging device can be obtained. Further, since the configuration for this is very simple, it is possible to avoid an increase in circuit scale.

It is a figure which shows the structural example (1st structural example) of the image sensor 100 used as the basis of embodiment of this invention. 3 is an equivalent circuit diagram illustrating a configuration example of a pixel 111. FIG. It is a timing chart which shows the basic operation example of the image sensor 100 when not performing sunspot correction. It is a timing chart which shows the operation example of the image sensor 100 at the time of performing sunspot correction. 5 is a timing chart illustrating an operation example of the image sensor 100 from the viewpoint of occurrence of a voltage drop in a row selection blank period. It is a timing chart which shows the operation example of the image sensor 100 according to actual operation | movement which combined generation | occurrence | production of the voltage drop of a row selection blank period, and sunspot correction. It is a figure which shows the structural example (2nd structural example) of image sensor 100A used as the basis of embodiment of this invention. It is a figure which shows the structural example of the image sensor 100B in embodiment of this invention. 3 is a circuit diagram showing a configuration example of a sunspot correction / voltage drop prevention circuit 240. FIG. It is a timing chart which shows the operation example of the image sensor 100B in embodiment of this invention.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (image sensor: an example in which a sunspot correction circuit and a voltage drop prevention circuit are integrated)
2. Modified example

<1. First Embodiment>
[Configuration Example of Image Sensor as a Base of the Embodiment of the Present Invention]
FIG. 1 shows a configuration example of an image sensor (solid-state imaging device) that is a basis of an embodiment of the present invention. In general, examples of an element employed in an image sensor include a charge coupled device (CCD) sensor and a complementary metal oxide semiconductor (CMOS) sensor. In the embodiment of the present invention, it is assumed that a CMOS sensor is employed.

  The image sensor 100 shown in FIG. 1 includes a pixel array 110, a row scanning circuit 120, a column ADC unit 130, a reference signal generation circuit 150, a timing control circuit 160, a column scanning circuit 170, a buffer amplifier 180, and a data output line 190. Further, the solar cell dot correction circuit 200 and the column unit voltage application circuits 210-1 to 210-3 corresponding to the column signal lines 113-1 to 113-3 are provided.

  The pixel array 110 is formed on, for example, a single chip (semiconductor substrate). However, the above-described portions, circuits, and the like other than the pixel array 110 shown in FIG. 1 are also integrated on the same chip as the pixel array 110. Formed.

  In the pixel array 110, a large number of pixels 111 are arranged in a matrix (matrix) with n rows × m columns. In this figure, an aspect in which six pixels 111 of 2 rows × 3 columns (n = 2, m = 3) are arranged is shown, but this is for convenience of explaining the illustration. Actually, a large number of pixels 111 of, for example, several million or more are arranged in a matrix.

  In the arrangement of the pixels 111 in the row direction in the pixel array 110, that is, in the horizontal direction, first, for each of the three pixels 111 arranged in the first row, a row signal line 112 drawn from the row scanning circuit 120. -1 is connected. For example, the row signal line 112-1 actually includes a set of three signal lines corresponding to each of the row selection signal SEL1, the reset signal RST1, and the transfer gate signal TRG1, as illustrated. Similarly, the row signal line 112-2 led out from the row scanning circuit 120 is connected to each of the pixels 111 arranged in the next second row. The row signal line 112-2 also includes a set of three signal lines corresponding to the row selection signal SEL2, the reset signal RST2, and the transfer gate signal TRG2.

  The row scanning circuit 120 is formed by, for example, a shift register or a decoder, and sequentially scans the pixel array 110 row by row. The row scanning circuit 120 receives, for example, a row selection signal SEL, a reset signal RST, and a transfer gate signal TRG sequentially from each of the row signal lines 112-1 to 112-n corresponding to each horizontal scanning period at a predetermined timing described later. Output. Accordingly, for example, the first row to the last row are sequentially scanned corresponding to one frame period. That is, row sequential scanning is performed in which scanning is performed in units of rows in the vertical direction. The signal output timing from the row scanning circuit 120 is set under the control of the timing control circuit 160.

  In the array of pixels 111 in the column (vertical) direction in the pixel array 110, a column (vertical) signal line 113-1 is commonly connected to each of the pixels 111 arranged in the first column. Similarly, in the remaining second column and third column, column signal lines 113-2 and 113-3 are commonly connected to the pixels 111 arranged in each column. One end of each of the column signal lines 113-1 to 113-1 is branched into two, and one branch is connected to the ground via the current source IS. The other branch is connected to one input terminal of each of the comparators 141-1 to 141-1.

  The column ADC unit 130 is provided to convert analog pixel signals output from the column signal lines 113-1 to 113-m into digital signals (imaging signal data) and output the signals. The column ADC unit 130 includes m unit ADCs 140-1 to 140-m corresponding to m column signal lines, that is, corresponding to the number m of columns forming the pixel array. In this figure, three unit ADCs 140-1 to 140-3 are shown corresponding to the three column signal lines 113-1 to 113-3.

  The unit ADC 140-1 includes a comparator 141-1 and a counter 142-1. A column signal line 113-1 corresponding to the first column is connected to one input terminal of the comparator 141-1. That is, the pixel signal Vx from the pixel 111 in the row selected by the row scanning of the row scanning circuit 120 among the pixels 111 connected to the column signal line 113-1 is connected to one input terminal of the comparator 141-1. Is entered. Further, a reference signal RAMP output from a reference signal generation circuit 150 described later is input to the other input terminal of the comparator 141-1. The comparator 141-1 outputs to the counter 142-1 a signal whose level is inverted according to the magnitude relationship between the pixel signal Vx input as described above and the reference signal RAMP.

  The counter 142-1 is configured as an up / down counter that can be executed by switching between an up-count operation and a down-count operation, for example. For example, the counter 142-1 performs a count operation at a count cycle corresponding to a clock input from the timing control circuit 160. The counter 142-1 starts up-counting and down-counting at a timing according to the control of the timing control circuit 160. Further, the end of the up count and the down count is set according to the timing at which the output of the comparator 141-1 is inverted. The counter 142-1 has a function of latching the count value obtained by the up-count operation and the down-count operation. The counter 142-1 of the unit ADC 140-1 outputs the latched count value to the data output line 190.

  The unit ADC 140-2 and the unit ADC 140-3 corresponding to the remaining second column and third column also include a comparator 141-2 and a counter 142-2, and a comparator 141-3 and a counter 142-3, respectively. The comparator 141-2 and the comparator 141-3 have the same configuration as the comparator 141-1, and the counter 142-2 and the counter 142-3 have the same configuration as the counter 142-1.

  As described above, the column ADC unit 130 includes m unit ADCs 140-1 to 140-m corresponding to the first to m-th columns in the pixel array of the pixel array 110, and for example, the reference signal RAMP. The signal line is connected in parallel, and the column parallel form is adopted.

  The column scanning circuit 170 is formed by, for example, a shift register or a decoder similarly to the row scanning circuit 120, and performs scanning corresponding to each column. This column scanning circuit 170 has units ADCs 140-1 to 140-m (m = 3 in correspondence with the figure) counters 142-1 to 142-m at timing according to the column scanning timing signal output from the timing control circuit 160. A column scanning signal is output in the order. Thereby, column sequential scanning is performed. That is, an operation of scanning the pixels in the selected row in the horizontal direction is performed. The latched count values are output to the data output line 190 in the order of counters 142-1 to 142-m in accordance with the timing at which this column sequential scanning is performed. The count value is expressed by a predetermined number N of bits. The count value of the number of bits N output in this way becomes image signal data obtained by converting the pixel signal Vx into a digital format. The imaging signal data is output to the outside of the image sensor 100 via the buffer amplifier 180, and is captured by, for example, a video signal processing unit not shown here to generate image data.

  For example, the timing control circuit 160 receives a master clock (not shown) from the outside of the image sensor 100 and generates a required clock, timing signal, and the like based on the master clock. The clock and timing signal generated in this way are output to appropriate parts in the image sensor 100, and the operation timing of each part is determined.

  The reference signal generation circuit 150 generates a reference signal RAMP having a ramp waveform with a predetermined slope at a timing described later, for example, according to the timing control of the timing control circuit 160. Then, the reference signal RAMP is output to the other input terminal of each of the comparators 141-1 to 141-m in the unit ADCs 140-1 to 140-m.

  The sunspot correction circuit 200 and the column unit voltage application circuit 210 (210-1 to m) are circuit units that are provided in order to eliminate a phenomenon called a sunspot described later. The sunspot correction circuit 200 outputs a preset predetermined voltage value in common to the column unit voltage application circuits 210-1 to 210-m at a timing according to the timing signal PCSUNEN output from the timing control circuit 160. . The column unit voltage application circuits 210-1 to 210-m are each provided with an on / off setting transistor TR11 and a voltage application transistor TR12 for each of the column signal lines 113-1 to 113-m.

  The drain of the on / off setting transistor TR11 is connected to the power supply voltage Vdd, and the source thereof is connected to the drain of the voltage application transistor TR12. The source of the voltage application transistor TR12 is connected to the corresponding column signal line 113.

  For example, an on / off setting signal output from the row scanning circuit 120 is commonly connected to the gates of the on / off setting transistors TR11 corresponding to the column signal lines 113-1 to 113-m. The voltage value output from the sunspot correction circuit 200 is commonly applied to the gates of the voltage application transistors TR12 corresponding to the column signal lines 113-1 to 113-m.

  When the sunspot correction function is enabled, an on / off setting signal for turning on / off setting transistor TR11 is output from row scanning circuit 120, and power supply voltage Vdd is applied to voltage application transistor TR12. It becomes. At this time, a gate voltage having a preset voltage value is applied from the sunspot correction circuit 200 to the gate of the voltage application transistor TR12. Thus, a voltage obtained by the voltage application transistor TR12 performing an amplification operation according to the gate voltage is applied to the corresponding column signal line 113. As a result, the column signal line 113 is clamped at a predetermined potential. The operation of clamping the column signal line 113 at a predetermined potential is the operation of correcting sunspots as will be described later.

  For example, there are cases where it is desired to disable the sunspot correction function in order to evaluate the image sensor 100 or the like. Further, depending on the operation mode, it may not be necessary to perform sunspot correction. In such a case, an on / off setting signal for turning off the on / off setting transistor TR11 is output from the row scanning circuit 120, and the supply of the power supply voltage Vdd to the voltage application transistor TR12 is stopped. As a result, no voltage is applied from the voltage application transistor TR12 to the column signal line 113, and the sunspot correction function is disabled.

[Example of pixel structure]
FIG. 2 shows a structural example of the pixel 111 by an equivalent circuit thereof. A pixel 111 shown in this figure includes a photodiode PD, a transfer transistor TR1, a reset transistor TR2, and an amplification transistor TR3.

  The photodiode PD is a portion where photoelectric conversion is performed, and a current corresponding to the amount of received light flows. The anode of the photodiode PD is connected to the ground, and the cathode is connected to the drain of the transfer transistor TR1. A signal line for the transfer gate signal TRG is connected to the gate of the transfer transistor TR1. The source of the transfer transistor TR1 is connected to the connection point between the source of the reset transistor TR2 and the gate of the amplification transistor TR3. This connection point is formed as a floating diffusion FD which is a capacitor for accumulating signal charges. Further, the signal line of the row selection signal SEL is connected to the drain of the reset transistor TR2, and the signal line of the reset signal RST is connected to the gate thereof. The drain of the amplification transistor TR3 is connected to the power supply voltage Vdd, and the source thereof is connected to the column signal line 113. The amplification transistor TR3 amplifies the potential obtained in the floating diffusion FD and outputs it to the column signal line 113.

[Operation example of image sensor]
The timing chart of FIG. 3 shows an operation example of the image sensor 100 having the configuration shown in FIGS. 3 shows the case where the sunspot correction operation by the sunspot correction circuit 200 and the column unit voltage application circuit 210 (210-1 to m) is disabled for convenience of explaining the most basic operation of the image sensor 100. An example of the operation is shown.

  In this figure, the period from the time t0 when the pulse of the horizontal synchronization signal HSYNC rises to the time t6 until the next pulse of the horizontal synchronization signal HSYNC rises is the first row scanning period. The first row scanning period is one horizontal scanning period corresponding to the first row of pixels 111 in the pixel array 110 of FIG.

  In the first row scanning period, first, the row scanning circuit 120 raises the row selection signal SEL1 to the H level and applies a voltage to the drain of the reset transistor TR2 at time t1 that is timing immediately after time t0. At the same time t1, an H level reset pulse is output as the reset signal RST1, and a gate voltage is applied to the reset transistor TR1. As a result, the reset transistor TR1 is turned on in the reset pulse output period from time t1 to time t2, and applies a voltage to the gate of the amplification transistor TR3, that is, the floating diffusion FD. By applying the voltage during the period from the time point t1 to the time point t2, the potential obtained by the charge accumulated in the floating diffusion FD becomes the reset level. This reset level is stabilized after, for example, time t2 after the reset pulse is output, and is held until time t3 when the transfer gate signal TRG1 is output. Accordingly, in the first row scanning period, the period from the time point t1 to t3 is a reset period. In this reset period, the amplification transistor TR3 amplifies the potential of the reset level and outputs it to the column signal line 113. Note that the ideal reset level obtained after time t2 is, for example, indicated by a wavy line in the pixel signal Vx.

  Next, at time t3, the row scanning circuit 120 outputs a gate pulse as the transfer gate signal TRG1. By applying the gate pulse, the transfer transistor TR1 is turned on, and a current corresponding to the charge accumulated according to the amount of light received by the photodiode PD flows. As a result, a potential corresponding to the amount of received light is generated in the floating diffusion FD, and the pixel signal Vx obtained on the corresponding column signal line 113 also changes from the previous reset potential to a potential corresponding to the amount of received light. . The period in which the potential corresponding to the amount of received light is output to the column signal line 113, that is, the signal output period is continued until, for example, time t4.

  When the signal output period ends at time t4, a reset pulse as the reset signal RST1 is output again during the period from time t4 to time t5. The row selection signal SEL1 is switched to the L level at time t4-1 when the reset pulse rises to the H level. Thereby, at time t4-1, the potential of the floating diffusion FD, that is, the gate voltage of the amplification transistor TR3 is initialized to the L level.

  Here, the operation of the unit ADC 140 corresponding to the first row scanning period will be described. First, the reference signal generation circuit 150, as the reference signal RAMP, is a ramp that decays with a certain slope from the initial level, for example, corresponding to each of a period from time t2 to t3 and a predetermined period from time t3 to t4. Generate a waveform. That is, in one row scanning period, the reference signal RAMP having a ramp waveform corresponding to each of the reset period and the signal output period is generated.

On the other hand, in the unit ADC 140, the counter 142 starts down-counting at a timing corresponding to the time point t2, for example. And until the time t3,
It is assumed that the ramp waveform of the reference signal RAMP is smaller than the pixel signal Vx and the output of the comparator 141 is inverted. The counter 142 stops down-counting at a timing according to this, and holds the count value at that time.

  Next, the counter 142 starts up-counting from the count value held by the previous down-counting at a timing when the pixel signal Vx may be considered to have stabilized at the signal level after a lapse of a predetermined time from the time point t3. Until the time point t4, the up-count is stopped at the timing when the ramp waveform of the reference signal RAMP becomes smaller than the pixel signal Vx and the output of the comparator 141 is inverted, and the count value at that time is held. . The count value held at this time is treated as a signal level corresponding to the amount of received light converted to a digital value.

  Then, the A / D conversion operation for obtaining the count value by using both the down-counting and the up-counting as described above is a CDS (Correlated Double Sampling) operation. Depending on the operation of this CDS, it can be considered that the total level composed of the signal component and the reset component corresponding to the amount of received light is obtained, and the reset component is subtracted from this total level. The reset component includes, for example, an offset component of the unit ADC 140 and a fluctuation component due to variations in the pixels 111. Therefore, the pixel signal level subjected to A / D conversion by the unit ADC 140 has a value faithful to the received light amount in which the offset component and the fluctuation component are canceled.

  The period from time t6 to t12 when the next horizontal synchronization signal HSYNC is obtained is the second row scanning period. In the second row scanning period, the row selection signal SEL2, the reset signal RST2, and the transfer gate signal TRG2 are output at the same timings as the time points t1 to t5 in the previous first row scanning period at time points t7 to t11. . Thereby, the same operation as that in the case of the first row is obtained corresponding to each pixel of each column forming the second row.

[About sunspot phenomenon]
By the way, it is known that a phenomenon called “sun sunspot” occurs in the image sensor of FIG. 1 having a pixel structure as shown in FIG. For example, it is assumed that the pixel 111 is irradiated with very strong light by directly capturing sunlight or the like. Then, not only a normal charge according to the reset level and the current from the photodiode PD, but also an unnecessary photoelectric conversion phenomenon occurs in a structural part other than the photodiode PD. Then, the electric charge generated by this unnecessary photoelectric conversion is output from the floating diffusion FD to leak to the column signal line 113 through the amplification transistor TR3. As a result, for example, a phenomenon occurs in which the potential that appears as the pixel signal Vx of the column signal line 113 temporarily drops during the period T1 in FIG.

  A period T1 in FIG. 3 is a period included in the reset period, for example. Then, as described above, the pixel signal Vx in the period T1 ideally maintains a level as indicated by a wavy line. However, when intense light is irradiated as described above, the level of the pixel signal Vx in the period T1 in FIG. 3 decreases to the same level as the signal output period after the time point t3, for example, as shown by the solid line. To do.

  When the level difference between the reset component in the reset period and the signal component in the signal output period becomes small in this way, in the A / D conversion operation by CDS of the ADC unit 130, imaging signal data at a very small level is output. It will be. In an image generated using this imaging signal data, for example, it appears as if there are black spots in the captured sun. Therefore, such a phenomenon is called a sunspot.

[Example of sunspot correction operation]
In the image sensor 100 shown in FIG. 1, a sunspot correction circuit 200 and column unit voltage application circuits 210-1 to 210-m are provided in order to prevent the above-described sunspot phenomenon. The timing chart of FIG. 4 shows a case where a sunspot correction operation is given to the basic operation shown in FIG.

  In FIG. 4, the timings of the horizontal synchronization signal HSYNC, row selection signals SEL1, SEL2, reset signals RST1, RST2, and transfer gate signals TRG1, TRG2 are the same as in FIG. In addition, FIG. 4 shows a timing signal PCSUNEN.

  The sunspot correction circuit 200 is configured to output a predetermined voltage value when the timing signal PCSUNEN is at the H level. For example, in the first row scanning period, the timing signal PCSUNEN in FIG. 4 is at the H level during the period from the time point t0 to t3-1. That is, it is at the H level in the period from immediately before the start time t0 of the reset period to immediately after the end time t3. That is, the timing signal PCSUNEN is output during a period in which the reset period is reliably included.

  By outputting the timing signal PCSUNEN as described above, a constant voltage is applied to the column signal line 113 in the period from time t0 to t3-1 including the reset period (time t1 to t3). It will be. As a result, for example, when the potential becomes stable at time t2 after a certain time has elapsed from time t1, the reset potential in the column signal line 113 is controlled to be clamped at a predetermined level. The clamp level at this time is set by the output voltage of the sunspot correction circuit 200, that is, the value of the voltage applied to the gate of the voltage application transistor TR12. As a result, the pixel signal Vx in the period T1 (time t2 to t3) can maintain an appropriate reset level as shown in FIG. In the second row scanning period, an appropriate reset level is similarly applied in the period T1 from the time point t8 to the time point t9 in response to the output of the H-level timing signal PCSUNEN over the period from the time point t6 to the time t9-1. Can be obtained.

  By operating the sunspot correction circuit 200 in this manner, the level of the pixel signal Vx does not decrease in the period T1 even when the pixel 111 is irradiated with strong light, and an appropriate reset level can be maintained. it can. As a result, each unit ADC 140 can output imaging signal data at a normal level. That is, even if sunlight is photographed, for example, the sunspot phenomenon can be prevented from appearing in the photographed image.

[Voltage drop of image signal during row selection blank period]
As shown in FIG. 2, the pixel 111 has a so-called three-transistor configuration. That is, the pixel 111 includes three transistors, that is, a transfer transistor TR1, a reset transistor TR2, and an amplification transistor TR3. As a configuration other than three transistors, a four-transistor configuration including a row selection transistor for selecting a pixel corresponding to a row unit, for example, in addition to a transfer transistor, a reset transistor, and an amplification transistor is also known. Yes.

  In the three-transistor configuration as shown in FIG. 2, it is necessary to avoid that the row selection timing is duplicated between the previous row and the subsequent row, for example. In order to guarantee that this overlap does not occur, a pause period (row selection blank period) is set between the row selection signal corresponding to one row and the row selection signal corresponding to the next row following this. is doing. Specifically, for example, in the timing charts of FIGS. 3 and 4, the row selection signal SEL1 for selecting the first row falls from the H level to the L level at time t4-1. Next, the row selection signal SEL2 for selecting the second row rises to the H level at the time t7 when the time indicated as the period T2 has elapsed from the time t4-1. A period from time t4-1 to t7 when the output of the row selection signal is in the L level is a row selection blank period T2.

  In the timing charts of FIG. 3 and FIG. 4 described above, for the sake of convenience in explaining the basic operation of the image sensor 100 and the sunspot correction operation, the malfunction of the operation that occurs in response to the setting of the row selection blank period T2 is described. Was not shown. However, in reality, the presence of the row selection blank period T2 causes an undesirable operation of lowering the voltage of the column signal line 113.

  With reference to the timing chart of FIG. 5, the operation of the voltage drop corresponding to the row selection blank period T2 will be described. In FIG. 5, for the sake of convenience of explaining the operation corresponding to the row selection blank period, the operation when the sunspot correction is not performed is shown.

  As understood from the description of the operation of the pixel 111 so far, in the row selection blank period T2, the row selection signal SEL is not applied to the pixels in any row in the pixel array 110, and accordingly, the reset transistor TR2 Is turned off. Further, since the transfer gate signal TRG is also at the L level at this time, the transfer transistor TR1 is also in the off state. Therefore, no signal is output from the pixel 111 in any row to the column signal line 113 in the row selection blank period T2.

  Therefore, in the actual row selection blank period T2, the current source IS connected to the column signal line 113 draws current, and as a result, the row selection blank period T2 in FIG. 5 (time points t2 to t7). As shown, the potential of the pixel signal Vx drops. Here, the potential difference between the original voltage value of the pixel signal Vx and the actually dropped voltage is represented by ΔVd.

  For example, at the time t7 when the row selection signal SEL2 rises to the H level in the second row scanning period, the pixel signal Vx substantially maintains the level before the time t4 as shown in FIGS. Need to be. However, if a voltage drop occurs during the row selection blank period T2 (time points t2 to t7) in FIG. 5, in fact, when the time point t7 is reached, the required level cannot be restored. FIG. 5 shows a state in which, for example, the state has returned to the required level at time t7-1 after a period T3 has elapsed from time t7. For this reason, for example, in the row scanning period after the second row, it is necessary to set the pixel driving timing in consideration of the voltage drop due to the row selection blank period T2 and the time required to recover the dropped voltage.

  Specifically, in the case of FIG. 5, the reset pulse of the reset signal RST2 is output at time t7-1 in the second row scanning period. Note that the time point t7-1 is the timing when the period T3 has elapsed from the time point t7 when the row selection signal SEL2 rises to the H level. Then, the gate pulse of the transfer gate signal TRG2 is raised at time t9 when the period T11 has elapsed from time t7-1. Further, when reaching the time point t10 after the passage of the period T12 from the time point t9, the reset pulse of the reset signal RST2 is output again over the period from the time point t10 to the time point t11. Further, the row selection signal SEL2 is inverted to the L level during the period from the time point t10 to the time point t11.

  Here, the above-described period T11 is the same period in each row scanning period as a period from the output start time of the reset pulse of the reset signal RST corresponding to the reset period to the output start time of the gate pulse of the transfer gate signal TRG. The length is set. Similarly, in the period T12, the same time length is set in each row scanning period as a period from the start of the pulse output of the transfer gate signal TRG to the start of the output of the second reset pulse. In addition, since the period T3 is set, the second row scanning period is set longer than the first row scanning period by a time corresponding to the period T3. Such extension setting of the row scanning period should be performed for each of the row scanning periods from the second row to the last row in one frame period. As a result, the time of one frame period is also extended accordingly, which leads to a decrease in the frame rate, for example.

  The timing chart of FIG. 6 shows an operation when the sun delay correction shown in FIG. 4 is combined with the timing delay caused by the voltage drop in the row selection blank period shown in FIG. As shown in this figure, in the second row scanning period, the timing signal PCSUNEN is output at the H level during the period from the time point t6 to t9-1. Thus, for example, an appropriate reset level is maintained as the pixel signal Vx in the period T1 corresponding to the time points t8 to t9. However, in the row selection blank period corresponding to the times t4-1 to t7, the pixel signal Vx drops due to the potential difference of ΔVd. For this reason, it is necessary to set a period T3 for waiting until the pixel signal Vx returns to the required level. As a result, the second row scanning period is equal to the time period T3 than the first row scanning period. Must be set longer.

[Configuration example of image sensor for preventing voltage drop during row selection blank period]
FIG. 7 shows a configuration example of the image sensor 100A for preventing the voltage drop of the pixel signal Vx in the row selection blank period T2 as described above. In this figure, the same parts as those in FIG.

  For the image sensor 100A shown in FIG. 7, a voltage drop prevention circuit 220 is added as an external circuit, for example. In addition, in the image sensor 100A, in correspondence with the provision of the voltage drop prevention circuit 220, column unit voltage application circuits 230-1 to 230-m (m = 3 in correspondence with the drawing) are added. Similarly to the column unit voltage application circuit 210, the column unit voltage application circuits 230-1 to 230-m are circuit units each including an on / off setting transistor TR21 and a voltage application transistor TR22. Correspondingly provided. The drain of the on / off setting transistor TR21 is connected to the power supply voltage Vdd, and the source thereof is connected to the drain of the voltage application transistor TR22. The source of the voltage application transistor TR22 is connected to the corresponding column signal line 113. Further, a signal line of an on / off setting signal drawn from the row scanning circuit 120 is connected in common to the gate of the on / off setting transistor TR21. A voltage having a predetermined value output from the voltage drop prevention circuit 220 is applied to the gate of the voltage application transistor TR22 as a gate voltage.

  The voltage drop prevention circuit 220 applies a preset voltage value at a timing according to the timing signal VCLEN output from the timing control circuit 160 to the gate of each voltage application transistor TR22 of the column unit voltage application circuits 230-1 to 230m. Apply to. Thereby, during the period when the voltage is output from the voltage drop prevention circuit 220, it is possible to obtain a state where the potential of the pixel signal Vx is clamped at a predetermined level corresponding to the output voltage value (gate voltage).

  In this case, for example, in correspondence with FIG. 6, the timing control circuit 160 outputs the timing signal VCLEN over a predetermined period including the row selection blank period T2 (time points t4-1 to t7). During the period in which the timing signal VCLEN is output, each of the column unit voltage application circuits 230-1 to 230-m applies a voltage having a predetermined value to the corresponding column signal line. As a result, the pixel signal Vx in the row selection blank period T2 is clamped at a predetermined level, and a drop due to a potential difference of ΔVd does not occur. Therefore, when the row selection blank period T2 elapses and the time point t7 is reached, it is possible to obtain a state where a necessary level is obtained as the pixel signal Vx. As a result, it is not necessary to set the period T3 for waiting for the level return, and for example, in actuality, the pixel can be driven at the timing as shown in FIG. That is, after the second row scanning period, the same time length as that of the first row scanning period can be set, and the above-described decrease in the frame rate can be avoided.

  However, in the configuration of the image sensor 100A shown in FIG. 7, for example, the voltage drop prevention circuit 220 is added externally to the configuration of the image sensor 100 shown in FIG. Also, the configuration becomes complicated. Further, in response to the addition of the voltage drop prevention circuit 220, the image sensor 100A must be additionally formed with the column unit voltage application circuits 230-1 to 230-m. Furthermore, the timing control circuit 160 also needs to be configured to output a timing signal VCLEN for controlling the voltage output timing from the voltage drop prevention circuit 220.

  In this way, the configuration of FIG. 7 in which the voltage drop prevention circuit 220 is added to the image sensor 100A has a more complicated circuit configuration and larger circuit scale than, for example, FIG. In addition, the process and structure of the image sensor 100A are complicated and require large changes.

[Configuration Example of Image Sensor as First Embodiment]
Therefore, as a first embodiment of the present invention, a configuration is proposed in which the sunspot correction and the prevention of voltage drop in the row selection blank period are effectively performed while taking the simplest possible configuration as an image sensor.

  FIG. 8 shows a configuration example of the image sensor 100B as the first embodiment of the present invention. In this figure, the same parts as those in FIG. 1 and FIG. The pixel 111 has a structure similar to that shown in FIG.

  The image sensor 100B shown in FIG. 8 includes a sunspot correction / voltage drop prevention circuit 240. As will be understood from the following description, this sunspot correction / voltage drop prevention circuit 240 is composed of the sunspot correction circuit 200 shown in FIGS. 1 and 7 and the voltage drop prevention circuit 220 shown in FIG. One function is integrated. Corresponding to the provision of the sunspot correction / voltage drop prevention circuit 240, the column unit voltage application circuits 210-1 to 210-m (m = 3 in correspondence with the figure) are provided for each of the column signal lines 113-1 to 113-m. Will be provided).

  The configuration of the row scanning circuit 120 that outputs the row selection signals SEL1 to SELn (n = 2 in correspondence with the drawing) is an example of the row selection unit described in the claims. The combination of the configuration of the pixel 111 including the reset transistor TR2 and the configuration of outputting the reset signals RST1 to RSTn as the row scanning circuit 120 is an example of the reset unit described in the claims. Further, the combination of the configuration of the pixel 111 including the transfer transistor TR1 and the configuration of outputting the transfer gate signals TRG1 to TRGn as the row scanning circuit 120 is an example of the light reception signal output means described in the claims. Further, the configuration composed of the combination of the sunspot correction / voltage drop prevention circuit 240 and the column unit voltage application circuits 210-1 to 210-m is an example of the voltage application means described in the claims. The sunspot correction / voltage drop prevention circuit 240 is an example of the voltage output means described in the claims, and the column-unit voltage application circuits 210-1 to 210-m include the column-corresponding voltage application described in the claims. An example of the means. A timing control circuit 160 that outputs a timing signal PCSUNEN at a timing shown in FIG. 10 described later is an example of the timing control means described in the claims.

[Configuration example of sunspot correction / voltage drop prevention circuit]
The circuit diagram of FIG. 9 shows a circuit configuration example of the sunspot correction / voltage drop prevention circuit 240. The sunspot correction / voltage drop prevention circuit 240 shown in this figure includes resistors R0 to Rn, switches SW1 to SWn, and a bias setting circuit 241.

  The resistors R0 to Rn each have a predetermined resistance value, are connected in series as shown in the figure, and are inserted between the power supply voltage Vdd and the ground. One end of each of the switches SW1 to SWn is connected to each connection point in the series connection of the resistors R0 to Rn. The switches SW1 to SWn are on / off switches, and the other ends of the switches SW1 to SWn are commonly connected to the gates of the voltage application transistors TR12 of the column-unit voltage application circuits 210-1 to 210-m.

  The bias setting circuit 241 is provided to output a voltage having a predetermined value to the gate of the voltage application transistor TR12 at a predetermined timing. That is, the timing signal PCSUNEN from the timing control circuit 160 is input to the bias setting circuit 241. For example, when the timing signal PCSUNEN is at L level, the bias setting circuit 241 turns off all the switches SW1 to SWn. At this time, the voltage application transistor TR12 is in an OFF state with its gate open, so that no voltage is applied to the column signal line 113.

  On the other hand, the bias setting circuit 241 operates to turn on a predetermined one of the switches SW1 to SWn, for example, when the timing signal PCSUNEN is at the H level. The designated switch is selected corresponding to the optimum value of the clamp potential of the pixel signal Vx. When the switch is turned on in this way, a voltage having a predetermined value obtained by dividing the power supply voltage Vdd by the voltage division ratio corresponding to the turned on switch is input to the gate of the voltage application transistor TR12. The As a result, the voltage application transistor TR12 applies a predetermined voltage amplified with respect to the gate voltage to the column signal line 113. As the pixel signal Vx at this time, a state of being clamped at a predetermined potential corresponding to the voltage value applied to the corresponding column signal line 113 is obtained.

[Operation Example of Image Sensor as First Embodiment]
The timing chart of FIG. 10 shows an operation example of the image sensor 100B shown in FIG. 8 as the first embodiment of the present invention. As a comparison, in the timing chart of FIG. 6, the timing signal PCSUNEN corresponding to the second row scanning period rises to the H level at time t7, which is the start time. On the other hand, the timing signal PCSUNEN corresponding to the second row scanning period in FIG. 10 rises, for example, at a time point t4-1 in the first row scanning period which is the previous row scanning period. That is, in this case, with respect to the timing signal PCSUNEN corresponding to one row scanning period, from the timing corresponding to the time when the output of the row selection signal SEL is stopped and becomes L level in the previous row scanning period. We are going to launch to H level. Note that the timing at which the timing signal PCSUNEN is inverted to the L level is the same time point t9-1 in both FIG. 6 and FIG.

  By outputting the timing signal PCSUNEN at the above timing, a predetermined potential is applied to the column signal line 113 over a period from the time t4-1 in the first row scanning period to the time t9-1 in the second row scanning period. The state to be obtained is obtained. As a result, the pixel signal Vx in the row selection blank period T2T2 in FIG. 10 does not drop due to the potential difference of ΔVd as shown in FIG. 6, for example, and rises so as to reach a predetermined clamp potential, for example. It becomes operation. Thus, for example, when the second row scanning period starts at time t7, a predetermined clamp potential is almost obtained. That is, the voltage drop in the row selection blank period T2 is prevented. As a result, for example, as in the case of FIG. 6, the period T3 for returning from the voltage drop becomes unnecessary, and the reset pulse RST2 can be raised to the H level at time t7. As a result, the second row scanning period is not extended for the period T3, and can be set to the same time length as the first row scanning period.

  Further, the timing at which the timing signal PCSUNEN corresponding to the second row scanning period is inverted from the H level to the L level is the time t9 within the period in which the transfer gate signal TRG2 is at the H level, as in FIGS. -1. Thereby, the operation of clamping the pixel signal Vx with the predetermined potential is continued until time t9-1 even after time t7. That is, the pixel signal Vx is ensured to be clamped at a predetermined potential in the period T1 (time t8 to t9) in the second row scanning period. This means that the sunspot correction operation is properly obtained.

  As an embodiment of the present invention, the timing signal PCSUNEN is output at the same cycle timing from time t4-1 to time t9-1 in FIG. 10 corresponding to each row scanning period after the second row scanning period. . This is also indicated by the fact that the timing signal PCSUNEN rises to the level at time t10-1 in FIG. 10, for example. Thereby, in the embodiment of the present invention, the sunspot correction is continuously performed, and the voltage drop in the row selection blank period is eliminated and the frame rate is not lowered.

  As described above, in the embodiment of the present invention, the operation of clamping the potential of the pixel signal Vx corresponding to the second row scanning period and thereafter is performed from the timing when the row selection blank period T2 of the previous row scanning period is started. We are going to start. And it continues until the period including the period T1 in the next row scanning period. As described above, this operation is obtained by timing setting in the timing control circuit 160 during a period in which the timing signal PCSUNEN is at the H level. That is, in the embodiment of the present invention, both the sunspot correction and the prevention of the voltage drop in the row selection blank period are realized by a circuit configuration that can be regarded as equivalent to, for example, the image sensor 100 shown in FIG. This can be regarded as being possible to correct the sunspot and prevent the voltage drop during the row selection blank period with a circuit configuration that is simple enough to be regarded as a necessary minimum.

  Specifically, in comparison with FIG. 7, in the embodiment of the present invention, the voltage drop prevention circuit 220 is omitted, and one sunspot correction / voltage drop prevention circuit 240 corresponding to the sunspot correction circuit 200 is provided. Need only be provided. At the same time, one column unit voltage application circuit 210-1 to m is provided for each of the column signal lines 113-1 to m, and the column unit voltage application circuits 230-1 to 230m are omitted. Further, there is no need to additionally form a signal line for inputting the timing signal VCLEN from the timing control circuit 160 to the voltage drop prevention circuit 220. Thus, in the embodiment of the present invention, it can be said that the circuit scale as the image sensor is suppressed to the minimum necessary.

  As understood from the configuration shown in FIG. 9, in the sunspot correction / voltage drop prevention circuit 240, one of the switches SW1 to SWn to be turned on by the bias setting circuit 241. The selection can be changed. As a result, the voltage division ratio with respect to the power supply voltage Vdd is changed, and the voltage value output from the bias setting circuit 241 is changed and set accordingly. That is, the gate voltage of the voltage application transistor TR12 is changed and set. As a result, the clamp potential obtained as the pixel signal Vx of the column signal line 113 is changed and set.

  The setting of the clamp potential, that is, the designation of the switch to be turned on by the bias setting circuit 241 can be performed as follows. That is, for example, one of the switches SW1 to SWn is sequentially turned on by a calibration operation at the time of manufacture or at the time of power activation, and the clamp potential obtained at that time is measured. Then, among the switches SW1 to SWn, a setting is made to designate the switch that was turned on when the clamp potential closest to the optimum value is obtained for the bias setting circuit 241. Thereafter, the bias setting circuit 241 operates to turn on the designated switch in response to the input of the H level timing signal PCSUNEN. As a result, an optimum clamp potential is applied to the column signal line 113 in order to correct sunspots and prevent a voltage drop during the row selection blank period.

<2. Modification>
Then, the modification of the 1st Embodiment of this invention is demonstrated. For example, in FIG. 10, the output of the H-level timing signal PCSUNEN is started from the time point 4-1, which is the start time point of the row selection blank period T2. That is, the application of the predetermined potential to the column signal line 113 is started from the start time of the row selection blank period T2. This operation is for obtaining a state in which the pixel signal Vx of a necessary level is obtained when the row selection signal rises to the H level, as understood from the above description. From this, if the above-described state can be obtained, the application of the predetermined potential to the column signal line 113 may be started at an arbitrary timing after the start time of the row selection blank period T2. I can say that.

  Therefore, the following configuration is adopted as a modification of the first embodiment of the present invention. That is, the output of the H level timing signal PCSUNEN is started at a timing when a predetermined time has elapsed from the start time of the row selection blank period T2 before reaching the start time of the next row scanning period. is there. For this purpose, the timing control circuit 160 is configured so as to obtain the output timing of the desired timing signal PCSUNEN. For example, depending on circuit design or the like, it may be considered that starting the output of the timing signal PCSUNEN at the same time as the start of the row selection blank period T2 may have some influence on the operation. In such a case, the above-described influence can be avoided by adopting the configuration of the above-described modified example and setting the output start time of the timing signal PCSUNEN to a timing different from the start time of the row selection blank period T2.

  In the description of the operation shown in FIG. 10, the column signal line is divided into the row selection blank period T2 corresponding to the time points t4-1 to t7 and the subsequent period from the time points t7 to t9-1 including the period T1. The same clamp potential is applied to each of 113. That is, the bias setting circuit 241 performs control so that the same switch is turned on during a period from the time point t4-1 to t9-1 when the timing signal PCSUNEN becomes H level. On the other hand, for example, as another modification, different clamp potentials are set in the first half row selection blank period T2 (time t4-1 to t7) and in the second half period t7 to time t9-1. It is also conceivable to configure as described above. That is, the clamp potential is individually set corresponding to the case where the optimum clamp potential differs greatly between the sunspot correction and the voltage drop prevention in the row selection blank period. There are several possible configurations for this. For example, the bias setting circuit 241 provides a count function, and starts counting from time t4-1 when the timing signal PCSUNEN becomes H level. For example, from the time point t 4-1, first, control is performed so as to turn on the designated switch corresponding to the voltage drop prevention in the row selection blank period. Next, when the count value corresponding to the timing at which the row selection blank period T2 is completed and the time point t7 is obtained is obtained, the designated switch is switched on in response to the sunspot correction. It is.

  Further, the embodiment of the present invention shows an example for embodying the present invention. As clearly shown in the embodiment of the present invention, the matters in the embodiment of the present invention and the claims Each invention-specific matter in the scope has a corresponding relationship. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present invention having the same names as the claims have a corresponding relationship. However, the present invention is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist of the present invention.

  In the description so far, the case where the pixel 111 has a three-transistor configuration is taken as an example. However, even with a pixel configuration other than three transistors, the configuration of the present invention can be effectively applied when, for example, an image sensor driving method in which a voltage drop of a signal line is generated by setting a row selection blank period. In the above description of the embodiments of the present invention, the configuration of the present invention is applied to a CMOS image sensor. However, it may be applied to an image sensor other than a CMOS such as a CCD.

100, 100A, 100B Image sensor 110 Pixel array 111 Pixel 112 Row signal line 113 Column signal line 120 Row scanning circuit 130 Column ADC section 140-1-3 Unit ADC
141-1-3 Comparator 142-1-3 Counter 150 Reference signal generation circuit 160 Timing control circuit 170 Column scanning circuit 180 Buffer amplifier 190 Data output line 200 Sunspot correction circuit 210-1 to m, 230-1 to m column unit Voltage application circuit 220 Voltage drop prevention circuit 240 Sunspot correction / voltage drop prevention circuit 241 Bias setting circuit

Claims (5)

A pixel array in which pixels are arranged in a matrix;
A row selection signal is sequentially output for each row in the pixel array, the output of the row selection signal for selecting one row is terminated, and the output of the row selection signal for selecting the next row is started. A row selection means for setting a pause period of a predetermined length in between,
Corresponding to each column of the pixel array, provided commonly connected to the pixels of the corresponding column, obtained from the pixels in the row selected by the row selection means among the connected pixels A column signal line from which a potential is output;
Reset means for resetting a potential output to the column signal line during a period in which the row selection signal is output;
In the period when the row selection signal is output, after the reset by the reset means is completed, the light reception that causes the pixel selected by the row selection signal to receive light and output the potential to the column signal line Signal output means;
Voltage applying means for applying a predetermined voltage value to the column signal lines;
The predetermined voltage value is applied to the column signal line by the voltage application means in a period from the end of outputting a row selection signal for selecting one row to the end of the reset. A solid-state imaging device comprising: The voltage application unit performs an operation of applying the predetermined voltage value when a timing signal is output from the timing control unit,
2. The solid-state imaging device according to claim 1, wherein the timing control unit outputs the timing signal in a period from the end of outputting a row selection signal for selecting the one row to the end of the reset. The voltage applying means includes
One voltage output means for outputting a predetermined voltage value;
One set corresponding to each column signal line is provided, and column-corresponding voltage applying means for applying an output amplified according to a predetermined voltage value output from the voltage output means to the corresponding column signal line. Item 2. The solid-state imaging device according to Item 1. The solid-state imaging device according to claim 3, wherein the voltage output unit is configured to change the predetermined voltage value to be output according to a setting. A row selection signal for sequentially outputting a row selection signal for each row in a pixel array in which pixels are arranged in a matrix, finishing the output of the row selection signal for selecting one row, and selecting the next row A row selection procedure for setting a pause period of a predetermined length of time before starting the output of
Corresponding to each column of the pixel array, provided commonly connected to the pixels of the corresponding column, obtained from the pixels in the row selected by the row selection means among the connected pixels A reset procedure for resetting a potential of a column signal line from which a potential to be output is output in a period in which the row selection signal is output;
Light reception for outputting, to the column signal line, a potential obtained by receiving light of a pixel selected by the row selection signal after the reset by the reset procedure is completed in a period in which the row selection signal is output. Signal output procedure;
A solid-state display including a voltage application procedure for applying a predetermined voltage value to the column signal line in a period from the end of outputting a row selection signal for selecting one row to the end of the reset. Driving method of imaging apparatus.

Images