JP2020025254A - Signal generation device and signal reading system - Google Patents

Abstract

To generate a code specifying signal capable of specifying a code corresponding to a logic signal transmitted to a communication path without being connected to a communication path via a connector.SOLUTION: A signal generation device includes a first impedance element 12a that is connected to one electrode 21 that is brought into contact with a coated portion of a coated conductor La and generates a first voltage signal Vc1 that changes in voltage according to the voltage Va transmitted to the coated conductor La capacitively coupled to the electrode 21, a second impedance element 12b that is connected to the other electrode 21 that is brought into contact with a coated portion of a coated conductor Lb and generates a second voltage signal Vc2 that changes in voltage according to the voltage Vb transmitted to the coated conductor Lb that is capacitively coupled to the electrode 21, and a differential amplifier 13 that outputs a single-ended signal Vd whose voltage changes in accordance with the difference voltage between the respective voltage signals Vc1 and Vc2, and a code specifying signal Sf is generated on the basis of the signal Vd.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a signal generation device that generates a code specifying signal capable of specifying a code corresponding to a logic signal based on a two-wire differential voltage type logic signal transmitted via a communication path, and the signal generation device The present invention relates to a signal reading system provided with:

  For example, Patent Literature 1 below discloses a vehicle data collection device (hereinafter referred to as a vehicle data collection device) configured to collect and record various CAN frames (control data) transmitted via a serial bus (in-vehicle LAN) for CAN communication. , Also simply referred to as “collection device”). This collection device is configured to be connectable to a diagnostic connector (connector for diagnostic device connection: hereinafter simply referred to as a “connector”) provided on a serial bus so that external devices can be connected for the purpose of failure diagnosis and maintenance. ing. In addition, in this collecting device, when connected to the connector, the collecting device operates by a power supply supplied through the connector, and automatically starts / stops collecting CAN frames from the serial bus in conjunction with operation of an ignition switch. Is executed.

JP 2008-70133 A (Page 4-11, FIG. 1-17)

  By the way, the above-mentioned connector provided on the serial bus is usually assumed to be connected to a vehicle developer (manufacturer) for the purpose of failure diagnosis and maintenance of the vehicle after shipment (for example, a device (for example, , A device for failure diagnosis and a device for maintenance provided by the manufacturer, which are collectively referred to as a diagnostic device hereinafter). Therefore, when performing a failure diagnosis or maintenance of a vehicle after shipment, it is necessary to prepare a dedicated diagnostic device corresponding to the vehicle (or a manufacturer of the vehicle). However, there are cases where it is necessary to perform fault diagnosis and the like on vehicles of multiple manufacturers, and in such a case, dedicated diagnostic equipment corresponding to each manufacturer must be prepared, which is troublesome and costly. However, there is a problem in that

  In recent years, a device that outputs a malicious CAN frame for the purpose of hindering the operation of various nodes connected to the serial bus is connected to a connector, or a CAN frame transmitted through the serial bus is maliciously transmitted. It has been confirmed that a device that transfers data to a third party via a mobile communication network or the like is connected to a connector. For this reason, in a vehicle development site or the like, adoption of a configuration in which the connector is not provided on the serial bus is being studied from the viewpoint of security. However, when such a configuration is adopted, the above-described dedicated diagnostic device that is assumed to be connected to the serial bus via a connector can perform vehicle failure diagnosis and maintenance after shipment. The problem that it becomes difficult arises.

  Although the problem in the field of automobiles has been exemplified, in fields other than automobiles, for example, in the field of mechanical equipment in factories, there is a configuration in which a dedicated diagnostic device is connected via a dedicated connector as described above. Since it is adopted, when acquiring a CAN frame (a sequence of codes indicated by a logic signal of a two-wire differential voltage system) transmitted through a serial bus (communication path) for CAN communication, A similar problem has occurred.

  The present invention has been made in view of such a problem to be solved, and can specify a code indicated by a logic signal transmitted to a communication path without being connected to the communication path via a connector. It is a main object to provide a signal generation device and a signal reading system described above.

  In order to achieve the above object, a signal generating apparatus according to claim 1 responds to a logic signal of a two-wire differential voltage system transmitted through a communication path including a pair of covered conductors. A signal generation device that generates a code identification signal capable of identifying a code, wherein the signal generation device is connected to one electrode of a pair of electrodes respectively brought into contact with a coating portion of the pair of coated conductors, and A first impedance element for generating a first voltage signal whose voltage changes according to a voltage transmitted to one of the coated conductors capacitively coupled to the one electrode of the conductor, and the other of the pair of electrodes To generate a second voltage signal whose voltage changes in accordance with the voltage transmitted to the other of the pair of covered conductors capacitively coupled to the other of the covered conductors. A two-impedance element, and a differential amplifier that receives the first voltage signal and the second voltage signal and outputs a single-ended signal whose voltage changes according to a difference voltage between the voltage signals. The code specifying signal is generated based on the single-ended signal.

  The signal generation device according to claim 2 is the signal generation device according to claim 1, wherein the signal generation unit generates the code specifying signal by binarizing the single-ended signal by comparing the single-ended signal with a threshold voltage. It has.

  According to a third aspect of the present invention, in the signal generating apparatus according to the first or second aspect, the differential amplifier inputs the first voltage signal and the second voltage signal and generates the differential voltage. A differential amplifier circuit that outputs a differential signal having a voltage that changes in response to the differential signal, wherein the differential signal has a peak-to-peak voltage equivalent to the peak-to-peak voltage of an AC component of the differential signal, and a voltage in a low voltage period is a target constant voltage. And a waveform shaping circuit for shaping the signal into the single-ended signal and outputting the signal.

  According to a fourth aspect of the present invention, in the signal generating apparatus according to the first or second aspect, the differential amplifier inputs the first voltage signal and the second voltage signal and generates the differential voltage. A differential amplifier circuit that outputs a differential signal having a voltage that changes in response to the differential signal, wherein the differential signal has a peak-to-peak voltage equivalent to the peak-to-peak voltage of an AC component of the differential signal, and a voltage during a high voltage period is a target constant voltage. And a waveform shaping circuit for shaping the signal into the single-ended signal and outputting the signal.

  According to a fifth aspect of the present invention, in the signal generating apparatus according to the third aspect, the waveform shaping circuit has one end connected to an input unit to which the difference signal is input and the other end connected to an output unit. A capacitor connected to the unit, and one end connected to the other end of the capacitor and a target constant voltage applied to the other end to supply the target constant voltage to the other end of the capacitor. A third impedance element, a series circuit including a fourth impedance element and a switch connected in series, one end of which is connected to the output unit, and the other end of which is applied with the target constant voltage; The switch is turned on during a low voltage period of the AC component of the difference signal, and the switch is turned off during a high voltage period of the AC component. And a switch control circuit for outputting a that control pulse signal, and outputs the single-ended signal from the output unit.

  According to a sixth aspect of the present invention, in the signal generating apparatus according to the fourth aspect, the waveform shaping circuit has one end connected to the input unit to which the difference signal is input and the other end connected to the output unit. A capacitor connected to the unit, and one end connected to the other end of the capacitor and a target constant voltage applied to the other end to supply the target constant voltage to the other end of the capacitor. A third impedance element, a series circuit including a fourth impedance element and a switch connected in series, one end of which is connected to the output unit, and the other end of which is applied with the target constant voltage; The switch is turned on during a high voltage period of the AC component of the difference signal, and the switch is turned off during a low voltage period of the AC component. And a switch control circuit for outputting a that control pulse signal, and outputs the single-ended signal from the output unit.

  According to a seventh aspect of the present invention, in the signal generating apparatus according to the third aspect, the waveform shaping circuit includes a capacitor having one end connected to an input section to which the difference signal is input, and A third impedance element connected to the other end of the capacitor and having a target constant voltage applied to the other end to supply the target constant voltage to the other end of the capacitor; A fifth impedance element having one end connected to the output unit and the other end connected to the output unit, and connected to the output unit and applying the target constant voltage to the output unit when in an on state. A switch for stopping the application of the target constant voltage to the output unit in the off state, and the switch in the on state during a low voltage period in the AC component of the difference signal. Together to line, and a switch control circuit for outputting a control pulse signal for shifting the switch to a high voltage period of the AC component in the off state, and outputs the single-ended signal from the output unit.

  In the signal generation device according to claim 8, in the signal generation device according to claim 4, the waveform shaping circuit includes a capacitor having one end connected to an input unit to which the difference signal is input, and a capacitor having one end connected to an input unit to which the difference signal is input. A third impedance element connected to the other end of the capacitor and having a target constant voltage applied to the other end to supply the target constant voltage to the other end of the capacitor; A fifth impedance element having one end connected to the output unit and the other end connected to the output unit, and connected to the output unit and applying the target constant voltage to the output unit when in an on state. A switch for stopping the application of the target constant voltage to the output unit in the off state, and the switch in the on state during a high voltage period in the AC component of the difference signal. Together to line, and a switch control circuit for outputting a control pulse signal for shifting the switch to the low voltage period of the AC component in the off state, and outputs the single-ended signal from the output unit.

  According to a ninth aspect of the present invention, in the signal generating apparatus according to the fifth or seventh aspect, the switch is turned on when the control pulse signal is at a high potential, and the switch is turned on when the control pulse signal is at a low level. The switch control circuit is configured to transition to an off state at the time of a potential, wherein the inverting input terminal is connected to the other end of the capacitor, and a reference voltage higher than the target constant voltage is a non-inverting input terminal. , And a comparator for outputting the control pulse signal from an output terminal.

  According to a tenth aspect of the present invention, in the signal generating device according to the fifth or seventh aspect, the switch is turned on when the control pulse signal is at a low potential, and the switch is turned on when the control pulse signal is at a high level. The switch control circuit is connected to a non-inverting input terminal at the other end of the capacitor, and a reference voltage higher than the target constant voltage is applied to the inverting input terminal. , And a comparator for outputting the control pulse signal from an output terminal.

  The signal generating device according to claim 11 is the signal generating device according to claim 6 or 8, wherein the switch is turned on when the control pulse signal is at a high potential, and the switch is turned on when the control pulse signal is at a low level. The switch control circuit is configured to shift to an off state when the potential is at a potential, a non-inverting input terminal is connected to the other end of the capacitor, and a reference voltage lower than the target constant voltage is an inverting input terminal. , And a comparator for outputting the control pulse signal from an output terminal.

  According to a twelfth aspect of the present invention, in the signal generation apparatus according to the sixth or eighth aspect, the switch is turned on when the control pulse signal is at a low potential, and the switch is turned on when the control pulse signal is at a high level. The switch control circuit is configured to transition to an off state at the time of a potential, wherein the inverting input terminal is connected to the other end of the capacitor, and a reference voltage lower than the target constant voltage is a non-inverting input terminal. , And a comparator for outputting the control pulse signal from an output terminal.

  According to a thirteenth aspect of the present invention, in the signal generating device according to the fifth or seventh aspect, the switch is turned on when the control pulse signal is at a high potential, and the switch is turned on when the control pulse signal is at a low level. A switch control circuit configured to shift to an off state when the potential is at a potential, wherein the switch control circuit has an inverting input terminal connected to the other end of the capacitor and outputs the control pulse signal from an output terminal; A part is connected to the output terminal, and any one of the target constant voltage and a voltage near the target constant voltage is applied to the other end, and any one of the voltage and the control pulse signal is applied. A resistive voltage dividing circuit for outputting a divided voltage defined by a voltage to a non-inverting input terminal of the comparator as a reference voltage.

  According to a fourteenth aspect of the present invention, in the signal generator of the fifth or seventh aspect, the switch is turned on when the control pulse signal is at a low potential, and the switch is turned on when the control pulse signal is at a high potential. The switch control circuit is configured to shift to an off state when the potential is at a potential, and the switch control circuit outputs any one of the target constant voltage and a voltage near the target constant voltage to the inverting input terminal and outputs the same. A comparator that outputs the control pulse signal from a terminal, one end of which is connected to the output terminal and the other end of which is connected to the other end of the capacitor, the voltage of the single-ended signal and the control pulse signal. And a resistor voltage dividing circuit for outputting a voltage dividing pulse signal defined by the following voltage to the non-inverting input terminal of the comparator.

  The signal generating device according to claim 15 is the signal generating device according to claim 6 or 8, wherein the switch is turned on when the control pulse signal is at a high potential, and the control pulse signal is at a low level. The switch control circuit is configured to shift to an off state when the potential is at a potential, and the switch control circuit outputs any one of the target constant voltage and a voltage near the target constant voltage to the inverting input terminal and outputs the same. A comparator that outputs the control pulse signal from a terminal, one end of which is connected to the output terminal and the other end of which is connected to the other end of the capacitor, the voltage of the single-ended signal and the control pulse signal. And a resistor voltage dividing circuit for outputting a voltage dividing pulse signal defined by the following voltage to the non-inverting input terminal of the comparator.

  Further, in the signal generating device according to claim 16, in the signal generating device according to claim 6 or 8, the switch is turned on when the control pulse signal is at a low potential, and the switch is turned on when the control pulse signal is at a high level. A switch control circuit configured to shift to an off state when the potential is at a potential, wherein the switch control circuit has an inverting input terminal connected to the other end of the capacitor and outputs the control pulse signal from an output terminal; A part is connected to the output terminal, and any one of the target constant voltage and a voltage near the target constant voltage is applied to the other end, and any one of the voltage and the control pulse signal is applied. A resistive voltage dividing circuit for outputting a divided voltage defined by a voltage to a non-inverting input terminal of the comparator as a reference voltage.

  According to a seventeenth aspect of the present invention, in the signal generation device according to the fifth aspect, the switch control circuit has one end connected to the output unit and the other end applied with the target constant voltage. A resistive voltage dividing circuit that divides the single-ended signal and outputs it as a divided pulse signal, a bias voltage source that generates a bias voltage based on the target constant voltage, and the bias voltage applied to the divided pulse signal. An adder for adding a voltage and outputting the control pulse signal.

  The signal generating device according to claim 18 is the signal generating device according to any one of claims 5 to 12, wherein the switch is controlled by the control pulse signal, and the target constant voltage when in the ON state. Is output from the output terminal to the output section, and the three-state buffer is configured to shift the output terminal to a high impedance state when in the off state.

  According to a nineteenth aspect of the present invention, in the signal generation device according to any one of the third to eighteenth aspects, the voltage data indicated by the voltage data is obtained by performing D / A conversion on voltage data input from the outside. A D / A converter for outputting the target constant voltage having a value.

  According to a twentieth aspect of the present invention, in the signal generation apparatus according to any one of the third to nineteenth aspects, the differential amplifier circuit is configured to receive the first voltage signal at a non-inverting input terminal and to invert the first voltage signal. A first series circuit of an input resistor and a capacitor is connected between the input terminal and the reference potential, and a feedback resistor is connected between the inverting input terminal and the output terminal to amplify the AC component of the first voltage signal. A first operational amplifier configured as an AC amplifier that outputs the second voltage signal, and the second voltage signal is input to a non-inverting input terminal of the first operational amplifier. A second operational amplifier configured as an AC amplifier that amplifies and outputs a component, and a differential amplifier that amplifies a difference between output signals of the first operational amplifier and the second operational amplifier and outputs the difference signal. And a third operational amplifier was made.

  The signal generating device according to claim 21 is the signal generating device according to any one of claims 1 to 20, wherein the first impedance element and the second impedance element are both high impedance resistors or capacitors, or These combination circuits have the same configuration.

  A signal generating device according to a twenty-second aspect is the signal generating device according to any one of the first to twenty-first aspects, wherein the one electrode has a first shield connected at a base end to the first impedance element. The other electrode is a second shielded cable separate from the first shielded cable, the second shielded cable having a base end connected to the second impedance element. Connected to the free end of the cable.

  Further, the signal generation device according to claim 23 can specify a code corresponding to the logic signal based on a two-wire differential voltage type logic signal transmitted through a communication path including a pair of covered conductors. A signal generation device that generates a code identification signal, which is mounted on one of the covered conductors of the pair of covered conductors, is a current flowing through the one covered conductor, and the one covered conductor is A first current detection probe that detects a current whose current value changes according to the voltage being transmitted, and outputs a first voltage signal whose voltage value changes according to the current value; and a pair of the covered conductors. A current that is attached to the other insulated wire and that flows through the other insulated wire, the current value of which changes according to the voltage transmitted to the other insulated wire, is detected, and the current is detected. value Connected to a second current detection probe that outputs a second voltage signal whose voltage value changes in response to the input of the first voltage signal and the second voltage signal and a voltage corresponding to a difference voltage between the voltage signals. And a differential amplifying unit that outputs a single-ended signal that varies, and generates the code specifying signal based on the single-ended signal.

  A signal reading system according to a twenty-fourth aspect corresponds to the signal generation device according to any one of the first to twenty-third aspects, and the logic signal based on the code specifying signal generated by the signal generation device. A coding device for specifying the code.

  According to the signal generating device of the first aspect and the signal reading system of the twenty-fourth aspect, the signal generating device is brought into contact with the covering portions of the pair of covered conductors respectively (without contacting the metal portion (core wire) of the pair of covered conductors). A configuration in which the pair of electrodes is connected to a pair of electrodes in a contact state (a state of non-metal contact) that is in contact with the pair of coated conductors. A single-ended signal that can generate a code specifying signal capable of specifying a code indicated by a logic signal transmitted through a pair of covered conductors by performing a simple operation of bringing a pair of electrodes into contact with a portion. Can be generated. Therefore, by providing a device capable of generating the code specifying signal based on the single-ended signal, the code specifying signal is generated, and the code indicated by the logic signal is specified based on the generated code specifying signal. Further, it is possible to specify a code string composed of the specified code string. Thereby, even if the connector is not disposed on the pair of covered conductors, or even if the connector is disposed on the pair of covered conductors, the logic signal is read at an arbitrary position of the pair of covered conductors, A code and a code sequence can be specified.

  According to the signal generating device of the second aspect and the signal reading system of the twenty-fourth aspect, the provision of the signal generating unit eliminates the need to separately provide a device for generating a code specifying signal based on a single-ended signal. be able to.

  In the signal generation device according to the third and fourth aspects and the signal reading system according to the twenty-fourth aspect, the differential amplifying unit outputs the differential signal as described above, and the differential amplifying circuit outputs the differential signal. And a peak-to-peak voltage equivalent to the peak-to-peak voltage of the AC component, and one of the high-potential-side voltage (voltage during the high-voltage period) and the low-potential-side voltage (voltage during the low-voltage period) is the target constant voltage. And a waveform shaping circuit for shaping (waveform shaping) the signal into a single-ended signal and outputting the signal. For this reason, according to this signal generation device, the signal generation unit disposed downstream of the differential amplification unit compares the target constant voltage with the threshold voltage defined on the basis of the target constant voltage, thereby reliably generating the single-ended signal. The value can be converted to a code specifying signal. Thereby, according to the signal reading system, the code indicated by the logic signal can be specified more reliably based on the code specifying signal, and furthermore, the code sequence constituted by the code can be further improved. It can be specified reliably.

  In the signal generation device according to the fifth and sixth aspects and the signal reading system according to the twenty-fourth aspect, the waveform shaping circuit includes a capacitor, a third impedance element, a series circuit, and a series circuit during a low voltage period in an AC component of the difference signal. A switch control circuit for switching the switch to the ON state and for switching the switch to the OFF state during a high voltage period of the AC component, or a capacitor, a third impedance element, a series circuit, and an AC component of the differential signal. And a switch control circuit that causes the switches of the series circuit to shift to the on state during the high voltage period and the switch to shift to the off state during the low voltage period of the AC component.

  Therefore, according to this signal generation device, unlike a configuration having a waveform shaping circuit configured using diodes (diodes as individual semiconductor elements (discrete components)) affected by a forward voltage, the waveform shaping circuit is The difference signal is a peak-to-peak voltage equivalent to the peak-to-peak voltage of the AC component of the difference signal, and the high-potential-side voltage (voltage during the high-voltage period) and the low-potential-side voltage (voltage during the low-voltage period) Either one can be reliably shaped (waveform shaped) into a single-ended signal defined as the target constant voltage and output. For this reason, according to this signal generation device, the signal generation unit disposed downstream of the differential amplification unit compares the target constant voltage with the threshold voltage defined as a reference, thereby further converting the single-ended signal. The code specifying signal can be generated by performing the binarization without fail. Thus, according to the signal reading system, the code indicated by the logic signal can be more reliably specified based on the code specifying signal, and further, the CAN constituted by the specified code sequence can be used. The frame can be specified more reliably.

  In the signal generation device according to the seventh and eighth aspects and the signal reading system according to the twenty-fourth aspect, the waveform shaping circuit includes a capacitor, a third impedance element, a fifth impedance element, a switch, and a low voltage period in an AC component of the difference signal. And a switch control circuit for shifting the switch to an off state during a high voltage period of the AC component, or a capacitor, a third impedance element, a fifth impedance element, a switch, and A switch control circuit that switches the switch to the on state during the high voltage period of the AC component of the differential signal and switches the switch to the off state during the low voltage period of the AC component. .

  Therefore, according to this signal generation device, unlike a configuration having a waveform shaping circuit configured using diodes (diodes as individual semiconductor elements (discrete components)) affected by a forward voltage, the waveform shaping circuit is The difference signal is a peak-to-peak voltage equivalent to the peak-to-peak voltage of the AC component of the difference signal, and the high-potential-side voltage (voltage during the high-voltage period) and the low-potential-side voltage (voltage during the low-voltage period) Either one can be reliably shaped (waveform shaped) into a single-ended signal defined as the target constant voltage and output. In addition, the rising and falling of the single-ended signal can be made steeper (the time required for shifting to the target constant voltage can be made shorter). For this reason, according to this signal generation device, the signal generation unit disposed downstream of the differential amplification unit compares the target constant voltage with the threshold voltage defined as a reference, thereby further converting the single-ended signal. The code specifying signal can be generated reliably and by binarizing with a more accurate pulse width. Thus, according to the signal reading system, the code indicated by the logic signal can be more reliably specified based on the code specifying signal, and further, the CAN constituted by the specified code sequence can be used. The frame can be specified more reliably.

  In the signal generating device according to the ninth and tenth aspects and the signal reading system according to the twenty-fourth aspect, the switch is turned on when the control pulse signal is at a high potential, and is turned off when the control pulse signal is at a low potential. When the switch control circuit is configured to shift, the inverting input terminal is connected to the other end of the capacitor, and a reference voltage higher (slightly higher) than the target constant voltage is input to the non-inverting input terminal. And a comparator that outputs a control pulse signal from an output terminal. The switch is turned on when the control pulse signal is at a low potential, and is turned off when the control pulse signal is at a high potential. When the switch control circuit is configured as described above, the non-inverting input terminal is connected to the other end of the capacitor and is higher than the target constant voltage (slightly higher). ) Reference voltage is input to the inverting input terminal, and a comparator for outputting a control pulse signal from the output terminal. Therefore, according to the waveform shaping circuit including the switch control circuit, noise is included in the single-ended signal in a state where the low-potential-side voltage of the single-ended signal (voltage in the low-voltage period) is specified as the target constant voltage. Even if it is superimposed, the switch control circuit keeps the switch on until the noise level reaches the reference voltage (until the reference voltage rises), and the other end of the capacitor with respect to the series circuit. The application of the target constant voltage to the unit (and the output unit) can be continued. Therefore, according to the signal generating device and the signal reading system including the waveform shaping circuit, a malfunction due to noise can be reduced, so that a code specifying signal can be stably generated even in the presence of noise. Based on the code specifying signal, a code and a CAN frame composed of the code can be specified and output stably.

  In the signal generating device according to the eleventh and twelfth aspects and the signal reading system according to the twenty-fourth aspect, the switch is turned on when the control pulse signal is at a high potential, and is turned off when the control pulse signal is at a low potential. When the switch control circuit is configured to shift, a non-inverting input terminal is connected to the other end of the capacitor, and a reference voltage lower (slightly lower) than the target constant voltage is input to the inverting input terminal. And a comparator that outputs a control pulse signal from an output terminal. The switch is turned on when the control pulse signal is at a low potential, and is turned off when the control pulse signal is at a high potential. In such a configuration, the switch control circuit has an inverting input terminal connected to the other end of the capacitor and is lower than the target constant voltage (slightly lower). ) Reference voltage is input to the non-inverting input terminal, and a comparator for outputting a control pulse signal from the output terminal. Therefore, according to the waveform shaping circuit including the switch control circuit, noise is included in the single-ended signal in a state where the high-potential-side voltage of the single-ended signal (voltage in the high voltage period) is specified as the target constant voltage. Even if it is superimposed, the switch control circuit keeps the switch on until the noise level reaches the reference voltage (until the reference voltage drops), and the other end of the capacitor with respect to the series circuit. The application of the target constant voltage to the unit (and the output unit) can be continued. Therefore, according to the signal generating device and the signal reading system including the waveform shaping circuit, a malfunction due to noise can be reduced, so that a code specifying signal can be stably generated even in the presence of noise. Based on the code specifying signal, a code and a CAN frame composed of the code can be specified and output stably.

  In the signal generation device according to the present invention, the comparator constituting the switch control circuit has a hysteresis characteristic (the comparator operates as a hysteresis comparator). According to the waveform shaping circuit provided with the shaping circuit, either when the single-ended signal is a low-potential-side voltage (voltage during a low-voltage period) or when the single-ended signal is a high-potential-side voltage (a voltage during a high-voltage period) In this case, even if noise is superimposed on the single-ended signal, when the noise level is lower than the level defined by the hysteresis characteristic, the switch control circuit changes the potential of the control pulse signal to the current potential. Maintain (that is, maintain this state when the switch is on, and turn off the switch Since it is possible) to maintain this state when the state, it is possible to maintain the voltage of the single-ended signal to the current state. Therefore, according to the signal generating apparatus and the signal reading system including the waveform shaping circuit, the malfunction due to the noise can be further reduced, so that the code specifying signal can be generated more stably even in the presence of the noise. Further, a code and a CAN frame composed of the code can be more stably specified and output based on the code specifying signal.

  According to the signal generating device of the seventeenth aspect and the signal reading system of the twenty-fourth aspect, even in a configuration in which the waveform shaping circuit does not use the comparator, the differential signal output from the differential amplifying circuit is used as the AC component of the differential signal. The peak-to-peak voltage equivalent to the peak-to-peak voltage, and the low-potential-side voltage (voltage during the low-voltage period) is reliably shaped into a single-ended signal defined by the target constant voltage, and the AC component of the difference signal A peak-to-peak voltage equivalent to the peak-to-peak voltage, and the high-potential-side voltage (voltage during the high-voltage period) must be reliably shaped into a single-ended signal specified by the target constant voltage and output from the output unit. Can be. Thus, according to the signal generating device and the signal reading system including the waveform shaping circuit, the degree of freedom in design can be increased.

  According to the signal generation device of the eighteenth aspect and the signal reading system of the twenty-fourth aspect, the switch forming the serial circuit of the waveform shaping circuit is formed of a three-state buffer (three-state logic IC). Therefore, according to the signal generating apparatus and the signal reading system including the waveform shaping circuit, the output buffer (or the input / output buffer (bidirectional buffer)) built in the integrated circuit is used as a switch constituting a serial circuit. be able to.

  According to the signal generating device of the nineteenth aspect and the signal reading system of the twenty-fourth aspect, the D / A converter is arranged in the waveform shaping circuit, and the target constant voltage is output from the D / A converter. Thus, the target constant voltage can be changed by changing the voltage data to the D / A converter, so that the high-potential side voltage (voltage in the high voltage period) or the low The potential side voltage (voltage during the low voltage period) can be changed according to the input specification of the signal generation unit. That is, according to the signal generating device and the signal reading system, the high-potential-side voltage and the low-potential-side voltage are adjusted so that the signal generating unit can reliably generate the code specifying signal from the single-ended signal. Can be.

  According to the signal generating device of the twentieth aspect and the signal reading system of the twenty-fourth aspect, a capacitor is connected in series to an input resistance of the first operational amplifier constituting the differential amplifier circuit, and an input of the second operational amplifier is provided. An output signal output from each output terminal of the first operational amplifier and the second operational amplifier is configured by connecting a capacitor in series with the resistor so that the first operational amplifier and the second operational amplifier function as an AC amplifier. Can be significantly reduced due to saturation caused by the DC components of the first voltage signal and the second voltage signal.

  According to the signal generating device of the twenty-first aspect and the signal reading system of the twenty-fourth aspect, each of the impedance elements is constituted by a high impedance resistor or a capacitor, or a combination thereof, so that the first voltage is reduced. The signal and the second voltage signal can be reliably generated with a simple configuration.

  According to the signal generating device of the present invention, the electrodes of the pair of electrode portions are connected to the free ends of the first shielded cable and the second shielded cable formed separately. Since they are (arranged), they can be attached at different positions along the length direction of the communication path (arbitrary positions where they can be easily attached).

  According to the signal generating device of the twenty-third aspect and the signal reading system of the twenty-fourth aspect, the current detecting probe is attached to an arbitrary portion in the longitudinal direction of the pair of covered conductors (or clamped in the case of the clamp type). By performing the operation, it is possible to generate a single-ended signal capable of generating a code specifying signal capable of specifying a code indicated by a logic signal transmitted through a pair of covered conductors. Therefore, by providing a device capable of generating the code specifying signal based on the single-ended signal, the code specifying signal is generated, and the code indicated by the logic signal is specified based on the generated code specifying signal. Further, it is possible to specify a code string composed of the specified code string. Thereby, even if the connector is not disposed on the pair of covered conductors, or even if the connector is disposed on the pair of covered conductors, the logic signal is read at an arbitrary position of the pair of covered conductors, A code and a code sequence can be specified.

1 is a configuration diagram illustrating a configuration of a signal reading system 1; FIG. 2 is a configuration diagram illustrating a configuration of a signal generation device 2. FIG. 9 is a circuit diagram illustrating another configuration of the differential amplifier circuit 41. FIG. 9 is a circuit diagram illustrating another configuration of the differential amplifier circuit 41. FIG. 3 is a circuit diagram illustrating a configuration of a waveform shaping circuit of FIG. 2 and a configuration of a signal generation unit. FIG. 6 is a waveform chart for explaining an operation of the signal generation device 2 including the waveform shaping circuit 42 and the signal generation unit 14 in FIG. 5. FIG. 9 is a circuit diagram illustrating another configuration of the waveform shaping circuit and another configuration of the signal generation unit. FIG. 8 is a waveform chart for explaining an operation of the signal generation device 2 including the waveform shaping circuit 42 and the signal generation unit 14 of FIG. 7. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 9 is an explanatory diagram for explaining another waveform shaping circuit 42. FIG. 9 is an explanatory diagram for explaining another waveform shaping circuit 42. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 9 is a circuit diagram of another waveform shaping circuit 42. FIG. 6 is a circuit diagram of a waveform shaping circuit when the switch of FIG. 5 is configured to operate with negative logic. FIG. 8 is a circuit diagram of the waveform shaping circuit 42 when the switch 42f of FIG. 7 operates in negative logic. FIG. 10 is a circuit diagram of the waveform shaping circuit 42 when the switch 42f of FIG. 9 is configured to operate with negative logic. FIG. 11 is a circuit diagram of the waveform shaping circuit 42 when the switch 42f of FIG. 10 is configured to operate with negative logic. FIG. 6 is a circuit diagram of a waveform shaping circuit having a configuration in which a fourth impedance element shown in FIG. 5 is omitted. FIG. 8 is a circuit diagram of a waveform shaping circuit 42 having a configuration in which a fourth impedance element 42e in FIG. 7 is deleted. FIG. 10 is a circuit diagram of a waveform shaping circuit having a configuration in which a fourth impedance element e in FIG. 9 is deleted. FIG. 11 is a circuit diagram of a waveform shaping circuit 42 having a configuration in which a fourth impedance element 42e in FIG. 10 is deleted. FIG. 14 is a circuit diagram of a waveform shaping circuit 42 having a configuration in which a fourth impedance element 42e in FIG. 13 is deleted. FIG. 15 is a circuit diagram of a waveform shaping circuit 42 having a configuration in which a fourth impedance element 42e in FIG. 14 is deleted. FIG. 16 is a circuit diagram of a waveform shaping circuit 42 having a configuration in which a fourth impedance element 42e in FIG. 15 is deleted. FIG. 17 is a circuit diagram of a waveform shaping circuit 42 having a configuration in which a fourth impedance element 42e in FIG. 16 is deleted. FIG. 3 is a configuration diagram for describing a configuration for connecting a signal generation device 2 to covered conductors La and Lb. FIG. 9 is a configuration diagram for explaining another configuration for connecting the signal generation device 2 to the covered conductors La and Lb. It is a block diagram for explaining the structure which connects the signal generation apparatus 2 to the coated conductors La and Lb by the current detection probes PLc and PLd.

  Hereinafter, embodiments of a signal generation device and a signal reading system will be described with reference to the accompanying drawings.

  The signal generation device generates a code specifying signal capable of specifying a code corresponding to the logic signal based on a two-wire differential voltage type logic signal transmitted through a communication path including a pair of covered conductors. Generate. Further, this signal reading system is a system that specifies a code corresponding to the logic signal based on the code specifying signal generated by the signal generation device, and specifies a code string composed of the specified code. Therefore, various "two-wire differential voltage logic signals" conforming to various communication protocols such as "CAN protocol", "CAN FD", "FlexRay (registered trademark)", and small amplitude and low consumption by "LVDS" Various "two-wire differential voltage-type logic signals" conforming to various communication protocols capable of power communication can be targeted. In this case, in the “CAN communication serial bus” of the “CAN protocol” and “CAN FD”, the “high-potential-side signal line (CANH) / low-potential-side signal line (CANL)” transmits “logic signal”. In the “Serial bus for FlexRay communication”, the “positive signal line (BP) / negative signal line (BM)” corresponds to “a pair of covered conductors for transmitting a logic signal”. In the "serial bus for performing LVDS communication", the "positive logic side signal line / negative logic side signal line" corresponds to "a pair of covered conductors for transmitting a logic signal". Further, since the signal reading system has a function of specifying a code and a code string corresponding to the above-described logic signal, as a result, the signal reading system also functions as an analyzer for detecting the logic signal transmitted to the communication path. Further, when it is configured to store the detected code string in the memory, it also functions as a recording device (recorder).

  In the following, as an example, for a “serial bus for CAN communication”, a series of CAN frames (sequences of codes indicated by logic signals of a two-wire differential voltage system) are transmitted from a serial bus (communication path) for CAN communication. (Hereinafter, also referred to as a code string)), a signal generation device and a signal reading system which are arranged and used between various electronic devices that operate by acquiring and operating the serial bus will be described as an example. Specifically, as an example, an example in which a logic signal is read from a communication path provided in an automobile and various processes using a corresponding code string (CAN frame) are executed in an external device (CAN communication-compatible device). Will be described.

  The signal reading system 1 illustrated in FIG. 1 is an example of a “signal reading system”, and includes a signal generation device 2 (an example of a “signal generation device”) and an encoding device 3 (an example of an “encoding device”). It is provided with. The signal reading system 1 reads a CAN frame (an example of a “logic signal transmitted through a communication path”) from a CAN communication serial bus SB (an example of a “communication path”) provided in an automobile. The CAN frame Cs (an example of a “code sequence corresponding to a logic signal”) that is the same as the read CAN frame is configured to be output to various CAN communication-compatible devices (as a so-called CAN bus analyzer). .

  In this case, at the time of communication conforming to the CAN protocol via the serial bus SB, as shown in FIG. 2, a logic signal Sa representing each code constituting the CAN frame (code string) is transmitted by two lines on the serial bus SB. Two voltage signals Va (hereinafter also referred to as a voltage signal Va itself for easy understanding) of a voltage signal transmitted to the covered conductor La as a signal line of CANHHigh (CANH) among the signal lines. Between the voltage signal Vb of the voltage signal transmitted to the covered conductor Lb as the signal line of CANLow (CANL) (hereinafter, also referred to as the voltage signal Vb for easy understanding). Is transmitted as a differential signal which is a potential difference (Va−Vb).

  Since the principle of transmission of the logic signal Sa via the serial bus SB is publicly known, detailed description is omitted, but the specifications of the voltage signal Va of CANHHigh (CANH) and the voltage signal Vb of CANLow (CANL) are simply described. Will be described. As shown in FIG. 6, the voltage signals Va and Vb are voltage signals that change in the opposite direction from the base voltage (+2.5 V). When the voltage signal Va is the base voltage, the voltage signal Vb is also changed. The code Cs (logical value) constituting the CAN frame transmitted during this period in which the voltage of the same base becomes the same over the same period and the potential difference (Va−Vb) becomes zero (minimum) indicates “1”. Become. On the other hand, when the voltage signal Va is a specified voltage (+3.5 V) higher than the base voltage, the voltage signal Vb is conversely over the same period and the other specified voltage (+1) lower than the base voltage. .5 V), the code Cs (logical value) constituting the CAN frame transmitted during this period in which the potential difference (Va−Vb) is the maximum indicates “0”. Further, illustration and description of “SG”, which is a signal line serving as a reference potential for transmitting a differential signal on the serial bus SB, and a signal line and a power line provided for purposes other than transmission of the differential signal Is omitted.

  As shown in FIG. 2, the signal generation device 2 includes electrode units 11a and 11b, impedance elements 12a and 12b, a differential amplifier 13, and a signal generator 14. Further, the signal generation device 2 is a two-wire differential voltage type transmission system that transmits a signal via a serial bus SB including a pair of covered conductors La and Lb (hereinafter, also referred to as “covered conductor L” unless otherwise specified). Based on the logic signal Sa (specifically, the voltage signal Va on the covered conductor La side and the voltage signal Vb on the covered conductor Lb side), as shown in FIG. 6, a code Cs (potential difference ( A code specifying signal Sf capable of specifying a code Cs (“1” or “0”) corresponding to the differential signal Va−Vb) is generated.

  The electrode portions 11a and 11b have the same configuration including the electrode 21 and the shield 22. Each of the electrode portions 11a and 11b is configured to be detachable from any one of the covered conductors La and Lb. For easy understanding, it is assumed that the electrode portion 11a is attached to the covered conductor La and the electrode portion 11b is attached to the covered conductor Lb, as shown in FIGS. Further, the electrodes 21a and 11b are arranged such that the electrode 21 contacts (contacts) an insulating coating portion (hereinafter, also simply referred to as a “covering portion”) of the coating conductor L when the electrode portion 11a and 11b are attached to the corresponding coating conductor L. Is configured. With this configuration, the electrodes 21 of the electrode portions 11a and 11b are capacitively coupled in a non-contact state (that is, a metal non-contact state) without contacting the metal portions (core wires) of the corresponding covered conductors La and Lb. . Further, in a state where each of the electrode portions 11a and 11b is attached to the corresponding covered conductors La and Lb, the shield 22 includes the contact portions of the electrodes 21 in the covering portions of the covered conductors La and Lb including the electrodes 21. The covering prevents the electrode 21 from being capacitively coupled to a metal part other than the metal part of the corresponding covered conductor La.

  In this example, the impedance element 12a (hereinafter, also referred to as a first impedance element 12a) includes, as an example, a resistor 31a and a capacitor 32a connected in parallel to the resistor 31a. The impedance element 12b) includes a resistor 31b (having the same resistance value as the resistor 31a) and a capacitor 32b (having the same capacitance value as the capacitor 32a) connected in parallel to the resistor 31b. In the impedance element 12a as the first impedance element, the resistor 31a is constituted by a resistor having a high resistance value (a high impedance resistance of at least several MΩ), and one end (one end of the impedance element 12a) is a shielded cable (a coaxial cable). ) CBa (hereinafter also referred to as a first shielded cable CBa) is connected to the electrode 21 (hereinafter also referred to as one electrode 21) of the electrode portion 11a via a core wire, and the other end (the other end of the impedance element 12a) is connected to a signal. It is connected to a portion (ground G) of the reference potential in the generator 2. In the impedance element 12b as the second impedance element, the resistor 31b is formed of a resistor having a high resistance value (a high impedance resistance of at least several MΩ), and one end (one end of the impedance element 12b) is a shielded cable ( A coaxial cable) CBb (hereinafter, also referred to as a second shielded cable CBb) is connected to the electrode 21 (hereinafter, the other electrode 21) of the electrode portion 11b via a core wire, and the other end (the other end of the impedance element 12b) is grounded. Connected to G. In the shield of the shielded cable CBa, the end on the electrode portion 11a side is connected to the shield 22 on the electrode portion 11a, and the end on the impedance element 12a side is connected to the ground G. In the shield of the shielded cable CBb, the end on the electrode portion 11b side is connected to the shield 22 on the electrode portion 11b, and the end on the impedance element 12b side is connected to the ground G.

  With this configuration, the voltage of the impedance element 12a changes according to the voltage Va of the voltage signal Va transmitted to the one covered conductor La that is capacitively coupled to the electrode 21 of the electrode portion 11a (the voltage Va is equal to the voltage of the base described above). A first voltage signal Vc1 is generated between both ends. The first voltage signal Vc1 changes to a low voltage when the voltage is high, and changes to a high voltage when the voltage Va is the specified voltage of the high voltage. The voltage of the impedance element 12b changes in accordance with the voltage Vb of the voltage signal Vb transmitted to the other coated conductive wire Lb that is capacitively coupled to the electrode 21 of the electrode portion 11b (the voltage Vb is a voltage of the base voltage). The second voltage signal Vc2 is generated between both ends when the voltage Vb becomes a high voltage and the voltage Vb changes to a low voltage when the voltage Vb is the specified voltage of the low voltage. Further, since both the first voltage signal Vc1 and the second voltage signal Vc2 are signals detected by capacitive coupling, changes in the voltage signals Va and Vb (changes in the pulse lengths of the voltage signals Va and Vb, , This signal changes in DC level (DC component) in accordance with the change in the pulse density).

  Note that the impedance elements 12a and 12b are not limited to the above configuration (a parallel circuit of the resistor 31a and the capacitor 32a, and a parallel circuit of the resistor 31b and the capacitor 32b). For example, a circuit having only the resistors 31a and 31b or a circuit having only the capacitors 32a and 32b may be used. The capacitors 32a and 32b can be composed of discrete components, and the wiring capacitances (core and shield) of shielded cables (coaxial cables) CBa and CBb that connect the impedance elements 12a and 12b and the corresponding electrodes 21 are formed. (Capacitor formed between them).

  The differential amplifier 13 receives the first voltage signal Vc1 and the second voltage signal Vc2, and outputs a single-ended signal Vd whose voltage changes according to a difference voltage (Vc1−Vc2) between the voltage signals Vc1 and Vc2. .

  Specifically, as shown in FIG. 2, the differential amplifier 13 includes a differential amplifier circuit 41 and a waveform shaping circuit 42, and the differential amplifier circuit 41 and the waveform shaping circuit 42 have a transformer as described later. Instead, it is mainly composed of an operational amplifier and a comparator, so that it is configured as a transformerless differential amplifier. In this example, as an example, the differential amplifier circuit 41 includes three operational amplifiers 41a, 41b, and 41c operating at a positive power supply voltage Vcc and a negative power supply voltage Vee (for example, ± 10 V), and seven resistors 41d and 41e. , 41f, 41g, 41h, 41i, and 41j, and is configured as an instrumentation amplifier as a whole. In the differential amplifier 41, the operational amplifier (first operational amplifier) 41a has a non-inverting input terminal connected to one end of the impedance element 12a, and a resistor 41d (feedback resistor) between the inverting input terminal and the output terminal. It is connected. The operational amplifier (second operational amplifier) 41b has a non-inverting input terminal connected to one end of the impedance element 12b, and a resistor 41e (a feedback resistor having the same resistance value as the resistor 41d) connected between the inverting input terminal and the output terminal. Have been. The inverting input terminals of the operational amplifier 41a and the operational amplifier 41b are connected via a resistor 41f (common input resistance of the operational amplifier 41a and the operational amplifier 41b). The operational amplifier (third operational amplifier) 41c has an inverting input terminal connected to the output terminal of the operational amplifier 41a via a resistor 41g (one input resistor), and a non-inverting input terminal having a resistor 41h (having the same resistance value as the resistor 41g). Is connected to the output terminal of the operational amplifier 41b via the other input resistor), a resistor 41i (feedback resistor) is connected between the inverting input terminal and the output terminal, and the inverting input terminal is connected to the resistor 41j (the resistor 41i). It is connected to the ground G via the same resistance value) and functions as a differential amplifier that amplifies and outputs a difference between output signals output from the operational amplifiers 41a and 41b.

  With this configuration, the differential amplifier circuit 41 inverts and amplifies the difference voltage (Vc1−Vc2) between the voltage signals Vc1 and Vc2 at a known amplification factor defined by the resistance values of the resistors 41d, 41e, 41f, 41g, and 41i. Then, a difference signal Vd0 as a voltage signal is output. The difference signal Vd0 is on the high potential side during the period when the code Cs (“1”) constituting the CAN frame (code string) is transmitted to the serial bus SB (when the voltages Va and Vb are both base voltages). During the period in which the code Cs (“0”) constituting the CAN frame is transmitted (when the voltage Va is the specified high voltage and the voltage Vb is the specified low voltage) Voltage signal. Further, as described above, since each of the voltage signals Vc1 and Vc2 is a signal whose DC level changes according to the change of the voltage signals Va and Vb, the difference signal Vd0 generated based on the voltage signals Vc1 and Vc2. This signal is also a signal whose DC level (DC component) changes although the change in the DC level is reduced in the differential amplifier circuit 41.

  The differential amplifier circuit 41 employs a configuration in which the input resistance connected to each inverting input terminal of the operational amplifier 41a and the operational amplifier 41b is one common resistor 41f (a configuration as an instrumentation amplifier). However, the present invention is not limited to this configuration. For example, as shown in FIG. 3, a resistor 41fa is connected as an individual input resistor to an inverting input terminal of an operational amplifier 41a, and the inverting input terminal is connected via the resistor 41fa. The input terminal is connected to the ground G, the resistor 41fb (the same resistance value as the resistor 41fa) is connected as an individual input resistor to the inverting input terminal of the operational amplifier 41b, and the inverting input terminal is grounded via the resistor 41fb. A configuration for connecting to G can also be adopted. Also in this configuration, the differential amplifier circuit 41 amplifies the differential voltage (Vc1−Vc2) at a known amplification factor defined by the resistance values of the resistors 41d, 41e, 41fa, 41fb, 41g, and 41i. , And outputs the difference signal Vd0.

  Further, in the differential amplifier circuit 41 shown in FIG. 3, the operational amplifier 41a and the operational amplifier 41b are configured to amplify not only the AC component but also the DC component of each of the voltage signals Vc1 and Vc2. When the DC component is large, the output signal output from each output terminal of the operational amplifier 41a and the operational amplifier 41b may be saturated. In order to reduce the saturation of the output signal, a capacitor is connected in series with a resistor 41fa connected between the inverting input terminal of the operational amplifier 41a and the ground G (reference potential) as in a differential amplifier circuit 41 shown in FIG. 41k, and a configuration in which a capacitor 41m is connected in series to a resistor 41fb connected between the inverting input terminal of the operational amplifier 41b and the ground G. The operational amplifier 41a and the operational amplifier 41b having this configuration function as AC amplifiers that amplify and output only the AC component without amplifying the DC components of the voltage signals Vc1 and Vc2, and thus output the output signal from the output terminal. It is possible to greatly reduce the occurrence of a situation where the signal is saturated due to the DC component of each of the voltage signals Vc1 and Vc2.

  The waveform shaping circuit 42 receives the difference signal Vd0 and converts the difference signal Vd0 into a peak-to-peak voltage (peak-to-peak voltage) equivalent to the peak-to-peak voltage (peak-to-peak voltage) of the AC component of the difference signal Vd0. In addition, a single-ended signal Vd in which one of the high-potential-side voltage (voltage in the high-voltage period) and the low-potential-side voltage (voltage in the low-voltage period) is defined as a predetermined target constant voltage Vtg (Waveform shaping) and output. With this configuration, the waveform shaping circuit 42 sets one of the voltages of the single-ended signal Vd to the reference potential (the voltage when the peak-to-peak voltage is zero volts; in this example, the target constant voltage Vtg) of the signal. It can also be referred to as a fixed reference potential fixing circuit.

  As an example, as shown in FIG. 5, the waveform shaping circuit 42 includes an input unit 42a to which the differential signal Vd0 is input, an output unit 42b to which the single-ended signal Vd is output, a capacitor 42c, a third impedance element 42d, and a diode. A series circuit SC including a fourth impedance element 42e and a switch 42f connected in series without being included, and a comparator and the like, and switches the switch 42f from the on state to the off state and from the off state to the on state. A switch control circuit SWC that outputs a control pulse signal Vct is provided.

  Specifically, the capacitor 42c has one end connected to the input unit 42a and the other end connected to the output unit 42b. As an example, the third impedance element 42d is configured by a resistor (a resistor circuit configured by connecting one resistor or a plurality of resistors in series or in parallel), and one end is connected to the other end of the capacitor 42c. At the same time, the target constant voltage Vtg is applied to the other end, and the target constant voltage Vtg is supplied to the other end (and the output unit 42b) of the capacitor 42c. Note that the target constant voltage Vtg is defined in advance as any one constant voltage lower than the positive power supply voltage Vcc and higher than the negative power supply voltage Vee. As the third impedance element 42d, the simplest configuration may be a configuration including only a resistor as described above, but is not limited to this configuration. Although not shown, the third impedance element 42d may be configured to use an inductor together with or instead of the resistor. Note that the third impedance element 42d has an overall impedance value (a resistance value when configured only with a resistor) greater than an impedance value (a resistance value when configured only with a resistance) of the fourth impedance element 42e. It is specified to a value (for example, about several kΩ to several hundred kΩ when only the resistance is used).

  As shown in FIG. 5, the series circuit SC includes a fourth impedance element 42e and a switch 42f connected in series, and has one end connected to the other end (and the output unit 42b) of the capacitor 42c. The target constant voltage Vtg is applied to the other end. With this configuration, when the switch 42f is turned on by the control pulse signal Vct output from the switch control circuit SWC, the series circuit SC outputs the other end of the capacitor 42c of the target constant voltage Vtg (and the output unit 42b). ) Is executed, and when the state is shifted to the off state, the application of the target constant voltage Vtg to the other end of the capacitor 42c (and the output unit 42b) is stopped.

  The switch 42f has a low impedance in the ON state, and changes the target constant voltage Vtg applied to the other end of the series circuit SC to the fourth impedance element 42e (for example, with respect to the resistance value of the entire third impedance element 42d). Any semiconductor switch that can be applied to the output unit 42b via a resistor having a sufficiently small resistance value) can be configured with various semiconductor switches such as an analog switch, a bipolar transistor, and a field-effect transistor. In this example, the switch 42f is turned on when the control pulse signal Vct is at a high potential, and is turned off when the control pulse signal Vct is at a low potential. (Highly active).

  In the present example, as an example, the fourth impedance element 42e applies the low-impedance target constant voltage Vtg applied to the other end to the other end (and the output unit 42b) of the capacitor 42c when the switch 42f is on. And a resistor defined to have a sufficiently low resistance value that can be supplied by the resistor. However, the resistance value of the fourth impedance element 42e is affected by this voltage change when the differential signal Vd0 falls or rises, even when the switch 42f is in the ON state (the supply state of the target constant voltage Vtg). , The voltage at the other end of the capacitor 42c may slightly fluctuate from the target constant voltage Vtg (the voltage may slightly decrease momentarily when the difference signal Vd0 falls, or slightly increase when the difference signal Vd0 rises). It is specified to a value (for example, a resistance value of about several tens of Ω to several tens of Ω). Further, as the simplest configuration, the fourth impedance element 42e can be configured by one resistor as shown in FIG. 5, but may be configured by connecting a plurality of resistors in series or in parallel. . Although not shown, the fourth impedance element 42e may be configured to use an inductor together with or instead of the resistor. Further, the order of arrangement of the fourth impedance element 42e and the switch 42f in the series circuit SC may be reverse to the order shown in FIG.

The switch control circuit SWC is configured without including a diode. In the configuration illustrated in FIG. 5, as illustrated in FIG. 6, the AC component Vd0 _ac (see FIG. 6) of the difference signal Vd0 input to the input unit 42a is input. In order to shift the switch 42f to the ON state during the low voltage period _TL , the potential becomes high (high level; for example, a voltage level near the positive power supply voltage Vcc for the comparator 42g described later), and the high voltage period in the AC component Vd0 _ac . a low potential (low level. for example, the voltage level in the vicinity of the negative power source voltage Vee of the comparator 42g to be described later) to the T _H shifts the switch 42f in the oFF state and outputs a control pulse signal Vct which becomes.

Specifically, as shown in FIG. 5, the switch control circuit SWC includes one comparator 42g operating with the positive power supply voltage Vcc and the negative power supply voltage Vee, and a DC constant voltage (bias voltage) Vbi1 (≠ 0 volt). It has one reference power source 42h for outputting. Further, the reference power supply 42h has the negative electrode connected to the target constant voltage Vtg, so that the voltage (Vtg + Vbi1) obtained by adding the DC constant voltage Vbi1 to the target constant voltage Vtg is used as the reference voltage (first reference voltage) Vr1. Output from The DC constant voltage Vbi1 is defined as a voltage value of, for example, several percent to ten and several percent of the peak-to-peak voltage Vp (see FIG. 6) for the AC component Vd0 _ac of the difference signal Vd0. Therefore, reference voltage Vr1 is defined as a voltage slightly higher than target constant voltage Vtg. The comparator 42g outputs the control pulse signal Vct from the output terminal when the inverted input terminal is connected to the other end of the capacitor 42c and the reference voltage Vr1 is input to the non-inverted input terminal. It is configured.

The control pulse signal Vct, switch 42f is, the AC component shifts to the ON state to the low voltage period _{T L} in _{Vd0 ac,} the AC component _Vd0 high voltage period in _{ac T H} waveform shaping when the transition to the OFF state to the circuit 42 Will be described. 6 shows the difference signal Vd0 in a state where the DC component A of the difference signal Vd0 greatly fluctuates within one cycle of the AC component Vd0 _ac of the difference signal Vd0 for easy understanding. Is that the DC component A fluctuates in a sufficiently long cycle with respect to one cycle of the AC component Vd0 _ac (usually several μs or less) due to superposition of low frequency noise of less than 100 Hz such as a commercial frequency. Therefore, the DC component A is described as being substantially constant within one cycle of the AC component Vd0 _ac of the difference signal Vd0. Further, a peak-to-peak voltage of the AC component _{Vd0 ac} by symbol Vp, the voltage value of the difference signal Vd0 in the high voltage period _{T H,} the DC component higher by a voltage Vp1 than A, the difference signal in the low voltage period _{T L} The voltage value of Vd0 is lower than DC component A by voltage Vp2. Further, sag occurring in the single-ended signal Vd is ignored.

First, in the low voltage period _TL in which the switch 42f is turned on, the target constant voltage Vtg is supplied from the series circuit SC at a low impedance via the fourth impedance element 42e, so that the other end of the capacitor 42c (and The voltage of the output section 42b), that is, the single-ended signal Vd is defined as the target constant voltage Vtg as shown in FIG. Further, the voltage at one end of the capacitor 42c to which the difference signal Vd0 is applied (the end on the side of the input unit 42a) is the voltage (A-Vp2) because it is in the low voltage period _TL . Thus, the capacitor 42c is charged to the voltage (A-Vp2-Vtg) when the voltage at one end is set to a positive voltage with reference to the voltage at the other end defined by the target constant voltage Vtg.

From this state, when it becomes a high voltage period T _H of the switch 42f is turned off, along with the supply of the target constant voltage Vtg of a series circuit SC is stopped, the one end of the capacitor 42c (input section 42a side end Part) becomes the voltage (A + Vp1). Accordingly, the voltage at the other end of the capacitor 42c (and the output unit 42b) is a voltage (A + Vp1- (A-Vp2-Vtg)) obtained by subtracting the voltage (A-Vp2-Vtg) from the voltage (A + Vp1), that is, the voltage. (Vp1 + Vp2 + Vtg). The voltage (Vp1 + Vp2) is a peak-to-peak voltage Vp of the AC component Vd0 _ac . Accordingly, the voltage (Vp1 + Vp2 + Vtg), which is the voltage at one end of the capacitor 42c (the end on the input unit 42a side), that is, the single-ended signal Vd is defined as the voltage (Vp + Vtg) as shown in FIG. .

From the above, the waveform shaping circuit 42 shown in FIG. 5 is configured such that the switch control circuit SWC alternately shifts the switch 42f between the ON state and the OFF state, thereby obtaining the difference signal Vd0 (peak to peak) as shown in FIG. A signal obtained by superimposing the DC component A on the AC component Vd0 _ac of the voltage Vp is converted into a peak-to-peak voltage Vp equivalent to the peak-to-peak voltage Vp of the AC component Vd0 _ac of the difference signal Vd0, and its lower potential side voltage (lower The voltage during the voltage period _TL ) is shaped (waveform shaped) into a single-ended signal Vd defined by the target constant voltage Vtg and output from the output unit 42b. That is, the waveform shaping circuit 42 has a function of removing the DC component A superimposed on the difference signal Vd0 (that is, removing low-frequency noise). As a result, the waveform shaping circuit 42 outputs a signal whose voltage changes in response to the change of the code Cs constituting the CAN frame, that is, the voltage of the signal becomes low potential (target) while the code Cs is “0”. A constant voltage Vtg), and outputs a single-ended signal Vd in which the voltage of the signal becomes a high potential during a period when the code Cs is “1”.

  Next, an operation in which the comparator 42g of the switch control circuit SWC outputs the above-described control pulse signal Vct will be described.

When AC component _{Vd0 ac} is switched from the low voltage period _{T L} to the high voltage period _{T H} (at the rise of the AC component _{Vd0 ac),} the target constant voltage with low impedance via a fourth impedance element 42e series circuit SC Vtg Is applied to the output portion 42b (the voltage at the other end of the capacitor 42c; that is, the voltage of the single-ended signal Vd) is changed from the target constant voltage Vtg by the influence of the change in the voltage of the AC component Vd0 _ac. It rises momentarily and exceeds the reference voltage Vr1. Therefore, the comparator 42g shifts the control pulse signal Vct from the high potential to the low potential as shown in FIG. In this case, in the series circuit SC, since the switch 42f is turned off, the application of the target constant voltage Vtg to the output unit 42b by the series circuit SC is stopped, and the voltage of the single-ended signal Vd becomes the voltage (Vp + Vtg). Transition. As a result, thereafter, the voltage of the single-ended signal Vd is maintained at a level higher than the reference voltage Vr1. During the low voltage period _TL of the AC component Vd0 _ac, the voltage of the single-ended signal Vd becomes the target constant voltage Vtg as described above, and the inverting input terminal of the comparator 42g also becomes the target constant voltage Vtg. However, since the reference voltage Vr1 (= Vtg + Vbi1) input to the non-inverting input terminal of the comparator 42g is higher than the target constant voltage Vtg (not the same voltage), the comparator 42g controls the high potential. The output of the pulse signal Vct is continued (that is, the application of the target constant voltage Vtg from the series circuit SC to the output unit 42b is continued).

Also, the AC component _{Vd0 ac} from high voltage period _{T H} when switching to the low voltage period _{T L} (fall time of the AC component _{Vd0 ac),} the voltage of the single-ended signal Vd, the voltage drop of the AC component _{Vd0 ac} , The voltage drops from the voltage (Vp + Vtg) and falls below the reference voltage Vr1. Therefore, the comparator 42g shifts the control pulse signal Vct from the low potential to the high potential as shown in FIG. In this case, in the series circuit SC, the switch 42f shifts to the ON state. Therefore, the application of the target constant voltage Vtg to the output unit 42b by the serial circuit SC is started, and thereafter, the voltage of the single-ended signal Vd is maintained at the target constant voltage Vtg lower than the reference voltage Vr1.

As an example, as shown in FIG. 5, the signal generating unit 14 outputs one comparator 14a operating with the positive power supply voltage Vcc and the negative power supply voltage Vee, and a DC constant voltage (bias voltage) Vbi2 (≠ 0 volt). It is configured to have one reference power supply 14b. Further, the reference power supply 14b outputs the voltage (Vtg + Vbi2) obtained by adding the DC constant voltage Vbi2 to the target constant voltage Vtg as the threshold voltage Vth from the positive electrode side when the negative electrode side is connected to the target constant voltage Vtg. The DC constant voltage Vbi2 is defined as a voltage value of, for example, several percent to several tens of percent of the peak-to-peak voltage Vp for the AC component Vd0 _ac of the difference signal Vd0. Therefore, the threshold voltage Vth is defined as a voltage slightly higher than the target constant voltage Vtg. Note that the magnitude relationship between the threshold voltage Vth and the above-described reference voltage Vr1 may be the same or may be higher (in FIG. 6, as an example, when the reference voltage Vr1 is the threshold voltage Vr1). Voltage Vth).

  The comparator 14a compares the single-ended signal Vd output from the output unit 42b with the threshold voltage Vth when the non-inverting input terminal is connected to the output unit 42b and the threshold voltage Vth is input to the inverting input terminal. Thus, the code specifying signal Sf is output from the output terminal. As described above, since the threshold voltage Vth is specified to be slightly higher than the target constant voltage Vtg, the signal generation unit 14 including the comparator 14a outputs the single-ended signal Vd ( A signal whose peak-to-peak voltage is the voltage Vp and whose lower potential side voltage is defined as the target constant voltage Vtg) is reliably binarized with the threshold voltage Vth, and the CAN frame transmitted via the serial bus SB is converted. A code specifying signal Sf that has a high potential (maximum output voltage of the comparator 14a) during a period in which the constituent code Cs is “1” and has a low potential (minimum output voltage of the comparator 14a) in a period during which the code Cs is “0”. Is generated and output.

  The target constant voltage Vtg is defined as any one constant voltage lower than the positive power supply voltage Vcc and higher than the negative power supply voltage Vee, as described above. However, the waveform shaping circuit 42 and the signal generation circuit having the configuration shown in FIG. In the unit 14, the potential is normally set to the potential of the ground G (zero volt) in the signal generating device 2. Therefore, the waveform shaping circuit 42 outputs the single-ended signal Vd whose peak-to-peak voltage is Vp and whose low-potential side voltage is defined as the target constant voltage Vtg (zero volt).

The waveform shaping circuit 42 receives the configuration of FIG. 5 described above, that is, receives the difference signal Vd0 and converts the difference signal Vd0 into a peak-to-peak voltage Vp equivalent to the peak-to-peak voltage Vp of the AC component of the difference signal Vd0. The present invention is not limited to the configuration in which Vp and its lower potential side voltage (voltage in the low voltage period _TL ; bottom voltage) is shaped (waveform shaped) into a single-ended signal Vd defined by the target constant voltage Vtg and output. For example, by configuring the waveform shaping circuit 42 as shown in FIG. 7, the peak-to-peak voltage Vp equivalent to the peak-to-peak voltage Vp of the AC component of the difference signal Vd0 and the high-potential-side voltage (high-voltage period) voltage of T _H. Top voltage) may be configured to output the shaping (waveform shaping) a single-ended signal Vd as defined in the target constant voltage Vtg.

  Hereinafter, the waveform shaping circuit 42 and the signal generator 14 shown in FIG. 7 will be described. Note that the same components as those of the waveform shaping circuit 42 and the signal generating unit 14 shown in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted.

  As an example, the waveform shaping circuit 42 includes an input unit 42a to which the difference signal Vd0 is input, an output unit 42b to which the single-ended signal Vd is output, a capacitor 42c, a third impedance element 42d, and a fourth impedance element without including a diode. And a switch control circuit SWC that outputs a control pulse signal Vct for switching the switch 42f from the on state to the off state and from the off state to the on state. It has.

  Specifically, the third impedance element 42d has, as an example, one resistor (one end is connected to the other end of the capacitor 42c, and the target constant voltage Vtg is applied to the other end as shown in FIG. Resistance).

As shown in FIG. 7, the switch control circuit SWC has one comparator 42g operating with the positive power supply voltage Vcc and the negative power supply voltage Vee, and one reference power supply 42h outputting the DC constant voltage (bias voltage) Vbi1. It is configured. In addition, the reference power supply 42h outputs the voltage (Vtg-Vbi1) obtained by subtracting the DC constant voltage Vbi1 from the target constant voltage Vtg as the reference voltage Vr1 from the negative electrode side when the positive electrode side is connected to the target constant voltage Vtg. Since the DC constant voltage Vbi1 is regulated to a voltage value of, for example, several percent to several tens of percent of the peak-to-peak voltage Vp, the reference voltage Vr1 is regulated to a voltage slightly lower than the target constant voltage Vtg. As shown in FIG. 8, the comparator 42g has an AC component Vd0 of the difference signal Vd0 when the non-inverting input terminal is connected to the other end of the capacitor 42c and the reference voltage Vr1 is input to the inverting input terminal. becomes a low potential in order to shift the switch 42f in the oFF state to the low voltage period T _L in _ac, high voltage and comprising control pulse signal to the high voltage period T _H of the AC component Vd0 _ac in order to shift the switch 42f in the oN state Vct is output.

The control pulse signal Vct, switch 42f is, the AC component shifts to the OFF state to the low voltage period _{T L} in _{Vd0 ac,} the AC component _{Vd0 ac} at high voltage period _T waveform when the transition to the ON state to the _H shaping circuit 42 Will be described. Note that FIG. 8 illustrates the difference signal Vd0 in a state where the DC component A of the difference signal Vd0 greatly fluctuates within one cycle of the AC component Vd0 _ac of the difference signal Vd0 for easy understanding. In other words, the DC component A fluctuates in a sufficiently long cycle with respect to one cycle of the AC component Vd0 _ac (generally, several μs or less). Therefore, the description will be made on the assumption that the DC component A is substantially constant within one cycle of the AC component Vd0 _ac of the difference signal Vd0. Further, a peak-to-peak voltage of the AC component _{Vd0 ac} by symbol Vp, the voltage value of the difference signal Vd0 in the high voltage period _{T H,} the DC component higher by a voltage Vp1 than A, the difference signal in the low voltage period _{T L} The voltage value of Vd0 is lower than DC component A by voltage Vp2. Further, sag occurring in the single-ended signal Vd is ignored.

First, the high voltage period T _H switch 42f is turned on, by the target constant voltage Vtg series circuit SC is supplied with low impedance via a fourth impedance element 42e, the other end of the capacitor 42c (and The voltage of the output section 42b), that is, the single-ended signal Vd is defined as the target constant voltage Vtg as shown in FIG. Further, the voltage of one end of the capacitor 42c (an end of the input portion 42a side) of the differential signal Vd0 is applied, since a high voltage period _{T H,} and has a voltage (A + Vp1). Thus, the capacitor 42c is charged to the voltage (A + Vp1-Vtg) when the voltage at one end is set to a positive voltage with reference to the voltage at the other end defined by the target constant voltage Vtg.

When a low voltage period _TL in which the switch 42f is turned off from this state is reached, the supply of the target constant voltage Vtg from the series circuit SC is stopped, and one end of the capacitor 42c (the end on the side of the input unit 42a) is stopped. Part) becomes the voltage (A-Vp2). Accordingly, the voltage at the other end of the capacitor 42c (and the output unit 42b) is a voltage (A-Vp2- (A + Vp1-Vtg)) obtained by subtracting the voltage (A + Vp1-Vtg) from the voltage (A-Vp2), that is, the voltage. (-(Vp1 + Vp2) + Vtg). The voltage (Vp1 + Vp2) is a peak-to-peak voltage Vp of the AC component Vd0 _ac . From this, the voltage (− (Vp1 + Vp2) + Vtg) which is the voltage at one end of the capacitor 42c (the end on the input unit 42a side), that is, the single-ended signal Vd is, as shown in FIG. 8, a voltage (−Vp + Vtg). ).

From the above, the waveform shaping circuit 42 shown in FIG. 7 is configured such that the switch control circuit SWC alternately shifts the switch 42f between the ON state and the OFF state, and as shown in FIG. 8, the difference signal Vd0 (peak to peak) A signal obtained by superimposing the DC component A on the AC component Vd0 _ac of the voltage Vp is converted into a peak-to-peak voltage Vp equivalent to the peak-to-peak voltage Vp of the AC component Vd0 _ac of the difference signal Vd0, and its high-potential side voltage (high voltage). and shaping (waveform shaping) a single-ended signal Vd voltage) is defined in the target constant voltage Vtg of the voltage period T _H, that is, from the output portion 42b by removing the effects of changes in the DC component a. As a result, the waveform shaping circuit 42 changes the voltage of the signal corresponding to the change of the code Cs constituting the CAN frame, that is, the voltage of the signal becomes low potential while the code Cs is “0”. During the period in which the code Cs is "1", a single-ended signal Vd in which the signal voltage becomes a high potential (target constant voltage Vtg) is output.

  The operation in which the comparator 42g of the switch control circuit SWC outputs the control pulse signal Vct will be described.

AC component _{Vd0 ac} from high voltage period _{T H} when switching to the low voltage period _{T L} (fall time of the AC component _{Vd0 ac),} the target constant voltage with low impedance via a fourth impedance element 42e series circuit SC The voltage of the output section 42b to which Vtg is applied (the voltage of the other end of the capacitor 42c; that is, the voltage of the single-ended signal Vd) is affected by the change in the voltage of the AC component Vd0 _ac , and the target constant voltage Vtg. And instantaneously drops below the reference voltage Vr1. Therefore, the comparator 42g shifts the control pulse signal Vct from the high potential to the low potential as shown in FIG. In this case, in the serial circuit SC, the switch 42f is turned off, so that the application of the target constant voltage Vtg to the output unit 42b by the serial circuit SC is stopped, and the voltage of the single-ended signal Vd becomes the voltage (−Vp + Vtg). Move to As a result, thereafter, the voltage of the single-ended signal Vd is maintained at a level lower than the reference voltage Vr1. Note that when the high-voltage period T _H of the AC component Vd0 _ac, the voltage of the single-ended signal Vd as described above becomes the target constant voltage Vtg, the non-inverting input terminal of the comparator 42g also becomes the target constant voltage Vtg. However, since the reference voltage Vr1 (= Vtg-Vbi1) input to the inverting input terminal of the comparator 42g is lower than the target constant voltage Vtg (not the same voltage), the comparator 42g is connected to the high potential The output of the control pulse signal Vct is continued (that is, the application of the target constant voltage Vtg from the series circuit SC to the output unit 42b is continued).

Further, when the AC component _{Vd0 ac} is switched from the low voltage period _{T L} to the high voltage period _{T H} (at the rise of the AC component _{Vd0 ac),} the voltage of the single-ended signal Vd is the increase in the voltage of the AC component _{Vd0 ac} Accordingly, the voltage rises from the voltage (−Vp + Vtg) and exceeds the reference voltage Vr1. Therefore, the comparator 42g shifts the control pulse signal Vct from a low potential to a high potential as shown in FIG. In this case, in the series circuit SC, the switch 42f shifts to the ON state. Therefore, the application of the target constant voltage Vtg to the output unit 42b by the serial circuit SC is started, and thereafter, the voltage of the single-ended signal Vd is maintained at the target constant voltage Vtg higher than the reference voltage Vr1.

  As an example, as shown in FIG. 7, the signal generation unit 14 includes one comparator 14a and one reference power supply 14b. In addition, the reference power supply 14b outputs a voltage (Vtg-Vbi2) obtained by subtracting the DC constant voltage Vbi2 from the target constant voltage Vtg as the threshold voltage Vth from the negative electrode side when the positive electrode side is connected to the target constant voltage Vtg. Since the DC constant voltage Vbi2 is regulated to a voltage value of, for example, several percent to several tens of percent of the peak-to-peak voltage Vp, the threshold voltage Vth is regulated to a voltage slightly lower than the target constant voltage Vtg.

  The comparator 14a compares the single-ended signal Vd output from the output unit 42b with the threshold voltage Vth when the non-inverting input terminal is connected to the output unit 42b and the threshold voltage Vth is input to the inverting input terminal. Thus, the code specifying signal Sf is output from the output terminal. As described above, since the threshold voltage Vth is specified to be slightly lower than the target constant voltage Vtg, the signal generation unit 14 including the comparator 14a outputs the single-ended signal Vd ( A signal whose peak-to-peak voltage is the voltage Vp and whose high-potential side voltage is defined as the target constant voltage Vtg) is surely binarized with the threshold voltage Vth, and the CAN frame transmitted via the serial bus SB is transmitted. A code specifying signal Sf that has a high potential (maximum output voltage of the comparator 14a) during a period in which the constituent code Cs is “1” and has a low potential (minimum output voltage of the comparator 14a) in a period during which the code Cs is “0”. Is generated and output.

  In the waveform shaping circuit 42 and the signal generation unit 14 having the configuration shown in FIG. 7, for example, the target constant voltage Vtg exceeds the potential of the ground G (zero volts) and is lower than the positive power supply voltage Vcc. In this case, the waveform shaping circuit 42 outputs the single-ended signal Vd having the peak-to-peak voltage Vp and the high-potential-side voltage defined by the positive target constant voltage Vtg.

  The waveform shaping circuit 42 having the configuration shown in FIG. 5 includes two resistors 42i and 42j connected in series like the waveform shaping circuit 42 having the configuration shown in FIG. End is connected to the output terminal of the comparator 42g, and the reference voltage Vr2 (second reference voltage) is applied to the other end (the end on the resistor 42j side), and the reference voltage Vr2 and the control pulse signal Vct are applied. Is provided as a reference voltage Vr1 at a non-inverting input terminal of the comparator 42g, and a resistance voltage dividing circuit 42k is provided to the comparator 42g to provide a hysteresis characteristic (the comparator 42g operates as a hysteresis comparator). Configuration). Note that the same components as those of the waveform shaping circuit 42 shown in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted.

  In the resistor voltage dividing circuit 42k, the resistance value of the resistor 42i is set to a value sufficiently larger than the resistance value of the resistor 42j (for example, the resistance 42i is about several MΩ when the resistance 42j is several tens kΩ). Further, in the resistance voltage dividing circuit 42k, a voltage (Vtg + Vbi1; a voltage equivalent to the reference voltage Vr1 in FIG. 5) output from the reference power supply 42h whose negative side is connected to the target constant voltage Vtg is used as a reference voltage Vr2 (target constant voltage). Although used as a voltage near Vtg (in this example, a voltage slightly higher than the target constant voltage Vtg), the present invention is not limited to this, and although not shown, a voltage near the target constant voltage Vtg is used. Alternatively, a configuration in which a voltage lower (slightly lower) than the target constant voltage Vtg is used as the reference voltage Vr2, or a configuration in which the target constant voltage Vtg itself is used as the reference voltage Vr2 can be adopted.

With this configuration, the waveform shaping circuit 42 having the configuration shown in FIG. 9, but when the AC component _{Vd0 ac} is switched from the low voltage period _{T L} to the high voltage period _{T H} (at the rise of the AC component _{Vd0 ac),} the series circuit SC From the output unit 42b (the voltage at the other end of the capacitor 42c; that is, the voltage of the single-ended signal Vd) to which the target constant voltage Vtg is applied with a low impedance via the fourth impedance element 42e. Under the influence of the voltage change of Vd0 _ac, the voltage instantaneously increases from the target constant voltage Vtg and exceeds the reference voltage Vr1. In this case, the resistor voltage dividing circuit 42k adds the voltage Vdv obtained by dividing the difference voltage (Vct−Vr2) between the high-potential control pulse signal Vct and the reference voltage Vr2 to the reference voltage Vr2, and It is output as a divided voltage Vr1. Therefore, in the comparator 42g, as compared with the comparator 42g shown in FIG. 5, the voltage of the output unit 42b is momentarily higher than the target constant voltage Vtg under the influence of the change in the voltage of the AC component Vd0 _ac (see FIG. When the voltage rises above the reference voltage Vr1, the control pulse signal Vct shifts from a high potential to a low potential.

Also, the AC component _{Vd0 ac} from high voltage period _{T H} when switching to the low voltage period _{T L} (fall time of the AC component _{Vd0 ac),} the voltage of the single-ended signal Vd, the voltage drop of the AC component _{Vd0 ac} , The voltage drops from the voltage (Vp + Vtg) and falls below the reference voltage Vr1. In this case, the resistance voltage dividing circuit 42k adds the voltage Vdv obtained by dividing the difference voltage (Vct-Vr2) between the low-potential control pulse signal Vct and the reference voltage Vr2 to the reference voltage Vr2, and It is output as a divided voltage Vr1. Therefore, in this comparator 42g, the voltage of the output section 42b is momentarily lower than the target constant voltage Vtg under the influence of the change in the voltage of the AC component Vd0 _ac as compared with the comparator 42g shown in FIG. When the control pulse signal Vct drops below the reference voltage Vr1 when the voltage drops (lower by the voltage Vdv than the configuration), the control pulse signal Vct shifts from a low potential to a high potential.

  In this manner, in the waveform shaping circuit 42 having the configuration shown in FIG. 9, the comparator 42g has a hysteresis characteristic (compared to the configuration in FIG. 5, the reference voltage Vr1 input to the non-inverting input terminal is centered on the reference voltage Vr2). (A hysteresis characteristic that varies with a hysteresis width of ± Vdv) and outputs the control pulse signal Vct, so that some noise is superimposed on the difference signal Vd0 input to the input unit 42a. However, the control pulse signal Vct can be generated while reducing the influence of the noise.

  Further, the waveform shaping circuit 42 having the configuration shown in FIG. 7 is configured by two resistors 42i and 42j connected in series like the waveform shaping circuit 42 having the configuration shown in FIG. The other end (the end on the resistor 42j side) is connected to the other end (and the output section 42b) of the capacitor 42c, and the other end (the end on the resistor 42j side) is connected to the output terminal of the comparator 42g. A configuration in which a resistor voltage dividing circuit 42k that outputs a voltage dividing pulse signal Vdp defined by the voltage and the voltage of the control pulse signal Vct to the non-inverting input terminal of the comparator 42g is provided, and the comparator 42g has hysteresis characteristics. Can also. Note that the same components as those of the waveform shaping circuit 42 shown in FIG. 7 are denoted by the same reference numerals, and redundant description will be omitted. The resistance voltage dividing circuit 42k has the same configuration as the resistance voltage dividing circuit 42k of the waveform shaping circuit 42 shown in FIG.

With this configuration, the waveform shaping circuit 42 having the configuration shown in FIG. 10, when the AC component _{Vd0 ac} switches from high voltage period _{T H} to the low voltage period _{T L} (fall time of the AC component _{Vd0 ac)} is a series circuit The voltage of the output section 42b (the voltage at the other end of the capacitor 42c; that is, the voltage of the single-ended signal Vd) to which the target constant voltage Vtg is applied with a low impedance from the SC via the fourth impedance element 42e is applied to the AC. Under the influence of the voltage change of the component Vd0 _ac, the voltage instantaneously drops from the target constant voltage Vtg and falls below the reference voltage Vr1. In this case, the resistance voltage dividing circuit 42k outputs a voltage dividing pulse signal Vdp obtained by dividing the difference voltage between the high-potential control pulse signal Vct and the voltage of the single-ended signal Vd to the non-inverting input terminal of the comparator 42g. . Therefore, in the comparator 42g, the voltage of the single-ended signal Vd (the voltage of the output unit 42b) is affected by the change in the voltage of the AC component Vd0 _ac , and the voltage of the target constant voltage Vtg is lower than that of the comparator 42g shown in FIG. When the voltage drops instantaneously (lower than the configuration of FIG. 7 by the voltage Vdv generated across the resistor 42j), the divided pulse signal Vdp to the non-inverting input terminal falls below the reference voltage Vr1, and The control pulse signal Vct is shifted from a high potential to a low potential.

Further, when the AC component _{Vd0 ac} is switched from the low voltage period _{T L} to the high voltage period _{T H} (at the rise of the AC component _{Vd0 ac),} the voltage of the single-ended signal Vd is the increase in the voltage of the AC component _{Vd0 ac} Accordingly, the voltage rises from the voltage (−Vp + Vtg) and exceeds the reference voltage Vr1. In this case, the resistance voltage dividing circuit 42k outputs a divided voltage signal Vdp obtained by dividing a difference voltage between the low-potential control pulse signal Vct and the voltage of the single-ended signal Vd to a non-inverting input terminal of the comparator 42g. . Therefore, in the comparator 42g, the voltage of the single-ended signal Vd (the voltage of the output unit 42b) is instantaneously higher than the voltage (−Vp + Vtg) as compared with the comparator 42g shown in FIG. When the voltage rises by the voltage Vdv generated across the resistor 42j), the divided pulse signal Vdp to the non-inverting input terminal exceeds the reference voltage Vr1, and the control pulse signal Vct shifts from a low potential to a high potential. Let it.

  In this manner, also in the waveform shaping circuit 42 having the configuration shown in FIG. 10, the comparator 42g has the hysteresis characteristic (compared to the configuration shown in FIG. 7, the voltage of the single-ended signal Vd is ± Vdv around the reference voltage Vr1). Only when the control pulse signal Vct changes from the high potential to the low potential and from the low potential to the high potential) after the potential exceeds the hysteresis width of the control pulse signal Vct. Therefore, even when some noise is superimposed on the difference signal Vd0 input to the input unit 42a, the control pulse signal Vct can be generated while reducing the influence of the noise. ing.

  In each of the waveform shaping circuits 42 shown in FIGS. 5, 7, 9, and 10, the series circuit SC is configured using a switch 42f provided separately from the comparator 42g. As shown, a configuration in which a comparator incorporating a PNP type open collector transistor as an output stage is used as the comparator 42g can be adopted in each of the waveform shaping circuits 42 shown in FIGS. In each waveform shaping circuit 42 adopting this configuration, as shown in FIG. 11, a target constant voltage Vtg is supplied to the emitter terminal of this output stage transistor via the fourth impedance element 42e, and the collector terminal of this transistor is The connected output terminal is connected to the output section 42b. This allows the transistor built in the comparator 42g to function as the switch 42f configuring the series circuit SC.

  Further, for example, as shown in FIG. 12, a configuration in which a comparator including an NPN open collector transistor as an output stage is used as the comparator 42g can be employed in each of the waveform shaping circuits 42 shown in FIGS. In each of the waveform shaping circuits 42 employing this configuration, as shown in FIG. 12, a target constant voltage Vtg is supplied to the emitter terminal of the transistor via the fourth impedance element 42e, and the collector terminal of the transistor is connected. The output terminal is connected to the output section 42b. This allows the transistor built in the comparator 42g to function as the switch 42f configuring the series circuit SC.

  By employing the configuration shown in FIGS. 11 and 12, the number of components of the waveform shaping circuit 42 can be reduced by the amount that the switch 42f can be omitted.

  Further, a three-state logic IC can be used as the switch 42f of the series circuit SC in each of the waveform shaping circuits 42 shown in FIGS. As an example, FIG. 13 illustrates a waveform shaping circuit 42 having a configuration using a three-state logic IC (hereinafter, also referred to as a logic IC 42f) as a switch 42f of the waveform shaping circuit 42 illustrated in FIG. Note that the same components as those of the waveform shaping circuit 42 shown in FIG. 9 are denoted by the same reference numerals, and redundant description will be omitted. In the waveform shaping circuit 42 shown in FIG. 13, a voltage corresponding to a low level in the logic IC 42f is defined as a target constant voltage Vtg, and the target constant voltage Vtg is input to the input terminal of the logic IC 42f, and the output terminal of the logic IC 42f is It is connected to the output section 42b via the fourth impedance element 42e, and the control pulse signal Vct is input to the control input terminal of the logic IC 42f. The logic IC 42f has a control input terminal of positive logic (high active. The logic IC 42f outputs the target constant voltage Vtg when the control pulse signal Vct is at a high potential, and sets the output to a high impedance state when the control pulse signal Vct is at a low potential. ) Logic IC.

  The serial circuit SC outputs the target constant voltage Vtg to the output unit 42b when the logic IC 42f is at the high potential of the control pulse signal Vct, and shifts the output to the high impedance state when the logic IC 42f is at the low potential of the control pulse signal Vct. As a result, the output of the target constant voltage Vtg to the output unit 42b is stopped.

The waveform shaping circuit 42 shown in FIG. 13 operates in the same manner as the waveform shaping circuit 42 shown in FIG. 9, and converts the difference signal Vd0 into the peak-to-peak AC component Vd0 _ac of the difference signal Vd0 as shown in FIG. A peak-to-peak voltage Vp equivalent to the voltage Vp, and a low-potential-side voltage thereof (a voltage in the low voltage period _TL ) is shaped (waveform shaped) into a single-ended signal Vd defined by the target constant voltage Vtg, and an output unit is formed. 42b. As a result, as shown in FIG. 6, the waveform shaping circuit 42 generates a signal whose voltage changes in response to the change of the code Cs constituting the CAN frame, that is, the signal during the period when the code Cs is “0”. Becomes a low potential (target constant voltage Vtg), and outputs a single-ended signal Vd in which the signal voltage becomes a high potential while the code Cs is “1”.

  Also, a three-state logic IC can be used as the switch 42f of the series circuit SC in each of the waveform shaping circuits 42 shown in FIGS. As an example, FIG. 14 shows a waveform shaping circuit 42 having a configuration using a logic IC 42f (a logic IC having the same positive logic as the logic IC 42f shown in FIG. 13) as the switch 42f of the waveform shaping circuit 42 shown in FIG. Note that the same components as those of the waveform shaping circuit 42 shown in FIG. 10 are denoted by the same reference numerals, and redundant description will be omitted. In the waveform shaping circuit 42 shown in FIG. 14, the voltage corresponding to the high level in the logic IC 42f is defined as the target constant voltage Vtg, and the target constant voltage Vtg is input to the input terminal of the logic IC 42f, and the output terminal of the logic IC 42f is It is connected to the output section 42b via the fourth impedance element 42e, and the control pulse signal Vct is input to the control input terminal of the logic IC 42f.

The waveform shaping circuit 42 shown in FIG. 14 operates similarly to the waveform shaping circuit 42 shown in FIG. 10, and as shown in FIG. 8, converts the difference signal Vd0 from the peak-to-peak of the AC component Vd0 _ac of the difference signal Vd0. voltage Vp equal to the peak-to-peak voltage Vp, and the high-potential voltage (voltage of the high voltage period T _H) is shaped into a single-ended signal Vd as defined in the target constant voltage Vtg (waveform shaping) to the output unit 42b. As a result, as shown in FIG. 8, the waveform shaping circuit 42 changes the voltage of the signal corresponding to the change of the code Cs constituting the CAN frame, that is, the signal during the period when the code Cs is “0”. Becomes a low potential, and outputs a single-ended signal Vd in which the voltage of the signal becomes a high potential (target constant voltage Vtg) during the period when the code Cs is “1”.

  By employing the configuration shown in FIGS. 13 and 14, an output buffer built in the integrated circuit can be used as the logic IC 42f.

Similarly to the waveform shaping circuit 42 shown in FIGS. 5, 9, and 13, the difference signal Vd0 is converted to a peak-to-peak voltage Vp equivalent to the peak-to-peak voltage Vp of the AC component Vd0 _ac of the difference signal Vd0, and to a low level. FIG. 15 shows a waveform shaping circuit that shapes (waveforms) the potential side voltage (voltage in the low voltage period _TL ) into a single-ended signal Vd defined by the target constant voltage Vtg and outputs the signal from the output unit 42b. The shaping circuit 42 may be employed. This waveform shaping circuit 42 uses a three-state logic IC as the switch 42f of the series circuit SC similarly to the waveform shaping circuit 42 shown in FIG. Explanation will be made while comparing. Note that the same components as those of the waveform shaping circuit 42 shown in FIG. 13 are denoted by the same reference numerals, and redundant description will be omitted.

  The waveform shaping circuit 42 shown in FIG. 15 includes an input section 42a to which the difference signal Vd0 is input, an output section 42b to which the single-ended signal Vd is output, a capacitor 42c, a third impedance element 42d, a fourth impedance element 42e, and a switch 42f. A series circuit SC composed of a three-state logic IC (hereinafter also referred to as a logic IC 42f), an adder 42m without a diode, and a switch 42f from an on state to an off state, and an off state And a switch control circuit SWC that outputs a control pulse signal Vct for shifting from the ON state to the ON state.

  The switch control circuit SWC includes a resistor voltage dividing circuit 42n and a bias voltage source 42p in addition to the adder 42m. The resistance voltage dividing circuit 42n is configured to have resistors connected in series, and has one end connected to the output unit 42b and the other end applied with the target constant voltage Vtg, and the output from the output unit 42b. The divided single-ended signal Vd is divided and output to the adder 42m as a divided pulse signal Vdp. The resistance voltage dividing circuit 42k of the present example is configured by two resistors 42n1 and 42n2 connected in series as an example, but may be configured by combining more resistors (not shown). The bias voltage source 42p adds the generated DC constant voltage (bias voltage) Vbi3 (≠ 0 volt) to the target constant voltage Vtg by connecting the negative electrode side to the target constant voltage Vtg, and outputs the result to the adder 42m. . In this case, the resistor voltage dividing circuit 42n and the bias voltage source 42p are controlled so that the amplitude and the DC level of the control pulse signal Vct output from the adder 42m match the input specifications of the control input terminal of the logic IC 42f described later. The voltage division ratio and the voltage value are defined in advance.

The adder 42m inputs the divided pulse signal Vdp, the added voltage (Vbi3 + Vtg) of the DC constant voltage Vbi3 and the target constant voltage Vtg, adds the voltages, and outputs a control pulse signal Vct (= Vdp + Vbi3 + Vtg). Since this control pulse signal Vct is a signal having the same phase as the divided pulse signal Vdp obtained by dividing the single-ended signal Vd, the voltage becomes low during the low voltage period _TL of the AC component Vd0 _ac , and the AC component Vd0 it is a high voltage signal that becomes a high voltage period T _H in _ac. That is, the control pulse signal Vct in FIG. 15 has a phase opposite to that of the control pulse signal Vct shown in FIG.

  For this reason, the serial circuit SC in the waveform shaping circuit 42 of FIG. 15 is the same as the logic IC 42f (the control input terminal is positive logic (high active; the control pulse signal Vct is Unlike the logic IC having a configuration in which the target constant voltage Vtg is output when the potential is high, the control input terminal is negative logic (low active. The configuration in which the target constant voltage Vtg is output when the control pulse signal Vct is low potential. ) Logic IC 42f.

The waveform shaping circuit 42 shown in FIG. 15 operates similarly to the waveform shaping circuits 42 shown in FIGS. 5, 9, and 13, and as shown in FIG. 6, converts the difference signal Vd0 into the AC component Vd0 _{ac of the} difference signal Vd0. Of the peak-to-peak voltage Vp which is equivalent to the peak-to-peak voltage Vp, and the lower potential side voltage thereof (the voltage of the low voltage period _TL ) is shaped into a single-ended signal Vd defined by the target constant voltage Vtg (waveform shaping). And outputs it from the output unit 42b. As a result, as shown in FIG. 6, the waveform shaping circuit 42 generates a signal whose voltage changes in response to the change of the code Cs constituting the CAN frame, that is, the signal during the period when the code Cs is “0”. Becomes a low potential (target constant voltage Vtg), and outputs a single-ended signal Vd in which the signal voltage becomes a high potential while the code Cs is “1”. In the waveform shaping circuit 42 shown in FIG. 15, the resistive voltage dividing circuit 42n has the function of dividing the single-ended signal Vd and the target constant voltage Vtg at the other end of the capacitor 42c (and the output section 42b). ) (The same function as the third impedance element 42d). Therefore, the third impedance element 42d can be omitted.

Although not shown, instead of using a logic IC having a negative logic (low active) control input terminal as the logic IC 42f configuring the series circuit SC of the waveform shaping circuit 42 shown in FIG. , The control input terminal may use a logic IC of positive logic (high active). According to this waveform shaping circuit, based on the control pulse signal Vct shown in FIG. 8, the logic IC 42f forming the series circuit SC executes the application of the target constant voltage Vtg when the control pulse signal Vct is at a high potential, Since the application of the target constant voltage Vtg is stopped when the pulse signal Vct is at a low potential, as shown in FIG. 8, the difference signal Vd0 is changed to the peak-to-peak voltage Vp of the AC component Vd0 _ac of the difference signal Vd0. peak-to-peak voltage Vp, and be output from the high-potential voltage (high voltage period T _H of the voltage) is shaped into a single-ended signal Vd as defined in the target constant voltage Vtg (waveform shaping) to the output unit 42b Can be. As a result, the waveform shaping circuit changes the voltage of the signal corresponding to the change of the code Cs constituting the CAN frame, that is, the voltage of the signal becomes low potential while the code Cs is “0”, During the period in which the code Cs is “1”, a single-ended signal Vd in which the voltage of the signal becomes high (target constant voltage Vtg) is output.

  In the waveform shaping circuit 42 shown in FIG. 15 and the waveform shaping circuit (not shown), the amplitude and the DC level of the divided pulse signal Vdp output from the resistance voltage dividing circuit 42n are input specifications of the control input terminal of the logic IC 42f. , The adder 42m and the bias voltage source 42p can be omitted, and the switch control circuit SWC can be configured only by the resistance voltage dividing circuit 42n as in the waveform shaping circuit 42 shown in FIG. In the waveform shaping circuit 42, the divided pulse signal Vdp output from the resistance voltage dividing circuit 42n is supplied as it is to the control input terminal of the logic IC 42f as the control pulse signal Vct.

Since the waveform shaping circuit 42 shown in FIG. 16 uses a logic IC having a positive logic (high active) control input terminal as the logic IC 42f constituting the serial circuit SC, as shown in FIG. 8, the difference signal Vd0 a peak-to-peak voltage Vp equal peak-to-peak voltage Vp of the AC component _{Vd0 ac} differential signal Vd0, and high-potential voltage (voltage of the high voltage period _{T H)} is defined on the target constant voltage Vtg that The signal is shaped (waveform shaped) into a single-ended signal Vd and output from the output unit 42b.

Although not shown, the waveform shaping circuit is configured using a logic IC having a negative logic (low active) control input terminal as the logic IC 42f configuring the serial circuit SC of the waveform shaping circuit 42 illustrated in FIG. Can also. As shown in FIG. 6, this waveform shaping circuit converts the difference signal Vd0 into a peak-to-peak voltage Vp equivalent to the peak-to-peak voltage Vp of the AC component Vd0 _ac of the difference signal Vd0, and a low-potential-side voltage (low). The voltage during the voltage period _TL ) is shaped (waveform shaped) into a single-ended signal Vd defined by the target constant voltage Vtg and output from the output unit 42b.

The target constant voltage Vtg used in each of the waveform shaping circuits 42 uses a DC constant voltage output from this DC constant voltage source by arranging a DC constant voltage source (not shown) in the waveform shaping circuit 42. Alternatively, as shown by a broken line in FIG. 5, the voltage data Dv input from outside the waveform shaping circuit 42 is D / A converted, and a DC voltage having a voltage value indicated by the voltage data Dv is output. The D / A converter 15 may be arranged in the waveform shaping circuit 42 to use the DC voltage output from the D / A converter 15 as the target constant voltage Vtg. Although the waveform shaping circuit 42 shown in FIG. 5 is taken as an example, the same applies to the waveform shaping circuits 42 shown in FIGS. 7, 9 to 16 and FIGS. When the configuration in which the D / A converter 15 is arranged in the waveform shaping circuit 42 is adopted, the voltage data Dv is changed to change the single-ended signal Vd to the high-potential-side voltage (high-voltage) defined by the target constant voltage Vtg. it is possible to change the period T voltage _H) and the low potential voltage (voltage of the low voltage period T _L). Therefore, the signal generator 14 can be adjusted so as to reliably generate the code specifying signal Sf from the single-ended signal Vd.

  Although the above-described waveform shaping circuits 42 employ a configuration that does not include a diode, a configuration that includes a diode, such as the waveform shaping circuits 42 shown in FIGS.

First, the waveform shaping circuit 42 shown in FIG. 17 receives the difference signal Vd0 and converts the difference signal Vd0 into the peak-to-peak AC component of the difference signal Vd0 in the same manner as the waveform shaping circuit 42 shown in FIG. The peak-to-peak voltage Vp equivalent to the voltage Vp, and the lower potential side voltage thereof (the voltage of the low voltage period _TL ; the bottom voltage) is shaped (waveform shaped) into a single-ended signal Vd defined by the target constant voltage Vtg. Output. The waveform shaping circuit 42 shown in FIG. 17 is different from the waveform shaping circuit 42 shown in FIG. 5 in that an input section 42a to which the difference signal Vd0 is input, an output section 42b to which the single-ended signal Vd is output, and a capacitor 42c. And a third impedance element 42d, and is different in that one diode 42x is provided instead of the series circuit SC and the switch control circuit SWC. The diode 42x has a cathode terminal connected to the output unit 42b and a target constant voltage Vtg applied to an anode terminal.

In the waveform shaping circuit 42 shown in FIG. 17, the diode 42x alone operates in the same manner as the series circuit SC and the switch control circuit SWC, and as shown in FIG. 6, the difference signal Vd0 input to the input section 42a is output. shifts to the oN state to the low voltage period _{T L} in an alternating current component _{Vd0 ac,} is applied to the target constant voltage Vtg the output unit 42b, and shifts to the oFF state to the high voltage period _{T H} of the AC component _{Vd0 ac,} target constant The application of the voltage Vtg to the output unit 42b is stopped. Accordingly, when the forward voltage of the diode 42x can be ignored, the waveform shaping circuit 42 shapes (waveforms) the difference signal Vd0 into the above-described single-ended signal Vd and outputs the signal.

Next, the waveform shaping circuit 42 shown in FIG. 18 receives the difference signal Vd0 and converts the difference signal Vd0 into the peak of the AC component of the difference signal Vd0 in the same manner as the waveform shaping circuit 42 of FIG. the peak voltage Vp equal peak-to-peak voltage Vp, and shaping to the single-ended signal Vd high potential side voltage (voltage. top voltage of the high voltage period T _H) is defined on the target constant voltage Vtg (waveform shaping) And output. The waveform shaping circuit 42 shown in FIG. 18 is different from the waveform shaping circuit 42 shown in FIG. 7 in that an input section 42a to which the difference signal Vd0 is input, an output section 42b to which a single-ended signal Vd is output, a capacitor 42c, They are common in that they have three impedance elements 42d, and they differ in that they have one diode 42x instead of the series circuit SC and the switch control circuit SWC. The diode 42x has an anode terminal connected to the output unit 42b and a target constant voltage Vtg applied to a cathode terminal.

In the waveform shaping circuit 42 shown in FIG. 17, the diode 42x operates alone and operates in the same manner as the series circuit SC and the switch control circuit SWC, and as shown in FIG. 8, the difference signal Vd0 input to the input section 42a is output. shifts to the oN state to the high voltage period _{T H} of the AC component _{Vd0 ac,} is applied to the target constant voltage Vtg the output unit 42b, and shifts to the oFF state in an alternating current component _{Vd0 ac} to low voltage period _{T L,} the target constant The application of the voltage Vtg to the output unit 42b is stopped. As a result, the waveform shaping circuit 42 shapes (waveforms) the difference signal Vd0 into the above-described single-ended signal Vd and outputs it.

  The coding device 3 executes a coding process for specifying a code Cs (see FIGS. 6 and 8) corresponding to the logic signal Sa based on the code specifying signal Sf output from the signal generation device 2, and executes the specified code. The column of Cs (that is, the same CAN frame as the CAN frame transmitted on the serial bus SB) is output to various CAN communication compatible devices connected to the signal reading system 1. Specifically, in the encoding process, in the encoding process, during the high-potential period of the code specifying signal Sf, the code Cs configuring the CAN frame transmitted via the serial bus SB is “1”. During the low potential period of the code specifying signal Sf, it is specified that the code Cs constituting the CAN frame is “0”, and the code string formed of the specified code Cs is serialized. The CAN frame is specified as a CAN frame transmitted via the bus SB and is output to various CAN communication compatible devices. In this case, the encoding device 3 outputs (transmits) the specified CAN frame to the CAN communication compatible device by wired communication when connected to the CAN communication compatible device via the wired transmission path, and When connected via a wireless transmission path, the specified CAN frame is output (transmitted) to the CAN communication compatible device by wireless communication.

  Next, a usage example of the signal reading system 1 and an operation of the signal reading system 1 at that time will be described with reference to the drawings. As shown in FIG. 2, the electrode 21 of the electrode portion 11a is connected to one end of the impedance element 12a via the core wire of the shielded cable CBa, and the shield 22 of the electrode portion 11a generates a signal via the shield of the shielded cable CBa. The electrode 21 of the electrode portion 11b is connected to one end of the impedance element 12b through the core wire of the shielded cable CBb, and the shield 22 of the electrode portion 11b is connected to the signal through the shield of the shielded cable CBb. It is assumed that it is connected to the ground G of the generator 2.

  First, as shown in FIG. 2, the electrode portions 11a and 11b are covered with the covered wires La and Lb such that the electrodes 21 contact (contact) the covered portions of the covered wires La and Lb in the serial bus SB laid on the automobile. And a CAN communication-compatible device that should output a CAN frame (column of code Cs) read from the serial bus SB is connected to the encoding device 3.

  In this case, in the signal reading system 1 of the present embodiment, the logic signal Sa is read from the serial bus SB only by mounting the electrode portions 11a and 11b without processing the coated conductors La and Lb themselves (stripping off the insulating coating). Therefore, it can be used even when no connector is provided on the serial bus SB. Further, even if the connector is provided, the connection place for the serial bus SB (the place where the electrode portions 11a and 11b are attached) is not limited to the place where the connector is provided, but may be any position in the longitudinal direction of the covered conductor La or Lb. (The electrode portions 11a and 11b are attached).

  In this state, logic from a CAN communication-compatible device (a controller that outputs a CAN frame indicating control information, a detector that outputs a CAN frame indicating an arbitrary measurement result, etc.) mounted on the automobile to the serial bus SB is transmitted to the serial bus SB. When the signal Sa is output, in the signal generating device 2, the voltage transmitted to the covered conductor La is applied to the electrode element 11a attached to the covered conductor La and the impedance element 12a connected via the shielded cable CBa. A first voltage signal Vc1 whose voltage changes in accordance with the voltage Va of the signal Va is generated, and the impedance element 12b connected to the electrode section 11b attached to the insulated conductor Lb via the shielded cable CBb is connected to the insulated conductor. A second voltage signal Vc2 whose voltage changes according to the voltage Vb of the voltage signal Vb transmitted to Lb is generated. .

  In the signal generating device 2, the differential amplifying unit 13 receives the first voltage signal Vc1 and the second voltage signal Vc2, and generates a voltage according to a difference voltage (Vc1−Vc2) between the voltage signals Vc1 and Vc2. Output a single-ended signal Vd. In this case, in the differential amplifying section 13, when the waveform shaping circuit 42 has a circuit configuration shown in any one of FIGS. 5, 9, 11, 13, 15, and 17, as shown in FIG. The signal voltage becomes low (target constant voltage Vtg) during the period when the code Cs constituting the transmitted CAN frame is “0”, and the signal voltage becomes high during the period when the code Cs is “1”. A single-ended signal Vd (that is, a signal whose waveform is shaped so that the voltage of the signal in the low potential period (the bottom voltage of the signal) is defined by the target constant voltage Vtg) is output. When the waveform shaping circuit 42 has a circuit configuration shown in any one of FIGS. 7, 10, 12, 14, 16, and 18, the CAN frame transmitted to the serial bus SB is configured as shown in FIG. The signal voltage becomes high potential (target constant voltage Vtg) during the period when the code Cs is “1”, and the single-ended signal Vd (the signal voltage becomes low potential while the code Cs is “0”). In other words, a signal whose waveform is shaped such that the voltage of the signal in the high potential period (the top voltage of the signal) is defined by the target constant voltage Vtg is output.

  Further, in the signal generation device 2, when the waveform shaping circuit 42 has a circuit configuration shown in any of FIGS. 5, 9, 11, 13, 15, and 17, a diagram corresponding to the circuit configuration of the waveform shaping circuit 42 is shown. As shown in FIG. 6, the signal generating unit 14 configured in the circuit shown in FIG. 5 becomes a “high potential period” in a period in which the code Cs constituting the CAN frame transmitted via the serial bus SB is “1”. In addition, a code specifying signal Sf which becomes a “low potential period” during a period when the code Cs is “0” is generated and output. When the waveform shaping circuit 42 has the circuit configuration shown in any of FIGS. 7, 10, 12, 14, 16, and 18, the circuit shown in FIG. As shown in FIG. 8, the signal generation unit 14 outputs a “high-potential period” during a period in which the code Cs configuring the CAN frame transmitted via the serial bus SB is “1”, and the code Cs is changed to “high-potential period”. In the period of “0”, the code specifying signal Sf which becomes the “low potential period” is generated and output.

  In addition, the coding device 3 specifies the code Cs that constitutes the CAN frame transmitted via the serial bus SB based on the code specifying signal Sf generated and output by the signal generation device 2 and specifies the code. A code string composed of the obtained code Cs is specified as a CAN frame transmitted via the serial bus SB, and is output to various CAN communication compatible devices. Thereby, in the CAN communication-compatible device, various predefined CAN frames (sequence of code Cs) output from the signal reading system 1 (read from the serial bus SB by the signal reading system 1). Is performed.

  As described above, in the signal generation device 2, the covering portions of the pair of covered conductors La and Lb are respectively brought into contact with each other (the contact portions are not in contact with the metal portions (core wires) of the covered conductors La and Lb (the non-contact state). In a contact state), the pair of electrodes 21 is brought into contact with the covering portions of the covered conductors La and Lb) via the shielded cables CBa and CBb, thereby reducing the voltage Va transmitted to one of the covered conductors La. A first voltage signal Vc1 whose voltage changes according to the voltage is generated in the first impedance element 12a, and a second voltage signal Vc2 whose voltage changes according to the voltage Vb transmitted to the other covered conductor Lb is changed to the second impedance element. 12b, the differential amplifier 13 outputs a single-ended signal Vd whose voltage changes in accordance with the difference voltage between the voltage signals Vc1 and Vc2, 14 generates a code specifying signal Sf capable of specifying a code Cs corresponding to the logic signal Sa transmitted via the serial bus SB by binarizing the single-ended signal Vd with the threshold voltage Vth. . Further, in the signal reading system 1, the signal generation device 2 described above and the coding device 3 that specifies the code Cs corresponding to the logic signal Sa based on the code specification signal Sf generated by the signal generation device 2 are included. Have.

  Therefore, according to the signal generating device 2 and the signal reading system 1, the electrodes 21 of the electrode portions 11a and 11b are brought into contact with the covering portion of the covered conductor L at an arbitrary portion in the longitudinal direction of the pair of covered conductors La and Lb. By performing a simple operation, a code specifying signal Sf capable of specifying the code Cs indicated by the logic signal Sa transmitted via the serial bus SB is generated, and based on the generated code specifying signal Sf. Thus, the code Cs indicated by the logic signal Sa can be specified, and further, a CAN frame composed of a column of the specified code Cs can be specified. Thereby, even if the connector is not provided on the serial bus SB, or even if the connector is provided on the serial bus SB, the logic signal Sa is read at an arbitrary position on the serial bus SB and the code Cs is read. , And a code Cs.

  In addition, according to the signal generating device 2, since the differential amplifying unit (transformerless differential amplifying unit having no transformer) 13 including the operational amplifier is provided to generate the code specifying signal Sf, In general, a transformer having a large outer shape and a transformer having a large mounting area can be dispensed with, so that the device can be downsized.

Further, in the signal generation device 2, the differential amplifier 13 receives the first voltage signal Vc1 and the second voltage signal Vc2 and outputs the difference signal Vd0 whose voltage changes according to the difference voltage (Vc1−Vc2). The differential amplifier circuit 41 and the differential signal Vd0 are supplied with a peak-to-peak voltage Vp equivalent to the peak-to-peak voltage Vp of the AC component Vd0 _ac of the differential signal Vd0, and a high-potential-side voltage thereof (high-voltage period _TH). ) And the low-potential-side voltage (the voltage of the low-voltage period _TL ) are shaped (waveform shaped) into a single-ended signal Vd defined by the target constant voltage Vtg and output (that is, the difference). It is provided with a waveform shaping circuit 42 which removes and outputs a DC component A (low frequency noise) superimposed on the signal Vd0.

  Therefore, according to the signal generation device 2, the signal generation unit 14 disposed downstream of the differential amplification unit 13 compares the target constant voltage Vtg with the threshold voltage Vth defined as a reference, thereby achieving a single The code specifying signal Sf can be generated by reliably binarizing the end signal Vd. Thus, according to the signal reading system 1, the code Cs indicated by the logic signal Sa can be more reliably specified based on the code specifying signal Sf, and furthermore, the specified code Cs Can be more reliably specified.

Further, in the signal generation device 2, the waveform shaping circuit 42 switches the capacitor 42c, the third impedance element 42d, the series circuit SC, and the switch 42f of the series circuit SC during the low voltage period _TL in the AC component Vd0 _ac of the difference signal Vd0. together with shifts in the oN state, or configuration and a switch control circuit SWC for shifting the switch 42f in the oFF state to the high voltage period _{T H} of the AC component _{Vd0 ac} or capacitor 42c,, third impedance element 42d, a series circuit SC, and the high voltage period _{T H} of the AC component _{Vd0 ac} differential signal Vd0 with shifts the switch 42f of the series circuit SC in the oN state, the switch 42f in the oFF state to the low voltage period _{T L} in the AC component _{Vd0 ac} Switch control circuit SWC for shifting It has become one of the configuration of growth.

Therefore, according to the signal generation device 2, unlike the configuration having the waveform shaping circuit 42 configured using the diode 42x affected by the forward voltage, the waveform shaping circuit 42 converts the differential signal Vd0 into the differential signal Vd0. in Vd0 of the AC component _{Vd0 ac} peak-to-peak voltage Vp equal peak-to-peak voltage Vp, and (voltage of the high voltage period _{T H)} the high potential side voltage and the low potential voltage (low voltage period _{T L} of the voltage ) Can be reliably shaped (waveform shaped) into a single-ended signal Vd defined by the target constant voltage Vtg and output. For this reason, according to the signal generation device 2, the signal generation unit 14 disposed downstream of the differential amplification unit 13 compares the signal with the threshold voltage Vth defined based on the target constant voltage Vtg. The single-ended signal Vd can be more reliably binarized to generate the code specifying signal Sf. Thus, according to the signal reading system 1, the code Cs indicated by the logic signal Sa can be more reliably specified based on the code specifying signal Sf, and furthermore, the sequence of the specified codes Cs Can be more reliably specified.

Further, in the waveform shaping circuit 42 shown in FIG. 5 constituting the signal generating device 2, the switch control circuit SWC has an inverting input terminal connected to the other end of the capacitor 42c and is higher than the target constant voltage Vtg. A (slightly higher) reference voltage Vr1 is input to the non-inverting input terminal, and the comparator 42g is configured to output a control pulse signal Vct from the output terminal. Therefore, according to the waveform shaping circuit 42, noise is included in the single-ended signal Vd in a state where the low-potential-side voltage of the single-ended signal Vd (voltage in the low-voltage period _TL ) is defined as the target constant voltage Vtg. Even in the case of superimposition, the switch control circuit SWC maintains the control pulse signal Vct at a high potential until the noise level reaches the reference voltage Vr1 (until it rises to the reference voltage Vr1). 42f), the application of the target constant voltage Vtg to the other end of the capacitor 42c (and the output unit 42b) can be continued with respect to the series circuit SC. Therefore, according to the signal generation device 2 and the signal reading system 1 including the waveform shaping circuit 42, malfunctions due to noise can be reduced.

Further, in the waveform shaping circuit 42 shown in FIG. 7 constituting the signal generating device 2, the switch control circuit SWC has a non-inverting input terminal connected to the other end of the capacitor 42c and a voltage higher than the target constant voltage Vtg. A low (slightly low) reference voltage Vr1 is input to the inverting input terminal, and a comparator 42g that outputs a control pulse signal Vct from the output terminal is provided. Therefore, according to the waveform shaping circuit 42, in a state where the high-potential-side voltage of the single-ended signal Vd (voltage of the high voltage period T _H) is defined on the target constant voltage Vtg, noise in a single-ended signal Vd Even in the case of superimposition, the switch control circuit SWC maintains the control pulse signal Vct at a high potential until the noise level reaches the reference voltage Vr1 (until the noise level decreases to the reference voltage Vr1). 42f), the application of the target constant voltage Vtg to the other end of the capacitor 42c (and the output unit 42b) can be continued with respect to the series circuit SC. Therefore, according to the signal generation device 2 and the signal reading system 1 including the waveform shaping circuit 42, malfunctions due to noise can be reduced.

  Thus, according to the signal generating device 2 and the signal reading system 1 including the waveform shaping circuit 42, the code specifying signal Sf can be stably generated even in the presence of noise, and the code specifying signal Sf can be generated. Based on Sf, the code Cs and the CAN frame composed of the code Cs can be stably specified and output.

Further, in the waveform shaping circuit 42 shown in FIGS. 9 and 10 constituting the signal generating device 2, the comparator 42g constituting the switch control circuit SWC has a hysteresis characteristic (the comparator 42g operates as a hysteresis comparator). ). Therefore, according to these waveform shaping circuits 42, when the single-ended signal Vd is the low-potential-side voltage (the voltage in the low-voltage period _TL ), and when the single-ended signal Vd is the high-potential-side voltage (the high-voltage period _TH). In any case, when the noise is superimposed on the single-ended signal Vd, when the level of the noise is lower than the level defined by the hysteresis characteristic, the switch control circuit SWC performs the control. Since the potential of the pulse signal Vct can be maintained at the current potential (that is, this state is maintained when the switch 42f is on, and this state is maintained when the switch 42f is off), single-ended The voltage of the signal Vd can be maintained at the current state. Therefore, according to the signal generation device 2 including the waveform shaping circuit 42, a malfunction due to noise can be further reduced.

  Thus, according to the signal generating device 2 and the signal reading system 1 including the waveform shaping circuit 42, the code specifying signal Sf can be generated more stably even in the presence of noise, and the code specifying signal Sf can be generated. Based on the signal Sf, the CAN frame composed of the code Cs and the code Cs can be more stably specified and output.

According to the signal generation device 2 including any one of the waveform shaping circuits 42 illustrated in FIGS. 15 and 16, even in a configuration not using a comparator, the difference signal Vd0 output from the differential amplification circuit 41 is A single-ended signal whose peak-to-peak voltage Vp is equal to the peak-to-peak voltage Vp of the AC component Vd0 _ac of the difference signal Vd0, and whose lower potential side voltage (voltage in the low voltage period _TL ) is defined as the target constant voltage Vtg. or reliably shaping the signal Vd, and in peak to peak voltage Vp equal peak-to-peak voltage Vp of the AC component _{Vd0 ac} differential signal Vd0, and the high-potential voltage (voltage of the high voltage period _{T H)} is The signal can be reliably shaped into a single-ended signal Vd defined by the target constant voltage Vtg and output from the output unit 42b. Thus, according to the signal generation device 2 including the waveform shaping circuit 42, the degree of freedom in design can be increased.

  In the waveform shaping circuit 42 shown in FIGS. 13 to 16 constituting the signal generating device 2, the switch 42f constituting the series circuit SC is constituted by a three-state logic IC (logic IC 42f) as a three-state buffer. Have been. Therefore, according to each of the waveform shaping circuits 42, an output buffer (or input / output buffer (bidirectional buffer)) built in the integrated circuit can be used as the logic IC 42f.

Further, according to the signal generation device 2, the D / A converter 15 is arranged in the waveform shaping circuit 42 and the target constant voltage Vtg is output from the D / A converter 15, so that the D / A is output. by changing the voltage data Dv to the transducer 15, (the voltage of the high voltage period T _H) this order can change the target constant voltage Vtg, high-potential-side voltage defined on the target constant voltage Vtg in the single-ended signal Vd Alternatively, the low-potential-side voltage (the voltage in the low-voltage period _TL ) can be changed according to the input specifications of the signal generation unit 14. That is, according to the signal generating device 2, it is possible to adjust the high-potential-side voltage and the low-potential-side voltage so that the signal generating unit 14 can reliably generate the code specifying signal Sf from the single-ended signal Vd. it can.

  Further, according to the signal generating device 2, the differential amplifier circuit 41 is configured as shown in FIG. 4, that is, the capacitor 41k is connected in series with the resistor 41fa of the operational amplifier 41a constituting the differential amplifier circuit 41. In addition, by connecting the capacitor 41m in series with the resistor 41fb of the operational amplifier 41b so that the operational amplifier 41a and the operational amplifier 41b function as an AC amplifier, the output terminals of the operational amplifier 41a and the operational amplifier 41b are The occurrence of the situation where the output signal to be output is saturated due to the DC component of each of the voltage signals Vc1 and Vc2 can be greatly reduced.

  In addition, according to the signal generating device 2 and the signal reading system 1, each of the impedance elements 12a and 12b is configured identically by using a high impedance resistor or a capacitor, or a combination circuit thereof (in the example shown in FIG. 2). , A parallel circuit of the resistor 31a and the capacitor 32a, and a parallel circuit of the resistor 31b and the capacitor 32b), the voltage of which changes according to the voltage Va of the voltage signal Va transmitted to the covered conductor La. The second voltage signal Vc2 whose voltage changes in accordance with the first voltage signal Vc1 and the voltage Vb of the voltage signal Vb transmitted to the covered conductor Lb can be reliably generated with a simple configuration.

  In addition, the above-described signal generation device 2 employs a configuration including the electrode units 11a and 11b. However, the signal generation device 2 employs a configuration in which the electrode units 11a and 11b are separated from each other. Alternatively, the electrode units 11a and 11b may be connected to the signal generation device 2 via shielded cables CBa and CBb.

  Further, in the above-described waveform shaping circuit 42 shown in FIGS. 5, 7, 9, and 10, the switch 42f of the series circuit SC is configured to operate with positive logic. However, the present invention is not limited to this configuration. Even when the control pulse signal Vct is at a low potential, the circuit is turned on, and when the control pulse signal Vct is at a high potential, the circuit is turned off. Good. If the switch 42f operates with negative logic, the configuration of the switch control circuit SWC that outputs the control pulse signal Vct also needs to be changed. In the following, the configuration of the waveform shaping circuit when the switch 42f of the waveform shaping circuit 42 shown in FIGS. 5, 7, 9, and 10 operates with negative logic corresponds to the waveform shaping circuit 42 of FIG. 19 for the waveform shaping circuit 42, and FIG. 20 for the waveform shaping circuit 42 corresponding to the waveform shaping circuit 42 in FIG. 7, and the waveform shaping circuit 42 corresponding to the waveform shaping circuit 42 in FIG. The circuit 42 will be described with reference to FIG. 21, and the waveform shaping circuit 42 corresponding to the waveform shaping circuit 42 in FIG. 10 will be described with reference to FIG. 22, including the configuration of the switch control circuit SWC.

  First, the configuration of the waveform shaping circuit 42 having the switch 42f operating with negative logic will be described with reference to FIG. The waveform shaping circuit 42 is different from the waveform shaping circuit 42 shown in FIG. 5 in that, in addition to the configuration in which the switch 42f operates with negative logic, the switch control circuit SWC that outputs the control pulse signal Vct as described above. Is the same as the waveform shaping circuit 42 shown in FIG. Therefore, the switch control circuit SWC of the waveform shaping circuit 42 will be mainly described.

The switch control circuit SWC of the waveform shaping circuit 42, like the switch control circuit SWC of the waveform shaping circuit 42 of FIG. 5, switches the switch 42f during the low voltage period _TL of the AC component Vd0 _{ac as} shown in FIG. defining a low-potential-side voltage (the voltage of the low voltage period _{T L)} to the target constant voltage Vtg of the single-ended signal Vd by shifting the on state (fixed), the switch 42f to the high voltage period _{T H} of the AC component _{Vd0 ac} To output a control pulse signal Vct for shifting the control signal to the OFF state. However, the switch 42f of the waveform shaping circuit 42 of FIG. 19 operates with negative logic, unlike the switch 42f of the waveform shaping circuit 42 of FIG. For this reason, the switch control circuit SWC in FIG. 19 outputs a control pulse signal Vct having a polarity opposite to the polarity of the control pulse signal Vct output from the switch control circuit SWC in FIG. 5 (that is, shown in FIG. 8). (It must be output with the same polarity as the control pulse signal Vct).

  Therefore, the switch control circuit SWC in the waveform shaping circuit 42 of FIG. 19 has the same basic configuration as the switch control circuit SWC of the waveform shaping circuit 42 shown in FIG. 7 which outputs the control pulse signal Vct with the polarity shown in FIG. I have. That is, in the switch control circuit SWC of FIG. 19, the non-inverting input terminal of the comparator 42g is connected to the other end of the capacitor 42c, and the reference voltage Vr1 is input to the inverting input terminal. However, in the waveform shaping circuit 42 of FIG. 19, the reference voltage Vr1 needs to be equivalent to that of the waveform shaping circuit 42 of FIG. 5, and therefore, as shown in FIG. It is configured similarly to the circuit 42 and outputs a voltage higher than the target constant voltage Vtg as the reference voltage Vr1.

With this configuration, the switch control circuit SWC that drives the negative logic switch 42f changes the voltage at the other end of the capacitor 42c (that is, the voltage of the single-ended signal Vd) from a state in which the voltage exceeds the reference voltage Vr1 to the reference voltage Vr1. When the voltage falls below the reference voltage Vr1, the voltage at the other end of the capacitor 42c (the voltage of the single-ended signal Vd) rises from a state below the reference voltage Vr1 and rises above the reference voltage Vr1. at the time the in the control pulse signal Vct (control pulse signal Vct the reverse polarity of the signal shown in FIG. 6 (low voltage period T _L of the transition from a low potential to a high potential becomes a low potential, a high potential in the high-voltage period T _H Is generated and output to the negative logic switch 42f. As a result, the negative logic switch 42f shifts from the on state to the off state and from the off state to the on state at the same timing as the positive logic switch 42f of the waveform shaping circuit 42 shown in FIG. That is, as shown in FIG. 19, the waveform shaping circuit 42 including the negative logic switch 42f and the switch control circuit SWC configured for the switch 42f is the waveform shaping circuit 42 (the positive logic switch) shown in FIG. 42f).

  Next, the configuration of the waveform shaping circuit 42 having the switch 42f operating with negative logic will be described with reference to FIG. The waveform shaping circuit 42 is different from the waveform shaping circuit 42 shown in FIG. 7 in that, in addition to the configuration in which the switch 42f operates in negative logic, the switch control circuit SWC that outputs the control pulse signal Vct as described above. 7 is the same as the waveform shaping circuit 42 shown in FIG. Therefore, the switch control circuit SWC of the waveform shaping circuit 42 will be mainly described.

Switch control circuit SWC of the waveform shaping circuit 42, as in the switch control circuit SWC of the waveform shaping circuit 42 in FIG. 7, as shown in FIG. 8, the switch 42f to the high voltage period _{T H} of the AC component _{Vd0 ac} defining a high-potential voltage (voltage of the high voltage period _{T H)} to the target constant voltage Vtg of the single-ended signal Vd by shifting the on state (fixed), the switch 42f in an alternating current component _{Vd0 ac} to low voltage period _{T L} To output a control pulse signal Vct for shifting the control signal to the OFF state. However, the switch 42f of the waveform shaping circuit 42 of FIG. 20 operates with negative logic, unlike the switch 42f of the waveform shaping circuit 42 of FIG. Therefore, the switch control circuit SWC of FIG. 20 outputs a control pulse signal Vct having a polarity opposite to the polarity of the control pulse signal Vct output from the switch control circuit SWC of FIG. 7 (that is, shown in FIG. 6). (It must be output with the same polarity as the control pulse signal Vct).

  Therefore, the switch control circuit SWC in the waveform shaping circuit 42 of FIG. 20 has the same basic configuration as the switch control circuit SWC of the waveform shaping circuit 42 shown in FIG. 5 that outputs the control pulse signal Vct with the polarity shown in FIG. I have. That is, in the switch control circuit SWC of FIG. 20, the inverting input terminal of the comparator 42g is connected to the other end of the capacitor 42c, and the reference voltage Vr1 is input to the non-inverting input terminal. However, in the waveform shaping circuit 42 of FIG. 20, the reference voltage Vr1 needs to be equal to that of the waveform shaping circuit 42 of FIG. 7, and therefore, as shown in FIG. It is configured in the same way as the circuit 42 and outputs a voltage lower than the target constant voltage Vtg as the reference voltage Vr1.

With this configuration, the switch control circuit SWC that drives the negative logic switch 42f changes the voltage at the other end of the capacitor 42c (that is, the voltage of the single-ended signal Vd) from a state in which the voltage exceeds the reference voltage Vr1 to the reference voltage Vr1. When the voltage falls below the reference voltage Vr1, the voltage at the other end of the capacitor 42c (the voltage of the single-ended signal Vd) rises from a state below the reference voltage Vr1 and rises above the reference voltage Vr1. Once the becomes a low potential in the control pulse signal Vct (opposite polarity of the signal from the control pulse signal Vct shown in FIG. 8 (high voltage period T _H of transition from the high potential to a low potential, a high potential in the low voltage period T _L Is generated and output to the negative logic switch 42f. As a result, the negative logic switch 42f shifts from the on state to the off state and from the off state to the on state at the same timing as the positive logic switch 42f of the waveform shaping circuit 42 shown in FIG. That is, as shown in FIG. 20, the waveform shaping circuit 42 including the negative logic switch 42f and the switch control circuit SWC configured for the switch 42f is the waveform shaping circuit 42 (the positive logic switch) shown in FIG. 42f).

  Subsequently, the configuration of the waveform shaping circuit 42 having the switch 42f operating with negative logic will be described with reference to FIG. The waveform shaping circuit 42 is different from the waveform shaping circuit 42 shown in FIG. 9 in that, in addition to the configuration in which the switch 42f operates in negative logic, the switch control circuit SWC that outputs the control pulse signal Vct as described above. Is the same as the waveform shaping circuit 42 shown in FIG. Therefore, the switch control circuit SWC of the waveform shaping circuit 42 will be mainly described.

As shown in FIG. 6, the switch control circuit SWC of the waveform shaping circuit 42 switches the switch 42f during the low voltage period _TL of the AC component Vd0 _ac in the same manner as the switch control circuit SWC of the waveform shaping circuit 42 of FIG. defining a low-potential-side voltage (the voltage of the low voltage period _{T L)} to the target constant voltage Vtg of the single-ended signal Vd by shifting the on state (fixed), the switch 42f to the high voltage period _{T H} of the AC component _{Vd0 ac} To output a control pulse signal Vct for shifting the control signal to the OFF state. However, the switch 42f of the waveform shaping circuit 42 of FIG. 21 operates with negative logic, unlike the switch 42f of the waveform shaping circuit 42 of FIG. For this reason, the switch control circuit SWC of FIG. 21 outputs a control pulse signal Vct having a polarity opposite to the polarity of the control pulse signal Vct output from the switch control circuit SWC of FIG. 9 (that is, shown in FIG. 8). (It must be output with the same polarity as the control pulse signal Vct).

  Therefore, the switch control circuit SWC in the waveform shaping circuit 42 of FIG. 21 has the same basic configuration as the switch control circuit SWC of the waveform shaping circuit 42 shown in FIG. 10 that outputs the control pulse signal Vct with the polarity shown in FIG. I have. That is, in the switch control circuit SWC of FIG. 21, the comparator 42g has a reference voltage Vr1 applied to its inverting input terminal, and the resistor voltage dividing circuit 42k has one end connected to the output terminal of the comparator 42g and the other end connected. Is connected to the other end of the capacitor 42c, and outputs the divided pulse signal Vdp defined by the voltage of the single-ended signal Vd and the voltage of the control pulse signal Vct to the non-inverting input terminal of the comparator 42g. I have. However, in the waveform shaping circuit 42 of FIG. 21, the reference voltage Vr1 needs to be equivalent to that of the waveform shaping circuit 42 of FIG. 5, and therefore, as shown in FIG. It is configured similarly to the circuit 42 and outputs a voltage higher than the target constant voltage Vtg as the reference voltage Vr1.

With this configuration, the switch control circuit SWC that drives the negative logic switch 42f outputs the divided pulse signal Vdp that decreases as the voltage at the other end of the capacitor 42c (that is, the voltage of the single-ended signal Vd) decreases. At the time when the voltage of the capacitor 42 changes from a state higher than the reference voltage Vr1 to a state lower than the reference voltage Vr1, the voltage changes from the high potential to the low potential, and conversely, the voltage at the other end of the capacitor 42c (the voltage of the single-ended signal Vd) increases. When the voltage of the divided pulse signal Vdp that rises with the transition from the state below the reference voltage Vr1 to the state above the reference voltage Vr1, the control pulse signal Vct that transitions from a low potential to a high potential (the control pulse signal Vct shown in FIG. is (becomes the low potential in the low voltage period T _L, the signal becomes a high potential in the high-voltage period T _H) reverse polarity signal to generate), negative logic Sui And outputs it to the switch 42f. As a result, the negative logic switch 42f shifts from the on state to the off state and from the off state to the on state at the same timing as the positive logic switch 42f of the waveform shaping circuit 42 shown in FIG. In other words, as shown in FIG. 21, the waveform shaping circuit 42 including the negative logic switch 42f and the switch control circuit SWC configured for the switch 42f is the waveform shaping circuit 42 (the positive logic switch) shown in FIG. 42f).

  Next, the configuration of the waveform shaping circuit 42 having the switch 42f operating with negative logic will be described with reference to FIG. The waveform shaping circuit 42 is different from the waveform shaping circuit 42 shown in FIG. 10 in that, in addition to the configuration in which the switch 42f operates in negative logic, the switch control circuit SWC that outputs the control pulse signal Vct as described above. Is the same as the waveform shaping circuit 42 shown in FIG. Therefore, the switch control circuit SWC of the waveform shaping circuit 42 will be mainly described.

Switch control circuit SWC of the waveform shaping circuit 42, as in the switch control circuit SWC of the waveform shaping circuit 42 in FIG. 10, as shown in FIG. 8, the switch 42f to the high voltage period _{T H} of the AC component _{Vd0 ac} defining a high-potential voltage (voltage of the high voltage period _{T H)} to the target constant voltage Vtg of the single-ended signal Vd by shifting the on state (fixed), the switch 42f in an alternating current component _{Vd0 ac} to low voltage period _{T L} To output a control pulse signal Vct for shifting the control signal to the OFF state. However, the switch 42f of the waveform shaping circuit 42 of FIG. 22 operates with negative logic, unlike the switch 42f of the waveform shaping circuit 42 of FIG. For this reason, the switch control circuit SWC of FIG. 22 outputs a control pulse signal Vct having a polarity opposite to the polarity of the control pulse signal Vct output from the switch control circuit SWC of FIG. 10 (that is, shown in FIG. 6). (It must be output with the same polarity as the control pulse signal Vct).

  Therefore, the switch control circuit SWC in the waveform shaping circuit 42 of FIG. 22 has the same basic configuration as the switch control circuit SWC of the waveform shaping circuit 42 shown in FIG. 9 which outputs the control pulse signal Vct with the polarity shown in FIG. I have. That is, in the switch control circuit SWC of FIG. 22, the inverting input terminal of the comparator 42g is connected to the other end of the capacitor 42c, and the resistive voltage dividing circuit 42k is connected to the output terminal of the comparator 42g. At the same time, the reference voltage Vr2 is applied to the other end, and the divided voltage defined by the reference voltage Vr2 and the voltage of the control pulse signal Vct is output to the non-inverting input terminal of the comparator 42g as the reference voltage Vr1. . However, in the waveform shaping circuit 42 of FIG. 22, the reference voltage Vr1 needs to be equal to that of the waveform shaping circuit 42 of FIG. 7, and therefore, as shown in FIG. Is configured to output a low voltage as the reference voltage Vr2.

With this configuration, the switch control circuit SWC that drives the negative logic switch 42f decreases the voltage (the voltage of the single-ended signal Vd) at the other end of the capacitor 42c from the state (target constant voltage Vtg) exceeding the reference voltage Vr1. When the voltage drops below the reference voltage Vr1 (lower than the configuration of FIG. 7 by the voltage Vdv), the potential shifts from a low potential to a high potential, and conversely, the voltage at the other end of the capacitor 42c (single voltage) When the end signal Vd rises from a state below the reference voltage Vr1 (rises higher than the configuration of FIG. 7 by the voltage Vdv) and exceeds the reference voltage Vr1, the potential is changed from a high potential to a low potential. migration control pulse signal Vct (opposite polarity of the signal from the control pulse signal Vct shown in FIG. 8 (in high voltage period T _H becomes a low potential, a high potential in the low voltage period T _L Comprising signal)) to generate, and outputs the negative logic of the switch 42f. As a result, the negative logic switch 42f shifts from the on state to the off state and from the off state to the on state at the same timing as the positive logic switch 42f of the waveform shaping circuit 42 shown in FIG. That is, as shown in FIG. 22, the waveform shaping circuit 42 including the negative logic switch 42f and the switch control circuit SWC configured for the switch 42f is the waveform shaping circuit 42 (the positive logic switch) shown in FIG. 42f).

  In this manner, a configuration (the configuration of the waveform shaping circuit 42 shown in FIGS. 19, 20, 21, 22) in which the switch 42f of the waveform shaping circuit 42 shown in FIGS. Can also be adopted.

  The signal generation device 2 employs a configuration including the signal generation unit 14 that binarizes the single-ended signal Vd output from the waveform shaping circuit 42 and outputs the binarized signal Vd as the code specifying signal Sf. When the encoding device 3 is configured to process the single-ended signal Vd as it is as the code specifying signal Sf (for example, when the encoding device 3 includes a device corresponding to the signal generation unit 14), the signal generation is performed. A configuration in which the device 2 outputs the single-ended signal Vd as it is as the code specifying signal Sf (a configuration without the signal generation unit 14) may be adopted.

  Further, in the signal reading system 1 described above, the signal generation device 2 outputs the logic pattern of the logic signal Sa in which the arrangement pattern of the “high-potential period” and the “low-potential period” is transmitted via the serial bus SB (ie, The encoding device 3 generates and outputs the code specifying signal Sf that inverts the potential difference (Va−Vb), and inverts the high potential period in the code specifying signal Sf to “1” of the binary data. Although a configuration is adopted in which the code sequence Cs (CAN frame) is specified by executing an encoding process for setting the low potential period in the code specifying signal Sf to “0” of binary data, although not shown, The signal generation device 2 generates a logic pattern (potential difference) of the logic signal Sa in which the arrangement pattern of the “high potential period” and the “low potential period” is transmitted via the serial bus SB. A code specifying signal (a signal whose phase is inverted from the above-described code specifying signal Sf) that matches the pattern of Va-Vb) is generated and output. The encoding process in which the low-potential period is set to “1” of binary data and the high-potential period of the code specifying signal is set to “0” of binary data to specify the code string Cs (CAN frame) A configuration can also be employed.

  Each of the above-described waveform shaping circuits 42 includes a series circuit SC including a fourth impedance element 42e and a switch 42f connected in series, and provides a high-potential-side voltage (voltage during a high voltage period) of the single-ended signal Vd. When defining (fixing) any one voltage of the low-potential-side voltage (voltage during the low-voltage period) to the target constant voltage Vtg, the series circuit SC (that is, the fourth impedance element 42e (the sufficiently low resistance)) is used. ), The target constant voltage Vtg is supplied (applied) with low impedance to the output section 42b from which the single-ended signal Vd is output, but is limited to this configuration. is not.

  For example, the respective waveform shaping circuits 42 shown in FIGS. 5, 7, 9, 10, 13 to 16 will be described as an example. As shown in the corresponding waveform shaping circuits 42 of FIGS. A configuration in which the target constant voltage Vtg can be directly supplied only through the ON-state switch 42f (a configuration in which the target constant voltage Vtg can be supplied in a lower impedance state) can be adopted by eliminating (short-circuiting) 42e. In this configuration, as shown in FIGS. 23 to 30, a configuration in which the fifth impedance element 42 r is provided between the other end of the capacitor 42 c and the output unit 42 b is adopted.

  First, the specific configuration of the waveform shaping circuit 42 of FIG. 23 will be described in comparison with the waveform shaping circuit 42 of FIG. Note that the same components as those of the waveform shaping circuit 42 in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted. In the waveform shaping circuit 42 of FIG. 23, the fourth impedance element 42e of the waveform shaping circuit 42 shown in FIG. 5 is deleted (short-circuited). That is, only the switch 42f is disposed between the potential of the target constant voltage Vtg and the output unit 42b. Further, in the waveform shaping circuit 42 of FIG. 23, a new fifth impedance element 42r is connected at one end to the other end of the capacitor 42c (the end to which the inverting input terminal of the comparator 42g is connected). The other end is connected to the output unit 42b, so that the capacitor 42c is provided between the other end of the capacitor 42c and the output unit 42b.

  With this configuration, in the waveform shaping circuit 42 of FIG. 23, the target is set to an extremely low impedance via the switch 42f in the ON state (lower impedance compared to the configuration of FIG. 5 applied via the fourth impedance element 42e). The voltage Vtg can be applied to the output unit 42b. Thereby, the waveform shaping circuit 42 of FIG. 23 functions in the same manner as the waveform shaping circuit 42 of FIG. 5 to generate and output the single-ended signal Vd from the differential signal Vd0, and to further reduce the falling of the single-ended signal Vd. The steepness can be increased (the time required to shift to the target constant voltage Vtg can be shortened). In addition, the signal generation unit 14 arranged at the subsequent stage compares the single-ended signal Vd with the threshold voltage Vth defined on the basis of the target constant voltage Vtg, so that the single-ended signal Vd is more reliably and more accurately pulse-width-controlled. To generate the code specifying signal Sf.

  Next, a specific configuration of the waveform shaping circuit 42 of FIG. 24 will be described in comparison with the waveform shaping circuit 42 of FIG. Note that the same components as those of the waveform shaping circuit 42 in FIG. 7 are denoted by the same reference numerals, and redundant description will be omitted. Also in the waveform shaping circuit 42 of FIG. 24, the fourth impedance element 42e of the waveform shaping circuit 42 shown in FIG. 7 is deleted (short-circuited). That is, only the switch 42f is disposed between the potential of the target constant voltage Vtg and the output unit 42b. In the waveform shaping circuit 42 of FIG. 24, a new fifth impedance element 42r is connected at one end to the other end of the capacitor 42c (the end to which the non-inverting input terminal of the comparator 42g is connected). The other end is connected to the output unit 42b, so that the capacitor 42c is disposed between the other end of the capacitor 42c and the output unit 42b.

  With this configuration, even in the waveform shaping circuit 42 of FIG. 24, the target is set at an extremely low impedance (a lower impedance than the configuration of FIG. 7 applied via the fourth impedance element 42e) via the switch 42f in the ON state. The voltage Vtg can be applied to the output unit 42b. Accordingly, the waveform shaping circuit 42 of FIG. 24 functions in the same manner as the waveform shaping circuit 42 of FIG. 7 to generate and output the single-ended signal Vd from the difference signal Vd0, and further steeply rises the single-ended signal Vd. (The time required for shifting to the target constant voltage Vtg can be shortened). Further, in this manner, similarly to the waveform shaping circuit 42 of FIG. 23, the signal generation unit 14 arranged at the subsequent stage can generate the code specifying signal Sf binarized with a more accurate pulse width. .

  Next, regarding the specific configuration of the waveform shaping circuit 42 in FIGS. 25 and 27, the waveform shaping circuit 42 in FIG. 25 is compared with the waveform shaping circuit 42 in FIG. The shaping circuit 42 will be described in comparison with the waveform shaping circuit 42 of FIG. The same components as those of the waveform shaping circuit 42 in FIGS. 9 and 13 are denoted by the same reference numerals, and redundant description will be omitted. Also in the waveform shaping circuit 42 of FIGS. 25 and 27, the fourth impedance element 42e of the waveform shaping circuit 42 shown in FIGS. 9 and 13 is deleted (short-circuited). That is, only the switch 42f is disposed between the potential of the target constant voltage Vtg and the output unit 42b. In the waveform shaping circuits 42 of FIGS. 25 and 27, one end of the new fifth impedance element 42r is connected to the other end of the capacitor 42c (the end to which the inverting input terminal of the comparator 42g is connected). At the same time, the other end is connected to the output unit 42b, so that the capacitor 42c is provided between the other end and the output unit 42b.

  With this configuration, the waveform shaping circuit 42 of FIGS. 25 and 27 has an extremely low impedance via the switch 42f in the ON state (a further lower impedance than the configuration of FIGS. 9 and 13 applied via the fourth impedance element 42e). ) Allows the target constant voltage Vtg to be applied to the output section 42b. Accordingly, the waveform shaping circuit 42 of FIGS. 25 and 27 functions in the same manner as the waveform shaping circuit 42 of FIGS. 9 and 13 to generate and output the single-ended signal Vd from the difference signal Vd0, and to generate the single-ended signal Vd. The fall can be made steeper (the time required for shifting to the target constant voltage Vtg can be shortened). Further, in this manner, similarly to the waveform shaping circuit 42 of FIG. 23, the signal generation unit 14 arranged at the subsequent stage can generate the code specifying signal Sf binarized with a more accurate pulse width. .

  Next, the specific configuration of the waveform shaping circuit 42 shown in FIGS. 26 and 28 will be compared with the waveform shaping circuit 42 shown in FIG. The circuit 42 will be described in comparison with the waveform shaping circuit 42 of FIG. The same components as those of the waveform shaping circuit 42 in FIGS. 10 and 14 are denoted by the same reference numerals, and redundant description will be omitted. Also in the waveform shaping circuit 42 of FIGS. 26 and 28, the fourth impedance element 42e of the waveform shaping circuit 42 shown in FIGS. 10 and 14 is deleted (short-circuited). That is, only the switch 42f is disposed between the potential of the target constant voltage Vtg and the output unit 42b. Also, in the waveform shaping circuit 42 of FIGS. 26 and 28, the new fifth impedance element 42r has a first end connected to the other end of the capacitor 42c (a resistive voltage divider formed of two resistors 42i and 42j connected in series). The other end of the circuit 42k (the end on the side of the resistor 42j) and the other end of the circuit 42k are connected to the output section 42b, thereby distributing the circuit between the other end of the capacitor 42c and the output section 42b. Has been established.

  With this configuration, the waveform shaping circuit 42 shown in FIGS. 26 and 28 also has an extremely low impedance via the switch 42f in the ON state (a further lower impedance than the configuration shown in FIGS. 10 and 14 in which the impedance is applied via the fourth impedance element 42e). ) Allows the target constant voltage Vtg to be applied to the output section 42b. Thus, the waveform shaping circuit 42 of FIGS. 26 and 28 functions in the same manner as the waveform shaping circuit 42 of FIGS. 10 and 14, generates and outputs the single-ended signal Vd from the differential signal Vd0, and outputs the single-ended signal Vd. The rise can be made steeper (the time required for shifting to the target constant voltage Vtg can be shortened). Further, in this manner, similarly to the waveform shaping circuit 42 of FIG. 23, the signal generation unit 14 arranged at the subsequent stage can generate the code specifying signal Sf binarized with a more accurate pulse width. .

  Also, in the waveform shaping circuit 42 shown in FIG. 15, the fourth impedance element 42e is deleted (short-circuited) and a new fifth impedance is formed in the same manner as the waveform shaping circuits 42 shown in FIGS. By adding the element 42r, it is possible to configure the waveform shaping circuit 42 shown in FIG. The waveform shaping circuit 42 shown in FIG. 16 also deletes (short-circuits) the fourth impedance element 42e and creates a new fifth impedance in the same manner as the waveform shaping circuits 42 shown in FIGS. By adding the element 42r, it is possible to configure the waveform shaping circuit 42 shown in FIG.

  The waveform shaping circuit 42 shown in FIG. 29 generates and outputs the single-ended signal Vd from the difference signal Vd0 and outputs the single-ended signal Vd in the same manner as the waveform shaping circuits 42 shown in FIGS. The fall can be made steeper (the time required for shifting to the target constant voltage Vtg can be shortened). The waveform shaping circuit 42 shown in FIG. 30 generates and outputs the single-ended signal Vd from the difference signal Vd0 and outputs the single-ended signal Vd in the same manner as the waveform shaping circuit 42 shown in FIGS. Can be made steeper (the time required for shifting to the target constant voltage Vtg can be shortened). Also, in this manner, the waveform shaping circuit 42 shown in FIGS. 29 and 30 is binarized with a more accurate pulse width in the signal generator 14 arranged at the subsequent stage, similarly to the waveform shaping circuit 42 of FIG. The generated code specifying signal Sf can be generated.

  The waveform shaping circuits 42 (circuits in which the switch 42f operates in negative logic) shown in FIGS. 19, 20, 21, and 22 are not shown, but are not shown in FIGS. Similarly, by adopting a configuration in which the fourth impedance element 42e is deleted (short-circuited) and the fifth impedance element 42r is added, the target constant voltage Vtg is directly supplied only through the ON-state switch 42f. You can also get it. Then, the signal having the signal generation device 2 including any one of the above-described waveform shaping circuits 42 adopting a configuration in which the fourth impedance element 42e is deleted (short-circuited) and the fifth impedance element 42r is added as described above. According to the reading system 1, the code Cs indicated by the logic signal Sa can be specified more reliably based on the code specifying signal Sf. The frame can be specified more reliably.

  Further, in the signal reading system 1, as described with reference to FIG. 2, the electrode portion 11a attached to one of the covered conductors La of the serial bus SB is connected to the signal generator 2 via the shielded cable CBa. At the same time, the electrode portion 11b attached to the other coated conductor Lb of the serial bus SB is connected to the signal generator 2 via a shielded cable CBb separate from the shielded cable CBa.

  That is, in the signal reading system 1, as shown in FIG. 31, one of the electrodes 21, which is the electrode 21 of the electrode portion 11 a, has a base end portion on the first impedance element 12 a in the signal generation device 2 (in FIG. (Not shown) is connected to the free end of the first shielded cable CBa connected to the first shielded cable CBa. For this reason, the electrode section 11a and the first shielded cable CBa connect the signal generating device 2 (specifically, the internal first impedance element 12a) to one of the covered conductors La in a non-metal contact state (coupling capacitance). Functions as a first detection probe PLa. The other electrode 21 of the electrode portion 11b is a second shielded cable whose base end is connected to a second impedance element 12b (not shown in the figure) in the signal generator 2. CBb (a shielded cable separate from the first shielded cable CBa) is connected to the free end side. For this reason, the electrode section 11b and the second shielded cable CBb connect the signal generating device 2 (specifically, the internal second impedance element 12b) to the other coated conductor Lb in a non-metallic state (coupling capacitance). Functions as a second detection probe PLb (a detection probe separate from the first detection probe PLa).

  With this configuration (the configuration in which the electrode portions 11a and 11b are arranged on the free ends of a pair of detection probes PLa and PLb formed separately), in the signal reading system 1, the electrode portions 11a and 11b are integrated. As shown in FIG. 31, unlike the configuration which is formed in an arbitrary manner, any two positions (in FIG. 31) at which the electrode portions 11a and 11b are separated along the longitudinal direction (length direction) W of the serial bus SB. As shown in the figure, the electrode portion 11a is connected to the serial bus SB at a first position P1 of the covered conductor La of the covered conductors La and Lb which are generally twisted (twisted) with each other. It can be attached to the second position P2) of the covered conductor Lb to be used. For this reason, although not shown, the electrode portions 11a and 11b are integrally formed, and are attached to the same position along the longitudinal direction W of the serial bus SB (the twisted covered conductors La and Lb are connected to each other). (A configuration in which it is necessary to perform the operation of unwinding at the position and separating the electrode portions 11a and 11b by a distance that can be attached and the operation of simultaneously attaching the electrode portions 11a and 11b to the corresponding covered conductors La and Lb at this position) In contrast, the electrode portions 11a and 11b can be attached to arbitrary positions P1 and P2 where they can be easily attached (in this example, the twisted covered conductors La and Lb are unwound at the positions P1 and P2). Can be attached). In addition, since the electrode portions 11a and 11b are attached to different positions P1 and P2 along the longitudinal direction W of the serial bus SB, the amount of twisting of the twisted covered conductors La and Lb at the positions P1 and P2 is reduced. Can be reduced. Therefore, according to the signal reading system 1, the electrodes 11a and 11b can be securely mounted on the serial bus SB, and the time required for mounting can be reduced (enhancement can be improved).

  Although not shown, each of the detection probes PLa and PLb may be configured to be detachably connected to the signal generation device 2 of the signal reading system 1 via a connector. In addition, the detection probes PLa and PLb are connected to the signal generating device 2 via one common connector, and the respective base end portions (for example, the portion X shown in FIG. 31) of the detection probes PLa and PLb are connected. Alternatively, the parts on the electrode parts 11a and 11b side may be unified (combined) with a heat-shrinkable tube or the like while being exposed to some extent. Further, the signal reading system 1 of FIG. 31 employs a configuration in which the base ends of the detection probes PLa and PLb are respectively connected to the signal generating device 2, but the configuration is not limited to this.

  For example, as in the signal reading system 1 shown in FIG. 32, the base end sides of the detection probes PLa and PLb are connected to a connection portion 51 such as a connection box connected to the signal generation device 2 via a two-core shielded wire CBc. It is also possible to adopt a configuration for connecting each. In this configuration, the base end of the two-core shielded wire CBc is connected to the signal generation device 2 via a connector (not shown), and the two core wires are connected to each impedance element in the signal generation device 2 via this connector. 12a and 12b, and a shield (not shown) is connected to a ground G in the signal generator 2 via a connector. Further, the connection portion 51 is connected to the free end side of the two-core shielded wire CBc. In this case, in the connection portion 51, one of the core wires included in the two-core shield wire CBc and connected to the impedance element 12a is connected to the core wire of the shielded cable constituting the corresponding detection probe PLa, and The other core wire included in the wire CBc and connected to the impedance element 12b is connected to the core wire of a shield cable constituting the corresponding detection probe PLb, and the shield of the two-core shield wire CBc is connected to the detection probes PLa and PLb. A connection circuit (not shown) for connecting to the shield of each shielded cable is provided.

  Also in the signal reading system 1 shown in FIG. 32, since the electrode portions 11a and 11b are arranged on the free ends of a pair of detection probes PLa and PLb formed separately, the signal reading system 1 shown in FIG. The same effect as that of the signal reading system 1 shown can be obtained.

  Further, in each of the signal reading systems 1 described above, the signal generation device 2 includes the covered conductors via the electrode portions 11a and 11b capacitively coupled to the metal parts (core wires) of the covered conductors La and Lb and the shielded cables CBa and CBb. Voltage signals Vc1 and Vc2, which are connected to La and Lb and change in voltage according to the voltages Va and Vb of the voltage signals Va and Vb transmitted to the covered conductors La and Lb, are generated. , Vc2 to generate a code specifying signal Sf capable of specifying a code Cs corresponding to the voltage signals Va, Vb (that is, a configuration using the detection probes PLa, PLb functioning as voltage detection probes). , But is not limited to this configuration.

  For example, instead of the detection probes PLa and PLb, as shown in FIG. 33, a pair of current detection probes PLc and PLd (a clamp type that can be attached to the covered conductors La and Lb without cutting the covered conductors La and Lb). A current detection probe (preferably) may be connected to the signal generation device 2 to generate the code specifying signal Sf. Various known current detection probes can be used as the current detection probes PLc and PLd. However, in the following, an example is disclosed in JP-A-2006-343109, which has already been proposed by the present applicant. An example using the current detection probe described above will be described.

  As shown in FIG. 33, the current detection probes PLc and PLd are formed in a substantially circular shape, and the tip thereof is configured to be freely openable and closable. And a current sensor (not shown) composed of a coil having a winding wound around a core. This current sensor flows through the corresponding covered conductor in a state where the corresponding covered conductor (the covered conductor La for the current detection probe PLc and the covered conductor Lb for the current detection probe PLd) is sandwiched (clamped) at each clamp portion 61. Current (current Ia flowing through the covered conductor La and current Ib flowing through the covered conductor Lb), and a current-corresponding signal Vi whose current value is proportional to the current value (a current-corresponding signal Via for the current Ia) And the current corresponding signal Vib) for the current Ib is output to the signal generator 2 as a detection signal. Although the current detection probes PLc and PLd are configured as AC current detection probes (AC current detection probes) in the above configuration, the current detection probes PLc and PLd measure not only the AC current but also the DC current as the current detection probes PLc and PLd. Needless to say, a DC current detection probe (DC current detection probe) that can be used may be employed.

  Since the current value of the current Ia flowing through the insulated wire La changes in accordance with the voltage Va of the voltage signal Va transmitted to the insulated wire La, the current corresponding signal Via changes in accordance with the voltage Va of the voltage signal Va. The voltage value changes. Further, the current value of the current Ib flowing through the insulated conductor Lb changes according to the voltage Vb of the voltage signal Vb transmitted to the insulated conductor Lb. The voltage value changes accordingly. Therefore, in the signal generation device 2, even in the configuration in which the current detection probes PLc and PLd are connected, the differential amplifier circuit 41 (the above-described various configurations) is connected in the same manner as in the configuration in which the detection probes PLa and PLb are connected. One of the differential amplifier circuits 41) generates and outputs the difference signal Vd0 based on the current-corresponding signals Via and Vib, and outputs the difference signal Vd0 to the waveform shaping circuit 42 (of the various waveform shaping circuits 42 described above). Any one of them generates and outputs a single-ended signal Vd from the difference signal Vd0, and the signal generation unit 14 (one corresponding to the waveform shaping circuit 42 among the various signal generation units 14 described above) generates the single-ended signal Vd. The single end signal Vd can be binarized to generate and output the code specifying signal Sf (see FIG. 2).

  Therefore, according to the signal generation device 2 having the configuration shown in FIG. 33 and the signal reading system 1 including the signal generation device 2, the current detection probe PLc is provided at an arbitrary position in the longitudinal direction W of the pair of covered conductors La and Lb. , PLd (in this example, clamping the clamp portion 61), the code Cs indicated by the logic signal Sa transmitted via the serial bus SB can be specified. The code specifying signal Sf is generated, and the code Cs indicated by the logic signal Sa can be specified based on the generated code specifying signal Sf. Can be specified. Thus, even if the connector is not provided on the serial bus SB, or even if the connector is provided on the serial bus SB, any location (the first position P1 and the second position P1) on the serial bus SB can be used. The logic signal Sa is read at the position P2), and the code Cs and the CAN frame including the code Cs can be specified.

1 Signal reading system
Reference Signs List 2 signal generator 12a first impedance element 12b second impedance element 13 differential amplifier 14 signal generator 21 electrode 41 differential amplifier 42 waveform shaping circuit La, Lb coated conductor Sa logic signal Sf code specifying signal Va, Vb Voltage (voltage transmitted to coated conductor)
Vc1 First voltage signal Vc2 Second voltage signal Vd Single-ended signal Vd0 Difference signal

Claims (24)

A signal generation device that generates a code specifying signal capable of specifying a code corresponding to the logic signal based on a two-wire differential voltage type logic signal transmitted via a communication path including a pair of covered conductors. So,
The one of the pair of electrodes, which is brought into contact with the covering portion of the pair of covered wires, is connected to one of the pair of covered wires, and is transmitted to the one of the covered wires that is capacitively coupled to the one of the pair of covered wires. A first impedance element that generates a first voltage signal whose voltage changes according to the voltage being applied;
A second voltage that is connected to the other electrode of the pair of electrodes and changes in voltage according to the voltage transmitted to the other coated conductor that is capacitively coupled to the other electrode of the pair of covered wires. A second impedance element for generating a voltage signal;
A differential amplifier that receives the first voltage signal and the second voltage signal and outputs a single-ended signal whose voltage changes in accordance with a difference voltage between the respective voltage signals. And a signal generation device for generating the code specifying signal.   The signal generation device according to claim 1, further comprising a signal generation unit configured to generate the code specifying signal by binarizing the single-ended signal by comparing the single-ended signal with a threshold voltage.   A differential amplifier circuit that receives the first voltage signal and the second voltage signal and outputs a differential signal having a voltage that changes in accordance with the differential voltage; 2. A waveform shaping circuit for shaping and outputting the single-ended signal having a peak-to-peak voltage equivalent to the peak-to-peak voltage of the AC component of the signal and having a low voltage period defined as a target constant voltage, and outputting the signal. Or the signal generator according to 2.   A differential amplifier circuit that receives the first voltage signal and the second voltage signal and outputs a differential signal having a voltage that changes in accordance with the differential voltage; 2. A waveform shaping circuit for shaping and outputting a single-ended signal having a peak-to-peak voltage equivalent to the peak-to-peak voltage of an AC component of a signal and a high-voltage period defined as a target constant voltage and outputting the signal. Or the signal generator according to 2. The waveform shaping circuit,
A capacitor having one end connected to the input unit to which the difference signal is input and the other end connected to the output unit;
A third impedance element having one end connected to the other end of the capacitor and a target constant voltage applied to the other end, and supplying the target constant voltage to the other end of the capacitor;
A series circuit comprising a fourth impedance element and a switch connected in series, one end of which is connected to the output unit and the other end of which is applied with the target constant voltage;
And a switch control circuit that outputs a control pulse signal that shifts the switch to an off state during a high voltage period of the AC component while the switch is turned on during a low voltage period of the AC component of the difference signal. 4. The signal generating device according to claim 3, wherein the single-ended signal is output from the output unit. The waveform shaping circuit,
A capacitor having one end connected to the input unit to which the difference signal is input and the other end connected to the output unit;
A third impedance element having one end connected to the other end of the capacitor and a target constant voltage applied to the other end, and supplying the target constant voltage to the other end of the capacitor;
A series circuit comprising a fourth impedance element and a switch connected in series, one end of which is connected to the output unit and the other end of which is applied with the target constant voltage;
A switch control circuit that outputs a control pulse signal that causes the switch to transition to an on state during a high voltage period in an AC component of the differential signal and transitions the switch to an off state during a low voltage period in the AC component. 5. The signal generator according to claim 4, wherein the single-ended signal is output from the output unit. The waveform shaping circuit,
A capacitor having one end connected to an input unit to which the difference signal is input;
A third impedance element having one end connected to the other end of the capacitor and a target constant voltage applied to the other end to supply the target constant voltage to the other end of the capacitor;
A fifth impedance element having one end connected to the other end of the capacitor and the other end connected to the output unit;
A switch that is connected to the output unit and applies the target constant voltage to the output unit when in an on state, and stops applying the target constant voltage to the output unit when in an off state.
A switch control circuit that outputs the control pulse signal that causes the switch to transition to the off state during the high voltage period of the AC component, while causing the switch to transition to the on state during the low voltage period of the AC component of the difference signal. 4. The signal generation device according to claim 3, further comprising: outputting the single-ended signal from the output unit. The waveform shaping circuit,
A capacitor having one end connected to an input unit to which the difference signal is input;
A third impedance element having one end connected to the other end of the capacitor and a target constant voltage applied to the other end to supply the target constant voltage to the other end of the capacitor;
A fifth impedance element having one end connected to the other end of the capacitor and the other end connected to the output unit;
A switch that is connected to the output unit and applies the target constant voltage to the output unit when in an on state, and stops applying the target constant voltage to the output unit when in an off state.
A switch control circuit that outputs the control pulse signal that causes the switch to shift to the off state during a low voltage period of the AC component while causing the switch to shift to the on state during a high voltage period of the AC component of the difference signal. The signal generation device according to claim 4, further comprising: outputting the single-ended signal from the output unit. The switch is configured to transition to an on state when the control pulse signal is at a high potential, and to transition to an off state when the control pulse signal is at a low potential,
The switch control circuit has an inverting input terminal connected to the other end of the capacitor, and a reference voltage higher than the target constant voltage is input to a non-inverting input terminal, and outputs the control pulse signal from an output terminal. The signal generation device according to claim 5, wherein the signal generation device includes a comparator that performs the operation. The switch is configured to transition to an on state when the control pulse signal is at a low potential, and to transition to an off state when the control pulse signal is at a high potential,
In the switch control circuit, a non-inverting input terminal is connected to the other end of the capacitor, and a reference voltage higher than the target constant voltage is input to an inverting input terminal, and the control pulse signal is output from an output terminal. The signal generation device according to claim 5, wherein the signal generation device includes a comparator that performs the operation. The switch is configured to transition to an on state when the control pulse signal is at a high potential, and to transition to an off state when the control pulse signal is at a low potential,
The switch control circuit has a non-inverting input terminal connected to the other end of the capacitor, and a reference voltage lower than the target constant voltage is input to an inverting input terminal, and the control pulse signal is output from an output terminal. 9. The signal generation device according to claim 6, wherein the signal generation device includes a comparator that performs the operation. The switch is configured to transition to an on state when the control pulse signal is at a low potential, and to transition to an off state when the control pulse signal is at a high potential,
The switch control circuit has an inverting input terminal connected to the other end of the capacitor, and a reference voltage lower than the target constant voltage is input to a non-inverting input terminal, and outputs the control pulse signal from an output terminal. 9. The signal generation device according to claim 6, wherein the signal generation device includes a comparator that performs the operation. The switch is configured to transition to an on state when the control pulse signal is at a high potential, and to transition to an off state when the control pulse signal is at a low potential,
The switch control circuit,
A comparator having an inverting input terminal connected to the other end of the capacitor and outputting the control pulse signal from an output terminal;
One end is connected to the output terminal, and the other end is applied with any one of the target constant voltage and a voltage near the target constant voltage. 8. The signal generating device according to claim 5, further comprising: a resistive voltage dividing circuit that outputs a divided voltage defined by the following voltage to a non-inverting input terminal of the comparator as a reference voltage. The switch is configured to transition to an on state when the control pulse signal is at a low potential, and to transition to an off state when the control pulse signal is at a high potential,
The switch control circuit,
A comparator that outputs any one of the target constant voltage and a voltage near the target constant voltage to the inverting input terminal and outputs the control pulse signal from an output terminal;
One end is connected to the output terminal and the other end is connected to the other end of the capacitor, and the divided pulse signal defined by the voltage of the single-ended signal and the voltage of the control pulse signal. 8. The signal generating device according to claim 5, further comprising: a resistor voltage dividing circuit that outputs a voltage to a non-inverting input terminal of the comparator. The switch is configured to transition to an on state when the control pulse signal is at a high potential, and to transition to an off state when the control pulse signal is at a low potential,
The switch control circuit,
A comparator that outputs any one of the target constant voltage and a voltage near the target constant voltage to the inverting input terminal and outputs the control pulse signal from an output terminal;
One end is connected to the output terminal and the other end is connected to the other end of the capacitor, and the divided pulse signal defined by the voltage of the single-ended signal and the voltage of the control pulse signal. 9. The signal generating device according to claim 6, further comprising: a resistor voltage dividing circuit that outputs a voltage to a non-inverting input terminal of the comparator. The switch is configured to transition to an on state when the control pulse signal is at a low potential, and to transition to an off state when the control pulse signal is at a high potential,
The switch control circuit,
A comparator having an inverting input terminal connected to the other end of the capacitor and outputting the control pulse signal from an output terminal;
One end is connected to the output terminal, and the other end is applied with any one of the target constant voltage and a voltage near the target constant voltage. 9. The signal generating device according to claim 6, further comprising: a resistor voltage dividing circuit that outputs a divided voltage defined by the following voltage to a non-inverting input terminal of the comparator as a reference voltage. The switch control circuit,
A resistor voltage dividing circuit having one end connected to the output unit and the other end applied with the target constant voltage, and dividing the single-ended signal to output a divided pulse signal;
A bias voltage source that generates a bias voltage based on the target constant voltage,
6. The signal generating device according to claim 5, further comprising an adder that adds the bias voltage to the divided pulse signal and outputs the added voltage as the control pulse signal.   The switch is controlled by the control pulse signal, and outputs the target constant voltage from the output terminal to the output unit when the switch is on, and shifts the output terminal to a high impedance state when the switch is off. The signal generation device according to claim 5, wherein the signal generation device includes a buffer.   19. The D / A converter according to claim 3, further comprising: a D / A converter that D / A converts voltage data input from the outside and outputs the target constant voltage having a voltage value indicated by the voltage data. Signal generator. The differential amplifier circuit,
The first voltage signal is input to a non-inverting input terminal, a first series circuit of an input resistor and a capacitor is connected between the inverting input terminal and a reference potential, and a feedback resistor is connected between the inverting input terminal and the output terminal. Are connected, and a first operational amplifier configured as an AC amplifier that amplifies and outputs an AC component of the first voltage signal;
A second operational amplifier configured identically to the first operational amplifier and configured as an AC amplifier that receives the second voltage signal at a non-inverting input terminal and amplifies and outputs an AC component of the second voltage signal. An amplifier,
20. The device according to claim 3, further comprising a third operational amplifier configured as a differential amplifier that amplifies a difference between respective output signals of the first operational amplifier and the second operational amplifier and outputs the difference signal. A signal generation device according to any one of claims 1 to 3.   21. The signal generation device according to claim 1, wherein the first impedance element and the second impedance element are both configured by a high impedance resistor or a capacitor, or a combination thereof. The one electrode is connected to a free end of a first shielded cable whose base end is connected to the first impedance element,
The other electrode is a second shielded cable separate from the first shielded cable, and has a base end connected to a free end of the second shielded cable connected to the second impedance element. The signal generation device according to claim 1. A signal generation device that generates a code specifying signal capable of specifying a code corresponding to the logic signal based on a two-wire differential voltage type logic signal transmitted via a communication path including a pair of covered conductors. So,
A current that is attached to one of the covered conductors of the pair of covered conductors and is a current flowing through the one covered conductor, and a current of which current value changes according to a voltage transmitted to the one covered conductor. A first current detection probe that detects and outputs a first voltage signal whose voltage value changes in accordance with the current value; and a first current detection probe that is attached to the other of the pair of coated conductors, and A current flowing through the conductor, the current of which changes according to the voltage transmitted to the other coated conductor is detected, and a second voltage signal whose voltage changes according to the current is output. Differential amplifier connected to the second current detection probe for receiving the first voltage signal and the second voltage signal and outputting a single-ended signal whose voltage changes according to a difference voltage between the voltage signals. It includes a signal generator for generating the code specific signal based on the single-ended signal. A signal generation device according to any one of claims 1 to 23,
A signal reading system comprising: an encoding device that identifies the code corresponding to the logic signal based on the code identification signal generated by the signal generation device.

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