JP2019521365A5 - - Google Patents

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JP2019521365A5
JP2019521365A5 JP2019503643A JP2019503643A JP2019521365A5 JP 2019521365 A5 JP2019521365 A5 JP 2019521365A5 JP 2019503643 A JP2019503643 A JP 2019503643A JP 2019503643 A JP2019503643 A JP 2019503643A JP 2019521365 A5 JP2019521365 A5 JP 2019521365A5
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logic
pattern
serializer
pulse
signal
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JP2019503643A
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JP2019521365A (ja
JP7267911B2 (ja
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JP2019503643A 2016-04-08 2017-04-07 マルチギガビットシリアルトランシーバ(serdes)に基づくビームフォーミング再構成可能な相関器(パルス圧縮受信機) Active JP7267911B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022083439A JP2022116118A (ja) 2016-04-08 2022-05-20 マルチギガビットシリアルトランシーバ(serdes)に基づくビームフォーミング再構成可能な相関器(パルス圧縮受信機)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662320159P 2016-04-08 2016-04-08
US62/320,159 2016-04-08
US15/406,113 2017-01-13
US15/406,113 US10656244B2 (en) 2016-04-08 2017-01-13 Reconfigurable correlator (pulse compression receiver) and beam former based on multi-gigabit serial transceivers (SERDES)
PCT/US2017/026715 WO2017177201A1 (en) 2016-04-08 2017-04-07 Beam-forming reconfigurable correlator (pulse compression receiver) based on multi-gigabit serial transceivers (serdes)

Related Child Applications (1)

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JP2022083439A Division JP2022116118A (ja) 2016-04-08 2022-05-20 マルチギガビットシリアルトランシーバ(serdes)に基づくビームフォーミング再構成可能な相関器(パルス圧縮受信機)

Publications (3)

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JP2019521365A JP2019521365A (ja) 2019-07-25
JP2019521365A5 true JP2019521365A5 (https=) 2021-06-10
JP7267911B2 JP7267911B2 (ja) 2023-05-02

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JP2019503643A Active JP7267911B2 (ja) 2016-04-08 2017-04-07 マルチギガビットシリアルトランシーバ(serdes)に基づくビームフォーミング再構成可能な相関器(パルス圧縮受信機)
JP2022083439A Pending JP2022116118A (ja) 2016-04-08 2022-05-20 マルチギガビットシリアルトランシーバ(serdes)に基づくビームフォーミング再構成可能な相関器(パルス圧縮受信機)

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Country Status (4)

Country Link
US (1) US10656244B2 (https=)
EP (1) EP3440479A4 (https=)
JP (2) JP7267911B2 (https=)
WO (2) WO2017177201A1 (https=)

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