JP2019517687A5 - - Google Patents

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Publication number
JP2019517687A5
JP2019517687A5 JP2018555617A JP2018555617A JP2019517687A5 JP 2019517687 A5 JP2019517687 A5 JP 2019517687A5 JP 2018555617 A JP2018555617 A JP 2018555617A JP 2018555617 A JP2018555617 A JP 2018555617A JP 2019517687 A5 JP2019517687 A5 JP 2019517687A5
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JP
Japan
Prior art keywords
processor
host
memory
coherence
cache
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JP2018555617A
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English (en)
Japanese (ja)
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JPWO2017209883A5 (https=
JP7160682B2 (ja
JP2019517687A (ja
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Priority claimed from US15/169,118 external-priority patent/US10503641B2/en
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JP2018555617A 2016-05-31 2017-05-02 メモリにおける処理のためのキャッシュコヒーレンス Active JP7160682B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/169,118 US10503641B2 (en) 2016-05-31 2016-05-31 Cache coherence for processing in memory
US15/169,118 2016-05-31
PCT/US2017/030586 WO2017209883A1 (en) 2016-05-31 2017-05-02 Cache coherence for processing in memory

Publications (4)

Publication Number Publication Date
JP2019517687A JP2019517687A (ja) 2019-06-24
JP2019517687A5 true JP2019517687A5 (https=) 2022-07-15
JPWO2017209883A5 JPWO2017209883A5 (https=) 2022-07-15
JP7160682B2 JP7160682B2 (ja) 2022-10-25

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US (1) US10503641B2 (https=)
EP (1) EP3465445B1 (https=)
JP (1) JP7160682B2 (https=)
KR (1) KR102442079B1 (https=)
CN (1) CN109154910B (https=)
WO (1) WO2017209883A1 (https=)

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