JP7160682B2 - メモリにおける処理のためのキャッシュコヒーレンス - Google Patents

メモリにおける処理のためのキャッシュコヒーレンス Download PDF

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JP7160682B2
JP7160682B2 JP2018555617A JP2018555617A JP7160682B2 JP 7160682 B2 JP7160682 B2 JP 7160682B2 JP 2018555617 A JP2018555617 A JP 2018555617A JP 2018555617 A JP2018555617 A JP 2018555617A JP 7160682 B2 JP7160682 B2 JP 7160682B2
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memory
processor
host
coherence
cache
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JP2019517687A5 (https=
JPWO2017209883A5 (https=
JP2019517687A (ja
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ダブリュ． ボイヤー マイケル
ジャヤセーナ ヌワン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1004—Compatibility, e.g. with legacy hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2018555617A 2016-05-31 2017-05-02 メモリにおける処理のためのキャッシュコヒーレンス Active JP7160682B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/169,118 US10503641B2 (en) 2016-05-31 2016-05-31 Cache coherence for processing in memory
US15/169,118 2016-05-31
PCT/US2017/030586 WO2017209883A1 (en) 2016-05-31 2017-05-02 Cache coherence for processing in memory

Publications (4)

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JP2019517687A JP2019517687A (ja) 2019-06-24
JP2019517687A5 JP2019517687A5 (https=) 2022-07-15
JPWO2017209883A5 JPWO2017209883A5 (https=) 2022-07-15
JP7160682B2 true JP7160682B2 (ja) 2022-10-25

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US (1) US10503641B2 (https=)
EP (1) EP3465445B1 (https=)
JP (1) JP7160682B2 (https=)
KR (1) KR102442079B1 (https=)
CN (1) CN109154910B (https=)
WO (1) WO2017209883A1 (https=)

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US11467834B2 (en) * 2020-04-01 2022-10-11 Samsung Electronics Co., Ltd. In-memory computing with cache coherent protocol
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KR102911993B1 (ko) 2020-09-07 2026-01-12 삼성전자 주식회사 가변적인 모드 설정을 수행하는 메모리 장치 및 그 동작방법
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Publication number Publication date
EP3465445A1 (en) 2019-04-10
US20170344479A1 (en) 2017-11-30
WO2017209883A1 (en) 2017-12-07
US10503641B2 (en) 2019-12-10
KR102442079B1 (ko) 2022-09-08
EP3465445A4 (en) 2020-01-22
CN109154910A (zh) 2019-01-04
CN109154910B (zh) 2023-08-08
EP3465445B1 (en) 2021-06-23
KR20190003564A (ko) 2019-01-09
JP2019517687A (ja) 2019-06-24

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