KR102442079B1 - 메모리에서의 처리를 위한 캐시 일관성 - Google Patents

메모리에서의 처리를 위한 캐시 일관성 Download PDF

Info

Publication number
KR102442079B1
KR102442079B1 KR1020187032457A KR20187032457A KR102442079B1 KR 102442079 B1 KR102442079 B1 KR 102442079B1 KR 1020187032457 A KR1020187032457 A KR 1020187032457A KR 20187032457 A KR20187032457 A KR 20187032457A KR 102442079 B1 KR102442079 B1 KR 102442079B1
Authority
KR
South Korea
Prior art keywords
memory
host
processor
coherency
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020187032457A
Other languages
English (en)
Korean (ko)
Other versions
KR20190003564A (ko
Inventor
마이클 더블유. 보이어
누완 자야세나
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20190003564A publication Critical patent/KR20190003564A/ko
Application granted granted Critical
Publication of KR102442079B1 publication Critical patent/KR102442079B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1004—Compatibility, e.g. with legacy hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020187032457A 2016-05-31 2017-05-02 메모리에서의 처리를 위한 캐시 일관성 Active KR102442079B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/169,118 US10503641B2 (en) 2016-05-31 2016-05-31 Cache coherence for processing in memory
US15/169,118 2016-05-31
PCT/US2017/030586 WO2017209883A1 (en) 2016-05-31 2017-05-02 Cache coherence for processing in memory

Publications (2)

Publication Number Publication Date
KR20190003564A KR20190003564A (ko) 2019-01-09
KR102442079B1 true KR102442079B1 (ko) 2022-09-08

Family

ID=60418710

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020187032457A Active KR102442079B1 (ko) 2016-05-31 2017-05-02 메모리에서의 처리를 위한 캐시 일관성

Country Status (6)

Country Link
US (1) US10503641B2 (https=)
EP (1) EP3465445B1 (https=)
JP (1) JP7160682B2 (https=)
KR (1) KR102442079B1 (https=)
CN (1) CN109154910B (https=)
WO (1) WO2017209883A1 (https=)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10866900B2 (en) 2017-10-17 2020-12-15 Samsung Electronics Co., Ltd. ISA extension for high-bandwidth memory
US10474545B1 (en) 2017-10-31 2019-11-12 EMC IP Holding Company LLC Storage system with distributed input-output sequencing
US10365980B1 (en) * 2017-10-31 2019-07-30 EMC IP Holding Company LLC Storage system with selectable cached and cacheless modes of operation for distributed storage virtualization
KR20190075363A (ko) * 2017-12-21 2019-07-01 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 모듈
KR102879034B1 (ko) * 2019-03-11 2025-10-29 삼성전자주식회사 연산 처리를 수행하는 메모리 장치 및 메모리 장치의 동작방법
DE102020106357A1 (de) 2019-03-11 2020-09-17 Samsung Electronics Co., Ltd. Speichereinrichtung und verfahren mit anweisungsringspeicherwarteschlange
US11288195B2 (en) * 2019-03-22 2022-03-29 Arm Limited Data processing
CN110059023B (zh) * 2019-04-04 2020-11-10 创新先进技术有限公司 一种刷新级联缓存的方法、系统及设备
US10922236B2 (en) 2019-04-04 2021-02-16 Advanced New Technologies Co., Ltd. Cascade cache refreshing
US11126537B2 (en) 2019-05-02 2021-09-21 Microsoft Technology Licensing, Llc Coprocessor-based logging for time travel debugging
US11586369B2 (en) * 2019-05-29 2023-02-21 Xilinx, Inc. Hybrid hardware-software coherent framework
CN111176582A (zh) * 2019-12-31 2020-05-19 北京百度网讯科技有限公司 矩阵存储方法、矩阵访问方法、装置和电子设备
US11138114B2 (en) * 2020-01-08 2021-10-05 Microsoft Technology Licensing, Llc Providing dynamic selection of cache coherence protocols in processor-based devices
US11023375B1 (en) * 2020-02-21 2021-06-01 SiFive, Inc. Data cache with hybrid writeback and writethrough
US11467834B2 (en) * 2020-04-01 2022-10-11 Samsung Electronics Co., Ltd. In-memory computing with cache coherent protocol
KR102935786B1 (ko) 2020-06-11 2026-03-09 삼성전자주식회사 메모리 모듈 및 그의 동작 방법
US11360906B2 (en) 2020-08-14 2022-06-14 Alibaba Group Holding Limited Inter-device processing system with cache coherency
KR102911993B1 (ko) 2020-09-07 2026-01-12 삼성전자 주식회사 가변적인 모드 설정을 수행하는 메모리 장치 및 그 동작방법
DE102021121105A1 (de) 2020-09-28 2022-03-31 Samsung Electronics Co., Ltd. Intelligente ablagespeichervorrichtung
US11556344B2 (en) * 2020-09-28 2023-01-17 Xilinx, Inc. Hardware coherent computational expansion memory
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
JP2023007601A (ja) * 2021-07-02 2023-01-19 株式会社日立製作所 ストレージシステム制御方法及びストレージシステム
US11797442B2 (en) * 2021-10-18 2023-10-24 Andes Technology Corporation Integrated circuit and method for executing cache management operation
US12136138B2 (en) 2021-11-11 2024-11-05 Samsung Electronics Co., Ltd. Neural network training with acceleration
US12333625B2 (en) 2021-11-11 2025-06-17 Samsung Electronics Co., Ltd. Neural network training with acceleration
US11989142B2 (en) 2021-12-10 2024-05-21 Samsung Electronics Co., Ltd. Efficient and concurrent model execution
US12197350B2 (en) 2021-12-10 2025-01-14 Samsung Electronics Co., Ltd. Low-latency input data staging to execute kernels
US12164445B1 (en) * 2022-02-03 2024-12-10 Amazon Technologies, Inc. Coherent agents for memory access
US12475050B2 (en) 2022-03-03 2025-11-18 Samsung Electronics Co., Ltd. Cache-coherent interconnect based near-data-processing accelerator
US11809323B1 (en) * 2022-06-22 2023-11-07 Seagate Technology Llc Maintaining real-time cache coherency during distributed computational functions
US12367144B2 (en) * 2023-06-16 2025-07-22 Google Llc Cache control instructions using object lifetime information
US12596650B2 (en) 2023-09-29 2026-04-07 Advanced Micro Devices, Inc. Preemptive flushing of processing-in-memory data structures
US12455826B2 (en) * 2024-03-29 2025-10-28 Advanced Micro Devices, Inc. Dynamic caching policies for processing-in-memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140149681A1 (en) 2012-11-27 2014-05-29 International Business Machines Corporation Coherent proxy for attached processor
US20140181417A1 (en) * 2012-12-23 2014-06-26 Advanced Micro Devices, Inc. Cache coherency using die-stacked memory device with logic die

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816474A (ja) * 1994-06-29 1996-01-19 Hitachi Ltd マルチプロセッサシステム
US5829034A (en) * 1996-07-01 1998-10-27 Sun Microsystems, Inc. Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains
US6269428B1 (en) 1999-02-26 2001-07-31 International Business Machines Corporation Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system
US6338123B2 (en) 1999-03-31 2002-01-08 International Business Machines Corporation Complete and concise remote (CCR) directory
US6751705B1 (en) * 2000-08-25 2004-06-15 Silicon Graphics, Inc. Cache line converter
US6470429B1 (en) * 2000-12-29 2002-10-22 Compaq Information Technologies Group, L.P. System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops
US6463510B1 (en) * 2000-12-29 2002-10-08 Compaq Information Technologies Group, L.P. Apparatus for identifying memory requests originating on remote I/O devices as noncacheable
US7177987B2 (en) 2004-01-20 2007-02-13 Hewlett-Packard Development Company, L.P. System and method for responses between different cache coherency protocols
US20050216637A1 (en) * 2004-03-23 2005-09-29 Smith Zachary S Detecting coherency protocol mode in a virtual bus interface
US7167956B1 (en) * 2004-05-03 2007-01-23 Sun Microsystems, Inc. Avoiding inconsistencies between multiple translators in an object-addressed memory hierarchy
US7552236B2 (en) 2005-07-14 2009-06-23 International Business Machines Corporation Routing interrupts in a multi-node system
US7395376B2 (en) 2005-07-19 2008-07-01 International Business Machines Corporation Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of shared memory blocks
US7376799B2 (en) 2005-07-21 2008-05-20 Hewlett-Packard Development Company, L.P. System for reducing the latency of exclusive read requests in a symmetric multi-processing system
US7748037B2 (en) 2005-09-22 2010-06-29 Intel Corporation Validating a memory type modification attempt
US8539164B2 (en) * 2007-04-30 2013-09-17 Hewlett-Packard Development Company, L.P. Cache coherency within multiprocessor computer system
US7941613B2 (en) 2007-05-31 2011-05-10 Broadcom Corporation Shared memory architecture
US8082400B1 (en) 2008-02-26 2011-12-20 Hewlett-Packard Development Company, L.P. Partitioning a memory pool among plural computing nodes
US8473644B2 (en) * 2009-03-04 2013-06-25 Freescale Semiconductor, Inc. Access management technique with operation translation capability
US8176220B2 (en) 2009-10-01 2012-05-08 Oracle America, Inc. Processor-bus-connected flash storage nodes with caching to support concurrent DMA accesses from multiple processors
US8543770B2 (en) * 2010-05-26 2013-09-24 International Business Machines Corporation Assigning memory to on-chip coherence domains
US20120124297A1 (en) 2010-11-12 2012-05-17 Jaewoong Chung Coherence domain support for multi-tenant environment
DE112011103433B4 (de) * 2010-11-26 2019-10-31 International Business Machines Corporation Verfahren, System und Programm zum Steuern von Cache-Kohärenz
US9753858B2 (en) 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows
GB2514024B (en) 2012-03-02 2020-04-08 Advanced Risc Mach Ltd Data processing apparatus having first and second protocol domains, and method for the data processing apparatus
US20140018141A1 (en) * 2012-07-11 2014-01-16 Sergey Anikin Method for expanding sales through computer game
US8922243B2 (en) 2012-12-23 2014-12-30 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
JP6139689B2 (ja) * 2012-10-22 2017-05-31 インテル・コーポレーション 装置
US9442852B2 (en) 2012-11-27 2016-09-13 International Business Machines Corporation Programmable coherent proxy for attached processor
US9235528B2 (en) 2012-12-21 2016-01-12 Advanced Micro Devices, Inc. Write endurance management techniques in the logic layer of a stacked memory
US9251069B2 (en) 2012-12-21 2016-02-02 Advanced Micro Devices, Inc. Mechanisms to bound the presence of cache blocks with specific properties in caches
US9135185B2 (en) 2012-12-23 2015-09-15 Advanced Micro Devices, Inc. Die-stacked memory device providing data translation
US9244629B2 (en) 2013-06-25 2016-01-26 Advanced Micro Devices, Inc. Method and system for asymmetrical processing with managed data affinity
CN106462501B (zh) 2014-05-08 2019-07-09 美光科技公司 基于混合存储器立方体系统互连目录的高速缓冲存储器一致性方法
US10825496B2 (en) 2014-05-08 2020-11-03 Micron Technology, Inc. In-memory lightweight memory coherence protocol
US9542316B1 (en) * 2015-07-23 2017-01-10 Arteris, Inc. System and method for adaptation of coherence models between agents

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140149681A1 (en) 2012-11-27 2014-05-29 International Business Machines Corporation Coherent proxy for attached processor
US20140181417A1 (en) * 2012-12-23 2014-06-26 Advanced Micro Devices, Inc. Cache coherency using die-stacked memory device with logic die

Also Published As

Publication number Publication date
EP3465445A1 (en) 2019-04-10
US20170344479A1 (en) 2017-11-30
WO2017209883A1 (en) 2017-12-07
US10503641B2 (en) 2019-12-10
JP7160682B2 (ja) 2022-10-25
EP3465445A4 (en) 2020-01-22
CN109154910A (zh) 2019-01-04
CN109154910B (zh) 2023-08-08
EP3465445B1 (en) 2021-06-23
KR20190003564A (ko) 2019-01-09
JP2019517687A (ja) 2019-06-24

Similar Documents

Publication Publication Date Title
KR102442079B1 (ko) 메모리에서의 처리를 위한 캐시 일관성
US11908546B2 (en) In-memory lightweight memory coherence protocol
US7373466B1 (en) Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
JP4230998B2 (ja) リモートキャッシュプレゼンス情報を記録するプロセッサキャッシュを備えたコンピュータシステム
JP4237142B2 (ja) 統合ディレクトリとプロセッサキャッシュを備えたコンピュータシステム
US9792210B2 (en) Region probe filter for distributed memory system
US10402327B2 (en) Network-aware cache coherence protocol enhancement
US8397030B2 (en) Efficient region coherence protocol for clustered shared-memory multiprocessor systems
KR102939786B1 (ko) 스케일러블 영역 기반 디렉토리
US20130073811A1 (en) Region privatization in directory-based cache coherence
WO2009018005A2 (en) Providing an inclusive shared cache among multiple core-cache clusters
US20080086601A1 (en) Hierarchical cache coherence directory structure
EP1611513B1 (en) Multi-node system in which global address generated by processing subsystem includes global to local translation information
US8285942B2 (en) Region coherence array having hint bits for a clustered shared-memory multiprocessor system
Bhat et al. Directory Based Protocol for Cache Coherency–Issues & Challenges

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 4