JP2019512794A5 - - Google Patents
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- JP2019512794A5 JP2019512794A5 JP2018548194A JP2018548194A JP2019512794A5 JP 2019512794 A5 JP2019512794 A5 JP 2019512794A5 JP 2018548194 A JP2018548194 A JP 2018548194A JP 2018548194 A JP2018548194 A JP 2018548194A JP 2019512794 A5 JP2019512794 A5 JP 2019512794A5
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/074,444 US9823854B2 (en) | 2016-03-18 | 2016-03-18 | Priority-based access of compressed memory lines in memory in a processor-based system |
| US15/074,444 | 2016-03-18 | ||
| PCT/US2017/018876 WO2017160480A1 (en) | 2016-03-18 | 2017-02-22 | Priority-based access of compressed memory lines in memory in a processor-based system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019512794A JP2019512794A (ja) | 2019-05-16 |
| JP2019512794A5 true JP2019512794A5 (enExample) | 2020-03-19 |
| JP6945544B2 JP6945544B2 (ja) | 2021-10-06 |
Family
ID=58213373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018548194A Active JP6945544B2 (ja) | 2016-03-18 | 2017-02-22 | プロセッサベースシステムにおけるメモリ内の圧縮メモリラインの優先度ベースのアクセス |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US9823854B2 (enExample) |
| EP (1) | EP3430519B1 (enExample) |
| JP (1) | JP6945544B2 (enExample) |
| KR (1) | KR102780546B1 (enExample) |
| CN (1) | CN108780420B (enExample) |
| CA (1) | CA3014444A1 (enExample) |
| ES (1) | ES2871123T3 (enExample) |
| TW (1) | TWI644216B (enExample) |
| WO (1) | WO2017160480A1 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9378560B2 (en) * | 2011-06-17 | 2016-06-28 | Advanced Micro Devices, Inc. | Real time on-chip texture decompression using shader processors |
| US10437747B2 (en) * | 2015-04-10 | 2019-10-08 | Rambus Inc. | Memory appliance couplings and operations |
| CN112083875B (zh) * | 2019-06-12 | 2022-09-30 | 三星电子株式会社 | 用于在存储系统中减少读取端口并加速解压缩的方法 |
| US11048413B2 (en) * | 2019-06-12 | 2021-06-29 | Samsung Electronics Co., Ltd. | Method for reducing read ports and accelerating decompression in memory systems |
| JP7310462B2 (ja) * | 2019-09-04 | 2023-07-19 | 富士通株式会社 | ストレージ制御装置，分散ストレージシステムおよびストレージ制御プログラム |
| US11868244B2 (en) * | 2022-01-10 | 2024-01-09 | Qualcomm Incorporated | Priority-based cache-line fitting in compressed memory systems of processor-based systems |
| US11829292B1 (en) | 2022-01-10 | 2023-11-28 | Qualcomm Incorporated | Priority-based cache-line fitting in compressed memory systems of processor-based systems |
| KR102731761B1 (ko) * | 2022-01-10 | 2024-11-20 | 퀄컴 인코포레이티드 | 프로세서 기반 시스템의 압축 메모리 시스템에서 우선순위 기반 캐시 라인 피팅 |
| US12287740B2 (en) * | 2023-06-07 | 2025-04-29 | Dell Products L.P | Data caching strategies for storage with ownership of logical address slices |
| CN120540577A (zh) * | 2024-02-26 | 2025-08-26 | 杭州阿里云飞天信息技术有限公司 | 数据处理方法、装置、设备、存储介质及程序产品 |
| GB2639633A (en) * | 2024-03-20 | 2025-10-01 | Advanced Risc Mach Ltd | Interleaved memory transaction tracking for transactions with unrelated lengths |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002411A (en) * | 1994-11-16 | 1999-12-14 | Interactive Silicon, Inc. | Integrated video and memory controller with data processing and graphical processing capabilities |
| US5752266A (en) * | 1995-03-13 | 1998-05-12 | Fujitsu Limited | Method controlling memory access operations by changing respective priorities thereof, based on a situation of the memory, and a system and an integrated circuit implementing the method |
| US20010054131A1 (en) | 1999-01-29 | 2001-12-20 | Alvarez Manuel J. | System and method for perfoming scalable embedded parallel data compression |
| US6697076B1 (en) * | 2001-12-31 | 2004-02-24 | Apple Computer, Inc. | Method and apparatus for address re-mapping |
| US20030225992A1 (en) * | 2002-05-29 | 2003-12-04 | Balakrishna Venkatrao | Method and system for compression of address tags in memory structures |
| US6775751B2 (en) * | 2002-08-06 | 2004-08-10 | International Business Machines Corporation | System and method for using a compressed main memory based on degree of compressibility |
| US6910106B2 (en) * | 2002-10-04 | 2005-06-21 | Microsoft Corporation | Methods and mechanisms for proactive memory management |
| KR100562906B1 (ko) * | 2003-10-08 | 2006-03-21 | 삼성전자주식회사 | 시리얼 플래시 메모리에서의 ｘｉｐ를 위한 우선순위기반의 플래시 메모리 제어 장치 및 이를 이용한 메모리관리 방법, 이에 따른 플래시 메모리 칩 |
| US7636810B2 (en) | 2003-11-26 | 2009-12-22 | Intel Corporation | Method, system, and apparatus for memory compression with flexible in-memory cache |
| US20060184718A1 (en) * | 2005-02-16 | 2006-08-17 | Sinclair Alan W | Direct file data programming and deletion in flash memories |
| US20060184719A1 (en) * | 2005-02-16 | 2006-08-17 | Sinclair Alan W | Direct data file storage implementation techniques in flash memories |
| US7877539B2 (en) * | 2005-02-16 | 2011-01-25 | Sandisk Corporation | Direct data file storage in flash memories |
| US7680992B1 (en) | 2006-06-14 | 2010-03-16 | Nvidia Corporation | Read-modify-write memory with low latency for critical requests |
| US8122216B2 (en) | 2006-09-06 | 2012-02-21 | International Business Machines Corporation | Systems and methods for masking latency of memory reorganization work in a compressed memory system |
| KR20140059102A (ko) * | 2009-06-10 | 2014-05-15 | 마이크론 테크놀로지, 인크. | 메모리 어레이들에서 감소된 읽기 지연시간에 대한 메모리 작업들의 서스펜션 |
| US8356137B2 (en) * | 2010-02-26 | 2013-01-15 | Apple Inc. | Data storage scheme for non-volatile memories based on data priority |
| US8719664B1 (en) * | 2011-04-12 | 2014-05-06 | Sk Hynix Memory Solutions Inc. | Memory protection cache |
| US8527467B2 (en) | 2011-06-30 | 2013-09-03 | International Business Machines Corporation | Compression-aware data storage tiering |
| US20130179642A1 (en) * | 2012-01-10 | 2013-07-11 | Qualcomm Incorporated | Non-Allocating Memory Access with Physical Address |
| US9772948B2 (en) * | 2012-07-06 | 2017-09-26 | Seagate Technology Llc | Determining a criterion for movement of data from a primary cache to a secondary cache |
| US20140258247A1 (en) | 2013-03-05 | 2014-09-11 | Htc Corporation | Electronic apparatus for data access and data access method therefor |
| US9626126B2 (en) * | 2013-04-24 | 2017-04-18 | Microsoft Technology Licensing, Llc | Power saving mode hybrid drive access management |
-
2016
- 2016-03-18 US US15/074,444 patent/US9823854B2/en active Active
-
2017
- 2017-02-17 TW TW106105193A patent/TWI644216B/zh active
- 2017-02-22 ES ES17708655T patent/ES2871123T3/es active Active
- 2017-02-22 CN CN201780015368.7A patent/CN108780420B/zh active Active
- 2017-02-22 CA CA3014444A patent/CA3014444A1/en not_active Abandoned
- 2017-02-22 KR KR1020187026788A patent/KR102780546B1/ko active Active
- 2017-02-22 EP EP17708655.0A patent/EP3430519B1/en active Active
- 2017-02-22 JP JP2018548194A patent/JP6945544B2/ja active Active
- 2017-02-22 WO PCT/US2017/018876 patent/WO2017160480A1/en not_active Ceased
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