ES2871123T3 - Acceso basado en prioridades de líneas de memoria comprimidas en la memoria en un sistema basado en procesador - Google Patents

Acceso basado en prioridades de líneas de memoria comprimidas en la memoria en un sistema basado en procesador Download PDF

Info

Publication number
ES2871123T3
ES2871123T3 ES17708655T ES17708655T ES2871123T3 ES 2871123 T3 ES2871123 T3 ES 2871123T3 ES 17708655 T ES17708655 T ES 17708655T ES 17708655 T ES17708655 T ES 17708655T ES 2871123 T3 ES2871123 T3 ES 2871123T3
Authority
ES
Spain
Prior art keywords
memory
access request
priority
compressed
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES17708655T
Other languages
English (en)
Spanish (es)
Inventor
Valenzuela Andres Oportus
Amin Ansari
Richard Senior
Nieyan Geng
Anand Janakiraman
Gurvinder Chhabra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ES2871123T3 publication Critical patent/ES2871123T3/es
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0626—Reducing size or complexity of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1056—Simplification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Detection And Correction Of Errors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
ES17708655T 2016-03-18 2017-02-22 Acceso basado en prioridades de líneas de memoria comprimidas en la memoria en un sistema basado en procesador Active ES2871123T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/074,444 US9823854B2 (en) 2016-03-18 2016-03-18 Priority-based access of compressed memory lines in memory in a processor-based system
PCT/US2017/018876 WO2017160480A1 (en) 2016-03-18 2017-02-22 Priority-based access of compressed memory lines in memory in a processor-based system

Publications (1)

Publication Number Publication Date
ES2871123T3 true ES2871123T3 (es) 2021-10-28

Family

ID=58213373

Family Applications (1)

Application Number Title Priority Date Filing Date
ES17708655T Active ES2871123T3 (es) 2016-03-18 2017-02-22 Acceso basado en prioridades de líneas de memoria comprimidas en la memoria en un sistema basado en procesador

Country Status (9)

Country Link
US (1) US9823854B2 (enExample)
EP (1) EP3430519B1 (enExample)
JP (1) JP6945544B2 (enExample)
KR (1) KR102780546B1 (enExample)
CN (1) CN108780420B (enExample)
CA (1) CA3014444A1 (enExample)
ES (1) ES2871123T3 (enExample)
TW (1) TWI644216B (enExample)
WO (1) WO2017160480A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9378560B2 (en) * 2011-06-17 2016-06-28 Advanced Micro Devices, Inc. Real time on-chip texture decompression using shader processors
US10437747B2 (en) * 2015-04-10 2019-10-08 Rambus Inc. Memory appliance couplings and operations
CN112083875B (zh) * 2019-06-12 2022-09-30 三星电子株式会社 用于在存储系统中减少读取端口并加速解压缩的方法
US11048413B2 (en) * 2019-06-12 2021-06-29 Samsung Electronics Co., Ltd. Method for reducing read ports and accelerating decompression in memory systems
JP7310462B2 (ja) * 2019-09-04 2023-07-19 富士通株式会社 ストレージ制御装置，分散ストレージシステムおよびストレージ制御プログラム
US11868244B2 (en) * 2022-01-10 2024-01-09 Qualcomm Incorporated Priority-based cache-line fitting in compressed memory systems of processor-based systems
US11829292B1 (en) 2022-01-10 2023-11-28 Qualcomm Incorporated Priority-based cache-line fitting in compressed memory systems of processor-based systems
KR102731761B1 (ko) * 2022-01-10 2024-11-20 퀄컴 인코포레이티드 프로세서 기반 시스템의 압축 메모리 시스템에서 우선순위 기반 캐시 라인 피팅
US12287740B2 (en) * 2023-06-07 2025-04-29 Dell Products L.P Data caching strategies for storage with ownership of logical address slices
CN120540577A (zh) * 2024-02-26 2025-08-26 杭州阿里云飞天信息技术有限公司 数据处理方法、装置、设备、存储介质及程序产品
GB2639633A (en) * 2024-03-20 2025-10-01 Advanced Risc Mach Ltd Interleaved memory transaction tracking for transactions with unrelated lengths

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002411A (en) * 1994-11-16 1999-12-14 Interactive Silicon, Inc. Integrated video and memory controller with data processing and graphical processing capabilities
US5752266A (en) * 1995-03-13 1998-05-12 Fujitsu Limited Method controlling memory access operations by changing respective priorities thereof, based on a situation of the memory, and a system and an integrated circuit implementing the method
US20010054131A1 (en) 1999-01-29 2001-12-20 Alvarez Manuel J. System and method for perfoming scalable embedded parallel data compression
US6697076B1 (en) * 2001-12-31 2004-02-24 Apple Computer, Inc. Method and apparatus for address re-mapping
US20030225992A1 (en) * 2002-05-29 2003-12-04 Balakrishna Venkatrao Method and system for compression of address tags in memory structures
US6775751B2 (en) * 2002-08-06 2004-08-10 International Business Machines Corporation System and method for using a compressed main memory based on degree of compressibility
US6910106B2 (en) * 2002-10-04 2005-06-21 Microsoft Corporation Methods and mechanisms for proactive memory management
KR100562906B1 (ko) * 2003-10-08 2006-03-21 삼성전자주식회사 시리얼 플래시 메모리에서의 ｘｉｐ를 위한 우선순위기반의 플래시 메모리 제어 장치 및 이를 이용한 메모리관리 방법, 이에 따른 플래시 메모리 칩
US7636810B2 (en) 2003-11-26 2009-12-22 Intel Corporation Method, system, and apparatus for memory compression with flexible in-memory cache
US20060184718A1 (en) * 2005-02-16 2006-08-17 Sinclair Alan W Direct file data programming and deletion in flash memories
US20060184719A1 (en) * 2005-02-16 2006-08-17 Sinclair Alan W Direct data file storage implementation techniques in flash memories
US7877539B2 (en) * 2005-02-16 2011-01-25 Sandisk Corporation Direct data file storage in flash memories
US7680992B1 (en) 2006-06-14 2010-03-16 Nvidia Corporation Read-modify-write memory with low latency for critical requests
US8122216B2 (en) 2006-09-06 2012-02-21 International Business Machines Corporation Systems and methods for masking latency of memory reorganization work in a compressed memory system
KR20140059102A (ko) * 2009-06-10 2014-05-15 마이크론 테크놀로지, 인크. 메모리 어레이들에서 감소된 읽기 지연시간에 대한 메모리 작업들의 서스펜션
US8356137B2 (en) * 2010-02-26 2013-01-15 Apple Inc. Data storage scheme for non-volatile memories based on data priority
US8719664B1 (en) * 2011-04-12 2014-05-06 Sk Hynix Memory Solutions Inc. Memory protection cache
US8527467B2 (en) 2011-06-30 2013-09-03 International Business Machines Corporation Compression-aware data storage tiering
US20130179642A1 (en) * 2012-01-10 2013-07-11 Qualcomm Incorporated Non-Allocating Memory Access with Physical Address
US9772948B2 (en) * 2012-07-06 2017-09-26 Seagate Technology Llc Determining a criterion for movement of data from a primary cache to a secondary cache
US20140258247A1 (en) 2013-03-05 2014-09-11 Htc Corporation Electronic apparatus for data access and data access method therefor
US9626126B2 (en) * 2013-04-24 2017-04-18 Microsoft Technology Licensing, Llc Power saving mode hybrid drive access management

Also Published As

Publication number Publication date
TWI644216B (zh) 2018-12-11
EP3430519A1 (en) 2019-01-23
WO2017160480A1 (en) 2017-09-21
CN108780420B (zh) 2022-05-03
TW201734820A (zh) 2017-10-01
US20170269851A1 (en) 2017-09-21
US9823854B2 (en) 2017-11-21
EP3430519B1 (en) 2021-05-05
BR112018068611A2 (pt) 2019-02-05
KR102780546B1 (ko) 2025-03-11
KR20180122357A (ko) 2018-11-12
JP6945544B2 (ja) 2021-10-06
CN108780420A (zh) 2018-11-09
JP2019512794A (ja) 2019-05-16
CA3014444A1 (en) 2017-09-21

Similar Documents

Publication Publication Date Title
ES2871123T3 (es) Acceso basado en prioridades de líneas de memoria comprimidas en la memoria en un sistema basado en procesador
US10169246B2 (en) Reducing metadata size in compressed memory systems of processor-based systems
US10236917B2 (en) Providing memory bandwidth compression in chipkill-correct memory architectures
US20180173623A1 (en) Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compressed memory system to avoid stalling write operations
US10198362B2 (en) Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems
CN107667355B (zh) 一种用于提供分区的转换高速缓存器的方法及其设备
TW201737095A (zh) 在以一中央處理單元（ｃｐｕ）為基礎之系統中使用多個最後階層快取線提供記憶體帶寬壓縮
US20160224241A1 (en) PROVIDING MEMORY BANDWIDTH COMPRESSION USING BACK-TO-BACK READ OPERATIONS BY COMPRESSED MEMORY CONTROLLERS (CMCs) IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM
US20150347016A1 (en) Input/output virtualization (iov) host controller (hc) (iov-hc) of a flash-memory-based storage device
TW201814518A (zh) 使用在以一中央處理器單元為基礎的系統中之適應性壓縮提供記憶體頻寬壓縮
US10061698B2 (en) Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
US10754795B2 (en) MMU assisted address sanitizer
US9891945B2 (en) Storage resource management in virtualized environments
JP2016509324A (ja) キャッシュメモリアクセスを高速化するためのキャッシュメモリフィルの重要ワード優先順序付け、ならびに関連するプロセッサベースのシステムおよび方法
BR112018068611B1 (pt) Acesso com base em prioridade de linhas de memória comprimidas em memória em um sistema com base em processador
CN112579489B (zh) 数据操作方法、装置、设备、存储介质及程序产品
US20170285939A1 (en) Generating compressed data streams with lookback pre-fetch instructions for pre-fetching decompressed data from a lookback buffer
TW201842448A (zh) 以處理器為基礎之裝置中之聚集快取維護指令
CN119396834A (zh) 存储索引方法、存储索引装置、电子设备及存储介质
BR112018069720B1 (pt) Provisão de compactação de largura de banda de memória utilizando múltiplas linhas de cache de último nível (llc) em um sistema baseado em unidade central de processamento (cpu)