BR112018068611A2 - acesso com base em prioridade de linhas de memória comprimidas em memória em um sistema com base em processador - Google Patents
acesso com base em prioridade de linhas de memória comprimidas em memória em um sistema com base em processadorInfo
- Publication number
- BR112018068611A2 BR112018068611A2 BR112018068611A BR112018068611A BR112018068611A2 BR 112018068611 A2 BR112018068611 A2 BR 112018068611A2 BR 112018068611 A BR112018068611 A BR 112018068611A BR 112018068611 A BR112018068611 A BR 112018068611A BR 112018068611 A2 BR112018068611 A2 BR 112018068611A2
- Authority
- BR
- Brazil
- Prior art keywords
- memory
- priority
- access
- compressed
- processor
- Prior art date
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0626—Reducing size or complexity of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0661—Format or protocol conversion arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
- G06F2212/1044—Space efficiency improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1056—Simplification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/15—Use in a specific computing environment
- G06F2212/152—Virtualized environment, e.g. logically partitioned system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/40—Specific encoding of data in memory or cache
- G06F2212/401—Compressed data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
os aspectos descritos referem-se a um acesso com base em prioridade de linhas de memória comprimidas em um sistema com base em processador. em um aspecto, um dispositivo de acesso de memória no sistema com base em processador recebe uma solicitação de acesso de leitura para memória. se a solicitação de acesso de leitura for de prioridade mais alta, o dispositivo de acesso de memória usa o endereço de memória lógica da solicitação de acesso de leitura como o endereço de memória física para acessar a linha de memória comprimida. entretanto, se a solicitação de acesso de leitura for de prioridade menos alta, o dispositivo de acesso de memória translada o endereço de memória lógica da solicitação de acesso de leitura para um ou mais endereços de memória física no espaço de memória deixado pela compressão de linhas de prioridade mais alta. desta maneira, a eficácia dos acessos à memória comprimida de prioridade mais alta é aperfeiçoada através da remoção de um nível de indireção que é de outra forma solicitado para encontrar e acessar linhas de memória comprimidas.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/074,444 US9823854B2 (en) | 2016-03-18 | 2016-03-18 | Priority-based access of compressed memory lines in memory in a processor-based system |
PCT/US2017/018876 WO2017160480A1 (en) | 2016-03-18 | 2017-02-22 | Priority-based access of compressed memory lines in memory in a processor-based system |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112018068611A2 true BR112018068611A2 (pt) | 2019-02-05 |
Family
ID=58213373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112018068611A BR112018068611A2 (pt) | 2016-03-18 | 2017-02-22 | acesso com base em prioridade de linhas de memória comprimidas em memória em um sistema com base em processador |
Country Status (10)
Country | Link |
---|---|
US (1) | US9823854B2 (pt) |
EP (1) | EP3430519B1 (pt) |
JP (1) | JP6945544B2 (pt) |
KR (1) | KR20180122357A (pt) |
CN (1) | CN108780420B (pt) |
BR (1) | BR112018068611A2 (pt) |
CA (1) | CA3014444A1 (pt) |
ES (1) | ES2871123T3 (pt) |
TW (1) | TWI644216B (pt) |
WO (1) | WO2017160480A1 (pt) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9378560B2 (en) * | 2011-06-17 | 2016-06-28 | Advanced Micro Devices, Inc. | Real time on-chip texture decompression using shader processors |
US10437747B2 (en) * | 2015-04-10 | 2019-10-08 | Rambus Inc. | Memory appliance couplings and operations |
US11048413B2 (en) * | 2019-06-12 | 2021-06-29 | Samsung Electronics Co., Ltd. | Method for reducing read ports and accelerating decompression in memory systems |
CN112083875B (zh) * | 2019-06-12 | 2022-09-30 | 三星电子株式会社 | 用于在存储系统中减少读取端口并加速解压缩的方法 |
JP7310462B2 (ja) * | 2019-09-04 | 2023-07-19 | 富士通株式会社 | ストレージ制御装置,分散ストレージシステムおよびストレージ制御プログラム |
US11868244B2 (en) * | 2022-01-10 | 2024-01-09 | Qualcomm Incorporated | Priority-based cache-line fitting in compressed memory systems of processor-based systems |
US11829292B1 (en) | 2022-01-10 | 2023-11-28 | Qualcomm Incorporated | Priority-based cache-line fitting in compressed memory systems of processor-based systems |
WO2023133019A1 (en) * | 2022-01-10 | 2023-07-13 | Qualcomm Incorporated | Priority-based cache-line fitting in compressed memory systems of processor-based systems |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6002411A (en) * | 1994-11-16 | 1999-12-14 | Interactive Silicon, Inc. | Integrated video and memory controller with data processing and graphical processing capabilities |
US5752266A (en) * | 1995-03-13 | 1998-05-12 | Fujitsu Limited | Method controlling memory access operations by changing respective priorities thereof, based on a situation of the memory, and a system and an integrated circuit implementing the method |
US20010054131A1 (en) | 1999-01-29 | 2001-12-20 | Alvarez Manuel J. | System and method for perfoming scalable embedded parallel data compression |
US6697076B1 (en) * | 2001-12-31 | 2004-02-24 | Apple Computer, Inc. | Method and apparatus for address re-mapping |
US20030225992A1 (en) * | 2002-05-29 | 2003-12-04 | Balakrishna Venkatrao | Method and system for compression of address tags in memory structures |
US6775751B2 (en) * | 2002-08-06 | 2004-08-10 | International Business Machines Corporation | System and method for using a compressed main memory based on degree of compressibility |
US6910106B2 (en) * | 2002-10-04 | 2005-06-21 | Microsoft Corporation | Methods and mechanisms for proactive memory management |
KR100562906B1 (ko) * | 2003-10-08 | 2006-03-21 | 삼성전자주식회사 | 시리얼 플래시 메모리에서의 xip를 위한 우선순위기반의 플래시 메모리 제어 장치 및 이를 이용한 메모리관리 방법, 이에 따른 플래시 메모리 칩 |
US7636810B2 (en) | 2003-11-26 | 2009-12-22 | Intel Corporation | Method, system, and apparatus for memory compression with flexible in-memory cache |
US20060184718A1 (en) * | 2005-02-16 | 2006-08-17 | Sinclair Alan W | Direct file data programming and deletion in flash memories |
US20060184719A1 (en) * | 2005-02-16 | 2006-08-17 | Sinclair Alan W | Direct data file storage implementation techniques in flash memories |
US7877539B2 (en) * | 2005-02-16 | 2011-01-25 | Sandisk Corporation | Direct data file storage in flash memories |
US7680992B1 (en) | 2006-06-14 | 2010-03-16 | Nvidia Corporation | Read-modify-write memory with low latency for critical requests |
US8122216B2 (en) | 2006-09-06 | 2012-02-21 | International Business Machines Corporation | Systems and methods for masking latency of memory reorganization work in a compressed memory system |
DE112009004900T5 (de) * | 2009-06-10 | 2012-08-16 | Micron Technology, Inc. | Vertagen von Speicheroperationen zum Reduzieren von Leselatenz in Speicherfeldern |
US8356137B2 (en) * | 2010-02-26 | 2013-01-15 | Apple Inc. | Data storage scheme for non-volatile memories based on data priority |
US8527467B2 (en) | 2011-06-30 | 2013-09-03 | International Business Machines Corporation | Compression-aware data storage tiering |
US20130179642A1 (en) * | 2012-01-10 | 2013-07-11 | Qualcomm Incorporated | Non-Allocating Memory Access with Physical Address |
US20140258247A1 (en) | 2013-03-05 | 2014-09-11 | Htc Corporation | Electronic apparatus for data access and data access method therefor |
US9626126B2 (en) * | 2013-04-24 | 2017-04-18 | Microsoft Technology Licensing, Llc | Power saving mode hybrid drive access management |
-
2016
- 2016-03-18 US US15/074,444 patent/US9823854B2/en active Active
-
2017
- 2017-02-17 TW TW106105193A patent/TWI644216B/zh active
- 2017-02-22 BR BR112018068611A patent/BR112018068611A2/pt unknown
- 2017-02-22 CN CN201780015368.7A patent/CN108780420B/zh active Active
- 2017-02-22 ES ES17708655T patent/ES2871123T3/es active Active
- 2017-02-22 WO PCT/US2017/018876 patent/WO2017160480A1/en active Application Filing
- 2017-02-22 KR KR1020187026788A patent/KR20180122357A/ko active Search and Examination
- 2017-02-22 CA CA3014444A patent/CA3014444A1/en not_active Abandoned
- 2017-02-22 JP JP2018548194A patent/JP6945544B2/ja active Active
- 2017-02-22 EP EP17708655.0A patent/EP3430519B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20170269851A1 (en) | 2017-09-21 |
KR20180122357A (ko) | 2018-11-12 |
TW201734820A (zh) | 2017-10-01 |
JP6945544B2 (ja) | 2021-10-06 |
US9823854B2 (en) | 2017-11-21 |
EP3430519B1 (en) | 2021-05-05 |
CA3014444A1 (en) | 2017-09-21 |
WO2017160480A1 (en) | 2017-09-21 |
CN108780420B (zh) | 2022-05-03 |
EP3430519A1 (en) | 2019-01-23 |
TWI644216B (zh) | 2018-12-11 |
CN108780420A (zh) | 2018-11-09 |
JP2019512794A (ja) | 2019-05-16 |
ES2871123T3 (es) | 2021-10-28 |
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Legal Events
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B350 | Update of information on the portal [chapter 15.35 patent gazette] | ||
B06W | Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette] |