CA3014444A1 - Priority-based access of compressed memory lines in memory in a processor-based system - Google Patents

Priority-based access of compressed memory lines in memory in a processor-based system Download PDF

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Publication number
CA3014444A1
CA3014444A1 CA3014444A CA3014444A CA3014444A1 CA 3014444 A1 CA3014444 A1 CA 3014444A1 CA 3014444 A CA3014444 A CA 3014444A CA 3014444 A CA3014444 A CA 3014444A CA 3014444 A1 CA3014444 A1 CA 3014444A1
Authority
CA
Canada
Prior art keywords
memory
access request
compressed
lower priority
read access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA3014444A
Other languages
English (en)
French (fr)
Inventor
Andres Alejandro OPORTUS VALENZUELA
Amin Ansari
Richard Senior
Nieyan Geng
Anand Janakiraman
Gurvinder Singh Chhabra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CA3014444A1 publication Critical patent/CA3014444A1/en
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0626—Reducing size or complexity of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1056—Simplification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Detection And Correction Of Errors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
CA3014444A 2016-03-18 2017-02-22 Priority-based access of compressed memory lines in memory in a processor-based system Abandoned CA3014444A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/074,444 US9823854B2 (en) 2016-03-18 2016-03-18 Priority-based access of compressed memory lines in memory in a processor-based system
US15/074,444 2016-03-18
PCT/US2017/018876 WO2017160480A1 (en) 2016-03-18 2017-02-22 Priority-based access of compressed memory lines in memory in a processor-based system

Publications (1)

Publication Number Publication Date
CA3014444A1 true CA3014444A1 (en) 2017-09-21

Family

ID=58213373

Family Applications (1)

Application Number Title Priority Date Filing Date
CA3014444A Abandoned CA3014444A1 (en) 2016-03-18 2017-02-22 Priority-based access of compressed memory lines in memory in a processor-based system

Country Status (9)

Country Link
US (1) US9823854B2 (enExample)
EP (1) EP3430519B1 (enExample)
JP (1) JP6945544B2 (enExample)
KR (1) KR102780546B1 (enExample)
CN (1) CN108780420B (enExample)
CA (1) CA3014444A1 (enExample)
ES (1) ES2871123T3 (enExample)
TW (1) TWI644216B (enExample)
WO (1) WO2017160480A1 (enExample)

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US9378560B2 (en) * 2011-06-17 2016-06-28 Advanced Micro Devices, Inc. Real time on-chip texture decompression using shader processors
US10437747B2 (en) * 2015-04-10 2019-10-08 Rambus Inc. Memory appliance couplings and operations
CN112083875B (zh) * 2019-06-12 2022-09-30 三星电子株式会社 用于在存储系统中减少读取端口并加速解压缩的方法
US11048413B2 (en) * 2019-06-12 2021-06-29 Samsung Electronics Co., Ltd. Method for reducing read ports and accelerating decompression in memory systems
JP7310462B2 (ja) * 2019-09-04 2023-07-19 富士通株式会社 ストレージ制御装置，分散ストレージシステムおよびストレージ制御プログラム
US11868244B2 (en) * 2022-01-10 2024-01-09 Qualcomm Incorporated Priority-based cache-line fitting in compressed memory systems of processor-based systems
US11829292B1 (en) 2022-01-10 2023-11-28 Qualcomm Incorporated Priority-based cache-line fitting in compressed memory systems of processor-based systems
KR102731761B1 (ko) * 2022-01-10 2024-11-20 퀄컴 인코포레이티드 프로세서 기반 시스템의 압축 메모리 시스템에서 우선순위 기반 캐시 라인 피팅
US12287740B2 (en) * 2023-06-07 2025-04-29 Dell Products L.P Data caching strategies for storage with ownership of logical address slices
CN120540577A (zh) * 2024-02-26 2025-08-26 杭州阿里云飞天信息技术有限公司 数据处理方法、装置、设备、存储介质及程序产品
GB2639633A (en) * 2024-03-20 2025-10-01 Advanced Risc Mach Ltd Interleaved memory transaction tracking for transactions with unrelated lengths

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US5752266A (en) * 1995-03-13 1998-05-12 Fujitsu Limited Method controlling memory access operations by changing respective priorities thereof, based on a situation of the memory, and a system and an integrated circuit implementing the method
US20010054131A1 (en) 1999-01-29 2001-12-20 Alvarez Manuel J. System and method for perfoming scalable embedded parallel data compression
US6697076B1 (en) * 2001-12-31 2004-02-24 Apple Computer, Inc. Method and apparatus for address re-mapping
US20030225992A1 (en) * 2002-05-29 2003-12-04 Balakrishna Venkatrao Method and system for compression of address tags in memory structures
US6775751B2 (en) * 2002-08-06 2004-08-10 International Business Machines Corporation System and method for using a compressed main memory based on degree of compressibility
US6910106B2 (en) * 2002-10-04 2005-06-21 Microsoft Corporation Methods and mechanisms for proactive memory management
KR100562906B1 (ko) * 2003-10-08 2006-03-21 삼성전자주식회사 시리얼 플래시 메모리에서의 ｘｉｐ를 위한 우선순위기반의 플래시 메모리 제어 장치 및 이를 이용한 메모리관리 방법, 이에 따른 플래시 메모리 칩
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Also Published As

Publication number Publication date
TWI644216B (zh) 2018-12-11
EP3430519A1 (en) 2019-01-23
WO2017160480A1 (en) 2017-09-21
CN108780420B (zh) 2022-05-03
TW201734820A (zh) 2017-10-01
US20170269851A1 (en) 2017-09-21
US9823854B2 (en) 2017-11-21
EP3430519B1 (en) 2021-05-05
BR112018068611A2 (pt) 2019-02-05
KR102780546B1 (ko) 2025-03-11
KR20180122357A (ko) 2018-11-12
ES2871123T3 (es) 2021-10-28
JP6945544B2 (ja) 2021-10-06
CN108780420A (zh) 2018-11-09
JP2019512794A (ja) 2019-05-16

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Legal Events

Date Code Title Description
FZDE Discontinued

Effective date: 20210831

FZDE Discontinued

Effective date: 20210831