JP2019507445A5 - - Google Patents

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JP2019507445A5
JP2019507445A5 JP2018550654A JP2018550654A JP2019507445A5 JP 2019507445 A5 JP2019507445 A5 JP 2019507445A5 JP 2018550654 A JP2018550654 A JP 2018550654A JP 2018550654 A JP2018550654 A JP 2018550654A JP 2019507445 A5 JP2019507445 A5 JP 2019507445A5
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  1. メモリ領域のタグ値を記憶する方法であって、
    前記メモリ領域の中の複数のメモリ位置の1つまたは複数のタグ値を受信するステップと、
    前記メモリ領域の前記複数のメモリ位置の前記1つまたは複数のタグ値の階層的な表現を作成するステップであって、前記階層的な表現が1つまたは複数のメモリ位置と各々関連付けられる1つまたは複数のノードを含む、ステップとを備え、前記階層的な表現の各ノードが、前記各ノードと関連付けられる1つまたは複数のメモリ位置の副範囲のタグ値を示すか、またはそうでなければ、前記階層的な表現の特定のレベルにある前記各ノードが前記各ノードと関連付けられる1つまたは複数のメモリ位置の前記副範囲のタグ値を指定せず、それにより、前記特定のレベルより低い1つまたは複数のレベルにある1つまたは複数の他のノードが前記各ノードと関連付けられる1つまたは複数のメモリ位置の前記副範囲の1つまたは複数のタグ値を指定することを示すかの、いずれかである、方法。
  2. 前記メモリ領域の第1のメモリ位置の現在のタグ値として記憶されることになる第1のタグ値を受信するステップと、
    前記第1のタグ値が前記第1のメモリ位置の前記現在のタグ値であることを示すように前記階層的な表現を更新するステップとをさらに備える、請求項1に記載の方法。
  3. 前記更新するステップを実行する前に、既存のタグ値が前記第1のメモリ位置の前記現在のタグ値として記憶され、前記既存のタグ値から前記第1のタグ値へと前記現在のタグ値を更新するように処理を実行するステップを含み、前記処理が、
    前記第1のメモリ位置を含むメモリ位置の第1の副範囲と関連付けられる前記階層的な表現の第1のノードを判定することであって、前記第1のノードがメモリ位置の前記第1の副範囲の一様なタグ値として前記既存のタグ値を示し、それにより、前記第1の副範囲の中の各メモリ位置が前記既存のタグ値を有する、判定することと、
    前記第1のノードの第1の子ノードを作成することであって、前記第1の子ノードが前記第1の副範囲の前記第1のメモリ位置の前記現在のタグ値として前記第1のタグ値を示す、作成することと、
    前記第1のノードの1つまたは複数の他の子ノードを作成することであって、前記1つまたは複数の他の子ノードが、前記第1のメモリ位置以外の前記第1の副範囲のメモリ位置の前記既存のタグ値を示す、作成することと、
    前記第1のノードが前記第1のノードと関連付けられる1つまたは複数のメモリ位置の前記副範囲のタグ値を指定せず、それにより、前記第1のノードのレベルより低い前記階層的な表現の1つまたは複数のレベルにある前記第1のノードの1つまたは複数の他の子孫ノードが前記第1の副範囲の1つまたは複数のタグ値を指定することを示すように、前記第1のノードを更新することとを備える、請求項2に記載の方法。
  4. 前記メモリ領域の第1のメモリ位置の現在のタグ値を判定するために第1の処理を実行するステップをさらに備え、前記第1の処理が、
    前記階層的な表現を横断することと、前記メモリ領域の1つまたは複数のメモリ位置の第1の副範囲と関連付けられる前記階層的な表現の第1のノードを位置特定することとを含み、前記第1の副範囲が前記第1のメモリ位置を含み、前記第1のノードが1つまたは複数のメモリ位置の前記第1の副範囲の既存のタグ値を示し、それにより、前記第1の副範囲の中の各メモリ位置が前記既存のタグ値を有し、前記既存のタグ値が前記第1のメモリ位置の前記現在のタグ値である、請求項1に記載の方法。
  5. 前記横断することが、前記階層的な表現のルートノードから始まり、前記階層的な表現のリーフノードに向かって前記階層的な表現のより低いレベルへと下方に進む、請求項4に記載の方法。
  6. 前記階層的な表現が、複数のキャッシングレベルに記憶されている前記複数のレベルのノードを有する複数のレベルを含み、前記複数のレベルの各々からのノードが、前記複数のキャッシングレベルの異なる対応するキャッシングレベルに記憶される、請求項4に記載の方法。
  7. 前記第1の処理が、前記キャッシングレベルの各々が前記第1のメモリ位置の前記現在のタグ値を定義するノードを含むかどうかを判定するために、前記複数のキャッシングレベルの各々の中の前記第1のメモリ位置をルックアップすることを含む、請求項6に記載の方法。
  8. 前記ルックアップすることが、前記複数のキャッシングレベルのうちのいずれが前記第1のメモリ位置の前記現在のタグ値を定義するかを判定するために前記複数のキャッシングレベルの並列なルックアップを実行する、請求項7に記載の方法。
  9. 前記複数のキャッシングレベルのうちの第1のキャッシングレベルが、前記第1のメモリ位置の前記現在のタグ値を指定し、前記第1のノードが前記第1のキャッシングレベルに含まれる、請求項8に記載の方法。
  10. 前記第1のキャッシングレベルが、前記第1のメモリ位置のタグ値を定義する前記階層の前記複数のレベルのうちの最高のレベルである、請求項9に記載の方法。
  11. 前記階層的な表現がツリーである、請求項1に記載の方法。
  12. 前記ツリーが、前記メモリ領域の前記複数のメモリ位置の現在のタグ値を指定する1つまたは複数のリーフノードを含む、請求項11に記載の方法。
  13. 前記ツリーが二分木である、請求項11に記載の方法。
  14. 前記ツリーの各ノードが、最大の許容可能な数の子ノードまで、より多くの子ノードの0を有する、請求項11に記載の方法。
  15. 前記階層的な表現が、複数のキャッシングレベルに記憶されている前記複数のレベルのノードを有する複数のレベルを含み、前記複数のレベルの各々からのノードが、前記複数のキャッシングレベルの異なる対応するキャッシングレベルに記憶され、
    前記メモリ領域の第1のメモリ位置に対してデータキャッシュヒットがあるかデータキャッシュミスがあるかを判定するステップと、
    前記第1のメモリ位置に対してデータキャッシュミスを判定したことに応答して、前記複数のキャッシングレベルの中の前記第1のメモリ位置のキャッシュされたタグ値をルックアップすることを含む第1の処理を実行するステップと、
    前記第1のメモリ位置に対するデータキャッシュヒットを判定したことに応答して、第2の処理を実行するステップとをさらに備え、前記第2の処理が、
    前記第1のメモリ位置のための前記データキャッシュに記憶されているような第1のキャッシュされたタグ値が前記第1のメモリ位置のための前記階層的な表現に記憶されているような現在のタグ値と一致するかどうかを判定することと、
    前記第1のキャッシュされたタグ値と前記現在のタグ値が一致しないと判定される場合、それに従って、前記データキャッシュに記憶されているような前記第1のキャッシュされたタグ値を更新することと
    を含む、請求項1に記載の方法。
  16. 前記データキャッシュに記憶されているような前記第1のキャッシュされたタグ値を更新することが、
    前記データキャッシュの前記第1のキャッシュされたタグ値を、前記階層的な表現に記憶されているような前記第1のメモリ位置の前記現在のタグ値で置換することと、
    前記複数のキャッシングレベルのうちのいずれが前記第1のメモリ位置の前記現在のタグ値を含むかを示す、前記データキャッシュに保持されている追加の情報を更新することとを含む、請求項15に記載の方法。
  17. 前記第1の処理が、前記複数のキャッシングレベルを並列に探索することによって、前記複数のキャッシングレベルの中の前記第1のメモリ位置の前記キャッシュされたタグ値をルックアップする、請求項15に記載の方法。
  18. 前記第1のメモリ位置の前記キャッシュされたタグ値をルックアップするときのタグキャッシュミスに応答して、前記タグキャッシュミスが前記複数のキャッシングレベルのうちの特定の1つにあり、前記複数のキャッシングレベルのうちの前記特定の1つが前記第1のメモリ位置のタグ値を含まず、実行される処理が、
    前記第1のメモリ位置のタグ値を指定するノードを位置特定するために前記階層的な表現を横断することと、
    前記横断することに従って前記複数のキャッシングレベルのうちの適切なものへと前記階層的な表現のノードのタグ値を挿入することとを含む、請求項17に記載の方法。
  19. 前記第1の処理が、前記キャッシングレベルの最高から前記キャッシングレベルの最低まで前記複数のキャッシングレベルを横断することによって、前記複数のキャッシングレベルの中の前記第1のメモリ位置の前記キャッシュされたタグ値をルックアップする、請求項15に記載の方法。
  20. 前記第1のメモリ位置の前記キャッシュされたタグ値をルックアップするときのタグキャッシュミスに応答して、前記タグキャッシュミスが前記複数のキャッシングレベルのうちの特定の1つにあり、前記複数のキャッシングレベルのうちの前記特定の1つが前記第1のメモリ位置のタグ値を含まず、実行される処理が、
    前記第1のメモリ位置のタグ値を指定するノードを位置特定するために前記階層的な表現を横断することと、
    前記横断することに従って前記複数のキャッシングレベルのうちの適切なものへと前記階層的な表現のノードの1つまたは複数のタグ値を挿入することとを含む、請求項19に記載の方法。
  21. 前記タグ値がメタデータ処理において使用されるメタデータタグである、請求項1に記載の方法。
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