JP2019220597A - Manufacturing condition determination method of epitaxial wafer and manufacturing method of the epitaxial wafer - Google Patents

Abstract

To provide a method of determining a condition capable of manufacturing an epitaxial wafer in which a slip dislocation does not occur and a manufacturing method of an epitaxial wafer.SOLUTION: At a first position on a susceptor provided in an epitaxial growth furnace, an evaluation silicon wafer is arranged so that a direction equivalent to <110> direction of a crystal in the evaluation silicon wafer is parallel to an introduction direction to the epitaxial growth furnace of a wafer, a heat stress that is larger than the heat stress to be loaded when manufacturing the epitaxial wafer is loaded, and it is evaluated whether a slip occurs in the evaluation silicon wafer. The same step is performed so as to shift a position of the wafer to the direction equivalent to <110> direction of the crystal in the evaluation silicon wafer, and a mounting position of the evaluation silicon wafer on the susceptor in which no slip occur when manufacturing the epitaxial wafer is specified. A wafer in which an impression is formed on a back surface is used for the evaluation.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method for determining manufacturing conditions for an epitaxial wafer and a method for manufacturing an epitaxial wafer.

  In recent years, in various semiconductor devices such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), various logics, power transistors and back-illuminated solid-state imaging devices, an epitaxial wafer having an epitaxial layer formed on a silicon wafer is used as a substrate. It is generally used.

  The epitaxial wafer is, for example, a silicon wafer placed in a single-wafer type epitaxial growth furnace, and a source gas such as dichlorosilane gas or trichlorosilane gas is supplied into the epitaxial growth furnace together with a carrier gas such as hydrogen gas at 1100 ° C. to 1150 ° C. It can be obtained by growing an epitaxial layer on a silicon wafer at a temperature (for example, see Patent Document 1).

JP 2003-073191 A

  In the above-described epitaxial wafer manufacturing process, the silicon wafer, which is a substrate of the epitaxial wafer, comes into contact with a dissimilar material such as a susceptor or a holder in the transport or epitaxial growth process. Therefore, formation of a flaw especially on the outer peripheral portion of the back surface of the silicon wafer cannot be avoided.

  If a scratch is formed on the outer peripheral portion of the back surface of the silicon wafer and a thermal stress is applied to the silicon wafer in the epitaxial wafer manufacturing process, slip dislocation may occur starting from the formed scratch. When slip dislocation occurs, the manufactured epitaxial wafer cannot be shipped as a product, and there is a problem that the product yield is reduced.

  Therefore, an object of the present invention is to propose a method for determining conditions under which an epitaxial wafer without slip dislocation can be manufactured and a method for manufacturing an epitaxial wafer.

  The gist configuration of the present invention for solving the above problems is as follows.

[1] A method for determining conditions for producing an epitaxial wafer by growing an epitaxial layer on a silicon wafer,
A silicon wafer for evaluation is introduced into an epitaxial growth furnace, and a direction equivalent to a <110> direction of a crystal in the silicon wafer for evaluation is placed at a first position on a susceptor provided in the epitaxial growth furnace. A first step of arranging the wafer so as to be parallel to the introduction direction of the wafer into the epitaxial growth furnace;
For the evaluation silicon wafer, a second step of applying a thermal stress equal to or greater than the thermal stress applied to the silicon wafer when manufacturing the epitaxial wafer,
A third step of evaluating whether a slip has occurred in the evaluation silicon wafer after the second step;
A fourth step in which the first to third steps are performed by disposing the evaluation silicon wafer at a position shifted from the first position in a direction equivalent to the <110> direction of the crystal in the evaluation silicon wafer. When,
Based on the result of the fourth step, the slip is not generated when manufacturing the epitaxial wafer, a fifth step of specifying the mounting position of the silicon wafer on the susceptor,
Including
As the evaluation silicon wafer, at least a polygonal indentation on an outer peripheral portion of the back surface, in which a bisector of at least one corner of the polygon is oriented in a direction equivalent to a <110> direction, A method for determining manufacturing conditions for an epitaxial wafer, comprising using a silicon wafer having one.

[2] The method for determining epitaxial wafer production conditions according to [1], wherein the second step is performed by forming an epitaxial layer on the silicon wafer for evaluation.

[3] The above-mentioned [1], wherein the second step is performed by performing a simulated heat treatment simulating a heat treatment applied to the silicon wafer in the process of manufacturing the epitaxial wafer on the evaluation silicon wafer. For determining epitaxial wafer manufacturing conditions.

[4] In the simulated heat treatment, the epitaxial silicon wafer according to [3], wherein a thermal stress exceeding a thermal stress applied to the silicon wafer when manufacturing the epitaxial wafer is applied to the evaluation silicon wafer. Method for determining wafer manufacturing conditions.

[5] The method according to any one of [1] to [4], wherein the fourth step is performed in two directions equivalent to the <110> direction.

[6] The silicon wafer for evaluation according to any one of [1] to [5], wherein a plane orientation (100) silicon wafer having four indentations at 90 ° intervals in a wafer circumferential direction is used. For determining epitaxial wafer manufacturing conditions.

[7] Placing a silicon wafer at a position specified by any one of the methods [1] to [6], in the epitaxial growth furnace, at a position where no slip occurs in the epitaxial wafer, A method for manufacturing an epitaxial wafer, comprising forming an epitaxial layer on a surface of the silicon wafer.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing conditions of the epitaxial wafer in which a slip dislocation does not generate can be determined.

It is a schematic diagram of the back surface of a silicon wafer for evaluation, (a) corresponds to the case where the direction of the notch faces the <100> direction, and (b) corresponds to the case where the direction of the notch faces the <110> direction. are doing. It is an optical microscope image of the impression formed in the silicon wafer for evaluation. FIG. 4 is a diagram illustrating mounting of an evaluation silicon wafer on a susceptor. 3 is an X-ray topography image of a slip dislocation generated in an epitaxial wafer. The relationship between the length of the slip dislocation generated in the silicon epitaxial wafer for evaluation and the mounting position of the silicon wafer for evaluation on the susceptor in the epitaxial growth furnace in the case of using the silicon wafer for evaluation with the <100> direction of the notch. It is a figure showing a relation. The relationship between the length of the slip dislocation generated in the evaluation silicon epitaxial wafer and the mounting position of the evaluation silicon wafer on the susceptor in the epitaxial growth furnace, when the evaluation silicon wafer having the notch orientation of <110> direction is used. It is a figure showing a relation. FIG. 6 is an enlarged view of the relationship shown in FIG. 5 where the shift amount is near zero, where (a) corresponds to FIG. 5 (a) and (b) corresponds to FIG. 5 (b). 7A is an X-ray topography image of an indentation, and FIG. 7A is a case where the shift amount is zero in FIG. 7A and FIG. 7B is a case where the shift amount is 0.15 mm in FIG. FIG. 4 is a diagram showing a relationship between a length of a slip dislocation generated in an epitaxial wafer and a mounting position of a silicon wafer on a susceptor in the epitaxial growth furnace, for three epitaxial growth furnaces.

(Method of determining epitaxial wafer manufacturing conditions)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. According to the method for determining manufacturing conditions of an epitaxial wafer according to the present invention, a silicon wafer for evaluation is introduced into an epitaxial growth furnace, and a crystal of the silicon wafer for evaluation is <110 in a first position on a susceptor provided in the epitaxial growth furnace. A first step of arranging the direction equivalent to the direction to be parallel to the direction of introduction of the evaluation silicon wafer into the epitaxial growth furnace; A second step of applying a thermal stress equal to or more than the thermal stress to be applied; a third step of evaluating whether or not a slip has occurred in the evaluation silicon wafer after the second step; and the first to third steps. The process is performed by moving the evaluation silicon wafer from the first position to <110> of the crystal in the evaluation silicon wafer. A fourth step performed by disposing the silicon wafer at a position shifted in a direction equivalent to the direction, and a mounting position of the silicon wafer on the susceptor based on the result of the fourth step, wherein no slip occurs when an epitaxial wafer is manufactured. And a fifth step of specifying Here, as the silicon wafer for evaluation, a polygonal indentation on the outer peripheral portion of the back surface, in which the bisector of at least one corner of the polygon is oriented in a direction equivalent to the <110> direction, is used. It is characterized by using a silicon wafer having at least one.

  As described above, in the epitaxial wafer manufacturing process, the silicon wafer as the substrate comes into contact with a dissimilar material, so that it is inevitable that a scratch is formed on the outer peripheral portion of the back surface of the wafer. However, thermal stress is required for slip dislocations to be generated and propagated from scratches on the outer peripheral portion of the rear surface of the wafer. When no thermal stress is applied, no slip dislocation is generated from the scratch and does not progress. Therefore, in order to reduce the occurrence of slip dislocation from the outer peripheral portion of the wafer, it is necessary to consider conditions that can reduce the thermal stress applied to the silicon wafer in the epitaxial wafer manufacturing process.

  The present inventors have considered that the thermal stress applied to the silicon wafer in the process of manufacturing the epitaxial wafer may depend on the mounting position of the silicon wafer on the susceptor in the epitaxial growth furnace.

  The present inventors have also considered that the thermal stress applied to the silicon wafer may depend on the orientation of the silicon wafer placed on the susceptor. That is, a notch indicating a specific direction of the crystal is often formed on the outer peripheral portion of the silicon wafer. For example, in the case of a silicon wafer having a plane orientation of (100), the orientations of the notches are substantially two types, the <100> direction and the <110> direction.

  Further, the silicon wafer is usually introduced into the epitaxial growth furnace with the notch facing the wafer unloading direction. Therefore, if the orientation of the notch of the wafer is different, the orientation of the crystal in the silicon wafer will be different when the silicon wafer is mounted on the susceptor.

  Therefore, two types of silicon wafers having a diameter of 300 mm, a plane orientation of (100), and a notch in a <100> direction and a <110> direction were used to form indentations imitating scratches on the back surface of the silicon wafer. A silicon wafer was prepared, and the mounting position of the evaluation silicon wafer on the susceptor in the epitaxial growth furnace was variously changed to produce a silicon epitaxial wafer. Then, the relationship between the length of the slip dislocation generated in the obtained silicon epitaxial wafer and the mounting position of the evaluation silicon wafer in the epitaxial growth furnace was examined. Hereinafter, this experiment will be described.

  First, in order to quantitatively evaluate the relationship between the length of the slip dislocation and the mounting position of the wafer on the susceptor, the two types of silicon wafers described above, using a Vickers hardness meter, the outer peripheral portion of the back surface of the silicon wafer Then, four substantially diamond-shaped indentations imitating scratches formed in the epitaxial wafer manufacturing process were formed.

  More specifically, as shown in FIG. 1, at a position 1 mm from the outer periphery of the back surface of the silicon wafer, a position shifted 45 ° clockwise in the wafer circumferential direction with respect to the notch position, Indentations were formed at a total of four positions shifted by 90 ° in the direction. At this time, the bisectors of the rhombic corners, that is, the diagonal lines of the rhombus of each indentation were all oriented in a direction equivalent to the <110> direction. The load at the time of forming the indentation was constant at 100 gf. 1A illustrates a case where the direction of the notch is the <100> direction, and FIG. 1B illustrates a case where the direction of the notch is the <110> direction. These silicon wafers were used as evaluation silicon wafers.

  FIG. 2 shows an example of an optical microscope image of the formed indentation. As shown in this figure, cracks occur from the vertices of the diamonds of each indentation, and the cracks extend in the <110> direction. When a large thermal stress is applied to the evaluation silicon wafer having such indentations, slip dislocations are generated and propagate from the tip of the crack.

  Using a silicon wafer for evaluation with these four indentations on the outer periphery of the back surface, the relationship between the length of the slip dislocation generated in the manufacturing process of the epitaxial wafer and the mounting position of the silicon wafer on the susceptor in the epitaxial growth furnace was investigated. Was.

  Specifically, first, in the wafer transfer robot, the silicon wafer for evaluation is set so that the notch is oriented in a direction shifted 45 ° clockwise in the circumferential direction of the wafer with respect to the wafer leading-out direction, as shown in FIG. Placed.

  As described above, when the silicon wafer is introduced into the epitaxial growth furnace, the notch is usually arranged on the wafer unloading direction side, but in this evaluation, the notch is arranged so as to be oriented in a direction shifted by 45 °. . In this case, when the direction of the notch shown in FIG. 1A is the <100> direction, the <110> direction of the crystal in the evaluation silicon wafer is introduced parallel to the wafer introduction direction. On the other hand, when the direction of the notch is the <110> direction shown in FIG. 1B, the <100> direction of the crystal in the evaluation silicon wafer is introduced parallel to the wafer introduction direction. Therefore, as described above, by arranging the notch in a direction shifted 45 ° clockwise in the circumferential direction of the wafer with respect to the wafer deriving direction, the introduction direction of the silicon wafer is similar to the general case described above. Are <110> direction and <100> direction in the evaluation silicon wafer.

  Next, the evaluation silicon wafer is introduced into the epitaxial growth furnace, and the first silicon wafer on the susceptor is positioned while visually confirming that the center of the evaluation silicon wafer is located above the center of the susceptor provided in the epitaxial growth furnace. Was placed in the position. Subsequently, a silicon epitaxial layer having a thickness of 2 μm was formed on the surface of the silicon wafer for evaluation by a known method, to produce a silicon epitaxial wafer for evaluation. At that time, the growth temperature of the epitaxial layer was 1120 ° C., the growth time was 1 minute, and the conditions before and after the epitaxial layer growth were all the same.

  The production of the silicon epitaxial wafer for evaluation was performed by shifting the position at which the silicon wafer for evaluation was placed on the susceptor with reference to the first position. Specifically, the shift was performed in two directions: a direction parallel to the wafer introduction direction (Y direction in FIG. 3) and a direction perpendicular to the wafer introduction direction (X direction in FIG. 3).

  Indentations were taken by X-ray topography for each of the evaluation silicon epitaxial wafers manufactured as described above, and it was confirmed whether or not slip dislocation had occurred. When a slip dislocation occurred, its length was evaluated.

  4 shows slip dislocations generated from indentations in an epitaxial wafer manufactured by disposing a silicon wafer for evaluation having a notch orientation of <100> direction at a position shifted by 2 mm in the X direction of FIG. 3 from the first position. It is an X-ray topography image. In this evaluation, the length of the slip dislocation was the length of the hexagonal black contrast diagonal of the captured image. When the length of the slip dislocation is shifted in the X direction, the average value of the indentations of (1) and (3) in FIG. 1 is obtained. The average value of the indentations of (4) was used.

  FIGS. 5 and 6 show the relationship between the length of the slip dislocation generated in the manufactured evaluation silicon epitaxial wafer and the mounting position of the evaluation silicon wafer on the susceptor in the epitaxial growth furnace. Here, FIG. 5 shows the results when using the evaluation silicon wafer with the notch orientation of <100> direction, and FIG. 6 shows the results when using the evaluation silicon wafer with the notch orientation of <110> direction. I have. In each of FIGS. 5 and 6, (a) shows the result when the object is moved in the X direction in FIG. 3, and (b) shows the result when the object is moved in the Y direction in FIG.

  In FIG. 5, the length of the slip dislocation in the evaluation silicon epitaxial wafer changes depending on the mounting position of the evaluation silicon wafer on the susceptor in the epitaxial growth furnace. That is, in the case of shifting in any of the X direction and the Y direction, the smaller the shift amount is, the smaller the length of the slip dislocation is, and the larger the shift is, the longer the slip dislocation is. Further, the position where the length of the slip dislocation becomes zero (that is, the position where the slip dislocation does not occur) is shifted from the position where the shift amount is zero. As described above, the position where the amount of displacement is zero (first position) is a position where the center of the evaluation silicon wafer is visually confirmed and placed so as to be located on the center of the susceptor. The center of the evaluation silicon wafer placed on the susceptor is not necessarily located at a position where no slip dislocation occurs, and the epitaxial growth furnace does not have a structure symmetric with respect to the introduction direction of the wafer. Since there is no limitation, such a shift is considered to be possible.

  On the other hand, in FIG. 6, when a silicon wafer for evaluation whose notch is oriented in the <110> direction is used, no slip dislocation occurs at the position mounted on the susceptor, and the X and Y directions are different. No slip dislocation occurred in any of the directions. That is, when the direction of the notch is the <110> direction, it is considered that the shear stress applied to the indentation is small.

  From FIGS. 5 and 6, the occurrence of slip dislocation is caused by the introduction direction into the epitaxial growth furnace when the evaluation silicon wafer is placed on the susceptor, the direction in which the wafer is shifted, and the direction of the notch, ie, the evaluation silicon wafer. Was found to depend on the direction of the crystal. This result is presumed to be due to the fact that the direction in which the slip dislocation develops changes depending on the direction of the indentation formed on the evaluation silicon wafer, and that the shear stress applied to the indentation changes.

  From the above, the direction equivalent to the <110> direction of the crystal in the evaluation silicon wafer is placed in the first position on the susceptor provided in the epitaxial growth furnace in the epitaxial growth furnace. A silicon wafer on a susceptor that does not slip when the notch is oriented in both <110> and <100> by being arranged parallel to the introduction direction and shifted in a direction equivalent to the <110> direction Can be specified. The present inventors have thus completed the present invention. Hereinafter, each step will be described.

<First step>
First, in a first step, an evaluation silicon wafer is introduced into an epitaxial growth furnace, and a first position on a susceptor provided in the epitaxial growth furnace is equivalent to a <110> direction of a crystal in the evaluation silicon wafer. The silicon wafer for evaluation is arranged so as to be parallel to the introduction direction of the silicon wafer for evaluation into the epitaxial growth furnace. As the evaluation silicon wafer, for example, a silicon wafer obtained by processing a single crystal silicon ingot grown by the Czochralski method can be used. The conductivity type and diameter of the silicon wafer, the type of dopant, the resistivity, and the like can be the same as those of an epitaxial wafer actually manufactured in an epitaxial growth furnace to be evaluated.

  The silicon wafer for evaluation has indentations on the outer peripheral portion of the back surface imitating scratches introduced into the silicon wafer in the manufacturing process of the epitaxial wafer. In the above experiment, the indentation was formed using a Vickers hardness tester. However, the present invention is not limited to this, and the indentation can be formed by any appropriate method.

  The indentation is preferably formed by applying a load approximately equal to the load applied to the outer peripheral portion of the silicon wafer by the dissimilar material in the actual epitaxial wafer manufacturing process. This load is about 10 to 2000 gf.

  Further, the shape of the indentation is not limited to a rhombus, and it is sufficient that the indentation has a shape that causes slip dislocation from the indentation in a direction equivalent to the <110> direction. Specifically, the polygon can be a polygon such as a quadrangle or a triangle, and at least one corner of the polygon is bisected such that a slip dislocation is generated from a vertex in a direction equivalent to the <110> direction and propagates. It is sufficient that the line is oriented in a direction equivalent to the <110> direction. For example, in the case of a rhombus, the bisector of at least one corner thereof, that is, at least one of the diagonal lines of the rhombus may be directed in a direction equivalent to the <110> direction. In the case of a triangle, at least one vertical bisector of the vertex may be directed to the <110> direction.

  In addition, the number of indentations is one or more, and two or more are preferable because the temperature in the epitaxial furnace is not always constant and the amount of displacement of the crystal in the equivalent direction to <110> can be confirmed at a plurality of points. Particularly preferred is four.

  As the silicon wafer for evaluation on which indentations satisfying the above requirements are formed, a silicon wafer having four indentations formed on a silicon wafer having a plane orientation of (100) shown in FIG. 1A is preferably used. be able to.

<Second step>
Next, in the second step, a thermal stress equal to or greater than the thermal stress applied to the silicon wafer when manufacturing the epitaxial wafer is applied to the evaluation silicon wafer. This can be performed by forming an epitaxial layer on an evaluation silicon wafer and forming an epitaxial wafer in an epitaxial growth furnace, as in the actual epitaxial wafer manufacturing process.

  However, if only thermal stress is applied to the evaluation silicon wafer, it is not necessary to form an epitaxial layer. Therefore, instead of forming the epitaxial layer, a simulated heat treatment simulating a heat treatment applied to the silicon wafer in the process of manufacturing the epitaxial wafer can be performed on the evaluation silicon wafer.

  When the simulated heat treatment is performed, a thermal stress larger than a thermal stress applied to a silicon wafer in an actual epitaxial wafer manufacturing process can be intentionally applied. By intentionally applying such a thermal stress larger than the actual one, it is possible to specify a position in the epitaxial growth furnace where slip dislocation does not occur even with a larger thermal stress.

<Third step>
Subsequently, in a third step, it is evaluated whether or not a slip has occurred in the evaluation silicon wafer after the second step. This can be performed by imaging the back surface of the evaluation silicon wafer by the X-ray topography method.

<Fourth step>
Next, in a fourth step, the first to third steps are arranged at a position where the evaluation silicon wafer is shifted from the first position in a direction equivalent to the <110> direction of the crystal in the evaluation silicon wafer. Do. This is performed, for example, at a number of positions where the evaluation silicon wafer is displaced from the first position where it is first placed in a direction equivalent to the <110> direction, for example, by 0.1 mm.

  The direction in which the evaluation silicon wafer is shifted may be only one direction (for example, the X direction in FIG. 3), but is preferably performed in two directions (the X direction and the Y direction in FIG. 3). Thereby, the shift amount of the crystal in the direction equivalent to <110> can be confirmed at a plurality of points.

<Fifth step>
Subsequently, in a fifth step, based on the result of the fourth step, a mounting position of the silicon wafer on the susceptor at which no slip occurs when manufacturing the epitaxial wafer is specified.

  In this way, in the manufacturing process of the epitaxial wafer, the mounting position of the silicon wafer on the susceptor where slip dislocation does not occur can be specified.

(Epitaxial wafer manufacturing method)
Next, a method for manufacturing an epitaxial wafer according to the present invention will be described. As described above, the method for determining the conditions for manufacturing an epitaxial wafer according to the present invention makes it possible to specify the mounting position of the silicon wafer on the susceptor provided in the epitaxial growth furnace, in which no slip dislocation occurs in the manufacturing process of the epitaxial wafer. it can.

  Therefore, in the method of manufacturing an epitaxial wafer according to the present invention, the silicon wafer is arranged at a position on the susceptor where slip dislocation is not generated by the method according to the present invention, and an epitaxial layer is formed on the surface of the silicon wafer. Form. Thereby, an epitaxial wafer free of slip dislocation can be obtained.

(Example 1)
FIGS. 7A and 7B are enlarged views of the relationship shown in FIG. 5 where the shift amount is near zero, and FIG. 7A corresponds to FIG. 5A and FIG. From FIG. 7A, slip dislocation occurs at the first position (position where the amount of sliding is zero) where the evaluation silicon wafer is visually located such that the center of the silicon wafer is located above the center of the susceptor. You can see that At the first position, as shown in the X-ray topography image in FIG. 8, it can be seen that slip dislocations are generated from each indentation.

  On the other hand, FIG. 7A shows that no slip dislocation occurs at a position where the evaluation silicon wafer is shifted by 0.1 to 0.2 mm in the X direction. In fact, at the position shifted by 0.15 mm in the X direction, no slip dislocation is generated from each indentation as shown in the X-ray topography image in FIG. As described above, according to the present invention, it is possible to specify a position in the epitaxial growth furnace where no slip dislocation occurs in the epitaxial manufacturing process.

(Example 2)
The experiments obtained by the present inventors were performed on three different epitaxial growth furnaces of the same type. The results obtained are shown in FIG. As is clear from FIG. 9, the position where the slip dislocation does not occur is different for each epitaxial growth furnace. Therefore, it can be seen that the amount of shift should be specified for each epitaxial growth furnace and adjusted so as to be a position where no slip dislocation occurs.

  ADVANTAGE OF THE INVENTION According to this invention, since the manufacturing conditions of the epitaxial wafer which do not generate | occur | produce a slip dislocation can be determined, it is useful in the semiconductor wafer manufacturing industry.

Claims (7)

A method of determining conditions for manufacturing an epitaxial wafer by growing an epitaxial layer on a silicon wafer,
A silicon wafer for evaluation is introduced into an epitaxial growth furnace, and a direction equivalent to a <110> direction of a crystal in the silicon wafer for evaluation is placed at a first position on a susceptor provided in the epitaxial growth furnace. A first step of arranging the wafer so as to be parallel to the introduction direction of the wafer into the epitaxial growth furnace;
For the evaluation silicon wafer, a second step of applying a thermal stress equal to or greater than the thermal stress applied to the silicon wafer when manufacturing the epitaxial wafer,
A third step of evaluating whether a slip has occurred in the evaluation silicon wafer after the second step;
A fourth step in which the first to third steps are performed by disposing the evaluation silicon wafer at a position shifted from the first position in a direction equivalent to the <110> direction of the crystal in the evaluation silicon wafer. When,
Based on the result of the fourth step, the slip is not generated when manufacturing the epitaxial wafer, a fifth step of specifying the mounting position of the silicon wafer on the susceptor,
Including
As the evaluation silicon wafer, at least a polygonal indentation on an outer peripheral portion of the back surface, in which a bisector of at least one corner of the polygon is oriented in a direction equivalent to a <110> direction, A method for determining manufacturing conditions for an epitaxial wafer, comprising using a silicon wafer having one.   2. The method according to claim 1, wherein the second step is performed by forming an epitaxial layer on the silicon wafer for evaluation.   2. The epitaxial wafer according to claim 1, wherein the second step is performed on the evaluation silicon wafer by performing a simulated heat treatment simulating a heat treatment applied to the silicon wafer in a process of manufacturing the epitaxial wafer. 3. Manufacturing condition determination method.   4. The epitaxial wafer manufacturing condition according to claim 3, wherein in the simulated heat treatment, a thermal stress exceeding a thermal stress applied to the silicon wafer when the epitaxial wafer is manufactured is applied to the evaluation silicon wafer. 5. Decision method.   The method for determining epitaxial wafer manufacturing conditions according to claim 1, wherein the fourth step is performed in two directions equivalent to the <110> direction.   The epitaxial wafer manufacturing condition according to any one of claims 1 to 5, wherein a plane orientation (100) silicon wafer having four indentations at 90 ° intervals in a wafer circumferential direction is used as the evaluation silicon wafer. Decision method.   A silicon wafer, specified by the method of any one of claims 1 to 6, in the epitaxial growth furnace, at a position specified that no slip occurs in the epitaxial wafer, on the surface of the silicon wafer A method for producing an epitaxial wafer, comprising forming an epitaxial layer.