JP2019220530A - Semiconductor device - Google Patents

Abstract

To suppress characteristic fluctuation in a semiconductor device including a TFT composed of an oxide semiconductor.SOLUTION: A semiconductor device includes a TFT composed of an oxide semiconductor 103. The oxide semiconductor 103 includes a channel region 1031, a drain region 1032, and a source region 1033. A silicon nitride film 104 is laminated in the drain region 1032 and the source region 1033. A gate insulation film 105 is laminated in the channel region 1031. An aluminum oxide film 106 is laminated on the gate insulation film 105, and a gate electrode 107 is laminated on the aluminum oxide film. In a plan view, the gate electrode 107 and the aluminum oxide film 106 overlap the silicon nitride film 104.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device such as a display device having a TFT using an oxide semiconductor.

  In a liquid crystal display device, a TFT substrate in which pixels having pixel electrodes and thin film transistors (TFTs) and the like are formed in a matrix, and a counter substrate facing the TFT substrate are arranged, and liquid crystal is sandwiched between the TFT substrate and the counter substrate. Configuration. An image is formed by controlling the light transmittance of the liquid crystal molecules for each pixel. On the other hand, an organic EL display device forms a color image by arranging a self-emitting organic EL layer and a TFT in each pixel. Since an organic EL display device does not require a backlight, it is advantageous for thinning.

  A TFT using an oxide semiconductor has a small leak current, and thus is suitable as a switching TFT in a pixel region. On the other hand, an oxide semiconductor has a problem that it is easily changed with time due to intrusion of hydrogen or oxygen.

  Patent Document 1 describes a configuration in which a TFT using an oxide semiconductor is surrounded by an insulating film having a property of blocking the oxide semiconductor from hydrogen and oxygen to suppress a change in characteristics of the oxide semiconductor.

JP-A-2006-184635

  A TFT used for switching a pixel needs to have a small leak current and a large ON current. That is, in the TFT, it is necessary to maintain a sufficiently large resistance in the channel region and to have a sufficiently small resistance in the source region and the drain region.

  In an oxide semiconductor, the semiconductor can be maintained by supplying sufficient oxygen to a channel region. On the other hand, a configuration is known in which hydrogen is supplied to a source region and a drain region from a silicon nitride film or the like to reduce an oxide semiconductor and reduce resistance.

  As a method for reducing the resistance of the oxide semiconductor by reducing the source and drain regions, in addition to stacking SiN or the like on the source and drain regions, the source and drain regions may be exposed to a plasma containing a large amount of hydrogen. There is a technique for diffusing hydrogen into the drain. On the other hand, in addition to stacking a silicon oxide film containing a large amount of oxygen in the channel portion in order to maintain the channel portion of the oxide semiconductor in the semiconductor, in order to supply oxygen more stably, an aluminum oxide film is used. A configuration of laminating on an SiO film is known.

  However, in the oxide semiconductor, since the channel region and the source and drain regions are adjacent to each other, a unit for supplying oxygen to the channel of the oxide semiconductor and a unit for supplying hydrogen to the source and the drain interfere with each other, There has been a problem that the characteristics of the TFT change during the operation period.

  An object of the present invention is to provide a method for supplying oxygen to a channel region of an oxide semiconductor, in particular, which has an effect on an oxide semiconductor drain region and a source region. This is a countermeasure for the phenomenon.

  The present invention overcomes the above problems, and specific means are as follows.

  (1) A semiconductor device including a TFT formed of an oxide semiconductor, wherein the oxide semiconductor has a channel region, a drain region, and a source region, and a silicon nitride film is stacked over the drain region and the source region. A gate insulating film is stacked in the channel region, an aluminum oxide film is stacked on the gate insulating film, and a gate electrode is stacked thereon, and the gate electrode and the aluminum oxide film are A semiconductor device overlapping with the silicon nitride film.

  (2) The semiconductor device according to (1), wherein the aluminum oxide film is formed in a portion overlapping the gate electrode, and is removed in a portion other than the portion overlapping the gate electrode. .

It is a top view of a liquid crystal display device. It is sectional drawing of the display area of a liquid crystal display device. It is an expanded sectional view of a TFT. FIG. 4 is a plan view of FIG. 3. FIG. 4 is a cross-sectional view illustrating a state where an interlayer SiN film is formed on an oxide semiconductor. It is sectional drawing in the state where the interlayer SiN film was patterned. FIG. 3 is a cross-sectional view showing a state where a gate insulating film and an AlO film are formed. FIG. 4 is a cross-sectional view showing a state where a metal serving as a gate electrode is formed. FIG. 4 is a cross-sectional view showing a state where a gate electrode and an AlO film are patterned. FIG. 6 is a cross-sectional view of a TFT according to a second embodiment. FIG. 10 is a cross-sectional view of a display area according to the second embodiment. It is sectional drawing of the display area of an organic EL display device.

  Examples of the oxide semiconductor include IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), and IGO (Indium Gallium Oxide). An oxide semiconductor which is optically transparent and not crystalline is called TAOS (Transparent Amorphous Oxide Semiconductor). Hereinafter, in this specification, an oxide semiconductor may be referred to as TAOS. Hereinafter, the contents of the present invention will be described in detail with reference to examples.

  FIG. 1 is a plan view of a liquid crystal display device to which the present invention is applied. In FIG. 1, a TFT substrate 100 and a counter substrate 200 are adhered by a sealant 16, and a liquid crystal layer is sandwiched between the TFT substrate 100 and the counter substrate 200. The display region 14 is formed in a portion where the TFT substrate 100 and the counter substrate 200 overlap.

  In the display area 14 of the TFT substrate 100, the scanning lines 11 extend in the horizontal direction (x direction) and are arranged in the vertical direction (y direction). The video signal lines 12 extend in the vertical direction and are arranged in the horizontal direction. A region surrounded by the scanning lines 11 and the video signal lines 12 is a pixel 13.

  The TFT substrate 100 is formed larger than the counter substrate 200, and a portion where the TFT substrate 100 does not overlap with the counter substrate 200 is a terminal region 15. The flexible wiring board 17 is connected to the terminal area 15. The driver IC for driving the liquid crystal display device is mounted on the flexible wiring board 17.

  Since the liquid crystal does not emit light by itself, a backlight is provided on the back surface of the TFT substrate 100. The liquid crystal display panel forms an image by controlling light from a backlight for each pixel. The flexible wiring board 17 is bent to the back of the backlight to reduce the outer shape of the entire liquid crystal display device.

  FIG. 2 is a cross-sectional view of a display area where pixels exist. FIG. 2 shows a liquid crystal display device of a type called FFS (Fringe Field Switching) of IPS (In Plane Switching). In FIG. 2, a TFT using the oxide semiconductor 103 is used. A TFT using the oxide semiconductor 103 has a small leakage current, and thus is suitable as a switching TFT.

  In FIG. 2, a light-shielding film 101 is formed of a metal on a TFT substrate 100 formed of a resin such as glass or polyimide. As this metal, the same metal as a gate electrode and the like described later may be used. The light-shielding film 101 is for shielding light so that light from a backlight is not irradiated to a channel portion of a TFT to be formed later.

  A base film 102 is formed to cover the light shielding film 101. The base film 102 prevents the semiconductor layer 103 formed thereon from being contaminated by impurities from a glass substrate or the like. The base film 102 is often formed of a stacked film of a silicon oxide film (hereinafter represented by SiO) and a silicon nitride film (hereinafter represented by SiN).

  When a stacked film of a SiN film and a SiO film is used, the SiO film comes into contact with the oxide semiconductor. This is because the resistance of the channel region 1031 of the oxide semiconductor 103 is not reduced. Note that an aluminum oxide film (hereinafter represented by AlO) may be further laminated.

  In FIG. 2, an oxide semiconductor 103 forming a TFT is formed over a base film 102. The thickness of the oxide semiconductor 103 is 10 nm to 100 nm. IGZO is used for the oxide semiconductor 103, for example.

  An interlayer SiN film 104 is formed to cover the drain region 1032 and the source region 1033 of the oxide semiconductor 103. The SiN film 104 emits hydrogen, and the hydrogen reduces the drain region 1032 and the source region 1033 of the oxide semiconductor to make them conductive. The interlayer SiN film 104 is not formed in the channel region 1031 of the oxide semiconductor 103.

  In FIG. 2, an oxygen-rich SiO film is formed as a gate insulating film 105 in a channel region 1031 of the oxide semiconductor 103. The gate insulating film 105 is formed so as to cover the entire display area. An aluminum oxide film (hereinafter represented by AlO) 106 is formed by laminating with a gate insulating film 105 formed of a SiO film. The AlO film 106 is formed only on a portion corresponding to the gate electrode 107, not on the entire display region. The AlO film 106 has a role of supplying oxygen to the channel region 1031 of the oxide semiconductor 103. In that sense, an oxide such as IGZO has an effect of supplying oxygen by diffusion, so that an AlO film can be used instead.

  A gate electrode 107 is formed on the gate insulating film 105 and the AlO film 106. The gate electrode 107 is formed of, for example, a laminated film of Ti-Al-Ti (titanium-aluminum-titanium) or a MoW alloy.

  Through holes 120 and 121 are formed through the gate insulating film 105 and the interlayer SiN film 104. The through hole 120 connects the drain region 1032 of the oxide semiconductor to the drain electrode 108, and the through hole 121 connects the source region 1033 of the oxide semiconductor to the source electrode 109.

  An interlayer insulating film 110 is formed by covering the gate electrode 107, the drain electrode 108, and the source electrode 109 with a SiN film, a SiO film, or a laminated film thereof. The interlayer insulating film 110 protects the oxide semiconductor 103 from moisture or the like from the organic passivation film 111. The drain electrode 108 is connected to the video signal line 12 via a through hole formed at another location, and the source electrode 109 is connected to the pixel electrode 114 via through holes 130 and 131.

  In FIG. 2, an organic passivation film 111 is formed to cover the interlayer insulating film 110. The organic passivation film 111 is formed of, for example, an acrylic resin. The organic passivation film 111 has a role as a flattening film, and is formed as thick as about 2 to 4 μm in order to reduce the stray capacitance between the video signal line 12 and the common electrode 112. In order to connect the source electrode 109 and the pixel electrode 114, a through hole 130 is formed in the organic passivation film 111.

  A common electrode 112 is formed on the organic passivation film 111 by using a transparent conductive film such as ITO. The common electrode 112 is formed in a planar shape. A capacitance insulating film 113 covering the common electrode 112 is formed of SiN. The pixel electrode 114 is formed of a transparent conductive film such as ITO (Indium Tin Oxide) so as to cover the capacitor insulating film 113. The pixel electrode 114 is formed in a comb shape. The capacitance insulating film 113 is called as such because it constitutes a pixel capacitance between the common electrode 112 and the pixel electrode 114.

  An alignment film 115 is formed to cover the pixel electrode 114. The alignment film 115 defines an initial alignment direction of the liquid crystal molecules 301. As the alignment treatment of the alignment film 115, rubbing alignment treatment or optical alignment treatment using polarized ultraviolet light is used. Since IPS does not require a pretilt angle, a photo-alignment treatment is advantageous.

  In FIG. 2, a counter substrate 200 is arranged with a liquid crystal layer 300 interposed therebetween. On the opposite substrate 200, a color filter 201 and a black matrix 202 are formed, and an overcoat film 203 is formed thereon. An alignment film 204 is formed on the overcoat film 203. The function and the alignment process of the alignment film 204 are the same as those of the alignment film 115 on the TFT substrate 100 side.

  2, when a voltage is applied between the common electrode 112 and the pixel electrode 114, lines of electric force are generated as indicated by arrows in FIG. The light transmittance from the light source. An image is formed by controlling the light transmittance for each pixel.

  FIG. 3 is an enlarged sectional view near the TFT. In FIG. 3, a light-shielding film 101 is formed on a TFT substrate 100, and a base film 102 is formed so as to cover the light-shielding film 101. An oxide semiconductor 103 is formed over the base film 102. The oxide semiconductor 103 has a thickness of 10 nm to 100 nm and is formed by a sputtering ring. An interlayer SiN film 104 is formed over the drain region 1032 and the source region 1033 of the oxide semiconductor 103. The interlayer SiN film 104 releases hydrogen at the time of annealing for forming its own film or at the time of annealing in a subsequent step, and the hydrogen reduces the drain region 1032 and the source region 1033 of the oxide semiconductor 103 to form a conductive film. I do. The interlayer SiN film 104 is patterned so as not to exist in the channel region 1031 of the oxide semiconductor 103.

  A gate insulating film 105 is formed to cover the channel region 1031 of the oxide semiconductor 103 and the interlayer SiN film 104. The thickness of the gate insulating film 105 is 50 to 200 nm. The gate insulating film 105 is formed over the entire display area. An AlO film 106 is formed on the gate insulating film 105. The AlO film 106 is patterned so as to exist only under the gate electrode. The thickness of the AlO film 106 is 2 to 20 nm. Since the AlO film 106 is formed by reactive sputtering, it contains a large amount of oxygen. With this oxygen, the insulation resistance of the channel region 1031 of the oxide semiconductor 103 is stabilized. Oxides such as IGZO also have an effect of supplying oxygen by diffusion by heat treatment or the like, but film formation by reactive sputtering has a high oxygen supply efficiency and is more preferable.

  A gate electrode 107 is formed on the AlO film 106. The material of the gate electrode 107 is as described in FIG. The gate electrode 107 and the AlO film 106 ride on the interlayer SiN film 104 and the gate insulating film 105. That is, the drain region 1032 and the source region 1033 of the oxide semiconductor 103 slightly overlap. In the present invention illustrated in FIG. 3, even when the gate electrode 107 and the AlO film 106 overlap the drain region 1032 and the source region 1033 of the oxide semiconductor 103 in plan view, the AlO film 106 and the drain region of the oxide semiconductor 103 Since the interlayer SiN film 104 exists between 1032 and the source region 1033, oxygen from the AlO film 106 and the like is blocked in the interlayer SiN film 104.

  Accordingly, a phenomenon in which the resistance of the drain region 1032 or the source region 1033 of the oxide semiconductor 103 increases due to oxygen from the AlO film 106 or the gate insulating film 105 and the ON current decreases can be prevented. In FIG. 3, the interlayer SiN film 104 is processed so as to have a forward taper at an end. The taper angle θ is, for example, 40 degrees to 70 degrees. This is to prevent so-called step disconnection from occurring at the end of the interlayer SiN film 104 to break the gate insulating film 105 and the AlO film 106 and to leak the gate voltage. This taper angle may be measured at the center of the interlayer SiN film 104 in the thickness direction.

  In FIG. 3, the gate electrode 107 and the AlO film 106 are formed not only at the tapered portions of the gate insulating film 105 and the interlayer SiN film 104 but also over the interlayer SiN film 104 and the gate insulating film 105. Therefore, fine processing of the gate electrode 107 and the AlO film 106 is easy.

  3, a through hole 120 is formed in the gate insulating film 105 and the interlayer SiN film 104, the drain electrode 108 is connected to the drain region 1032 of the oxide semiconductor 103, and a through hole 121 is formed to form the source of the oxide semiconductor 103. The region 1033 is connected to the source electrode 109. In FIG. 3, the gate electrode 107, the drain electrode 108, and the source electrode 109 are formed under the same layer. When the distance d between the gate electrode 107 and the drain electrode 108 or between the gate electrode 107 and the source electrode 109 cannot be sufficiently secured, as shown in Embodiment 2, the drain electrode 108 and the source electrode 109 are formed on the interlayer insulating film. It may be formed.

  FIG. 4 is a plan view of FIG. In FIG. 4, the insulating film is omitted. In FIG. 4, an oxide semiconductor 103 is formed in a band shape over a light-shielding film 101 with a base film interposed therebetween. In FIG. 4, a drain region 1032 and a source region 1033 of the oxide semiconductor 103 are visible. A gate electrode 107 is formed over the oxide semiconductor 103 with an interlayer SiN film 104, a gate insulating film 105, and the like interposed therebetween. In FIG. 4, a portion indicated by a dotted line in the gate electrode 107 corresponds to an end of the interlayer SiN film 104, and the inside of the dotted line corresponds to the channel region 1031.

  The oxide semiconductor 103 extends to the left and connects to the drain electrode 108, and extends to the right and connects to the source electrode 109. In the oxide semiconductor 103, since the drain region 1032 between the gate electrode 107 and the drain electrode 108 is covered with the interlayer SiN film 104, the drain region 1032 is reduced by hydrogen from the interlayer SiN film 104 and becomes a conductive film. . The same applies to the source region 1033 between the gate electrode 107 and the source electrode 109 of the oxide semiconductor 103.

  5 to 9 are cross-sectional views showing a configuration in each process for realizing the configuration of FIG. FIG. 5 shows a light-shielding film 101 formed on a TFT substrate 100, a base film 102 formed thereon, an oxide semiconductor 103 formed thereon, and an interlayer SiN film 104 covering the oxide semiconductor 103. FIG. 4 is a cross-sectional view showing a state in which is formed by plasma CVD.

Hydrogen in the interlayer SiN film 104 can be appropriately controlled by plasma CVD. As the CVD gas, for example, silane (SiH ₄ ), ammonia (NH ₃ ), and nitrogen (N ₂ ) can be used. The flow rate ratio between silane and ammonia is set to, for example, 1/10 to 1/30. The nitrogen flow rate is adjusted so that the film formation pressure can be controlled. The film formation temperature is, for example, 250 ° C. to 400 ° C. The thickness of the interlayer SiN film 104 is adjusted according to the amount of hydrogen contained in the interlayer SiN film 104, and is generally 50 nm to 500 nm.

  FIG. 6 is a cross-sectional view showing a state in which the interlayer SiN film 104 is patterned. A resist 400 is formed on the interlayer SiN film 104, and as shown by an arrow, the interlayer SiN is dry-etched using a fluorine-based gas. The film 104 is opened. At this time, the opening of the interlayer SiN film 104 is controlled to have a forward taper. The taper angle θ is preferably 40 degrees to 70 degrees. Note that the interlayer SiN film 104 only needs to exist on the oxide semiconductor 103 side. For example, a layer corresponding to the interlayer SiN film 104 has a two-layer structure, and the lower side, that is, the oxide semiconductor 103 side is a SiN film. The upper side may be a SiO film.

FIG. 7 is a cross-sectional view showing a state where a gate insulating film 105 is formed to cover an opening of the interlayer SiN film 104, that is, a channel region 1031 of the oxide semiconductor 103 and the interlayer SiN film 104, and then an AlO film 106 is formed. FIG. The gate insulating film 105 is a SiO film. Plasma CVD can be used for forming the gate insulating film 105. As the CVD gas, for example, silane (SiH ₄ ) and nitrous oxide (N ₂ O) are used. The gas flow ratio between silane and nitrous oxide is set to, for example, 1/10 to 1/100.

  The film formation temperature is, for example, 200 degrees to 400 degrees. The thickness of the gate insulating film 105 is 50 to 200 nm. The film quality, the film thickness, and the like of the gate insulating film 105 are determined in consideration of the withstand voltage, the TFT characteristics, and the balance of the amount of oxygen diffusion from the AlO film to the oxide semiconductor 103.

  It is preferable that the gate insulating film 105 be formed in a portion other than the lower portion of the gate electrode 107. As shown in FIG. 3, in this embodiment, the gate electrode 107, the source electrode 109, and the drain electrode 108 are formed in the same layer. When the source electrode and the drain electrode are formed of a laminated film of titanium (Ti) and aluminum (Al), when processed by dry etching, if the underlying layer is SiO, the over-etched film thickness is smaller than that of, for example, SiN. It is possible to do.

  In FIG. 7, an AlO film 106 is formed on the SiO film constituting the gate insulating film 105. It is desirable that the AlO film 106 be formed by reactive sputtering. This is because the AlO film 106 formed by reactive sputtering contains a large amount of oxygen. The thickness of the AlO film 106 is preferably 2 to 20 nm, and the film quality is preferably amorphous from the viewpoint of workability.

  In FIG. 7, when annealing is performed, when the AlO film 106 is formed, a large amount of oxygen implanted into the AlO film by reactive sputtering diffuses into the channel region 1031 of the oxide semiconductor 103, and the channel of the oxide semiconductor 103 is formed. To keep. The annealing condition for diffusing oxygen into the oxide semiconductor 103 is about 300 ° C. to 400 ° C. for about 1 hour.

  FIG. 8 is a cross-sectional view showing a state in which a metal to be the gate electrode 107 covering the AlO film 106 is formed by sputtering. The metal material and the like of the gate electrode 107 are as described in FIG.

  FIG. 9 is a cross-sectional view showing a state where the gate electrode 107 and the AlO film 106 are patterned. In FIG. 9, the gate electrode 107 and the AlO film 106 are formed beyond the tapered portions of the interlayer SiN film 104 and the gate insulating film 105. This facilitates dimensional control.

  9, the AlO film 106 is left only under the gate electrode 107. When the AlO film 106 extends to a portion other than the gate electrode, oxygen from the AlO film 106 diffuses in the SiO film which is the gate insulating film 105, reaches the oxide semiconductor 103, and This is because supply of excess oxygen to the drain region 1032 and the source region 1033 may cause an increase in the resistance of the source region 1033 and the drain region 1032 of the oxide semiconductor 103.

  Processing of the AlO film 106 can be performed by dry etching using a chlorine (Cl) -based gas or wet etching using DHF (Diluted Hydrofluoric acid), a mixed acid, or the like. In the patterning of the AlO film 106, a resist for patterning the gate electrode 107 may be used as it is, or the gate electrode 107 may be used as a mask.

  After that, through holes 120 and 121 are formed in the gate insulating film 105 and the interlayer SiN film 104 formed of the SiO film, and the drain electrode 108 and the drain region 1031 of the oxide semiconductor, and the source electrode 109 and the oxide By connecting the semiconductor source region 1033, the configuration shown in FIG. 3 is obtained. Note that the drain electrode 108 and the source electrode 109 can have a stacked structure of titanium-aluminum-titanium (Ti-Al-Ti), for example.

  As described above, according to the present invention, sufficient oxygen is supplied from the AlO film 106 to the channel region 1031 of the oxide semiconductor 103. On the other hand, since the interlayer SiN film 104 is stacked in the drain region 1032 and the source region 1033 of the oxide semiconductor 103, hydrogen is supplied from the interlayer SiN film 104 and oxygen from the AlO film 106 and the like is blocked. Therefore, a display device using a highly reliable oxide semiconductor with stable characteristics can be realized.

  In the first embodiment, as shown in FIG. 3, the gate electrode 107, the drain electrode 108, and the source electrode 109 are formed in the same layer. In such a case, the distance between the gate electrode 107 and the drain electrode 108 or the distance between the gate electrode 107 and the source electrode 109 as shown by d in FIG. 3 may not be sufficient.

  In the second embodiment, in order to avoid this problem, a drain electrode 108 and a source electrode 109 are formed on an interlayer insulating film 110 as shown in FIG. In FIG. 10, through holes 120 and 121 are formed through three layers of an interlayer insulating film 110, a gate insulating film 105, and an interlayer SiN film 104. The drain electrode 108 and the source electrode 109 are formed on the interlayer insulating film 110.

  FIG. 11 is a sectional view of a display area of the liquid crystal display device according to the present embodiment. FIG. 11 corresponds to FIG. 2 of the first embodiment. FIG. 11 differs from FIG. 2 in that through holes 120 and 121 are formed through three layers of an interlayer insulating film 110, a gate insulating film 105, and an interlayer SiN film 104, and a drain electrode 108 and a source electrode 109 That is, it is formed on the film 110.

  With the configuration of FIG. 11, the drain electrode 108 can be directly connected to the video signal line 12 without passing through the through hole. The source electrode 109 is connected to the pixel electrode 114 via a through hole 130 formed in the organic passivation film 111 and a through hole 131 formed in the capacitance insulating film 113.

  The configuration of the TFT and its surroundings is the same as in the first embodiment, and the effect is the same.

  In the first and second embodiments, the liquid crystal display device has been described as an example. The present invention can be similarly applied to an organic EL display device. FIG. 12 is a sectional view of a pixel portion of the organic EL display device. In FIG. 12, a glass substrate or a resin substrate such as polyimide is used for the TFT substrate 100. In FIG. 12, the process from the TFT substrate 100 to the formation of the drain electrode 108 and the source electrode 109 is the same as that of the liquid crystal display device of the second embodiment shown in FIG. Therefore, the configuration of the present invention described in the first and second embodiments can be applied as it is.

  Other configurations of the organic EL display device in FIG. 12 are as follows. An organic passivation film 111 is formed to cover the drain electrode 108 and the source electrode 109, and a through hole 130 is formed in the organic passivation film 111. On the organic passivation film 111, a lower electrode 150 is formed by a stacked film of a reflective electrode made of a metal or an alloy and an anode made of an oxide conductive film.

  An organic film such as acryl, which becomes the bank 151, is formed thereon, and holes are formed in this film. An organic EL film 152 serving as a light emitting layer is formed in the hole. The organic EL film 152 is usually formed by a plurality of films. A cathode 153 is formed to cover the organic EL film 152 and the bank 151. The cathode 153 is formed of a transparent oxide conductive film such as ITO, AZO (Antimony Zinc Oxide), or a metal thin film.

  After that, a protection film 154 for protecting the organic EL film 152 is formed with SiN or the like. After that, a polarizing plate 156 for preventing reflection is attached on the protective film 154 via the adhesive 155. Note that the protective film 154 may be not only an inorganic film such as SiN but also a transparent organic film such as acryl laminated thereon.

  As described above, the configuration of the present invention described in Embodiments 1 and 2 can be applied to the organic EL display device.

  In each of the above embodiments, the display device is described as an example. However, the TFT using the oxide semiconductor of this structure can be used for an optical sensor device.

  DESCRIPTION OF SYMBOLS 11 ... scanning line, 12 ... video signal line, 13 ... pixel, 14 ... display area, 15 ... terminal area, 16 ... sealing material, 17 ... flexible wiring board, 100 ... TFT substrate, 101 ... light shielding film, 102 ... base film 103, an oxide semiconductor, 104, an interlayer SiN film, 105, a gate insulating film, 106, an AlO film, 107, a gate electrode, 108, a drain electrode, 109, a source electrode, 110, an interlayer insulating film, 111, an organic passivation film , 112: Common electrode, 113: Capacitive insulating film, 114: Pixel electrode, 115: Alignment film, 120: Through hole, 121: Through hole, 130: Through hole, 131: Through hole, 150: Lower electrode, 151: Bank 152, an organic EL layer; 153, a cathode; 154, a protective layer, 15 5: adhesive, 156: polarizing plate, 200: counter substrate, 201: color filter, 202: black matrix, 203: overcoat film, 204: alignment film, 300: liquid crystal layer, 301: liquid crystal molecule, 400: resist, 1031: channel region, 1032: drain region, 1033: source region

Claims (13)

A semiconductor device having a TFT composed of an oxide semiconductor,
The oxide semiconductor has a channel region, a drain region, and a source region,
A silicon nitride film is laminated on the drain region and the source region,
A gate insulating film is laminated on the channel region,
An aluminum oxide film is stacked on the gate insulating film, and a gate electrode is stacked thereon,
The semiconductor device, wherein the gate electrode and the aluminum oxide film overlap with the silicon nitride film in a plan view.   2. The semiconductor device according to claim 1, wherein the aluminum oxide film overlaps with the gate electrode in a plan view, and a removed portion is arranged in a portion not overlapping with the gate electrode. 3.   3. The semiconductor device according to claim 2, wherein the gate insulating film is formed in a portion other than a portion overlapping with the gate electrode and the aluminum oxide film.   2. The semiconductor device according to claim 1, wherein the silicon nitride film has a tapered cross section at an end portion close to a channel region of the oxide semiconductor.   The semiconductor device according to claim 4, wherein the angle of the taper of the silicon nitride is 40 degrees to 70 degrees.   The semiconductor device according to claim 4, wherein the gate electrode and the aluminum oxide film extend beyond the taper of the silicon nitride to an upper part of the silicon nitride.   2. The semiconductor device according to claim 1, wherein said silicon nitride has a thickness of 50 nm to 500 nm.   2. The semiconductor device according to claim 1, wherein said aluminum oxide film has a thickness of 2 nm to 20 nm.   2. The semiconductor device according to claim 1, wherein said aluminum oxide film is formed by reactive sputtering.   2. The semiconductor device according to claim 1, wherein a drain electrode of the TFT is formed on the gate insulating film, and a source electrode is formed on the gate insulating film.   An interlayer insulating film is formed to cover the gate electrode, a drain electrode of the TFT is formed on the interlayer insulating film, and a source electrode is formed on the interlayer insulating film. Item 2. The semiconductor device according to item 1.   The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device.   The semiconductor device according to claim 1, wherein the semiconductor device is an organic EL display device.

Images