JP2019217654A - Image forming device - Google Patents

Abstract

To improve image quality by increasing a grayscale of image data while suppressing costs of an interface part between a controller part and an exposure head.SOLUTION: A control board 415 includes: a CPU 400 having an image data generating part 401 for generating binary image data by second resolution and a data transmitting part 405 for transmitting image data to an exposure head 106; and a control board 415 mounting the CPU 400. The exposure head 106 has a drive part 303 having a data receiving part 407 for receiving the image data from the control board 415, and controlling light emission from a surface light-emitting element, and a drive substrate 202 mounting the drive part 303. The control board 415 and the drive substrate 202 are connected by a cable. The CPU 400 transmits, by serial communication, the image data to the drive part 303 via a cable, and the drive part 303 has a filter processing part 408 for converting the binary image data received by the data receiving part 407 into image data of resolution of a multivalued surface light-emitting element array chip.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an electrophotographic image forming apparatus.

  2. Description of the Related Art In a printer which is an electrophotographic image forming apparatus, a method of exposing a photosensitive drum using an exposure head to form a latent image is generally known. Note that, as the exposure head, an LED (Light Emitting Diode), an organic EL (Organic Electro Luminescence), or the like is used. The exposure head includes a light emitting element array arranged in the longitudinal direction of the photosensitive drum, and a rod lens array for forming an image of light from the light emitting element array on the photosensitive drum. It is known that an LED or an organic EL has a surface emission shape in which a light irradiation direction from a light emission surface is the same as that of a rod lens array. Here, the length of the light emitting element row is determined according to the image area width on the photosensitive drum, and the interval between the light emitting elements is determined according to the resolution of the printer. For example, in the case of a 1200 dpi printer, the interval between pixels is 21.16 μm, and therefore, the interval between light emitting elements is also an interval corresponding to 21.16 μm. Since a printer using such an exposure head uses a smaller number of parts than a laser scanning printer that scans a photosensitive drum with a laser beam deflected by a rotating polygon mirror, the apparatus is downsized. It is easy to reduce the cost. Further, in a printer using an exposure head, the sound generated by the rotation of the rotary polygon mirror is reduced.

  In the configuration using such an exposure head, since the exposure head side has a large number of light emitting elements, the number of signal lines for transmitting data between the controller and the exposure head to light each light emitting element of the exposure head is enormous. It becomes. For this reason, a system using a data communication module for serializing image data and transmitting / receiving the image data is generally known as an interface between a controller unit for outputting image data and an exposure head. For example, Patent Document 1 discloses a method of multiplexing and transmitting image data for controlling light emission timing of a plurality of light emitting elements and generating a signal corresponding to a light emission pulse width of each light emitting element on a receiving side. .

Japanese Patent No. 4432920

  However, when the controller transmits image data to the exposure head and generates a pulse signal corresponding to a pulse width corresponding to the light emission amount of the light emitting element on the exposure head side, the communication speed between the controller and the exposure head is , And increases in proportion to the amount of data to be transmitted and received. For example, if the controller unit increases the number of gradations of one pixel in order to improve the image quality such as improving the gradation of an image, the amount of data to be transmitted and received increases. Increase occurs.

  The transfer speed (unit: Hz) of the image data, which is the communication speed between the controller unit and the exposure head, can be calculated by the following (Equation 1).

Transfer speed = (number of surface light emitting elements × number of gradations) ÷ (1 line cycle × number of data wirings) (Equation 1)
Here, the number of surface light emitting elements is the number of light emitting elements included in the exposure head, and the number of gradations is the number of bits for expressing the gradation of one pixel (for example, 1 bit in the case of binary) and one line cycle Is a time for exposing one line in the main scanning direction of the photosensitive drum. The number of data lines is the number of signal lines for transferring image data between the controller and the exposure head. For example, in the case of an exposure head that prints in binary (0, 1), the one-line cycle TL is 100 μs (microsecond), the number of surface emitting elements is 14,964 (image width is about 316 mm at 1200 dpi), and the number of data wires is Is 6 lines. When the transfer rate of the image data is calculated using (Equation 1), the transfer rate is about 25 MHz. On the other hand, in the case of an exposure head that prints in a multi-valued manner (the number of gradations indicating one pixel gradation is 8 bits), the one-line cycle TL is 100 μs, the number of surface emitting elements is 14,964 elements (image width is about 1200 dpi, and 316 mm) and the number of data wirings is six. When the transfer rate of the image data is calculated using (Equation 1), the transfer rate is about 200 MHz. The transfer speed is increased by making the gradation of one pixel multi-valued. Therefore, if the number of wires for performing data transfer between the controller unit and the exposure head is increased in order to reduce the transfer speed, the number of components increases with the increase in the number of wires, resulting in an increase in cost. In addition, an increase in the transfer speed necessitates the addition of a radiation noise countermeasure component, resulting in an increase in cost.

  The present invention has been made under such circumstances, and an object of the present invention is to improve the image quality by increasing the gradation of image data while suppressing the cost of the interface between the controller and the exposure head.

  In order to solve the above-described problem, the present invention has the following configuration.

  (1) A photoreceptor rotating in a first direction and a plurality of surface light emitting elements arranged in a second direction orthogonal to the first direction, and the surface light emitting elements expose the photoreceptor. An image forming apparatus comprising: an exposure unit; and a control unit configured to output image data to the exposure unit and control image formation, wherein the control unit includes a second unit having a second resolution larger than a first resolution of the surface light emitting element. A controller having: a generating unit that generates the binary image data at a resolution of; and a transmitting unit that transmits the image data generated by the generating unit to the exposure unit; and a control board on which the controller is mounted. And the exposure unit has a receiving unit that receives the image data transmitted from the control unit, a driver that controls light emission of the surface light emitting element, and a drive board that mounts the driver , And the system The board and the drive board are connected by a cable, the controller transmits the image data to the driver via the cable by serial communication, and the driver transmits the image data received by the reception unit. A conversion means for converting the resolution in the second direction from the second resolution to the first resolution, wherein the density of the converted pixel is adjacent to the density of the pixel before conversion and the density of the pixel before conversion. An image forming apparatus comprising: a conversion unit configured to perform conversion by interpolation processing based on the density of pixels to be converted and to convert the binary image data into multi-value image data larger than the binary. .

  According to the present invention, it is possible to improve the image quality by increasing the gradation of image data while suppressing the cost of the interface between the controller and the exposure head.

1 is a schematic cross-sectional view illustrating a configuration of an image forming apparatus according to an embodiment. FIG. 2 is a diagram illustrating a positional relationship between an exposure head and a photosensitive drum according to the embodiment, and a diagram illustrating a configuration of the exposure head. FIG. 2 is a schematic diagram of a driving substrate according to an embodiment, and a diagram illustrating a configuration of a surface emitting element array chip. Control block diagram of control board and drive board of embodiment Control block diagram and timing chart of a chip data conversion unit of an embodiment FIG. 4 is a diagram illustrating an interface signal between the control board and the drive board according to the embodiment. FIG. 6 is a view for explaining filter processing according to the embodiment. FIG. 6 is a view for explaining filter processing according to the embodiment. FIG. 4 is a diagram for explaining pulse response characteristics of the light emitting thyristor of the embodiment. FIG. 4 is a diagram illustrating temperature characteristics of a light-emitting thyristor of an example. FIG. 4 is a view for explaining a lookup table according to the embodiment. Conversion table showing an example of a lookup table according to the embodiment. FIG. 4 is a diagram illustrating a circuit of a surface emitting element array chip according to an embodiment. FIG. 4 is a view for explaining a distribution state of a gate potential of the shift thyristor of the embodiment. FIG. 7 is a diagram showing a drive signal waveform of the surface emitting element array chip of the embodiment. The figure which shows the cross section of the surface emitting thyristor of an Example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Configuration of Image Forming Apparatus]
FIG. 1 is a schematic cross-sectional view illustrating a configuration of an electrophotographic image forming apparatus according to a first embodiment. The image forming apparatus illustrated in FIG. 1 is a multifunction peripheral (MFP) having a scanner function and a printer function, and includes a scanner unit 100, an image forming unit 103, a fixing unit 104, a sheet feeding / conveying unit 105, and a printer that controls these units. It comprises a control unit (not shown). The scanner unit 100 optically reads a document image by illuminating a document placed on a document table, and converts the read image into an electric signal to create image data.

  The image forming unit 103 is arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K) along the rotation direction (counterclockwise direction) of the endless transport belt 111. It has a series of image forming stations. The four image forming stations have the same configuration, and each image forming station includes a photosensitive drum 102, which is a photosensitive member that rotates in the direction of an arrow (clockwise), an exposure head 106, a charger 107, and a developing device 108. I have. The suffixes a, b, c, and d of the photosensitive drum 102, the exposure head 106, the charger 107, and the developing device 108 are black (K), yellow (Y), magenta (M), and cyan ( C). In the following, the suffixes of the reference numerals will be omitted except for the case where a specific photosensitive drum or the like is indicated.

  In the image forming unit 103, the photosensitive drum 102 is driven to rotate, and the charger 107 charges the photosensitive drum 102. The exposure head 106, which is an exposure unit, emits light from the arrayed LED array according to image data, and condenses light emitted from the chip surface of the LED array onto the photosensitive drum 102 (photosensitive member) by the rod lens array. Thus, an electrostatic latent image is formed. The developing device 108 develops the electrostatic latent image formed on the photosensitive drum 102 with toner. Then, the developed toner image is transferred to a recording sheet on a transport belt 111 that transports the recording sheet. Such a series of electrophotographic processes is executed in each image forming station. At the time of image formation, after a predetermined time elapses after image formation in the cyan (C) image forming station is started, each of the magenta (M), yellow (Y), and black (K) image forming stations is sequentially performed. Then, the image forming operation is executed.

  The image forming apparatus illustrated in FIG. 1 includes, as units for feeding recording paper, internal feeding units 109a and 109b included in the feeding / conveying unit 105, an external feeding unit 109c that is a large-capacity feeding unit, and A manual sheet feeding unit 109d is provided. At the time of image formation, the recording paper is fed from a paper feeding unit designated in advance, and the fed recording paper is conveyed to the registration roller 110. The registration roller 110 conveys the recording paper to the conveyance belt 111 at the timing when the toner image formed in the image forming unit 103 is transferred onto the recording paper. The toner images formed on the photosensitive drums 102 of the respective image forming stations are sequentially transferred onto the recording paper transported by the transport belt 111. The recording paper to which the unfixed toner image has been transferred is conveyed to the fixing unit 104. The fixing unit 104 has a built-in heat source such as a halogen heater, and fixes the toner image on the recording paper to the recording paper by heating and pressing with two rollers. The recording paper on which the toner image has been fixed by the fixing unit 104 is discharged to the outside of the image forming apparatus by the discharge roller 112.

  An optical sensor 113 as a second detection unit is disposed at a position facing the transport belt 111 downstream of the black (K) image forming station in the recording paper transport direction. The optical sensor 113 detects the position of a test image formed on the transport belt 111 to derive the amount of color shift of the toner image between the image forming stations. The color misregistration amount derived by the optical sensor 113 is notified to a CPU 400 (see FIG. 4) of the control board 415 described later, and the image position of each color is shifted so that a full-color toner image without color misregistration is transferred onto the recording paper. Will be corrected. Further, a printer control unit (not shown) controls the above-described scanner unit 100, image forming unit 103, fixing unit 104, and supply unit in accordance with an instruction from an MFP control unit (not shown) that controls the entire multifunction peripheral (MFP). The image forming operation is executed while controlling the paper / transport unit 105 and the like. Further, a thermistor 421, which is a first detecting means, is provided near the image forming unit 103 in order to measure an ambient temperature of an exposure head 106 (see FIG. 2), which is provided above the photosensitive drum 102 and described later. Is provided.

  Here, as an example of an electrophotographic image forming apparatus, an image forming apparatus of a method of directly transferring a toner image formed on a photosensitive drum 102 of each image forming station to a recording sheet on a conveyor belt 111 has been described. The present invention is not limited to such a printer that directly transfers the toner image on the photosensitive drum 102 to recording paper. For example, the present invention is also applicable to an image forming apparatus including a primary transfer unit that transfers the toner image on the photosensitive drum 102 to the intermediate transfer belt and a secondary transfer unit that transfers the toner image on the intermediate transfer belt to recording paper. can do.

[Structure of exposure head]
Next, the exposure head 106 that exposes the photosensitive drum 102 will be described with reference to FIG. FIG. 2A is a perspective view showing a positional relationship between the exposure head 106 and the photosensitive drum 102, and FIG. 2B is a view showing the internal configuration of the exposure head 106 and a light beam from the exposure head 106 being a rod lens array. FIG. 3 is a diagram illustrating a state where light is condensed on a photosensitive drum 102 by 203. As shown in FIG. 2A, the exposure head 106 is mounted on the image forming apparatus by a mounting member (not shown) at a position facing the photosensitive drum 102 above the photosensitive drum 102 rotating in the direction of the arrow. (Fig. 1).

  As shown in FIG. 2B, the exposure head 106 includes a driving substrate 202, a surface light emitting element array element group 201 mounted on the driving substrate 202, a rod lens array 203, and a housing 204. The rod lens array 203 and the drive board 202 are attached to the housing 204. The rod lens array 203 condenses the light beam from the surface light emitting element array element group 201 on the photosensitive drum 102. In the factory, the assembling and adjusting work is performed with the exposure head 106 alone, and the focus adjustment and the light amount adjustment of each spot are performed. Here, the assembly and adjustment are performed so that the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the surface light emitting element array element group 201 are at predetermined intervals. Thus, light from the surface light emitting element array element group 201 is imaged on the photosensitive drum 102. Therefore, at the time of focus adjustment at a factory, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the surface light emitting element array element group 201 becomes a predetermined value. When adjusting the light amount at the factory, the light emitting elements of the surface light emitting element array element group 201 are sequentially caused to emit light, and the light collected on the photosensitive drum 102 via the rod lens array 203 reaches a predetermined light amount. Thus, the drive current of each light emitting element is adjusted.

[Configuration of surface light emitting element array element group]
FIG. 3 is a diagram illustrating the surface light emitting element array element group 201. FIG. 3A is a schematic diagram illustrating a configuration of a surface of the driving substrate 202 on which the surface light emitting element array element group 201 is mounted, and FIG. 3B is a diagram illustrating the surface light emitting element array element group 201 of the driving substrate 202. FIG. 4 is a schematic diagram showing a configuration of a surface (second surface) opposite to a surface on which is mounted (first surface).

  As shown in FIG. 3A, the surface emitting element array element group 201 mounted on the driving substrate 202 includes 29 surface emitting element array chips 1 to 29 staggered along the longitudinal direction of the driving substrate 202. It has a configuration arranged in two rows. In FIG. 3A, the vertical direction indicates the sub-scanning direction (the rotation direction of the photosensitive drum 102) which is the first direction, and the horizontal direction is the main scanning which is the second direction orthogonal to the sub-scanning direction. Direction (the longitudinal direction of the exposure head 106). Inside each surface light emitting element array chip, each element of the surface light emitting element array chip having a total of 516 light emitting points is arranged at a predetermined resolution pitch in the longitudinal direction of the surface light emitting element array chip. In this embodiment, the pitch of each element of the surface-emitting element array chip is approximately 21.16 μm (≒ 2.54 cm / 1200 dots), which is the pitch of the first resolution of 1200 dpi. As a result, the distance between the ends of the 516 light-emitting points in one surface light-emitting element array chip is about 10.9 mm (．21.16 μm × 516). The surface light emitting element array element group 201 is composed of 29 surface light emitting element array chips. The number of light emitting elements that can be exposed in the surface light emitting element array element group 201 is 14,964 elements (= 516 elements × 29 chips), corresponding to an image width of about 316 mm (１６about 10.9 mm × 29 chips) in the main scanning direction. Image formation can be performed.

  FIG. 3C is a diagram showing a state of a boundary portion between the surface light emitting element array chips arranged in two rows in the longitudinal direction, and the horizontal direction shows the surface light emitting element array element of FIG. This is the longitudinal direction of the group 201. As shown in FIG. 3C, a wire bonding pad to which a control signal is input is arranged at an end of the surface light emitting element array chip, and the transfer unit and the light emitting unit are driven by a signal input from the wire bonding pad. The element is driven. The surface light emitting element array chip has a plurality of light emitting elements. Also at the boundary between the surface light emitting element array chips, the pitch in the longitudinal direction of the light emitting elements (the distance between the center points of the two light emitting elements) is about 21.16 μm, which is the pitch of the resolution of 1200 dpi. . Also, in the surface light emitting element array chips arranged in the upper and lower two rows, the distance between the light emitting points of the upper and lower surface light emitting element array chips (indicated by an arrow S in the drawing) is about 84 μm (4 pixels at 1200 dpi, 8 pixels at 2400 dpi) (A distance of an integral multiple of each minute).

  Further, as shown in FIG. 3B, on the surface of the drive substrate 202 opposite to the surface on which the surface light emitting element array element group 201 is mounted, the drive units 303a and 303b and the connector 305 are mounted. I have. Drive units 303a and 303b arranged on both sides of the connector 305 are driver ICs for driving the surface light emitting element array chips 1 to 15 and the surface light emitting element array chips 16 to 29, respectively. The driving units 303a and 303b are connected to the connector 305 via the patterns 304a and 304b, respectively. The connector 305 is connected to a signal line for controlling the driving units 303a and 303b from a control board 415 (see FIG. 4) described later, a power supply voltage, and a ground, and is connected to the driving units 303a and 303b. From the driving units 303a and 303b, wiring for driving the surface light emitting element array element group 201 passes through the inner layer of the drive substrate 202, and the surface light emitting element array chips 1 to 15 and the surface light emitting element array chips 16 to 29 It is connected to the.

[Control configuration of control board and drive board]
FIG. 4 shows a control board 415 that processes image data and outputs the processed data to the drive board 202 of the exposure head 106, and a drive board of the exposure head 106 that exposes the photosensitive drum 102 based on the image data input from the control board 415. It is a control block diagram of 202. Regarding the drive substrate 202, surface light emitting element array chips 1 to 15 controlled by the drive unit 303a illustrated in FIG. 4 will be described. The surface light emitting element array chips 16 to 29 controlled by the driving unit 303b (not shown in FIG. 4) perform the same operation as the surface light emitting element array chips 1 to 15 controlled by the driving unit 303a. In addition, for simplicity of description, image processing of one color will be described here. However, in the image forming apparatus of the present embodiment, similar processing is performed in parallel for four colors simultaneously. The control board 415 shown in FIG. 4 has a connector 416 for transmitting a signal for controlling the exposure head 106 to the drive board 202. From the connector 416, image data, a line synchronization signal described later, and a control signal from the CPU 400 of the control board 415 are transmitted via cables 417, 418, and 419 connected to the connector 305 of the drive board 202, respectively.

[Configuration of control board]
In the control board 415, processing of image data, processing of print timing, and acquisition of temperature data from the thermistor 421 are performed by the CPU 400 as a controller. The control board 415 includes functional blocks of an image data generation unit 401, a line data shift unit 402, a chip data conversion unit 403, a chip data shift unit 404, a data transmission unit 405, and a synchronization signal generation unit 406. In this embodiment, it is assumed that the image data generation unit 401 is configured by one integrated circuit (IC). Further, the line data shift unit 402, the chip data conversion unit 403, the chip data shift unit 404, the data transmission unit 405, and the synchronization signal generation unit 406 are different from the integrated circuit having the image data generation unit 401 in one integrated circuit ( IC). Note that an image data generation unit 401, a line data shift unit 402, a chip data conversion unit 403, a chip data shift unit 404, a data transmission unit 405, and a synchronization signal generation unit 406 represent modules inside an integrated circuit (IC). . The CPU 400 is an integrated circuit different from these integrated circuits, and the control board 415 has the CPU 400, an integrated circuit having the image data generation unit 401, an integrated circuit having the line data shift unit 402, and a connector 416 mounted thereon. ing. Note that the image data generation unit 401, the line data shift unit 402, the chip data conversion unit 403, the chip data shift unit 404, the data transmission unit 405, and the synchronization signal generation unit 406 may be included in one integrated circuit. Further, the image data generation unit 401, the line data shift unit 402, the chip data conversion unit 403, the chip data shift unit 404, the data transmission unit 405, the synchronization signal generation unit 406, and the CPU 400 are included in one integrated circuit. Is also good. Hereinafter, processing in each functional block will be described in the order in which image data is processed in the control board 415.

(Image data generator)
An image data generation unit 401 serving as a data generation unit performs dithering processing on input image data received from the scanner unit 100 or an external computer connected to the image forming apparatus at a resolution instructed by the CPU 400, and converts the image data. Generate. In the present embodiment, the image data generation unit 401 performs dithering processing at a resolution of 2400 dpi, which is the second resolution. That is, the image data generated by the image data generation unit 401 is pixel data equivalent to 2400 dpi. The pixel data corresponding to 2400 dpi in this embodiment is one bit, but one pixel may be represented by a plurality of bits. The pixel data generated by the image data generation unit 401 is line data corresponding to a line corresponding to 2400 dpi in the sub-scanning direction (the rotation direction of the photosensitive drum 102 and the conveyance direction of the recording paper). Then, the image data generation unit 401 generates the pixel data corresponding to each pixel whose resolution is equivalent to 2400 dpi in association with the position of the pixel in the main scanning direction (the longitudinal direction of the exposure head 106).

(Line data shift section)
The CPU 400 determines the image shift amount in the main scanning direction and the sub-scanning direction in units of 2400 dpi based on the color shift amount detected by the optical sensor 113. The image shift amount is determined by the CPU 400 based on, for example, a relative color shift amount between colors calculated based on a detection result of the color shift detection pattern image by the optical sensor 113. Then, the CPU 400 instructs an image shift amount to the line data shift unit 402 which is a shift correction unit. The line data shift unit 402 converts the image data (also referred to as line data) input from the image data generation unit 401 into the entire image area within one page of the recording paper based on the image shift amount specified by the CPU 400. Shift processing is performed in units of 2400 dpi. The shift position corrects the image forming position. Note that the line data shift unit 402 may divide the image area in one page of the recording paper into a plurality of areas, and execute the shift process for each of the plurality of divided image areas.

(Synchronous signal generator)
The synchronization signal generation unit 406 generates a periodic signal for one line in the rotation direction of the photosensitive drum 102 (hereinafter, referred to as a Line synchronization signal) with a signal synchronized with the rotation speed of the photosensitive drum 102. The CPU 400 instructs the synchronizing signal generation unit 406 to set the pixel size (approximately 10 .5 μm) Indicate the time to move. For example, when printing at a speed of 200 mm / sec in the sub-scanning direction, the CPU 400 sets the cycle of the Line synchronization signal (the cycle of one line in the sub-scanning direction) to about 52.9 μs (≒ (25.4 mm / 2400 dots). ) / 200 mm) to the synchronization signal generation unit 406. When the image forming apparatus has a detection unit that detects the rotation speed of the photosensitive drum 102, the CPU 400 determines the photosensitive drum in the sub-scanning direction based on the detection result of the detection unit (generation cycle of a signal output by the encoder). The rotation speed of 102 is calculated, and the cycle of the Line synchronization signal is determined based on the calculation result. The detection unit here is, for example, an encoder installed on the rotating shaft of the photosensitive drum. On the other hand, if the image forming apparatus does not have a detection unit that detects the rotation speed of the photosensitive drum 102, the rotation speed of the photosensitive drum 102 is calculated based on the following information. That is, the CPU 400 determines the cycle of the Line synchronization signal based on information on the paper type such as the sheet basis weight (g / cm ² ) and the sheet size input by the user from the operation unit.

(Chip data converter)
The chip data conversion unit 403 reads line data from the line data shift unit 402 one line at a time in the sub-scanning direction of the photosensitive drum 102 in synchronization with the Line synchronization signal. Then, the chip data conversion unit 403 executes data processing for dividing the read line data into line data for each chip.

  FIG. 5A is a block diagram illustrating a configuration of the chip data conversion unit 403. In FIG. 5A, the Line synchronization signal output from the synchronization signal generation unit 406 is input to the counter 530. The counter 530 includes a frequency modulation circuit that modulates the input Line synchronization signal to generate a CLK signal having a higher frequency than the Line synchronization signal. The counter 530 may include an oscillator that generates a clock signal (CLK) having a higher frequency than the Line synchronization signal instead of the frequency modulation circuit. Hereinafter, a configuration in which the chip data conversion unit 403 reads line data from the line data shift unit 402 will be described as an example, but the embodiment is not limited thereto. That is, a Line synchronization signal is supplied to the line data shift unit 402, and a clock signal is generated internally by the line data shift unit 402. May be transmitted.

  When the line synchronization signal is input, the counter 530 resets the count value to 0, and then increments the counter value in synchronization with the number of pulses of the CLK (clock) signal (see FIG. 5B). The frequency of the CLK signal generated by the counter 530 includes the capacity (the number of bits) of pixel data that the chip data conversion unit 403 should read within one cycle of the Line synchronization signal, the data processing speed of the chip data conversion unit 403 described later, Is determined at the design stage based on For example, as described above, the surface light emitting element array element group 201 has 14,964 light emitting elements (1200 dpi conversion) that expose one line in the sub-scanning direction. On the other hand, the image data generation unit 401 performs dithering processing at a resolution of 2400 dpi. Therefore, the number of pixels of one line of image data output from the line data shift unit 402 in the sub-scanning direction is 29,928 pixels (= 14,964 × (2400 dpi / 1200 dpi)). The chip data conversion unit 403 reads out line data for one line in the sub-scanning direction during the Line synchronization signal and writes the line data to a line memory 500 described later, and writes image data to memories 501 to 529 described later. . Therefore, the counter 530 performs a count operation of twice (59, 856) the number of pixels (29, 928) included in one line of line data. The period when the count value of the counter 530 is from 1 to 29,928 is Tm1, and the period when the count value is from 29,929 to 59,856 is Tm2 (see FIG. 5B). READ control section 531 reads line data from line data shift section 402 according to the count value of counter 530. That is, the READ control unit 531 stores the line data (29,928 pixels) for one line in the main scanning direction in the line memory 500 during the period Tm1 in which the count value of the counter 530 is from 1 to 29,928. The WR control unit 532 divides the line data for one line in the sub-scanning direction stored in the line memory 500 into the memories 501 to 529 during the period Tm2 in which the count value of the counter 530 is 29,929 to 59,856. Write. The memories 501 to 529 are memories having a smaller storage capacity than the line memory 500, and store line data (divided line data) divided for each chip. The memories 501 to 529 are FIFO (First In First Out) memories provided corresponding to the surface emitting element array chips 1 to 29. That is, the memory 501 stores line data corresponding to the surface light emitting element array chip 1, the memory 502 stores line data corresponding to the surface light emitting element array chip 2,. Is stored.

  Subsequently, the writing of the line data read from the line data shift unit 402 to the memories 501 to 529 and the output of the image data written to the memories 501 to 529 executed by the chip data conversion unit 403 will be described. FIG. 5B is a time chart for explaining input / output timing of line data in the chip data conversion unit 403. In FIG. 5B, the Line synchronization signal indicates a pulse signal output from the synchronization signal generation unit 406. In the drawing, TL1, TL2,... TL10 indicate the cycle numbers of one line in the sub-scanning direction. One cycle of the Line synchronization signal is divided into a period Tm1 and a period Tm2 according to the counter value of the counter 530. The input data to the line memory 500 indicates image data from the line data shift unit 402, and is input from the line data shift unit 402 during a period Tm1 of the periods TL1, TL2,. The first line data in FIG. 5B indicates the line data of the first line in the sub-scanning direction (for one line in the main scanning direction). Similarly, the second line data,..., The tenth line data are the line data of the second line in the sub-scanning direction,. Minute).

  The “input data to the memory 501” shown in FIG. 5B is the line data corresponding to the surface light emitting element array chip 1 among the line data for one line in the main scanning direction stored in the line memory 500. The timing at which data is written to the memory 501 is shown. Similarly, the input data to the memory 502, the input data to the memory 503,... The input data to the memory 529 are line data corresponding to the surface light emitting element array chips 2, 3,. ,.., 529 are shown. Note that the first line data of the input data to the memory 501 is not line data of one line in the main scanning direction, but line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1. pointing. The same applies to the input data of the memories 502 to 529.

  The “output data from the memory 501” shown in FIG. 5B indicates the timing at which the line data written in the memory 501 is read out to be output to the surface emitting element array chip 1. Similarly, the “output data from the memory 502”,..., The “output data from the memory 529” shown in FIG. 5B are stored in the surface light emitting element array chips 2,. The timing for reading for output is shown. Note that the first line data of the output data from the memory 501 is not line data of one line in the main scanning direction but line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1. pointing. The same applies to output data from the memories 502 to 529.

  In the present embodiment, line data for one line in the main scanning direction is sequentially read from the line memory 500, and first, writing to the memory 501 for storing the line data of the surface emitting element array chip 1 is performed. Next, writing to the memory 502 for storing the image data of the surface light emitting element array chip 2 is performed, and thereafter, writing to the memory 529 for storing the image data of the surface light emitting element array chip 29 is sequentially performed. . In the chip data shift unit 404 at the subsequent stage of the chip data conversion unit 403, data shift processing in the sub-scanning direction is performed for each surface light emitting element array chip. Therefore, the memories 501 to 529 store line data for 10 lines in the sub-scanning direction.

  Further, the line data stored in the memories 501 to 529 includes, in addition to the line data for one chip corresponding to each surface light emitting element array chip, the pixel data obtained by copying the pixel data at the end of the adjacent surface light emitting element array chip. Data is also stored together. For example, the memory 502 stores the following pixel data at both ends of the line data corresponding to the surface-emitting element array chip 2. That is, the pixel data at the end of the surface light emitting element array chip 1 on the surface light emitting element array chip 2 side and the pixel data at the end of the surface light emitting element array chip 3 on the surface light emitting element array chip 2 side are added. Then, it is stored in the memory 502. As a result, the number of image data corresponding to the surface light emitting element array chip 2 is equal to the number of light emitting elements of the surface light emitting element array chip 2 (516), and the light emission at the end portions of the adjacent surface light emitting element array chips 1 and 3. 518 (= 516 + 1 + 1) is obtained by adding the image data of the elements one by one.

  In the memory 501, the end of the line data corresponding to the surface light emitting element array chip 1 is added with pixel data of the end of the surface light emitting element array chip 2 on the side of the surface light emitting element array chip 1 and stored. . In the memory 529, pixel data at the end of the surface light emitting element array chip 28 on the side of the surface light emitting element array chip 29 is added to the end of the line data corresponding to the surface light emitting element array chip 29 and stored. .

  As described above, in this embodiment, the pixel data at the end of the adjacent surface emitting element array chip is added to both ends of the line data of the corresponding surface emitting element array chip for each of the surface emitting element array chips. To 529. By the operation of the above-described chip data conversion unit 403, the line data for one line in the main scanning direction is stored in the memory 501 to 529 provided corresponding to the surface light emitting element array chips 1 to 29. Is stored together with the pixel data at the end of the. The pixel data at the end of the adjacent surface light emitting element array chip is used in a filter processing unit 408 described later.

(Chip data shift section)
The chip data shift unit 404, which is a shift correcting unit, performs the following control. That is, the relative read timing of line data from the memories 501 to 529 is controlled based on data (2400 dpi units) relating to the image shift amount in the sub-scanning direction for each surface light emitting element array chip instructed in advance by the CPU 400. Hereinafter, the image shift processing in the sub-scanning direction performed by the chip data shift unit 404 will be specifically described.

  In the longitudinal direction of the exposure head 106, it is desirable that the mounting positions of the even-numbered surface emitting element array chips do not shift. Similarly, in the longitudinal direction of the exposure head 106, it is desirable that the mounting positions of the odd-numbered surface emitting element array chips do not shift. The mounting positional relationship between the even-numbered surface light-emitting element array chips and the odd-numbered surface light-emitting element array chips in the sub-scanning direction is equivalent to 2400 dpi and is a predetermined number of pixels (for example, 8 pixels). preferable. Further, it is preferable that the arrangement positions of the light emitting element rows in the sub-scanning direction in each surface light emitting element array chip are constant without any individual difference. However, the mounting position of the surface light emitting element array chip and the arrangement position of the light emitting element array include errors, and these errors may cause deterioration of the image quality of the output image.

  The memory 420 (ROM) shown in FIG. 4 has a correction calculated from the relative positional relationship in the sub-scanning direction of each light emitting element array of the surface light emitting element array chips 1 to 29 mounted in a staggered manner on the drive substrate 202. Data is stored. For example, the memory 420 stores correction data based on the following measurement data. The light emitting element rows of the other surface light emitting element array chips 2 to 29 are shifted by a number of pixels corresponding to 2400 dpi in the sub scanning direction with respect to the light emitting element rows of the surface light emitting element array chip 1 serving as a reference in the sub scanning direction. Correction data indicating whether the device is mounted on the substrate 202 is stored. The measurement data is obtained by mounting the surface light emitting element array chips 2 to 29 on the drive substrate 202, lighting the light emitting elements of each surface light emitting element array chip by a measuring device, and measuring the light receiving result. The CPU 400 sets the correction data read from the memory 420 in the internal register of the chip data shift unit 404 in response to the power of the image forming apparatus being turned on. The chip data shift unit 404 shifts line data for forming the same line stored in the memories 501 to 529 based on the correction data set in the internal register. For example, when the light emitting element array of the surface light emitting element array chip 2 is mounted on the driving board with a displacement of 8 pixels in the sub-scanning direction corresponding to 2400 dpi with respect to the light emitting element array of the surface light emitting element array chip 1, The shift unit 404 performs the following processing. That is, the chip data shift unit 404 determines the output timing of the line data corresponding to the surface light emitting element array chip 2 on the same line as the output timing of the line data corresponding to the surface light emitting element array chip 1 to the drive substrate 202. Delays by eight pixels. Therefore, the chip data shift unit 404 shifts all line data corresponding to the surface light emitting element array chip 2 with respect to line data corresponding to the surface light emitting element array chip 1.

(Data transmission section)
The data transmission unit 405, which is a transmission unit, transmits the line data after performing the data processing on the series of line data described above to the drive substrate 202 of the exposure head 106. The transmission timing of the image data will be described with reference to FIG. As shown in FIG. 3A, among the surface light-emitting element array chips, the odd-numbered surface light-emitting element array chips 1, 3, 5,... 29 are arranged on the upstream side in the sub-scanning direction. Are disposed on the downstream side in the sub-scanning direction. In the time chart shown in FIG. 5B, writing of image data to the memories 501,... 529 corresponding to the odd-numbered surface light emitting element array chips 1,. It is performed in a period (TL1 in the figure). In the next line synchronization signal period (TL2 in the figure), the first line in the sub-scanning direction from the memories 501,... 529 corresponding to the odd-numbered surface emitting element array chips 1,. Is read. Similarly, in the period of the next Line synchronization signal, the data of the second line in the sub-scanning direction is read out from the memories 501, 529 corresponding to the odd-numbered surface light emitting element array chips 1,. Is performed. In the period of the tenth Line synchronization signal (TL10 in the figure), nine lines from the memories 501,... 529 corresponding to the odd-numbered surface emitting element array chips 1,. The reading of the eye data is performed. In addition, the memory 502 corresponding to the even-numbered surface light emitting element array chip 2 has a period (TL10 in the figure) from a period TL1 in which image data is written to the memory 502 to a period after 9 pulses of the Line synchronization signal. Image data is read from the memory 502.

  The data transmission unit 405 transmits the line data processed by the chip data shift unit 404 to the drive substrate 202. The data transmission unit 405 includes, instead of the oscillator, a frequency modulation circuit that modulates an input Line synchronization signal and generates a clock signal having a higher frequency than the Line synchronization signal. Further, the data transmission unit 405 may include an oscillator that generates a clock signal having a higher frequency than the Line synchronization signal instead of the frequency modulation circuit. In the present embodiment, the clock signal (CLK of FIG. 5B) is set so that the count value becomes 59,856 (twice the number of pixel data in one line) or more within one cycle of the Line synchronization signal. Determines the frequency. This allows input (write) of image data to the line memory 500 and output (write) of image data from the line memory 500 to the memories 501 to 529 within one cycle of the Line synchronization signal.

  On the other hand, the reading of data from the memories 501 to 529 is performed within one period of the line synchronization signal by the image of one line in the main scanning direction corresponding to each surface light emitting element array chip from the 29 memories 501 to 529. Output data in parallel. Therefore, the reading speed of the image data from the memories 501 to 529 may be lower than the writing speed to the memory. For example, in the present embodiment, it is assumed that the image data is read from the memories 501 to 529 at a cycle that is 58 times longer than the cycle of the clock signal at the time of writing the image data to the memories 501 to 529.

[Interface between control board and drive board]
FIG. 6 is a timing chart illustrating an input signal to the data transmission unit 405 of the control board 415 and an interface signal which is a serial signal transmitted and received between the control board 415 and the drive board 202. FIG. 6 illustrates that 518 pieces of image data stored in the memories 501 to 529 are input to the data transmission unit 405 during one cycle of a Line synchronization signal indicating a scanning period for one line in the main scanning direction. . In this embodiment, the interface signal is one bit of image data 2400 dpi (a binary value of 0 and 1 can be displayed) and transfers the image data of the surface emitting element array chip for 29 chips. Further, in order to realize space saving and cost reduction, it is necessary to reduce the number of wires between the control board 415 and the drive board 202 for transmitting interface signals as much as possible. Therefore, the data transmission unit 405 performs parallel-to-serial conversion of the image data of 29 chips, and superimposes and transmits the image data on six signal lines (communication paths). Here, the six signal lines are associated with the surface light emitting element array chips 1 to 5, 6 to 10, 11 to 15, 16 to 20, 21 to 25, and 26 to 29 so as to transmit image data. This is a signal line. In FIG. 6, the output signal from the data transmitting unit 405 transmitted to the driving unit 303a of the driving substrate 202 is the image data transmitted to the surface light emitting element array chips 1 to 5, 6 to 10, 11 to 15 in order from the top. Is shown. Similarly, the output signal from the data transmitting unit 405 transmitted to the driving unit 303b of the driving substrate 202 is the image signal transmitted to the surface light emitting element array chips 16 to 20, 21 to 25, and 26 to 29 in order from the top. Show. The data receiving unit 407 of the driving unit 303a of the driving substrate 202 on the side of the exposure head 106 performs serial-parallel conversion of the image data received via the six signal lines to correspond to each surface light emitting element array chip. The configuration is such that the original image data is restored.

  The signal data name corresponding to each chip in FIG. 6 is represented by M_N. M indicates the chip number (1 to 29) of the surface light emitting element array chip, and N indicates the number of image data (1 to 518) in one chip of the surface light emitting element array chip. Note that the signal data name “emp” indicates that the corresponding surface light emitting element array chip is not used (not mounted). The data transmission unit 405 adds the image data of the light emitting element at the end of the adjacent surface light emitting element array chip to the number 516 of surface light emitting elements in one chip by the processing in the chip data conversion unit 403 described above 518. Pixel data is transmitted as one chip. The image data is transmitted in synchronization with the Line synchronization signal generated by the synchronization signal generation unit 406, in order from the first pixel of each surface light emitting element array. The data transmission unit 405 has a parallel-serial conversion circuit for distributing image data corresponding to 29 surface light emitting element array chips to six signal lines. The parallel-serial conversion circuit converts the image data (parallel data) of the five surface emitting element array chips into a serial signal transmitted through the same signal line. The parallel-serial conversion circuit enables communication of image data between the data transmission unit 405 and the data reception unit 407 by using six signal lines. By performing parallel-serial conversion of image data and performing serial communication, the number of wires between the data transmission unit 405 and the data reception unit 407 can be reduced, while the transfer speed of an interface signal for transmitting image data is reduced. Speed up.

  In this embodiment, the number of gradations of each pixel is 1 bit, the line period TL is 100 μs, the number of surface light emitting elements of the surface light emitting element array chips 1 to 29 is 14,964 (image width is about 316 mm at 1200 dpi), and the number of chips is Is 29 chips. When the frequency of the input signal to the data transmission unit 405 is calculated using (Equation 1) described above, the calculated frequency is about 5 MHz. Further, assuming that the number of wiring lines for transmitting image data between the data transmitting unit 405 and the data receiving unit 407 is six, the frequency of the interface signal to the data transmitting unit 405 is about 25 MHz from (Equation 1). When the number of bits indicating the number of gradations of each pixel is increased in order to improve the gradation, the frequency of the output signal becomes the frequency when the number of gradations is 1 bit, and the number of bits indicating the number of gradations. Multiplied by, and the speed is further increased. Therefore, in the present embodiment, in order to improve the gradation, the process of increasing the number of bits of the image data is performed after the data receiving unit 407, that is, inside the driving substrate 202 of the exposure head 106. Note that the frequency of the interface signal to the data transmission unit 405 in this embodiment is about 25 MHz, which is not a frequency that requires the above-described components for radiation noise suppression. Therefore, there is no increase in cost due to performing parallel-serial conversion in order to reduce the number of wires for transmitting and receiving data between the control board 415 and the drive board 202.

[Configuration of exposure head drive substrate]
Next, processing inside the driving unit 303a mounted on the driving substrate 202 of the exposure head 106 will be described. The drive unit 303a includes functional blocks of a data reception unit 407, a filter processing unit 408, an LUT 410, a PWM signal generation unit 411, a timing control unit 412, a control signal generation unit 413, and a drive voltage generation unit 414. Hereinafter, processing of each functional block will be described in the order in which the image data is processed in the driving unit 303a.

(Data receiving unit)
The data receiving unit 407 of the driving unit 303a as a receiving unit is a serial-parallel conversion circuit that converts image data (serial data) of five surface light emitting element array chips into parallel signals for each of the five surface light emitting element array chips. have. Data receiving section 407 receives an interface signal composed of a serial signal transmitted from data transmitting section 405. Then, the data receiving unit 407 performs parallel conversion of the received interface signal (serial data) into an image data sequence for each of the surface light emitting element array chips (1 to 15) by a serial-parallel conversion circuit. The processing blocks subsequent to the driving unit 303a are configured to process image data for 15 chips of the surface light emitting element array chips 1 to 15 in parallel.

(Filter processing section)
The filter processing unit 408, which is a conversion unit, performs interpolation processing by filter processing in the main scanning direction on image data for each surface light emitting element array chip, and converts the resolution in the main scanning direction from 2400 dpi to 1200 dpi. FIG. 7 is a diagram illustrating a state of the filter processing in the filter processing unit 408. In FIG. 7, D1 to D9 indicate image data (input data of 2400 dpi) of the surface light emitting element array chip. Here, the image data D1 to D8 are the image data of the corresponding surface light emitting element array chip, and the image data D9 is the pixel data at the end of the adjacent surface light emitting element array chip. D1 ′ to D4 ′ indicate image data (1200 dpi output data) after the filter processing by the filter processing unit 408. The resolution (1200 dpi) of the output data is one half of the resolution (2400 dpi) of the input data, and the calculation formula of the image data of each pixel is represented by the following (Formula 1).
Dn ′ = D (2 × n−1) × K2 + D (2 × n) × K1 + D (2 × n + 1) × K2 (Equation 2)
Here, n corresponds to the number 516 of the surface light emitting elements inside each surface light emitting element array chip, and based on the lighting order of the light emitting elements, the calculation of the image data in each light emitting element sequentially in the order of n = 1 to 516. Is performed. K1 which is the first coefficient is a weight coefficient for the output data and the input data at the same coordinate position in the main scanning direction. K2, which is the second coefficient, is a weighting coefficient for input data whose coordinates are shifted by a half pixel in the main scanning direction with respect to output data. In the present embodiment, the interpolation calculation (filter processing) is performed with the values of K1 = 0.5 and K2 = 0.25, but a different weighting coefficient from that of the present embodiment may be used. In this embodiment, by setting the weight coefficient K2 to a value larger than 0, information of image data generated at a resolution (2400 dpi) higher than the resolution (1200 dpi) of the output data can be reflected on the output data. More specifically, the processing from the image data generation unit 401 of the control board 415 to the data reception unit 407 of the exposure head 106 is performed by moving the image position in the main scanning direction at 2400 dpi. Convert the resolution to 1200 dpi. This makes it possible to generate a 1200 dpi image while maintaining the image movement accuracy in units of 2400 dpi.

  FIG. 8 is a diagram illustrating a shift of image data before and after filter processing and a change in image data due to filter processing. FIG. 8A is a diagram illustrating 2400 dpi image data after the surface light emitting element array chips 1, 2, and 3 have been subjected to dithering processing by the image data generation unit 401 of the control board 415. In FIG. 8A, the image data is represented by two gradations of black and white. The vertical axis in FIG. 8A indicates the sub-scanning direction, and m to m + 3 indicate lines in the sub-scanning direction. The horizontal axis in FIG. 8A indicates the main scanning direction, and 1, 2 to n−1, and n indicate the arrangement order of the light emitting elements in the surface light emitting element array chip at 2400 dpi. FIG. 8B is a diagram showing image data after the image data shown in FIG. 8A has been shifted in units of 2400 dpi by the line data shift unit 402 and the chip data shift unit 404 of the control board 415. It is. FIG. 8B shows an example in which the image data shown in FIG. 8A is shifted by one pixel to the left in the main scanning direction to simplify the description, and an image corresponding to the surface light emitting element array chip 1 is obtained. An example is shown in which data is shifted by one pixel downward in the sub-scanning direction in array chip units.

  FIG. 8C shows the image data in the main scanning direction by the filter processing unit 408 of the driving unit 303a of the driving substrate 202 with respect to the image shifted in the main scanning direction and the sub-scanning direction in FIG. The image data after resolution conversion from 2400 dpi to 1200 dpi is shown. .., N / 2-1, n in the horizontal axis direction indicate the arrangement order of the light emitting elements of the surface light emitting element array chip after resolution conversion to 1200 dpi. The size in the main scanning direction of each pixel (1200 dpi) after resolution conversion in FIG. 8C is twice as large as one pixel (2400 dpi) shown in FIG. 8B. Further, the position of each pixel is a position shifted to the right by a half pixel in FIG. 8B (a position advanced by a half pixel in the main scanning direction), but before and after resolution conversion, the center of gravity of the image is does not change. For example, the size and position of the pixel 1 ′ of the surface emitting element array chip 1 after the resolution conversion in FIG. 8C are the same as the pixel position 1 of the surface light emitting element array chip 1 before the resolution conversion in FIG. The size and position are obtained by adding half of the pixel, the pixel at pixel position 2, and half of the pixel at pixel position 3. Similarly, the size and the position of the pixel 2 ′ of the surface emitting element array chip 1 after the resolution conversion in FIG. 8C are the same as the pixel position 3 of the surface light emitting element array chip 1 before the resolution conversion in FIG. Of the pixel at the pixel position 4, and the half of the pixel at the pixel position 5 are added in size and position.

  Further, the size and position of the pixel (n / 2-1) of the surface emitting element array chip 1 after resolution conversion in FIG. 8C are as follows. That is, half of the pixel at the pixel position (n-3), the pixel at the pixel position (n-2), and the pixel position (n-1) of the surface light emitting element array chip 1 before the resolution conversion in FIG. The size and the position are obtained by adding half of the pixel of. Similarly, the size and the position of the pixel (n / 2) of the surface emitting element array chip 1 after the resolution conversion in FIG. 8C are as follows. That is, half of the pixel at the pixel position (n−1) of the surface light emitting element array chip 1 before resolution conversion in FIG. 8B, the pixel at the pixel position (n), and the adjacent surface light emitting element array chip 2 The size and position are obtained by adding half of the pixel at pixel position 1. The number in each pixel in FIG. 8C indicates the density value of each pixel. In this embodiment, it is assumed that after the resolution conversion, processing is performed with the number of gradations of 8 bits. In the drawing, assuming that the density value of the black portion is 100% and the density value of the white portion (including the frame portion not shown in the drawing) is 0%, the density value of each pixel is calculated from the above (Equation 1). Then, the density value is expressed by five values of 0%, 25%, 50%, 75%, and 100%. In order to express the density value of one pixel with five values, the gradation needs three bits. By processing the number of gradations of one pixel after resolution conversion with 3 bits or more, smooth processing without density steps can be performed. In the resolution conversion process, 1-bit data of 2400 dpi resolution and data of 2 pixels in the main scanning direction (total of 2 bits) transmitted from the control board 415 are converted into 3-bit data of 1200 dpi resolution. Therefore, the bus width (the number of bits) of the image data after the filter processing unit 408 becomes 1.5 times (= 3 bits / 2 bits).

  For example, the density value of the pixel 1 ′ of the surface light emitting element array chip 1 in the (m + 3) row in FIG. 8C is calculated as follows by using (Equation 1) and the pixel density in FIG. Is calculated. That is, the density value of the pixel 1 '= the density of the pixel 1 (1) × K2 (0.25) + the density of the pixel 2 (1) × K1 (0.5) + the density of the pixel 3 (0) × K2 (0 .25) = 0.75 (75%). Similarly, the density value of the pixel 2 ′ of the surface emitting element array chip 1 in the (m + 3) row in FIG. 8C is calculated as follows using the expression 1 and the pixel density in FIG. become. That is, the density value of the pixel 2 ′ = the density (0) of the pixel 3 × K2 (0.25) + the density (0) of the pixel 4 × K1 (0.5) + the density of the pixel 5 (0) × K2 (0 .25) = 0 (0%). Further, the density value of the pixel (n / 2) of the surface emitting element array chip 1 in the (m + 3) row in FIG. 8C is calculated by using (Equation 1) and the pixel density in FIG. become that way. That is, the density value of the pixel (n / 2) = the density (1) of the pixel (n-1) × K1 (0.25) + the density of the pixel (n) (1) × K1 (0.5) + surface light emission The density (0) × K2 (0.25) of the pixel 1 of the element array chip 2 is 0.751 (75%).

  In addition, in performing the filtering process, when processing the pixel at the end of the surface emitting element array chip, if there is no pixel data of the adjacent surface emitting element array chip, an image is lost and an image defect occurs. Therefore, as described above, the chip data conversion unit 403 of the control board 415 adds the pixel data on the end side of the adjacent surface light emitting element array chip and arranges the image data so that the image is not lost. Filter processing can be performed.

(LUT)
The LUT 410, which is a light amount correction unit, converts a data value (density data value) for each pixel into light amount value data using a look-up table (Look Up Table). As described above, the data after the resolution conversion processing by the filter processing unit 408 is composed of 3 bits per pixel which performs switching at 0%, 25%, 50%, 75%, and 100% light intensity within one pixel. Image data (density data). Therefore, the LUT 410 receives image data of one pixel having three bits. The LUT 410 performs data conversion on the 3-bit image data to adjust the light emission time. The pulse response characteristics of the surface emitting element may vary depending on driving conditions, and the resulting variation may cause an image defect. Therefore, in the processing of the LUT 410, when performing pulse width control in one pixel with multiple values, the image data value (density data) is set so that the integrated light amount (exposure condition) when the surface light emitting element emits light becomes a predetermined value. Value). For example, when the pulse response of the surface emitting element is slow and the integrated light amount is smaller than the target value, the LUT 410 performs conversion so as to increase the density data value, and adjusts the target light amount (light emission amount).

  Further, in the present embodiment, the value of the conversion table set in the lookup table includes the set value of the driving voltage of the surface light emitting element (light emitting thyristor) and the temperature detection result of the thermistor 421 installed near the surface light emitting element. The switching is performed based on the following. Switching of the values in the conversion table is performed at a timing before image formation is started. Here, the characteristics of the driving voltage and the temperature of the light emitting thyristor will be described. Generally, a light-emitting thyristor has a delay time from when a voltage is applied between an anode terminal and a cathode terminal to when the thyristor is turned on and light emission is started. It is known that the delay time varies depending on the drive voltage applied between the anode terminal and the cathode terminal. Generally, in the image forming apparatus, in order to keep the density of an image to be formed constant with respect to deterioration of the photosensitive drum 102 and toner over time, a light amount control for switching an exposure amount is performed. In this embodiment, since the control voltage is switched to control the light amount, the switching of the control voltage causes the above-described fluctuation of the delay time.

  FIG. 9 is a diagram for explaining the response characteristics of the light emitting thyristor in the present embodiment. The vertical axis indicates the integrated light amount, and the horizontal axis indicates a pulse width signal (hereinafter, referred to as a PWM signal) generated by a PWM signal generation unit 411 described later. ) Indicates the pulse width (input PWM). The graph in FIG. 9 shows the pulse response characteristics of the light emitting thyristor with respect to the input pulse when the control voltages 1 and 2 are the control values of the drive voltage. In the case of the control voltage 1 for controlling the output to a high light quantity, the threshold (threshold 1) of the minimum pulse width of the input pulse at which the light emitting thyristor starts emitting light is low. Therefore, the response is quick to an input pulse having a narrower pulse width. On the other hand, in the case of the control voltage 2 for controlling the output to a relatively low light quantity, the threshold (threshold 2) of the minimum pulse width at which the light emitting thyristor starts emitting light is higher (increased) than the threshold 1. ). Therefore, the response to the input pulse is slower than the case of the control voltage 1. Therefore, in order to set the minimum pulse width to a predetermined exposure amount, it is necessary to adjust the light emission time of the minimum pulse width with respect to the control voltage value. In the present embodiment, the CPU 400 sets the control voltage in the drive voltage generation unit 414 and notifies the LUT 410 of the control voltage.

  On the other hand, the light-emitting thyristor has a characteristic that the exposure amount decreases due to an increase in the temperature of the element. FIG. 10 is a diagram for explaining the difference in the exposure amount with respect to the input pulse when the light emitting thyristor is at normal temperature and when the temperature is raised. The vertical axis indicates the integrated light amount, and the horizontal axis indicates the pulse width (input PWM) of the PWM signal. . As shown in FIG. 10, the minimum pulse width (threshold 1) of the input PWM pulse for turning on the light-emitting thyristor does not change at the time of normal temperature or at the time of temperature rise. However, the exposure amount of the light-emitting thyristor when the input PWM pulse has the maximum pulse width in one pixel greatly decreases at the time of temperature rise as compared with the case of normal temperature. In the case of having such temperature characteristics, if there is a self-heating inside the image forming apparatus or a change in the surrounding temperature environment, the exposure amount of the light emitting thyristor fluctuates, and as a result, the density fluctuates. The LUT 410 determines the adjustment value of the minimum pulse width according to the control voltage and the maximum value according to the temperature detection result of the thermistor 421 in response to the fluctuation of the exposure amount due to the control voltage and the temperature change, which are the exposure control information described above. Determine the pulse width adjustment value. In the LUT 410, the data value of the conversion table of the LUT 410 is determined based on the data obtained by linearly interpolating between the minimum pulse width and the maximum pulse width.

  FIG. 11 is a diagram illustrating the relationship between input data and output data converted by a lookup table. The horizontal axis represents input data (density value) represented by five values of 0%, 25%, 50%, 75%, and 100%, and the vertical axis represents light intensity in 8-bit 256 levels. The output data (pulse width of the PWM signal) is shown. As shown in FIG. 9, in the case of the control voltage 1, since the light emission of the light emitting thyristor starts from the pulse width of the threshold value 1, the data obtained by adding a predetermined offset to the input data with respect to the minimum pulse width. Output. On the other hand, the maximum pulse width at normal temperature is set to be narrow (small) so that a predetermined light amount is output with respect to the maximum value of the internal temperature of the image forming apparatus. The pulse width is set to be large (large). In order to finely adjust the exposure amount based on the pulse width of the PWM signal described above, the output data width (the number of bits) of the LUT 410 is adjusted with an adjustment accuracy of 8 bits (256 steps). In the present embodiment, a method in which the surface light-emitting element (light-emitting thyristor) is driven by a voltage has been described as an example. What is necessary is just to determine the conversion table of the LUT410.

  FIG. 12 shows a table showing an example of the look-up table. The LUT 410 converts pixel data equivalent to 1200 dpi into a PWM signal using any of the conversion tables shown in FIGS. 12 (a) to 12 (c). I do. The look-up table shown in FIG. 12 stores the pixel density values (five values of 0%, 25%, 50%, 75%, and 100%) which are pixel data equivalent to 1200 dpi converted by the filter processing unit 408. It is a conversion table to be converted in association with 8-bit PWM data. The binary numbers “000”, “001”, “010”, “011”, and “100” in the columns on the left side of the conversion tables shown in FIGS. , 25%, 50%, 75%, and 100% corresponding to 1200 dpi. The PWM data in the conversion tables shown in FIGS. 12A to 12C indicate 8-bit data corresponding to pixel density values. “1” of the PWM data is LED on data (light emission data), and “0” is off data (non-light emission data). The PWM data corresponds to ΦW1 to ΦW4 described later. For example, the PWM data corresponding to “000” corresponding to a pixel density value of 0% is “00000000” in any of the conversion tables in FIGS. The PWM data corresponding to “100” corresponding to the pixel density value of 100% is “11111111” in any of the conversion tables in FIGS. 12A to 12C. On the other hand, the PWM data corresponding to “001”, “010”, and “011” corresponding to the pixel density values of 25%, 50%, and 75% have different 8-bit data in FIGS. Data. For example, the PWM data corresponding to “010” having a pixel density value of 50% is “000011111” in FIG. 12A, “11110000” in FIG. 12B, and “11110000” in FIG. 12C. 00111100 ".

(PWM signal generator, timing controller, control signal generator, drive voltage generator)
Subsequently, the PWM signal generation unit 411 generates a pulse width signal (hereinafter, referred to as a PWM signal) corresponding to a light emission time during which the surface light emitting element array chip emits light within one pixel section according to the data value of each pixel. The timing of outputting the PWM signal is controlled by the timing control unit 412. The timing control unit 412 generates a synchronization signal corresponding to the pixel section of each pixel from the Line synchronization signal generated by the synchronization signal generation unit 406 of the control board 415, and outputs the synchronization signal to the PWM signal generation unit 411. The drive voltage generator 414 generates a drive voltage for driving the surface light emitting element array chip in synchronization with the PWM signal. Note that the drive voltage generation unit 414 has a configuration in which the CPU 400 can adjust the voltage level of the output signal around 5 V so that a predetermined light amount is obtained. In this embodiment, each surface light emitting element array chip has a configuration in which four light emitting elements can be simultaneously driven independently. The drive voltage generation unit 414 supplies a drive signal to four lines for each surface light emitting element array chip, and a drive signal to one line (15 chips) × 4 = 60 lines in a staggered configuration for the entire exposure head 106. The drive signals supplied to each surface light emitting element array chip are ΦW1 to ΦW4 (see FIG. 15). ΦW1 to ΦW4 are pulse signals for controlling the light emission time in each pixel, and the pulse width is configured by adjusting the data value in the LUT 410 described above (details will be described later). On the other hand, the surface light emitting element chip array is sequentially driven by the operation of a shift thyristor (see FIG. 15) described later. The control signal generator 413 generates control signals Φs, Φ1, and Φ2 for transferring the shift thyristor for each pixel from the synchronization signal corresponding to the pixel section generated by the timing controller 412 (see FIG. 15).

[Description of SLED circuit]
FIG. 13 is an equivalent circuit extracted from a part of a self-scanning light-emitting element (Self-Scanning LED: SLED) chip array of the present embodiment. In FIG. 13, Ra and Rg are an anode resistance and a gate resistance, respectively, Tn is a shift thyristor, Dn is a transfer diode, and Ln is a light emitting thyristor. Gn represents the corresponding shift thyristor Tn and the common gate of the light emitting thyristor Ln connected to the shift thyristor Tn. Here, n is an integer of 2 or more. Φ1 is a transfer line of the odd-numbered shift thyristor T, and Φ2 is a transfer line of the even-numbered shift thyristor T. ΦW1 to ΦW4 are lighting signal lines of the light emitting thyristor L, and are connected to the resistors RW1 to RW4, respectively. VGK is a gate line, and Φs is a start pulse line. As shown in FIG. 13, four light-emitting thyristors L4n-3 to L4n are connected to one shift thyristor Tn, and four light-emitting thyristors L4n-3 to L4n can be turned on at the same time. It has become.

[Operation of SLED circuit]
Next, the operation of the SLED circuit shown in FIG. 13 will be described. In the circuit diagram of FIG. 13, it is assumed that 5 V is applied to the gate line VGK, and the voltages input to the transfer lines Φ1, Φ2 and the lighting signal lines ΦW1 to ΦW4 are also 5V. In FIG. 13, when the shift thyristor Tn is in the ON state, the potential of the common gate Gn of the shift thyristor Tn and the light emitting thyristor Ln connected to the shift thyristor Tn is reduced to about 0.2V. Since the common gate Gn of the light emitting thyristor Ln and the common gate Gn + 1 of the light emitting thyristor Ln + 1 are connected by the coupling diode Dn, a potential difference substantially equal to the diffusion potential of the coupling diode Dn occurs. In this embodiment, since the diffusion potential of the coupling diode Dn is about 1.5 V, the potential of the common gate Gn + 1 of the light-emitting thyristor Ln + 1 becomes 0.2 V of the potential of the common gate Gn of the light-emitting thyristor Ln and 1 It becomes 1.7 V (= 0.2 V + 1.5 V) obtained by adding 0.5 V. Hereinafter, similarly, the potential of the common gate Gn + 2 of the light-emitting thyristor Ln + 2 is 3.2 V (= 1.7 V + 1.5 V), and the potential of the common gate Gn + 3 (not shown) of the light-emitting thyristor Ln + 3 (not shown) is 4.7 V (=). 3.2V + 1.5V). However, the potential after the common gate Gn + 4 of the light emitting thyristor Ln + 4 is 5 V since the voltage of the gate line VGK is 5 V and does not become higher than this. Further, regarding the potential of the common gate Gn-1 before the common gate Gn of the light emitting thyristor Ln (left side of the common gate Gn in FIG. 13), since the coupling diode Dn-1 is in the reverse bias state, the gate line The voltage of VGK is applied as it is, and becomes 5V.

  FIG. 14A is a diagram showing the distribution of the gate potential of the common gate Gn of each light-emitting thyristor Ln when the above-mentioned shift thyristor Tn is in the ON state, and the common gates Gn-1, Gn, Gn + 1. , The common gate of the light emitting thyristor L in FIG. The vertical axis in FIG. 14A indicates the gate potential. The voltage required to turn on each shift thyristor Tn (hereinafter referred to as a threshold voltage) is obtained by adding a diffusion potential (1.5 V) to the gate potential of the common gate Gn of each light emitting thyristor Ln; The potentials are almost the same. When the shift thyristor Tn is on, the shift thyristor Tn + 2 has the lowest gate potential of the common gate among the shift thyristors connected to the transfer line Φ2 of the same shift thyristor Tn. The potential of the common gate Gn + 2 of the light-emitting thyristor Ln + 2 connected to the shift thyristor Tn + 2 is 3.2 V (= 1.7 V + 1.5 V) (FIG. 14A) as described above. Therefore, the threshold voltage of shift thyristor Tn + 2 is 4.7 V (= 3.2 V + 1.5 V). However, since the shift thyristor Tn is on, the potential of the transfer line Φ2 is pulled to about 1.5 V (diffusion potential), and is lower than the threshold voltage of the shift thyristor Tn + 2, so that the shift thyristor Tn + 2 is on. Can not do it. The other shift thyristors connected to the same transfer line Φ2 cannot be turned on similarly because the threshold voltage is higher than the shift thyristor Tn + 2, and only the shift thyristor Tn can be kept on.

  Further, regarding the shift thyristor connected to the transfer line Φ1, the threshold voltage of the shift thyristor Tn + 1 whose threshold voltage is the lowest is 3.2V (= 1.7V + 1.5V). The shift thyristor Tn + 3 (not shown in FIG. 13) having the next lowest threshold voltage is 6.2 V (= 4.7 V + 1.5 V). In this state, when 5 V is input to the transfer line Φ1, only the shift thyristor Tn + 1 can transition to the ON state. In this state, shift thyristor Tn and shift thyristor Tn + 1 are simultaneously turned on. Therefore, the gate potentials of the shift thyristors Tn + 1 to Tn + 3 provided on the right side in the circuit diagram of FIG. 13 are reduced by the diffusion potential (1.5 V) from the shift thyristor Tn + 1. However, since the voltage of the gate line VGK is 5V and the voltage of the common gate of the light emitting thyristor L is limited by the voltage of the gate line VGK, the gate potential on the right side of the shift thyristor Tn + 5 is 5V. FIG. 14B is a diagram showing the gate voltage distribution of each of the common gates Gn-1 to Gn + 4 at this time, and the vertical axis indicates the gate potential. In this state, when the potential of the transfer line Φ2 is reduced to 0 V, the shift thyristor Tn is turned off, and the potential of the common gate Gn of the shift thyristor Tn rises to the VGK potential. FIG. 14C is a diagram showing the gate voltage distribution at this time, and the vertical axis shows the gate potential. Thus, the transfer of the ON state from the shift thyristor Tn to the shift thyristor Tn + 1 is completed.

[Light emitting operation of light emitting thyristor]
Next, the light emitting operation of the light emitting thyristor will be described. When only the shift thyristor Tn is on, the gates of the four light-emitting thyristors L4n-3 to L4n are commonly connected to a common gate Gn of the shift thyristor Tn. Therefore, the gate potential of the light emitting thyristors L4n-3 to L4n is 0.2 V, which is the same as the common gate Gn. Therefore, the threshold value of each light emitting thyristor is 1.7 V (= 0.2 V + 1.5 V), and if a voltage of 1.7 V or more is input from the lighting signal lines ΦW 1 to ΦW 4 of the light emitting thyristor, L4n-3 to L4n can be turned on. Therefore, when the shift thyristor Tn is on, by inputting a lighting signal to the lighting signal lines ΦW1 to ΦW4, the four light emitting thyristors L4n-3 to L4n can selectively emit light. It is possible. At this time, the potential of the common gate Gn + 1 of the shift thyristor Tn + 1 adjacent to the shift thyristor Tn is 1.7 V, and the threshold voltage of the light emitting thyristors L4n + 1 to 4n + 4 connected to the common gate Gn + 1 is 3.2 V (= (1.7V + 1.5V). Since the lighting signal input from the lighting signal lines ΦW1 to ΦW4 is 5 V, the light emitting thyristors L4n + 1 to L4n + 4 are also likely to light in the same lighting pattern as the lighting pattern of the light emitting thyristors L4n-3 to 4n. However, since the threshold voltages of the light emitting thyristors L4n-3 to L4n are lower, when a lighting signal is input from the lighting signal lines ΦW1 to ΦW4, the light emitting thyristors L4n + 1 to L4n + 4 are turned on earlier. Once the light-emitting thyristors L4n-3 to L4n are turned on, the connected lighting signal lines ΦW1 to ΦW4 are lowered to about 1.5 V (diffusion potential). Therefore, since the potentials of the lighting signal lines ΦW1 to ΦW4 become lower than the threshold voltages of the light emitting thyristors L4n + 1 to L4n + 4, the light emitting thyristors L4n + 1 to L4n + 4 cannot be turned on. In this way, by connecting a plurality of light emitting thyristors L to one shift thyristor T, a plurality of light emitting thyristors L can be simultaneously turned on.

  FIG. 15 is a timing chart of the driving signals of the SLED circuit shown in FIG. In FIG. 15, the voltage waveforms of the drive signals of the gate line VGK, the start pulse line Φs, the transfer lines Φ1 and Φ2 of the odd-numbered and even-numbered shift thyristors, and the lighting signal lines ΦW1 to ΦW4 of the light-emitting thyristor are shown in order from the top. I have. Each drive signal has an on-state voltage of 5 V and an off-state voltage of 0 V. The horizontal axis in FIG. 15 indicates time. Tc indicates the period of the clock signal Φ1, and Tc / 2 indicates a half (= １ ／) of the period Tc.

  5 V is always supplied to the gate line VGK. A clock signal Φ1 for the odd-numbered shift thyristor and a clock signal Φ2 for the even-numbered shift thyristor are input at the same cycle Tc, and 5 V is supplied to the signal Φs of the start pulse line. Shortly before the clock signal φ1 for the odd-numbered shift thyristor first becomes 5V, the signal φs of the start pulse line is dropped to 0V in order to give a potential difference to the gate line VGK. As a result, the gate potential of the first shift thyristor Tn-1 is pulled down from 5 V to 1.7 V, the threshold voltage becomes 3.2 V, and the shift thyristor Tn-1 is turned on by a signal from the transfer line Φ1. 5 V is applied to the transfer line Φ1, and a little after the first shift thyristor Tn-1 is turned on, 5 V is supplied to the start pulse line Φs, and thereafter, 5 V is supplied to the start pulse line Φs. to continue.

  The transfer line Φ1 and the transfer line Φ2 have a time Tov when their ON states (here, 5V) overlap each other, and are configured to have a substantially complementary relationship. The light emitting thyristor lighting signal lines ΦW1 to ΦW4 are transmitted at a half cycle of the cycle of the transfer lines Φ1 and Φ2. When the corresponding shift thyristor is in the ON state, it is turned on when 5V is applied. For example, in a period a, all four light-emitting thyristors connected to the same shift thyristor are in a lighting state, and in a period b, three light-emitting thyristors are simultaneously turned on. In the period c, all the light emitting thyristors are turned off, and in the period d, two light emitting thyristors are simultaneously turned on. In the period e, only one light-emitting thyristor is turned on.

  In the present embodiment, the number of light-emitting thyristors connected to one shift thyristor is four, but is not limited to this, and may be smaller or larger than four depending on the application. In the above-described circuit, a circuit in which the cathode of each thyristor is common has been described. However, an anode common circuit can be applied by appropriately inverting the polarity.

[Structure of surface-emitting thyristor]
FIG. 16 is a schematic diagram of the surface-emitting thyristor unit of the present embodiment. FIG. 16A is a plan view (schematic diagram) of a light emitting element array in which a plurality of light emitting elements formed in a mesa (trapezoidal) structure 922 are arranged. FIG. 16B is a schematic cross-sectional view when the light emitting element formed in the mesa structure 922 is cut along the line BB shown in FIG. The mesa structures 922 on which the light emitting elements are formed are arranged at a predetermined pitch (interval between the light emitting elements) (for example, approximately 21.16 μm in the case of a resolution of 1200 dpi). 924 separate from each other.

  In FIG. 16B, reference numeral 900 denotes a first conductivity type compound semiconductor substrate, 902 denotes a buffer layer of the same first conductivity type as the substrate 900, and 904 denotes a stack of two types of semiconductor layers of the first conductivity type. It is a distributed Bragg reflection (DBR) layer. 906 is a first first conductivity type semiconductor layer, 908 is a first second conductivity type semiconductor layer different from the first conductivity type, 910 is a second first conductivity type semiconductor layer, and 912 is A second second conductivity type semiconductor layer. As shown in FIG. 16B, a pnpn-type (or npnp-type) thyristor structure is formed by alternately stacking semiconductors having different conductivity types of the semiconductor layers 906, 908, 910, and 912. In this embodiment, an n-type GaAs substrate is used for the substrate 900, n-type GaAs or n-type AlGaAs layer is used for the buffer layer 902, and n-type high Al composition AlGaAs and low Al composition are used for the DBR layer 904. AlGaAs laminated structure is used. The first first conductivity type semiconductor layer 906 on the DBR layer is made of n-type AlGaAs, and the first second conductivity type semiconductor layer 908 is made of p-type AlGaAs. Further, n-type AlGaAs is used for the second semiconductor layer 910 of the first conductivity type, and p-type AlGaAs is used for the semiconductor layer 912 of the second second conductivity type.

  Further, in the mesa structure type surface emitting element, the light emission efficiency is improved by using a current confinement mechanism and preventing a current from flowing to the side surface of the mesa structure 922. Here, the current confinement mechanism in the present embodiment will be described. As shown in FIG. 16B, in this embodiment, a p-type GaP layer 914 is formed on a p-type AlGaAs which is a second second-conductivity-type semiconductor layer 912, and an n-type GaP layer 914 is further formed thereon. An ITO layer 918 that is a transparent conductor of a mold is formed. The p-type GaP layer 914 is formed to have a sufficiently high impurity concentration at a portion in contact with the ITO layer 918 which is a transparent conductor. When a forward bias is applied to the light-emitting thyristor (for example, when the back electrode 926 is grounded and a positive voltage is applied to the front electrode 920), the p-type GaP layer 914 is in contact with the transparent conductor ITO layer 918. Is formed to have a sufficiently high impurity concentration, thereby forming a tunnel junction. As a result, current flows. With such a structure, the p-type GaP layer 914 concentrates a current at a portion in contact with the ITO layer 918 which is an n-type transparent conductor, thereby forming a current confinement mechanism. In this embodiment, an interlayer insulating layer 916 is provided between the ITO layer 918 and the p-type AlGaAs layer 912. However, the additional diode formed by the n-type ITO layer 918 and the p-type AlGaAs layer 912 has a reverse bias with respect to the forward bias of the light emitting thyristor. Basically, no current flows. Therefore, if the additional diode formed by the n-type ITO layer 918 and the p-type AlGaAs layer 912 is sufficient for an application requiring a reverse breakdown voltage, it can be omitted. With such a structure, the lower part of the semiconductor lamination portion substantially equal to the portion where the p-type GaP layer 914 and the n-type transparent conductor ITO layer 918 contact each other emits light, and the DBR layer 904 almost emits light. Is reflected to the side opposite to the substrate 900.

  In the exposure head 106 in the present embodiment, the density of light emitting points (interval between light emitting elements) is determined according to the resolution. Each light emitting element in the surface light emitting element array chip is separated into a mesa structure 922 by an element separating groove 924. When an image is formed at a resolution of, for example, 1200 dpi, a distance between element centers of adjacent light emitting elements (light emitting points). Are arranged to be 21.16 μm.

  As described above, in the present embodiment, the exposure head 106 performs resolution conversion of binary image data having a resolution of 2400 dpi into image data (density data) of 1200 dpi multivalued by the filter processing unit 408. Further, in the processing of the LUT 410, the image quality can be improved by adjusting the pulse width of the PWM signal for controlling the light amount of the surface light emitting element according to the control voltage and the temperature using a look-up table. Further, when the image data is multi-valued, the communication speed of the interface between the control board 415 and the drive board 202 increases due to the increase in the data transfer amount, and the radiation noise countermeasure cost increases. In the present embodiment, the image data transmitted from the control board 415 to the drive board 202 is binary, and the multi-valued image data is performed in the exposure head 106, so that the multi-valued data can be output without increasing the communication speed. Can be processed.

  As described above, according to this embodiment, the image quality can be improved by increasing the gradation of the image data while suppressing the cost of the interface between the controller and the exposure head.

1-29 surface emitting element array chip 102 photosensitive drum 106 exposure head 202 drive substrate 303 drive unit 400 CPU
415 control board

Claims (12)

A photoreceptor rotating in a first direction;
An exposure unit having a plurality of surface light emitting elements arranged in a second direction orthogonal to the first direction, and exposing the photoconductor by the surface light emitting elements;
A control unit that outputs image data to the exposure unit, and controls image formation.
An image forming apparatus comprising:
The control unit includes:
Generating means for generating the binary image data at a second resolution larger than the first resolution of the surface light emitting element, and transmitting means for transmitting the image data generated by the generating means to the exposure unit; And a controller having
A control board on which the controller is mounted,
Has,
The exposure unit,
A driver for receiving the image data transmitted from the control unit, and controlling light emission of the surface light emitting element;
A drive board on which the driver is mounted;
Has,
The control board and the drive board are connected by a cable,
The controller transmits the image data to the driver by serial communication via the cable,
The driver is a conversion unit that converts the resolution in the second direction of the image data received by the reception unit from the second resolution to the first resolution, and calculates the density of the converted pixel. And converting the binary image data into multi-valued image data larger than the binary by performing an interpolation process based on the density of the pixel before the conversion and the density of the pixel adjacent to the pixel before the conversion. An image forming apparatus comprising: a conversion unit configured to convert the image into an image.   The image forming apparatus according to claim 1, wherein a light emission amount of the light emitting element is controlled by a pulse width of an input signal.   The driver may include a light amount correction unit that corrects a light amount of the surface light emitting element based on the image data converted to the first resolution by the conversion unit and exposure control information that determines an exposure condition. The image forming apparatus according to claim 2, wherein: The exposure control information is a voltage value or a current value for driving the surface light emitting element,
The image forming apparatus according to claim 3, wherein the light quantity correction unit determines a minimum pulse width of the input signal based on the voltage value or the current value. A first detecting unit for detecting a temperature of the exposure unit,
The exposure control information is a temperature of the exposure unit detected by the first detection unit,
The image forming apparatus according to claim 4, wherein the light quantity correction unit determines a maximum pulse width of the input signal based on the temperature. The cable has a plurality of communication paths for transmitting the image data,
6. The communication path according to claim 1, wherein each of the communication paths is associated in advance with the light-emitting element whose light emission is controlled by the driver based on the image data. 7. Image forming device.   When performing the interpolation processing of the density of the pixel at the end of the surface light emitting element, the conversion unit is configured to calculate the density based on the density of the pixel at the end of the surface light emitting element adjacent to the end of the surface light emitting element. The image forming apparatus according to claim 1, wherein the interpolation processing is performed.   The conversion means, the image data of the pixel at the first resolution after the conversion, a value obtained by multiplying the image data of the pixel at the second resolution before the conversion by a first coefficient, The image forming apparatus according to claim 7, wherein the value is obtained by multiplying pixel data of a pixel adjacent to the pixel at the second resolution by a second coefficient.   The control unit may further include a color shift in the first direction and a color shift in the second direction of the image data having the second resolution generated by the generation unit, and a second direction of the surface light emitting element. 9. The image forming apparatus according to claim 1, further comprising a shift correcting unit configured to correct the shift of the image forming apparatus. 10. A second detection unit configured to detect a color shift amount in the first direction and a color shift amount in the second direction of an image formed on the photoconductor by the exposure unit;
The image data generated by the generation unit based on the color shift amount in the first direction and the color shift amount in the second direction detected by the second detection unit. The image forming apparatus according to claim 9, wherein the color shift in the first direction and the color shift in the second direction are corrected. Storage means for storing a positional shift amount of the surface light emitting element with respect to the photoconductor in the second direction,
The shift correcting unit corrects the image data in which the color shift in the first direction and the color shift in the second direction have been corrected based on the positional shift amount stored in the storage unit. The image forming apparatus according to claim 10, wherein   The surface light-emitting elements of the exposure unit are arranged in two rows in the first direction, and an interval between the surface light-emitting elements arranged in each row in the second direction is an integral multiple of the second resolution. The image forming apparatus according to any one of claims 1 to 11, wherein

Images