JP7130469B2 - image forming device - Google Patents

Description

The present invention relates to an electrophotographic image forming apparatus.

2. Description of the Related Art In printers, which are electrophotographic image forming apparatuses, a method of forming a latent image by exposing a photosensitive drum using an exposure head is generally known. For the exposure head, an LED (Light Emitting Diode), an organic EL (Oganic Electro Luminescence), or the like is used. The exposure head is composed of a row of light emitting elements arranged in the longitudinal direction of the photosensitive drum and a rod lens array that forms an image of the light from the row of light emitting elements on the photosensitive drum. LEDs and organic ELs are known to have a surface emitting shape in which the direction of light emitted from the light emitting surface is the same as that of the rod lens array. Here, the length of the light emitting element row is determined according to the width of the image area on the photosensitive drum, and the interval between the light emitting elements is determined according to the resolution of the printer. For example, in the case of a 1200 dpi printer, the pixel spacing is 21.16 μm, which is the spacing corresponding to the resolution, so the spacing between the light emitting elements is also the spacing corresponding to 21.16 μm. A printer using such an exposure head uses fewer parts than a laser scanning printer that scans a photosensitive drum with a laser beam deflected by a rotating polygonal mirror, resulting in a smaller device. , the cost can be easily reduced. Also, in a printer using an exposure head, noise caused by the rotation of a rotating polygonal mirror is reduced.

An exposure head using an LED generally has a configuration in which a plurality of surface emitting element array chips are arranged and capable of forming an image corresponding to an image width of about 316 mm. The driving unit of the exposure head and the image controller are separately mounted on separate substrates. For example, the image controller is mounted on the control board, and the drive section of the exposure head is mounted on the drive board. For this reason, the image data is converted into an image signal, and transferred from the image controller to the exposure head driving unit via a cable such as a flexible flat cable (hereinafter referred to as FFC). The image signals transferred from the image controller to the exposure head driving unit are converted from parallel data to serial data on the image controller side for the purpose of reducing the number of cable pins (hereinafter referred to as parallel-serial conversion). ) signal is used. In addition, since parallel-serial conversion requires a transfer time, a channel link SerDes (SERializer/DESerializer) or the like that differentially transfers data at high speed is generally used. In such a data transfer configuration, there is a problem that radiation noise is generated. As a countermeasure against radiation noise, it is known to provide a cable with a dedicated member for the purpose of removing radiation noise. Also, there is known a method of reducing the influence of radiation noise by providing a fixed voltage regulator in the power supply of an IC that performs parallel-to-serial conversion of an image controller to keep the swing width of the voltage of the image signal low (for example, See Patent Document 1).

JP 2009-262435 A

However, besides the power supply voltage, the pattern of the input image also influences radiation noise. For example, when an image pattern (for example, a screen image) in which a specific pattern is repeated at a predetermined cycle is input, a predetermined frequency component becomes conspicuous, which may cause radiation noise and degrade quality. .

SUMMARY OF THE INVENTION An object of the present invention is to reduce radiation noise regardless of the pattern of input image data.

In order to solve the above problems, the present invention has the following configurations.

(1) A photoreceptor that is rotationally driven and a chip that has a plurality of light-emitting elements that expose the photoreceptor, and the plurality of chips are arranged at different positions in a direction that intersects the rotation direction of the photoreceptor. corresponding to each pixel corresponding to a second resolution higher than the first resolution based on the input image data, in order to drive the exposed head and the plurality of light emitting elements of the plurality of chips. and a first generation means for generating pixel data for forming an image having the first resolution corresponding to the arrangement interval of the plurality of light emitting elements in the cross direction, the image forming apparatus comprising: a first conversion unit that acquires pixel data generated by the generating means of the first method, executes encoding processing in which the order of arrangement of the pixel data is rearranged, and converts the data into a signal; a transmission section for transmitting the signal transmitted from the transmission section; a control board on which the first generation means, the first conversion section, and the transmission section are mounted; and a reception section for receiving the signal transmitted from the transmission section. a second conversion unit that performs decoding processing for restoring the pixel data from the signal received by the reception unit; and the plurality of chips based on the pixel data restored by the second conversion unit. A cable that connects a drive unit that drives the plurality of light emitting elements respectively, a drive board on which the reception unit, the second conversion unit, and the drive unit are mounted, and the control board and the drive board, , and the cable for transmitting the signal, and the first conversion unit converts the pixel data generated by the first generation means into a plurality of pixels in units of a predetermined number of pixels for each of the plurality of chips. The plurality of chips are divided into blocks, and the arrangement order of all pixel data in blocks having the same block number of the plurality of chips is not the arrangement order of the chips in the cross direction, and the light emitting elements in the blocks are arranged in the cross direction. , wherein the second conversion unit converts the pixel data encoded by the first conversion unit to the order of the pixel data in 1. An image forming apparatus, wherein the pixels are restored in a pixel order corresponding to the arrangement order of the chips in the cross direction and the arrangement order of the light emitting elements in the cross direction.

According to the present invention, radiation noise can be reduced regardless of the pattern of input image data.

Schematic cross-sectional view showing the configuration of an image forming apparatus according to an embodiment FIG. 4 is a diagram for explaining the positional relationship between the exposure head and the photosensitive drum of the embodiment, and a diagram for explaining the configuration of the exposure head; Schematic diagram of a printed circuit board of an embodiment and a diagram for explaining the configuration of a surface emitting element array chip Control block diagram of the control board and drive board of the embodiment Control Block Diagram and Timing Chart of Chip Data Conversion Unit of Embodiment FIG. 4 is a diagram for explaining processing of image data by the chip data conversion unit of the embodiment; Diagram for explaining filter processing of the embodiment Diagram for explaining filter processing of the embodiment A diagram showing the lookup table of the embodiment FIG. 4 is a diagram for explaining the circuit of the surface emitting element array chip of the embodiment; FIG. 4 is a diagram for explaining the distribution state of the gate potential of the shift thyristor of the embodiment; FIG. 4 is a diagram showing drive signal waveforms of the surface emitting element array chip of the embodiment; The figure which shows the cross section of the surface emitting thyristor of an Example Block diagram of the data transmission unit and data reception unit of the embodiment Block diagram of LVDS transmission unit and LVDS reception unit of embodiment, transfer bit arrangement diagram of channel link SerDes Block diagram showing the flow of resolution in the embodiment, bit array diagram of data transfer Flowchart showing processing of the transmission format conversion unit of the embodiment Block diagram of the transmission format converter of the embodiment Buffer storage diagram of image data for each chip of the embodiment Buffer storage diagram in an arrangement not in chip order and pixel order in the embodiment, image arrangement diagram input to the LVDS transmission unit Block diagram of reception format conversion unit of embodiment, buffer storage diagram of data of reception format conversion unit FFT analysis diagram of conventional transfer data for comparison with the embodiment, FFT analysis diagram of transfer data of the embodiment Block diagram of another embodiment Block diagram of another embodiment

Next, an embodiment of the present invention will be described with appropriate reference to the drawings. In the following description, first, the overall configuration and control of an image forming apparatus as an example will be described, and then details of features of the present invention will be described.

[Configuration of Image Forming Apparatus]
FIG. 1 is a schematic cross-sectional view showing the configuration of an electrophotographic image forming apparatus according to the first embodiment. The image forming apparatus shown in FIG. 1 is a multifunction peripheral (MFP) having a scanner function and a printer function. It is composed of a control unit (not shown). The scanner unit 100 illuminates a document placed on a document platen, optically reads the document image, converts the read image into an electrical signal, and creates image data.

The image forming units 103 are arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K) along the rotation direction (counterclockwise direction) of the endless conveying belt 111 . A series of imaging stations are provided. The four image forming stations have the same configuration, and each image forming station includes a photosensitive drum 102 that rotates in the direction of the arrow (clockwise), an exposure head 106, a charger 107, and a developer 108. there is The suffixes a, b, c, and d of the photosensitive drum 102, the exposure head 106, the charger 107, and the developer 108 are black (K), yellow (Y), magenta (M), and cyan (Y) of the image forming station, respectively. It shows that the configuration corresponds to C). Note that suffixes of reference numerals are omitted below unless they refer to a specific photosensitive drum or the like.

The image forming unit 103 rotates the photosensitive drum 102 and charges the photosensitive drum 102 with the charger 107 . The exposure head 106, which is an exposure means, emits light from the arrayed LED array according to image data, and the light emitted from the chip surface of the LED array is condensed onto the photosensitive drum 102 (on the photosensitive member) by the rod lens array. to form an electrostatic latent image. A developing device 108 develops the electrostatic latent image formed on the photosensitive drum 102 with toner. Then, the developed toner image is transferred onto the recording paper on the transport belt 111 that transports the recording paper. A series of such electrophotographic processes are performed at each image forming station. During image formation, the magenta (M), yellow (Y), and black (K) image forming stations are sequentially formed after a predetermined time has passed since the image forming station for cyan (C) started forming images. , the image forming operation is executed.

The image forming apparatus shown in FIG. 1 includes internal paper feed units 109a and 109b included in a paper feed/conveyance unit 105, an external paper feed unit 109c as a large-capacity paper feed unit, and an external paper feed unit 109c. A manual sheet feeding unit 109d is provided. At the time of image formation, recording paper is fed from a paper feeding unit that has been instructed in advance, and the fed recording paper is conveyed to registration rollers 110 . The registration roller 110 conveys the recording paper to the conveying belt 111 at the timing when the toner image formed by the image forming unit 103 is transferred to the recording paper. A toner image formed on the photosensitive drum 102 of each image forming station is sequentially transferred onto the recording paper conveyed by the conveying belt 111 . The recording paper onto which the unfixed toner image has been transferred is conveyed to fixing section 104 . The fixing unit 104 incorporates a heat source such as a halogen heater, and heats and presses the toner image on the recording paper with two rollers to fix the toner image on the recording paper. The recording paper on which the toner image is fixed by the fixing unit 104 is discharged to the outside of the image forming apparatus by the discharge roller 112 .

An optical sensor 113 serving as detection means is arranged at a position facing the transport belt 111 downstream of the black (K) image forming station in the recording paper transport direction. The optical sensor 113 detects the position of the test image formed on the conveying belt 111 in order to derive the amount of color misregistration of the toner images between the image forming stations. The amount of color misregistration derived by the optical sensor 113 is notified to a control board 415 (see FIG. 4), which will be described later, and the image position of each color is corrected so that a full-color toner image without color misregistration is transferred onto the recording paper. be. In addition, a printer control unit (not shown) controls the scanner unit 100, the image forming unit 103, the fixing unit 104, the feeder unit 100, and the image forming unit 103 according to an instruction from an MFP control unit (not shown) that controls the entire multifunction peripheral (MFP). An image forming operation is executed while controlling the paper/conveyance unit 105 and the like.

Here, as an example of an electrophotographic image forming apparatus, an image forming apparatus that directly transfers the toner image formed on the photosensitive drum 102 of each image forming station onto the recording paper on the conveying belt 111 has been described. The present invention is not limited to printers that directly transfer the toner image on the photosensitive drum 102 to the recording paper. For example, the present invention can also be applied to an image forming apparatus having a primary transfer section that transfers the toner image on the photosensitive drum 102 to an intermediate transfer belt and a secondary transfer section that transfers the toner image on the intermediate transfer belt to recording paper. can do.

[Configuration of Exposure Head]
Next, the exposure head 106 that exposes the photosensitive drum 102 will be described with reference to FIG. FIG. 2A is a perspective view showing the positional relationship between the exposure head 106 and the photosensitive drum 102, and FIG. 2B shows the internal structure of the exposure head 106 and how the light beam from the exposure head 106 passes through the rod lens array. FIG. 2 is a diagram for explaining how light is focused on a photosensitive drum 102 by a light 203; As shown in FIG. 2A, the exposure head 106 is attached to the image forming apparatus by an attachment member (not shown) at a position facing the photosensitive drum 102 on the upper portion of the photosensitive drum 102 rotating in the direction of the arrow. (Fig. 1).

As shown in FIG. 2B, the exposure head 106 is composed of a drive board 202, a surface emitting element array element group 201 mounted on the drive board 202, a rod lens array 203, and a housing 204. . A rod lens array 203 and a driving substrate 202 are attached to the housing 204 . The rod lens array 203 converges the light flux from the surface emitting element array element group 201 onto the photosensitive drum 102 . At the factory, the exposure head 106 alone is assembled and adjusted, and the focus and light amount of each spot are adjusted. Here, assembly adjustment is performed so that the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the surface emitting element array element group 201 are at predetermined intervals. As a result, light from the surface emitting element array element group 201 forms an image on the photosensitive drum 102 . Therefore, when adjusting the focus at the factory, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the surface emitting element array element group 201 becomes a predetermined value. Further, when adjusting the amount of light in the factory, the light emitting elements of the surface light emitting element array element group 201 are sequentially caused to emit light so that the light condensed on the photosensitive drum 102 via the rod lens array 203 has a predetermined light amount. Then, the driving current of each light emitting element is adjusted.

[Structure of Surface Emitting Element Array Element Group]
FIG. 3 is a diagram for explaining the surface emitting element array element group 201. As shown in FIG. FIG. 3A is a schematic diagram showing the configuration of the surface of the driving substrate 202 on which the surface emitting element array element group 201 is mounted, and FIG. is a schematic diagram showing the configuration of the surface (second surface) opposite to the surface (first surface) on which is mounted.

As shown in FIG. 3A, in the surface emitting element array element group 201 mounted on the driving substrate 202, 29 surface emitting element array chips 1 to 29 are staggered along the longitudinal direction of the driving substrate 202. It has a configuration arranged in two rows in a shape. In FIG. 3A, the vertical direction indicates the sub-scanning direction (the rotation direction of the photosensitive drum 102), which is the direction of rotation, and the horizontal direction indicates the main scanning direction, which is the second direction orthogonal to the sub-scanning direction. show. The main scanning direction is also a crossing direction crossing the rotation direction of the photosensitive drum 102 . Inside each surface emitting element array chip, each element of the surface emitting element array chip having a total of 516 light emitting points is arranged at a predetermined resolution pitch in the longitudinal direction of the surface emitting element array chip. In this embodiment, the pitch of each element of the surface emitting element array chip is approximately 21.16 μm (≈2.54 cm/1200 dots), which is the pitch of the first resolution of 1200 dpi. As a result, the arrangement interval from end to end of the 516 light emitting points in one surface emitting element array chip is approximately 10.9 mm (≈21.16 μm×516). The surface emitting element array element group 201 is composed of 29 surface emitting element array chips. The number of light emitting elements that can be exposed in the surface emitting element array element group 201 is 14,964 elements (=516 elements x 29 chips), corresponding to an image width of approximately 316 mm (approximately 10.9 mm x 29 chips) in the main scanning direction. It is possible to form an image with

FIG. 3(c) is a view showing the boundary between chips of the surface emitting element array chips arranged in two rows in the longitudinal direction. It is the longitudinal direction of the group 201 . As shown in FIG. 3(c), wire bonding pads to which control signals are input are arranged at the ends of the surface emitting element array chip, and signals input from the wire bonding pads control the transfer section and the light emission. The element is driven. Also, the surface emitting element array chip has a plurality of light emitting elements. Even at the boundary between the surface emitting element array chips, the pitch of the light emitting elements in the longitudinal direction (the distance between the center points of the two light emitting elements) is about 21.16 μm, which is the pitch of the resolution of 1200 dpi. . In addition, the surface emitting element array chips arranged in two vertical rows have an interval (indicated by an arrow S in the figure) between the light emitting points of the upper and lower surface emitting element array chips of about 84 μm (4 pixels at 1200 dpi, 8 pixels at 2400 dpi). are arranged so that the distance is an integral multiple of each resolution of minutes).

Further, as shown in FIG. 3B, on the surface of the driving substrate 202 opposite to the surface on which the surface emitting element array element group 201 is mounted, driving units 303a and 303b and a connector 305 are mounted. there is The driving units 303a and 303b are driver ICs. Driving units 303a and 303b arranged on both sides of the connector 305 drive the surface emitting element array chips 1 to 15 and the surface emitting element array chips 16 to 29, respectively. Drive units 303a and 303b are connected to connector 305 via patterns 304a and 304b, respectively. The connector 305 is connected to signal lines, power supply voltage, and ground for controlling the drive units 303a and 303b from a control board 415 (see FIG. 4), which will be described later, and is connected to the drive units 303a and 303b. Wiring for driving the surface emitting element array element group 201 passes through the inner layer of the driving substrate 202 from the driving units 303a and 303b, and the surface emitting element array chips 1 to 15 and the surface emitting element array chips 16 to 29 are connected to the surface emitting element array chips 1 to 15. It is connected to the.

[Control configuration of image controller unit and exposure head]
FIG. 4 shows a control board 415 which is output means for processing image data and outputting it to the drive board 202, and a control block of the drive board 202 for exposing the photosensitive drum 102 based on the image data input from the control board 415. It is a diagram. Each block 401-414 described below represents a module inside the IC. As for the driving substrate 202, the surface emitting element array chips 1 to 15 controlled by the driving section 303a shown in FIG. 4 will be described. The surface emitting element array chips 16 to 29 controlled by the driving section 303b (not shown in FIG. 4) also operate in the same manner as the surface emitting element array chips 1 to 15 controlled by the driving section 303a. In order to simplify the explanation, image processing for one color will be described here, but in the image forming apparatus of this embodiment, similar processing is performed simultaneously for four colors in parallel. A control board 415 shown in FIG. 4 has a connector 416 for transmitting signals for controlling the exposure head 106 . From the connector 416, image data and a line synchronization signal, which will be described later, are transmitted through cables 417 and 419 connected to the connector 305 of the drive board 202, respectively. Also, a control signal from the CPU 400 of the control board 415 is transmitted from the connector 416 via the cable 418 connected to the connector 305 .

[Control board]
The control board 415 transmits signals for controlling the exposure head 106 to the drive board 202 . This signal is a signal obtained by parallel-serial conversion of the image data and the line synchronization signal. This signal is input from the connector 416 on the control board 415 side to the connector 305 on the drive board 202 side via the cable 417 that transmits the signal. A communication signal from the CPU 400 is input to the connector 305 on the drive board 202 side via the transmission cable 418 .

In the control board 415, the CPU 400 performs image data processing and print timing processing. The control board 415 is composed of functional blocks of an image data generator 401 , a line data shifter 402 , a chip data converter 403 , a chip data shifter 404 , a data transmitter 405 and a sync signal generator 406 . Note that the image data generation unit 401, the line data shift unit 402, the chip data conversion unit 403, and the chip data shift unit 404 generate pixel data corresponding to each pixel corresponding to 2400 dpi based on the input image data. It functions as a generating means. Processing in each functional block will be described below in the order in which image data is processed in the control board 415 .

(Image data generator)
An image data generation unit 401 serving as data generation means performs dithering processing on image data received from an external computer connected to the scanner unit 100 or the image forming apparatus at a resolution designated by the CPU 400 . Thereby, image data for print output is generated. In this embodiment, the image data generation unit 401 performs dithering processing at a resolution of 2400 dpi, which is the second resolution higher than 1200 dpi. That is, the image data generated by the image data generation unit 401 is pixel data equivalent to 2400 dpi. Pixel data equivalent to 2400 dpi in this embodiment is assumed to be 1 bit, but one pixel may be represented by a plurality of bits. The pixel data generated by the image data generation unit 401 is line data corresponding to lines corresponding to 2400 dpi in the sub-scanning direction. Note that the image data generator 401 is one integrated circuit 401A.

(Line data shift section)
The CPU 400 determines the main scanning direction (longitudinal direction of the exposure head 106) and the sub-scanning direction (both the rotation direction of the photosensitive drum 102 and the conveyance direction of the recording paper) based on the amount of color misregistration detected by the optical sensor 113. is determined in units of 2400 dpi. The image shift amount is determined by the CPU 400 based on, for example, the relative amount of color shift between colors calculated based on the detection result of the color shift detection pattern image by the optical sensor 113 . Then, the CPU 400 instructs the image shift amount to the line data shift unit 402, which is correction means. The line data shift unit 402 shifts the image data input from the image data generation unit 401 in units of 2400 dpi for the entire image area within one page of the recording paper based on the image shift amount instructed by the CPU 400 . . Note that the line data shift unit 402 may divide the image area in one page of the recording paper into a plurality of areas, and perform shift processing for each of the divided image areas.

(synchronization signal generator)
A synchronization signal generation unit 406, which is a second generation means, generates a line period signal (hereinafter referred to as a line synchronization signal) for one line in the rotation direction of the photosensitive drum 102, which is a signal synchronized with the rotation speed of the photosensitive drum 102. . When the magnification in the sub-scanning direction is 1:1, the CPU 400 instructs the synchronization signal generator 406 about the cycle of the line synchronization signal. The cycle of the Line synchronizing signal is also the time for the surface of the photosensitive drum 102 to move in the rotational direction (sub-scanning direction) by a pixel size of 2400 dpi (approximately 10.5 μm) with respect to the predetermined rotational speed of the photosensitive drum 102 . For example, when printing at a speed of 200 mm/sec in the sub-scanning direction, the CPU 400 sets the cycle of the line synchronization signal (the cycle of one line in each main scanning direction in the sub-scanning direction) to approximately 52.9 μs (≈(25 .4 mm/2400 dots)/200 mm) is instructed to the synchronization signal generator 406 . If the image forming apparatus has a detection unit that detects the rotation speed of the photosensitive drum 102, the CPU 400 detects the rotation speed of the photosensitive drum in the sub-scanning direction based on the result of the detection unit (the generation cycle of the signal output by the encoder). 102 rotation speed is calculated. Here, as the detection unit, for example, there is an encoder or the like installed on the rotary shaft of the photosensitive drum. The CPU 400 determines the period of the Line synchronization signal based on the calculation result. On the other hand, if the image forming apparatus does not have a detection unit for detecting the rotation speed of the photosensitive drum 102, the rotation speed of the photosensitive drum 102 is calculated based on the following information. That is, the CPU 400 determines the period of the line synchronization signal based on the sheet basis weight (g/cm 2 ), the sheet size, and other sheet type information input by the user from the operation unit.

(Chip data converter)
The chip data conversion unit 403 reads line data from the line data shift unit 402 in synchronization with the line synchronization signal for each line in the sub-scanning direction of the photosensitive drum 102 in the main scanning direction . Then, the chip data conversion unit 403 executes data processing for dividing the read line data into line data for each chip.

FIG. 5A is a block diagram showing the configuration of the chip data conversion section 403. As shown in FIG. In FIG. 5( a ), the Line synchronizing signal output from the synchronizing signal generator 406 is input to the counter 530 . The counter 530 includes a frequency modulation circuit that modulates the input Line synchronizing signal to generate a CLK signal having a higher frequency than the Line synchronizing signal. The counter 530 may incorporate an oscillator that generates a clock signal (CLK) having a higher frequency than the Line synchronization signal instead of the frequency modulation circuit. A configuration in which the chip data conversion unit 403 reads line data from the line data shift unit 402 will be exemplified below, but the embodiment is not limited to this. That is, the line synchronization signal is supplied to the line data shifter 402, and the line data shifter 402 internally generates the clock signal. As a result, the line data shifter 402 may be configured to proactively transmit the line data to the chip data converter 403 .

When the Line synchronization signal is input, the counter 530 resets the count value to 0, and then increments the counter value in synchronization with the number of pulses of the clock signal (CLK) (see FIG. 5B). The frequency of the CLK signal generated by the counter 530 is determined by the capacity (number of bits) of pixel data to be read by the chip data conversion unit 403 within one cycle of the Line synchronization signal, the data processing speed of the chip data conversion unit 403 described later, determined at the design stage based on For example, as described above, the surface emitting element array element group 201 has 14,964 light emitting elements (converted to 1200 dpi) for exposing one line in the main scanning direction. On the other hand, the image data generation unit 401 performs dithering processing at a resolution of 2400 dpi. Therefore, the number of pixels in one line of image data in the main scanning direction output from the line data shift unit 402 is 29,928 pixels (=14,964×(2400 dpi/1200 dpi)). The chip data conversion unit 403 reads image data for one line in the main scanning direction and writes it to a line memory 500 (to be described later) and writes image data to memories 501 to 529 (to be described later) during the line synchronization signal. . Therefore, the counter 530 counts twice the number of pixels (29,928) included in one line of line data (59,856). The period during which the count value of the counter 530 is from 1 to 29,928 is Tm1, and the period during which the count value is from 29,929 to 59,856 is Tm2 (see FIG. 5B).

The READ control section 531 reads line data from the line data shift section 402 according to the count value of the counter 530 . That is, the READ control unit 531 stores line data (29,928 pixels) for one line in the main scanning direction in the line memory 500 during the period Tm1 when the count value of the counter 530 is from 1 to 29,928. Further, the WR control unit 532 divides the line data for one line in the main scanning direction stored in the line memory 500 into the memories 501 to 529 during the period Tm2 when the count value of the counter 530 is 29,929 to 59,856. write. Memories 501 to 529 have a smaller storage capacity than the line memory 500, and store line data (divided line data) divided for each chip. The memories 501-529 are FIFO (First In First Out) memories provided corresponding to the surface emitting element array chips 1-29. That is, the memory 501 stores line data corresponding to the surface emitting element array chip 1, the memory 502 stores line data corresponding to the surface emitting element array chip 2, . store line data corresponding to .

Next, the writing of the line data read from the line data shift unit 402 to the memories 501 to 529 and the output of the image data written to the memories 501 to 529 executed by the chip data conversion unit 403 will be described. FIG. 5(b) is a time chart for explaining input/output timing of line data in the chip data conversion unit 403. As shown in FIG. In FIG. 5B, the line synchronization signal indicates a pulse signal output from the synchronization signal generator 406. In FIG. In the figure, TL1, TL2 , . One period of the Line synchronization signal is divided into periods Tm1 and Tm2 according to the counter value of the counter 530 . Input data to the line memory 500 indicates image data from the line data shifter 402, and is input from the line data shifter 402 during the period Tm1 of the cycles TL1, TL2, . . . TL10. The first line data in FIG. 5B indicates the line data of the first line in the sub-scanning direction (for one line in the main scanning direction). Similarly , the 2nd line data , . minutes).

5(b), among the line data for one line in the main scanning direction stored in the line memory 500, the line data corresponding to the surface emitting element array chip 1 is The timing of writing to the memory 501 is shown. Similarly, input data to the memory 502, input data to the memory 503, . 503, . . . , 529 are shown. The first line data of the input data to the memory 501 is line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1, not all line data for one line in the main scanning direction. pointing. The same applies to the input data of the memories 502 to 529. FIG.

'Output data from memory 501' shown in FIG. Similarly, 'output data from memory 502', . . . 'output data from memory 529' shown in FIG. It shows the timing of reading for output. Note that the first line data of the output data from the memory 501 is line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1, not all line data for one line in the main scanning direction. pointing. The same applies to output data from the memories 502 to 529. FIG.

In this embodiment, line data for one line in the main scanning direction are sequentially read out from the line memory 500 and firstly written to the memory 501 that stores the line data of the surface emitting element array chip 1 . Next, writing is performed to the memory 502 that stores the image data of the surface emitting element array chip 2, and thereafter, writing is continuously performed sequentially up to the memory 529 that stores the image data of the surface emitting element array chip 29. . A chip data shifter 404 subsequent to the chip data converter 403 performs data shift processing in the sub-scanning direction for each surface emitting element array chip. Therefore, it is assumed that the memories 501 to 529 store line data for 10 lines in the sub-scanning direction.

Furthermore, the line data stored in the memories 501 to 529 are the line data for one chip corresponding to each surface emitting element array chip, and the pixel data obtained by copying the pixel data at the edge of the adjacent surface emitting element array chip. Data is also stored together. For example, the memory 502 stores the following pixel data at each end of the line data corresponding to the surface emitting element array chip 2 . That is, the pixel data of the edge of the surface emitting element array chip 2 on the surface emitting element array chip 1 and the pixel data of the edge of the surface emitting element array chip 3 on the surface emitting element array chip 2 side are added. and stored.

FIG. 6 is a diagram for explaining the relationship between the line data stored in the line memory 500 and the image data stored in the memories 501-529. FIG. 6(a) is a diagram showing line data for each surface emitting element array chip stored in the line memory 500, showing an image of the line data array before being rearranged in the memories 501 to 529. FIG. . The line memory 500 stores line data of the surface emitting element array chip (N−1) (hatched display), line data of the surface emitting element array chip N (outlined display), and line data of the surface emitting element array chip (N+1). (hatched display) is stored.

On the other hand, FIG. 6B shows an image of line data stored in each of the memories 501 to 529 corresponding to the surface emitting element array chip N. FIG. As described above, the memories 502 to 528 corresponding to the surface emitting element array chips store the line data of the corresponding surface emitting element array chip and the pixel data of the edge of the adjacent surface emitting element array chip. be done. Of the line data of the surface emitting element array chip N shown in FIG. 6(b), the leftmost pixel data is adjacent to the surface emitting element array chip N included in the line data of the surface emitting element array chip (N−1). This is the pixel data at the edge of the line (see the arrow in the figure). On the other hand, among the line data of the surface emitting element array chip N shown in FIG. 6B, the rightmost pixel data is adjacent to the surface emitting element array chip N among the line data of the surface emitting element array chip (N+1). This is the pixel data at the edge of the line (see the arrow in the figure).

In the memory 501, pixel data of the edge of the surface emitting element array chip 2 on the side of the surface emitting element array chip 1 is added to the edge of the line data corresponding to the surface emitting element array chip 1 and stored. . In addition, in the memory 529, the end of the line data corresponding to the surface emitting element array chip 29 is added with the pixel data of the edge of the surface emitting element array chip 28 on the side of the surface emitting element array chip 29 and stored. .

As described above, in this embodiment, the pixel data of the edge of the surface emitting element array chip adjacent to each surface emitting element array chip is added to both ends of the line data of the corresponding surface emitting element array chip, and the memory 501 ~529. By the operation of the chip data conversion unit 403 described above, the line data for one line in the main scanning direction is stored in the memories 501 to 529 provided corresponding to the surface emitting element array chips 1 to 29, and the adjacent surface emitting element array chips. is stored with the pixel data at the end of the . Note that the pixel data at the edge of the adjacent surface emitting element array chip is used in the filter processing section 408, which will be described later.

(Chip data shift part)
The chip data shifter 404, which is correction means, performs the following control. That is, based on the data information (2400 dpi unit) regarding the image shift amount in the sub-scanning direction for each surface emitting element array chip instructed in advance by the CPU 400, the relative read timing of the line data from the memories 501 to 529 is controlled. . The image shift processing in the sub-scanning direction executed by the chip data shift unit 404 will be specifically described below.

In the longitudinal direction of the exposure head, it is desirable that there is no shift in the mounting positions of the even-numbered surface emitting element array chips. Similarly, in the longitudinal direction of the exposure head, it is desirable that the mounting positions of the odd-numbered surface emitting element array chips do not deviate. Further, the mounting positional relationship in the sub-scanning direction between the even-numbered surface-emitting element array chips and the odd-numbered surface-emitting element array chips is equivalent to 2400 dpi and has a predetermined number of pixels (e.g., 8 pixels) by design. preferable. Furthermore, it is preferable that the arrangement positions of the light emitting element arrays in the sub-scanning direction in each surface emitting element array chip are constant without individual differences. However, the mounting positions and the arrangement positions of the light emitting element arrays contain errors, and these errors may lead to deterioration of the image quality of the output image.

In the memory 420 (ROM) shown in FIG. 4, a correction calculated from the relative positional relationship in the sub-scanning direction of the light emitting element arrays of the surface emitting element array chips 1 to 29 mounted on the drive substrate 202 in a zigzag pattern. data is stored. For example, the memory 420 stores correction data based on the following measurement data. Each light emitting element array of the other surface light emitting element array chips 2 to 29 is driven with a shift of several pixels corresponding to 2400 dpi in the sub scanning direction with respect to the light emitting element array of the surface light emitting element array chip 1 serving as the reference of the position in the sub scanning direction. Correction data indicating whether or not it is mounted on the board 202 is stored. After the surface emitting element array chips 2 to 29 are mounted on the drive substrate 202, the measurement data is obtained by turning on the light emitting element of each surface emitting element array chip with a measuring device and measuring based on the light reception result. The CPU 400 sets the correction data read from the memory 420 in the internal register of the chip data shift section 404 in response to the power of the image forming apparatus being turned on. The chip data shifter 404 shifts the line data stored in the memories 501 to 529 to form the same line based on the correction data set in the internal register. For example, when the light emitting element array of the surface light emitting element array chip 2 is mounted on the drive substrate 202 with a shift of 8 pixels in the sub-scanning direction corresponding to 2400 dpi with respect to the light emitting element array of the surface light emitting element array chip 1, the chip The data shifter 404 performs the following processing. That is, the chip data shift unit 404 shifts the output timing of the line data corresponding to the surface emitting element array chips 2 forming the same line to the output timing of the line data corresponding to the surface emitting element array chips 1 to the driving substrate 202. is delayed by 8 pixels. Therefore, the chip data shifter 404 shifts all the line data corresponding to the surface emitting element array chip 2 with respect to the line data corresponding to the surface emitting element array chip 1 .

(data transmitter)
The data transmission unit 405 transmits line data to the driving substrate 202 after performing data processing corresponding to the series of line data described above. A detailed circuit configuration of the data transmission unit 405 will be described later. The transmission timing of image data will be described with reference to FIG. As shown in FIG. 3A, among the surface emitting element array chips, odd-numbered surface emitting element array chips 1, 3, 5, . are arranged downstream in the sub-scanning direction. In the time chart shown in FIG. 5(b), writing of image data to the memories 501 and 529 corresponding to the odd-numbered surface emitting element array chips 1 and 29 is performed during the period of the first Line synchronization signal (TL1 in the figure). , TL10). Then, during the period of the next Line synchronizing signal (TL2 in the figure), the line data of the first line in the sub-scanning direction is read out from the memories 501 and 529 corresponding to the odd-numbered surface emitting element array chips 1 and 29. is done. Similarly, during the period of the next Line synchronizing signal, line data of the second line in the sub-scanning direction is read out from the memories 501 and 529 corresponding to the odd-numbered surface emitting element array chips 1 and 29 . In the period of the tenth line synchronization signal (TL10 in the figure), the line data of the ninth line in the sub-scanning direction is read from the memory 501 and the memory 529 corresponding to the odd-numbered surface emitting element array chips 1 and 29. A read is performed. In addition, the memory 502 corresponding to the even-numbered surface emitting element array chip 2 has a period (TL10 in the figure) after 9 pulses of the Line synchronization signal 424 from the period TL1 during which the image data is written to the memory 502. , image data is read from the memory 502 .

The data transmission section 405 transmits the line data processed by the chip data shift section 404 to the drive substrate 202 . The counter 530 includes a frequency modulation circuit instead of an oscillator that modulates the input Line synchronization signal to generate a CLK signal having a higher frequency than the Line synchronization signal. The counter 530 may incorporate an oscillator that generates a clock signal (CLK) having a higher frequency than the Line synchronization signal instead of the frequency modulation circuit. In this embodiment, the clock signal (CLK in FIG. 5B) is adjusted so that the count value becomes 59,856 (twice the number of pixel data in one line) or more within one cycle of the Line synchronizing signal. determines the frequency. As a result, it is possible to input (write) image data to the line memory 500 and output (write) image data from the line memory 500 to the memories 501 to 529 within one period of the line synchronization signal.

On the other hand, reading out data from the memories 501 to 529 is carried out within one period of the line synchronizing signal. Output data in parallel. Therefore, the speed of reading image data from the memories 501 to 529 may be slower than the speed of writing to the memory. For example, in this embodiment, it is assumed that the image data is read from the memories 501-529 at a cycle that is 58 times longer than the cycle of the clock signal when writing the image data to the memories 501-529.

Line data shifter 402, chip data converter 403, chip data shifter 404, data transmitter 405, and sync signal generator 406 are integrated circuit 402A different from integrated circuit 401A. Also, the CPU 400 is an integrated circuit different from the integrated circuits 401A and 402A.

[Construction of drive substrate for exposure head]
(Data receiver)
Next, processing inside the drive unit 303a of the drive board 202 will be described. The data receiver 407 receives data transmitted from the data transmitter 405 of the control board 415 . A detailed circuit configuration of the data receiving unit 407 will be described later. Further, the drive unit 303 a operates based on the clock signal received by the data reception unit 407 . This is because it becomes possible to eliminate the need for a clock oscillator and a crystal oscillator in the drive unit 303a.

Here, the data receiving unit 407 and the data transmitting unit 405 are assumed to transmit and receive image data in units of lines in the sub-scanning direction in synchronization with the line synchronization signal. As described above, the chip data conversion unit 403 arranges data for each of the surface emitting element array chips 1 to 29, and the subsequent processing blocks process the data of the surface emitting element array chips 1 to 29 in parallel. It is configured to It is assumed that the drive unit 303a has a circuit capable of receiving image data corresponding to the surface emitting element array chips 1 to 15 and processing the data in parallel for each chip.

(filter processing part)
The filter processing unit 408, which is a conversion means, performs interpolation processing by filtering in the main scanning direction on the image data for each of the surface emitting element array chips 1 to 29, and converts the resolution in the main scanning direction from 2400 dpi to 1200 dpi. .

When processing the pixels at the edge of the surface emitting element array chip during filter processing, if there is no pixel data for the adjacent surface emitting element array chip, the image will be missing and an image defect will occur. Therefore, as described above, the chip data conversion unit 403 of the control board 415 adds the pixel data on the edge side of the adjacent surface emitting element array chips to arrange the image data, thereby preventing the image from missing. Filtering can be performed (see FIG. 6).

FIG. 7 is a diagram for explaining how filtering is performed by the filtering unit 408. As shown in FIG. In FIG. 7, D1 to D9 represent image data (2400 dpi input data) of the surface emitting element array chip. Here, the image data D1 to D8 are the image data of the corresponding surface emitting element array chip, and the image data D9 is the pixel data of the end portion of the adjacent surface emitting element array chip. D1' to D4' indicate image data (output data of 1200 dpi) after filtering by the filter processing unit 408. FIG. The resolution of the output data (1200 dpi) is half the resolution of the input data (2400 dpi), and the formula for calculating the image data of each pixel is expressed by (Formula 1) below.
Dn′=D(2×n−1)×K2+D(2×n)×K1+D(2×n+1)×K2 (Formula 1)

Here, n corresponds to the number of light emitting elements 516 inside each surface emitting element array chip, and image data is calculated in each light emitting element sequentially in the order of n=1 to 516 based on the lighting order of the light emitting elements. done. The first coefficient K1 is a weighting coefficient for output data and input data at the same coordinate position in the main scanning direction. The second coefficient K2 is a weighting coefficient for input data whose coordinates are shifted by 1/2 pixel in the main scanning direction from the output data. In this embodiment, interpolation calculation (filtering) is performed with values of K1=0.5 and K2=0.25, but weighting coefficients different from those in this embodiment may be used. In this embodiment, by setting the weighting factor K2 to a value greater than 0, the information of the image data generated at a resolution (2400 dpi) higher than the resolution (1200 dpi) of the output data can be reflected in the output data. Specifically, in the processing from the image data generation unit 401 of the control board 415 to the data reception unit 407 of the drive board 202, the image position movement in the main scanning direction is performed at 2400 dpi, and the image data is processed by the filter processing unit 408 in the subsequent stage. Convert the resolution to 1200dpi. As a result, it is possible to generate an image of 1200 dpi while maintaining image movement accuracy in units of 2400 dpi.

FIG. 8 is a diagram for explaining the shift of image data before and after filtering, and the change in image data due to filtering. FIG. 8A is a diagram showing 2400 dpi image data after dithering the surface emitting element array chips 1, 2 and 3 in the image data generator 401 of the control board 415. FIG. In FIG. 8(a), the image data is shown in two gradations of black and white. The vertical axis in FIG. 8A indicates the sub-scanning direction, and m to m+3 indicate lines in the sub-scanning direction. The horizontal axis of FIG. 8(a) indicates the main scanning direction, and 1, 2 to n−1, n indicate the arrangement order of the light emitting elements in the surface emitting element array chip at 2400 dpi. FIG. 8(b) is a diagram showing image data after the image data shown in FIG. 8(a) has been shifted in units of 2400 dpi by the line data shifter 402 and the chip data shifter 404 of the control board 415. is. FIG. 8B shows an image corresponding to the surface emitting element array chip 1 by shifting the image data shown in FIG. An example in which data is shifted downward in the sub-scanning direction by one pixel in units of array chips is shown.

In FIG. 8C, the image data shifted in the main scanning direction and the sub-scanning direction in FIG. The image data after resolution conversion from 2400 dpi to 1200 dpi is shown. , 1', 2', ..., n/2-1, n on the horizontal axis indicate the arrangement order of the light emitting elements of the surface light emitting element array chip after resolution conversion to 1200 dpi. Also, the size of each pixel (1200 dpi) in the main scanning direction after resolution conversion in FIG. 8C is twice the size of one pixel (2400 dpi) shown in FIG. 8B. Furthermore, the position of each pixel is shifted to the right by half a pixel in FIG. 8B (position advanced by half a pixel in the main scanning direction). does not change. For example, the size and position of pixel 1′ of surface emitting element array chip 1 after resolution conversion in FIG. It has the size and position of half the pixel plus the pixel at pixel position 2 plus half the pixel at pixel position 3 . Similarly, the size and position of the pixel 2' of the surface emitting element array chip 1 after resolution conversion in FIG. plus half the pixel at pixel position 4 and half the pixel at pixel position 5.

Also, the size and position of the pixel (n/2-1) of the surface emitting element array chip 1 after resolution conversion in FIG. 8(c) are as follows. That is, half of the pixel position (n-3) of the surface emitting element array chip 1 before resolution conversion in FIG. 8B, the pixel position (n-2), and the pixel position (n-1) is the size and position of half of the pixels of . Similarly, the size and position of the pixel (n/2) of the surface emitting element array chip 1 after resolution conversion in FIG. 8(c) are as follows. That is, half of the pixels at the pixel position (n−1) of the surface emitting element array chip 1 before resolution conversion in FIG. It has the size and position of half the pixel at pixel position 1 plus. The number in each pixel in FIG. 8(c) indicates the density value of each pixel. In this embodiment, it is assumed that processing is performed with the number of gradations of 8 bits after resolution conversion. Assuming that the density value of the black portion in the drawing is 100% and the density value of the white portion (including the frame portion not shown in the drawing) is 0%, the density value of each pixel is calculated from the above-described (Formula 1). Then, the density value is represented by five values of 0%, 25%, 50%, 75% and 100%. By processing the number of gradations of one pixel after resolution conversion with 3 bits or more, it is possible to perform smooth processing without causing a density step.

For example, the density value of the pixel 1' of the surface emitting element array chip 1 on the (m+3) row in FIG. Calculated. That is, density value of pixel 1′=density of pixel 1 (1)×K2 (0.25)+density of pixel 2 (1)×K1 (0.5)+density of pixel 3 (0)×K2 (0 .25)=0.75 (75%). Similarly, the density value of the pixel 2' of the surface emitting element array chip 1 on the (m+3) row in FIG. become. That is, density value of pixel 2′=density of pixel 3 (0)×K2 (0.25)+density of pixel 4 (0)×K1 (0.5)+density of pixel 5 (0)×K2 (0 .25)=0 (0%). Further, the density value of the pixel (n/2) of the surface emitting element array chip 1 in the (m+3) row in FIG. become that way. That is, density value of pixel (n/2)=density of pixel (n−1) (1)×K1 (0.25)+density of pixel (n) (1)×K1 (0.5)+surface emission The density of pixel 1 of element array chip 2 is (0)×K2(0.25)=0.751 (75%).

Further, when processing pixels at the edge of a surface emitting element array chip during filter processing, if there is no pixel data for the adjacent surface emitting element array chip, an image will be lost and an image defect will occur. Therefore, as described above, the chip data conversion unit 403 of the control board 415 adds the pixel data on the edge side of the adjacent surface emitting element array chips to arrange the image data, thereby preventing the image from missing. Filtering can be performed.

(LUT)
The subsequent LUT 410 performs data conversion by referring to a Look Up Table for image data values (density data values) for each pixel corresponding to light emitting elements in the surface emitting element array chip. The LUT 410 converts the data value for each pixel based on the response characteristics of the light emitting time of the surface emitting element array chip so that the integrated amount of light when pulsed light is emitted becomes a predetermined value. For example, when the light emitting time response of the surface emitting element array chip is slow and the integrated amount of light is smaller than the target value, data conversion is performed to increase the data value. In this embodiment, before starting image formation, the CPU 400 sets the values of the conversion table set in the lookup table to predetermined values based on experimentally obtained response characteristics of the light emitting element array. shall be

FIG. 9 is a diagram showing an example of a lookup table. The LUT 410 converts pixel data equivalent to 1200 dpi into PWM signals using any of (a) to (c). (a) to (c) are tables for converting pixel data equivalent to 1200 dpi into 8-bit PWM data. Here, "000, 001, 010, 011, 100" are pixel data equivalent to 1200 dpi indicating "density 0%, density 25%, density 50%, density 75%, density 100%" respectively. "1" of the PWM data indicates ON data (light emission data) of the LED, and "0" indicates OFF data (non-light emission data). PWM data corresponds to ΦW1 to ΦW4 described later.

(PWM signal generator, timing controller, control signal generator, drive voltage generator)
The PWM signal generator 411, which is the third generation means, generates a pulse width signal (hereinafter referred to as a PWM signal) corresponding to the light emission time of the surface emitting element array chip within one pixel section according to the data value of each pixel. to generate The timing of outputting the PWM signal is controlled by the timing control section 412 . The timing control unit 412 generates a synchronization signal corresponding to the pixel interval of each pixel from the line synchronization signal generated by the synchronization signal generation unit 406 of the control board 415 and outputs the synchronization signal to the PWM signal generation unit 411 . The drive voltage generator 414 generates a drive voltage for driving the surface emitting element array chip in synchronization with the PWM signal. The drive voltage generation unit 414 is configured so that the voltage level of the output signal can be adjusted around 5V by the CPU 400 so as to obtain a predetermined amount of light. In this embodiment, each surface emitting element array chip has a configuration capable of driving four light emitting elements independently at the same time. The drive voltage generator 414 supplies drive signals to 4 lines for each surface emitting element array chip, and 1 line (15 chips)×4=60 lines in a staggered configuration for the entire exposure head 106 . The drive signals supplied to each surface emitting element array chip are ΦW1 to ΦW4 (see FIG. 10). On the other hand, the surface emitting element array chips are sequentially driven by the operation of a shift thyristor (see FIG. 10), which will be described later. The control signal generator 413 generates control signals Φs, Φ1, and Φ2 for transferring the shift thyristors for each pixel from the synchronization signals corresponding to the pixel intervals generated by the timing controller 412 (see FIG. 10).

[Explanation of SLED circuit]
FIG. 10 is an equivalent circuit of a part of the self-scanning LED (SLED) array chip of this embodiment. In FIG. 10, Ra and Rg are anode resistance and gate resistance, respectively, Tn is a shift thyristor, Dn is a transfer diode, and Ln is a light emitting thyristor. Gn represents the common gate of the corresponding shift thyristor Tn and the light-emitting thyristor Ln connected to the shift thyristor Tn. Here, n is an integer of 2 or more. Φ1 is the transmission line of the odd-numbered shift thyristors T, and Φ2 is the transmission line of the even-numbered shift thyristors T. In FIG. ΦW1 to ΦW4 are lighting signal lines for the light-emitting thyristors L, which are connected to resistors RW1 to RW4, respectively. VGK is the gate line and Φs is the start pulse line. As shown in FIG. 10, four light-emitting thyristors L4n-3 to L4n are connected to one shift thyristor Tn, and the four light-emitting thyristors L4n-3 to L4n can be lit at the same time. It has become.

[Operation of SLED circuit]
Next, the operation of the SLED circuit shown in FIG. 10 will be described. In the circuit diagram of FIG. 10, 5V is applied to the gate line VGK, and the voltages input to the transfer lines Φ1, Φ2 and the lighting signal lines ΦW1 to ΦW4 are also 5V. In FIG. 10, when the shift thyristor Tn is in the ON state, the potential of the common gate Gn of the shift thyristor Tn and the light-emitting thyristor Ln connected to the shift thyristor Tn is lowered to about 0.2V. Since the common gate Gn of the light emitting thyristor Ln and the common gate Gn+1 of the light emitting thyristor Ln+1 are connected by the coupling diode Dn, a potential difference substantially equal to the diffusion potential of the coupling diode Dn is generated. In this embodiment, the diffusion potential of the coupling diode Dn is about 1.5 V, so the potential of the common gate Gn+1 of the light emitting thyristor Ln+1 is 0.2 V of the potential of the common gate Gn of the light emitting thyristor Ln, and 1 of the diffusion potential. It becomes 1.7V (=0.2V+1.5V) by adding 0.5V. Similarly, the potential of the common gate Gn+2 of the light-emitting thyristor Ln+2 is 3.2 V (=1.7 V+1.5 V), and the potential of the common gate Gn+3 (not shown) of the light-emitting thyristor Ln+3 (not shown) is 4.7 V (= 3.2V+1.5V). However, the potential after the common gate Gn+4 of the light-emitting thyristor Ln+4 is 5V because the voltage of the gate line VGK is 5V and cannot reach a higher voltage. Further, the potential of the common gate Gn-1 before the common gate Gn of the light-emitting thyristor Ln (to the left of the common gate Gn in FIG. 10) is the gate line potential because the coupling diode Dn-1 is in a reverse bias state. The voltage of VGK is applied as it is and becomes 5V.

FIG. 11(a) is a diagram showing the distribution of the gate potential of the common gate Gn of each light-emitting thyristor Ln when the shift thyristor Tn described above is in the ON state. , refers to the common gate of the light-emitting thyristor L in FIG. The vertical axis of FIG. 11(a) indicates the gate potential. The voltage required to turn on each shift thyristor Tn (hereinafter referred to as threshold voltage) is obtained by adding the diffusion potential (1.5 V) to the gate potential of the common gate Gn of each light emitting thyristor Ln, Almost the same potential. When the shift thyristor Tn is on, the shift thyristor Tn+2 has the lowest common gate potential among the shift thyristors connected to the transfer line Φ2 of the same shift thyristor Tn. The potential of the common gate Gn+2 of the light-emitting thyristor Ln+2 connected to the shift thyristor Tn+2 is 3.2 V (=1.7 V+1.5 V) (FIG. 11(a)) as described above. Therefore, the threshold voltage of shift thyristor Tn+2 is 4.7V (=3.2V+1.5V). However, since the shift thyristor Tn is turned on, the potential of the transfer line Φ2 is drawn to about 1.5 V (diffusion potential), which is lower than the threshold voltage of the shift thyristor Tn+2, so the shift thyristor Tn+2 is turned on. Can not do it. Other shift thyristors connected to the same transfer line Φ2 cannot be similarly turned on because their threshold voltages are higher than that of shift thyristor Tn+2, and only shift thyristor Tn can be kept on.

Regarding the shift thyristors connected to the transfer line Φ1, the threshold voltage of the shift thyristor Tn+1, which has the lowest threshold voltage, is 3.2V (=1.7V+1.5V). The next lowest threshold voltage of the shift thyristor Tn+3 (not shown in FIG. 7) is 6.2V (=4.7V+1.5V). In this state, when 5V is input to the transfer line Φ1, only the shift thyristor Tn+1 can be turned on. In this state, the shift thyristor Tn and the shift thyristor Tn+1 are turned on at the same time. Therefore, the gate potentials of shift thyristors Tn+1 to shift thyristors Tn+2, Tn+3, etc. provided on the right side in the circuit diagram of FIG. 10 are lowered by the diffusion potential (1.5 V). However, since the voltage of the gate line VGK is 5V and the voltage of the common gate of the light-emitting thyristor L is limited by the voltage of the gate line VGK, the gate potential on the right side of the shift thyristor Tn+5 is 5V. FIG. 11(b) shows the gate voltage distribution of each of the common gates Gn−1 to Gn+4 at this time, and the vertical axis represents the gate potential. In this state, when the potential of the transfer line Φ2 is lowered to 0V, the shift thyristor Tn is turned off, and the potential of the common gate Gn of the shift thyristor Tn rises to the VGK potential. FIG. 11(c) is a diagram showing the gate voltage distribution at this time, and the vertical axis indicates the gate potential. Thus, the ON state transfer from the shift thyristor Tn to the shift thyristor Tn+1 is completed.

[Light emitting operation of light emitting thyristor]
Next, the light emitting operation of the light emitting thyristor will be described. When only the shift thyristor Tn is turned on, the gates of the four light emitting thyristors L4n-3 to L4n are commonly connected to the common gate Gn of the shift thyristor Tn. Therefore, the gate potential of the light-emitting thyristors L4n-3 to L4n is 0.2 V, which is the same as the common gate Gn. Therefore, the threshold value of each light-emitting thyristor is 1.7V (=0.2V+1.5V). L4n-3 to L4n can be lit. Therefore, by inputting lighting signals to the lighting signal lines ΦW1 to ΦW4 while the shift thyristor Tn is on, the four light emitting thyristors L4n-3 to L4n can be selectively caused to emit light. It is possible. At this time, the potential of the common gate Gn+1 of the shift thyristor Tn+1 adjacent to the shift thyristor Tn is 1.7 V, and the threshold voltage of the light-emitting thyristors L4n+1 to 4n+4 gate-connected to the common gate Gn+1 is 3.2 V (= 1.7V+1.5V). Since the lighting signal input from the lighting signal lines ΦW1 to ΦW4 is 5V, it is likely that the light emitting thyristors L4n+1 to L4n+4 will also light in the same lighting pattern as the light emitting thyristors L4n−3 to 4n. However, since the light-emitting thyristors L4n−3 to L4n have lower threshold voltages, they turn on earlier than the light-emitting thyristors L4n+1 to L4n+4 when the lighting signal is input from the lighting signal lines ΦW1 to ΦW4. Once the light-emitting thyristors L4n-3 to L4n are turned on, the connected lighting signal lines ΦW1 to ΦW4 are pulled down to approximately 1.5 V (diffusion potential). Therefore, the potentials of the lighting signal lines ΦW1 to ΦW4 become lower than the threshold voltages of the light emitting thyristors L4n+1 to L4n+4, so that the light emitting thyristors L4n+1 to L4n+4 cannot be turned on. By connecting a plurality of light-emitting thyristors L to one shift thyristor T in this manner, the plurality of light-emitting thyristors L can be lit simultaneously.

FIG. 12 is a timing chart of drive signals for the SLED circuit shown in FIG. FIG. 12 shows voltage waveforms of driving signals of the gate line VGK, the start pulse line Φs, the transmission lines Φ1 and Φ2 of the odd-numbered and even-numbered shift thyristors, and the lighting signal lines ΦW1 to ΦW4 of the light-emitting thyristors in order from the top. there is Each drive signal has a voltage of 5V when turned on and a voltage of 0V when turned off. Moreover, the horizontal axis of FIG. 12 indicates time. Also, Tc indicates the period of the clock signal Φ1, and Tc/2 indicates a period half (=1/2) of the period Tc.

5V is always supplied to the gate line VGK. The clock signal Φ1 for the odd-numbered shift thyristors and the clock signal Φ2 for the even-numbered shift thyristors are input at the same period Tc, and the signal Φs of 5V is supplied to the start pulse line. Shortly before the clock signal Φ1 for the odd-numbered shift thyristors first goes to 5V, the signal Φs on the start pulse line is dropped to 0V to create a voltage difference on the gate line VGK. As a result, the gate potential of the first shift thyristor Tn-1 is pulled from 5V to 1.7V, the threshold voltage becomes 3.2V, and the shift thyristor Tn-1 becomes ready to be turned on by a signal from the transfer line Φ1. A voltage of 5 V is applied to the transfer line Φ1, and after a short delay after the first shift thyristor Tn−1 is turned on, 5 V is supplied to the start pulse line Φs, and thereafter 5 V is supplied to the start pulse line Φs. continue.

The transfer line Φ1 and the transfer line Φ2 have a time Tov during which their ON states (here, 5 V) overlap, and are configured to have a substantially complementary relationship. The light-emitting thyristor lighting signal lines ΦW1 to ΦW4 are transmitted at half the cycle of the transmission lines Φ1 and Φ2, and are lit when 5 V is applied while the corresponding shift thyristors are in the ON state. For example, in period a, all four light-emitting thyristors connected to the same shift thyristor are lit, and in period b, three light-emitting thyristors are simultaneously lit. Further, all the light-emitting thyristors are turned off during period c, and two light-emitting thyristors are simultaneously turned on during period d. Only one light-emitting thyristor is lit during period e.

In this embodiment, the number of light-emitting thyristors connected to one shift thyristor is four, but the number is not limited to this, and may be less or more than four depending on the application. In the circuit described above, the circuit in which the cathodes of the thyristors are shared has been described, but the anode common circuit can also be applied by appropriately reversing the polarity.

[Structure of Surface Emitting Thyristor]
FIG. 13 is a schematic diagram of the surface emitting thyristor section of this embodiment. FIG. 13A is a plan view (schematic diagram) of a light-emitting element array in which a plurality of light-emitting elements formed in a mesa (trapezoidal) structure 922 are arranged. FIG. 13(b) is a schematic cross-sectional view of the light emitting element formed in the mesa structure 922 taken along line BB shown in FIG. 13(a). The mesa structures 922 formed with light emitting elements are arranged at a predetermined pitch (interval between light emitting elements) (for example, about 21.16 μm in the case of a resolution of 1200 dpi), and each mesa structure 922 has an element isolation groove. are separated from each other by 924 .

In FIG. 13(b), 900 is a compound semiconductor substrate of the first conductivity type, 902 is a buffer layer of the same first conductivity type as the substrate 900, and 904 is a stack of two types of semiconductor layers of the first conductivity type. Distributed Bragg Reflector (DBR) layer. 906 is a first first conductivity type semiconductor layer, 908 is a first second conductivity type semiconductor layer different from the first conductivity type, 910 is a second first conductivity type semiconductor layer, and 912 is a second conductivity type semiconductor layer. It is a second conductivity type semiconductor layer. As shown in FIG. 13B, semiconductor layers 906, 908, 910, and 912 of different conductivity types are alternately stacked to form a pnpn-type (or npnp-type) thyristor structure. In this embodiment, the substrate 900 is an n-type GaAs substrate, the buffer layer 902 is an n-type GaAs or n-type AlGaAs layer, and the DBR layer 904 is an n-type high Al composition AlGaAs layer and a low Al composition AlGaAs layer. A laminated structure of AlGaAs is used. The first first conductivity type semiconductor layer 906 on the DBR layer is n-type AlGaAs, the first second conductivity type semiconductor layer 908 is p-type AlGaAs, and the second first conductivity type semiconductor layer 910 is n-type AlGaAs. Type AlGaAs, p-type AlGaAs is used for the second second conductivity type semiconductor layer 912 .

In addition, in the mesa structure type surface light emitting device, a current constriction mechanism is used to prevent the current from flowing to the side surface of the mesa structure 922, thereby improving the luminous efficiency. Here, the current constriction mechanism in this embodiment will be described. As shown in FIG. 13(b), in this embodiment, a p-type GaP layer 914 is formed on the p-type AlGaAs that is the second second conductivity type semiconductor layer 912, and an n-type layer is further formed thereon. An ITO layer 918, which is a transparent conductor, is formed. The p-type GaP layer 914 is formed with a sufficiently high impurity concentration in the portion in contact with the transparent conductive ITO layer 918 . When a forward bias is applied to the light-emitting thyristor (for example, when the back electrode 926 is grounded and the front electrode 920 is applied with a positive voltage), the p-type GaP layer 914 is partially in contact with the transparent conductor ITO layer 918 . Since the impurity concentration is sufficiently high, it becomes a tunnel junction. As a result, current flows. With such a structure, the p-type GaP layer 914 concentrates current in the portion in contact with the n-type transparent conductor ITO layer 918, forming a current constriction mechanism. Note that an interlayer insulating layer 916 is provided between the ITO layer 918 and the p-type AlGaAs layer 912 in this embodiment. However, the attached diode formed of the n-type ITO layer 918 and the p-type AlGaAs layer 912 is reverse biased with respect to the forward bias of the light emitting thyristor, and when forward biased, the diode other than the tunnel junction is basically current does not flow to Therefore, if the reverse withstand voltage of the attached diode formed of the n-type ITO layer 918 and the p-type AlGaAs layer 912 is sufficient for the application, it may be omitted. With such a configuration, the lower semiconductor lamination portion of the portion substantially equivalent to the portion where the p-type GaP layer 914 and the n-type transparent conductor ITO layer 918 contact each other emits light, and most of the emitted light is emitted by the DBR layer 904. 900 is reflected to the opposite side.

In the exposure head 106 of this embodiment, the density of light emitting points (interval between light emitting elements) is determined according to the resolution. Each light emitting element inside the surface emitting element array chip is separated into a mesa structure 922 by an element separating groove 924. For example, when forming an image with a resolution of 1200 dpi, the distance between the element centers of adjacent light emitting elements (light emitting points) is are arranged to be 21.16 μm.

Data transfer between the control board 415 and the drive board 202, which characterizes the present invention, will be described below.

[Transfer format of data transmission unit and data reception unit]
FIG. 14(a) is a diagram showing the configuration of the data transmission section 405. As shown in FIG. Data transmission section 405 has transmission format conversion section 1101 as a first conversion section and LVDS transmission section 1102 as a transmission section. A transmission format conversion unit 1101 executes encoding processing in which the order of pixel data is rearranged, and converts the pixel data into a signal. The transmission format conversion unit 1101 performs encoding for rearranging the pixel data in an order that is not in the order in which the surface emitting element array chips are arranged in the cross direction and is not in the pixel order corresponding to the order in which the light emitting elements are arranged in the cross direction. Execute the process.

FIG. 14B is a diagram showing the configuration of the data receiving section 407. As shown in FIG. Data receiver 407 has LVDS receiver 1201 as a receiver and reception format converter 1202 as a second converter. A reception format conversion unit 1202 executes decoding processing to restore pixel data from the signal received by the LVDS reception unit 1201 . The reception format conversion unit 1202 converts the pixel data encoded by the transmission format conversion unit 1101 into the order of arrangement of the pixel data in the order of arrangement in the intersecting direction of the surface emitting element array chips and the order of arrangement in the intersecting direction of the light emitting elements. Restore in corresponding pixel order.

FIG. 15(a) is a block diagram of the data transmission unit 405 and the data reception unit 407 and a diagram showing a connection state, and shows a channel link SerDes. Each channel transmits signals so that the phases thereof are opposite to each other through two signal lines forming a pair. In FIG. 15A, the signal is directly connected from the differential transmission section 1303 to the differential reception section 1304, but the detailed connection configuration is omitted for explanation. 4, the connection from the data transmission unit 405 to the data reception unit 407 is from the connector 416 to the connector 305 via cables 417, 418, and 419. FIG.

LVDS transmission section 1102 has parallel-serial conversion section 1301 , PLL 1302 , and differential transmission section 1303 . The parallel-serial converter 1301 converts a 21-bit input signal (parallel signal) into a serial signal. The PLL 1302 adjusts the phase of the input clock signal (hereinafter referred to as CLK signal). A differential transmission unit 1303 transmits the parallel-serial converted signal as a differential signal. LVDS receiver 1201 has differential receiver 1304 , PLL 1305 , and serial-parallel converter 1306 . Differential receiver 1304 receives the serial signal from differential transmitter 1303 . The PLL 1305 generates a CLK signal by multiplying the received CLK signal by 7, for example. A serial-parallel converter 1306 converts the serial signal into a 21-bit parallel signal. Hereinafter, the LVDS transmission unit 1102 and the LVDS reception unit 1201 of the embodiment will be described as a configuration using channel link SerDes for transmitting and receiving 21-bit data through three pairs of LVDS channels and one pair of clock lines. Here, LVDS means Low-Voltage Differential Signaling.

FIG. 15(b) shows the bit arrangement of the differential clock and differential data (corresponding to a 21-bit input signal) transferred from the differential transmission section 1303. FIG. The array in FIG. 15(b) is the format of a general channel link SerDes. Each of the three pairs of LVDS channels (TA±, TB±, TC±) is multiplexed with 7-bit data. The relationship between the 21-bit input signal input to the LVDS transmission unit 1102 and the bit arrangement of the parallel-serial converted signal is as follows. Packages will be discussed later.
TA±: Input data 20-14 bits correspond to A6-A0 TB±: Input data 13-bits-7 bits correspond to B6-B0 TC±: Input data 6-0 bits correspond to C6-C0 corresponds to

[Block configuration of transmission format converter]
A transmission format conversion unit 1101 converts the pixel arrangement of image data divided for each surface emitting element array chip, and serial-parallel converts the converted image data. Hereinafter, an example of a configuration in which light emitting elements each composed of 516 elements of each surface emitting element array chip are lit simultaneously in units of 6 elements for the surface emitting element array chips 1 to 15 shown in FIG. 3(a) will be described. do.

FIG. 16A shows a diagram in which each part (only the main part is drawn) in FIG. 4 and the resolution of the image data of the embodiment are associated with each other. The longitudinal pitch of the light emitting elements in the example corresponds to a resolution of 1200 dpi as described above. Image data (line data) of 2400 dpi is transferred from the control board 415 and the resolution is converted to 1200 dpi image data by the filtering section 408 of the driving board 202 . The image data input to the transmission format conversion unit 1101 of the data transmission unit 405 is image data corresponding to a resolution of 2400 dpi. is. Therefore, the LVDS transmission unit 1102 of the data transmission unit 405 needs to transfer image data corresponding to the number of pixels twice the number of simultaneously lit light emitting elements. As shown in FIG. 16A, in the embodiment, image data corresponding to a resolution of 2400 dpi is transmitted up to the filter processing unit 408 of the drive board 202, and after the resolution conversion is executed by the filter processing unit 408, the resolution is reduced to 1200 dpi. image data corresponding to is transmitted. In the following description, it is assumed that one pixel corresponds to 1-bit data.

In the LVDS transmission unit 1102, in order to simultaneously turn on the six light emitting elements of the surface emitting element array chips 1 to 15, it is necessary to transfer 180 bits (15 chips×6 elements×2) of image data. The LVDS transmission unit 1102 also transfers the Line synchronization signal in addition to the image data. The Line synchronizing signal is transferred, for example, corresponding to the bit position of A6 shown in FIG. 15(b). The LVDS transmitter 1102 can transfer 21-bit data in one cycle of the CLK signal output from the PLL 1302 . The 21-bit data means the data of A0 to A6, B0 to B6, and C0 to C6 in FIG. 15(b), and hereinafter, the 21-bit data is expressed as a package as one unit. That is, one package consists of 21-bit data.

FIG. 16B is a diagram showing an example of transferring data of 10 packages (=21 bits×10=210 bits). In one package of 21-bit data, 18 bits are assigned to image data, 1 bit to Line synchronization signals, and 2 bits to spare data. Therefore, the amount of pixel data that can be transferred in one transfer is 18 pixels. When transferring 10 packages configured in this manner, a total of 210-bit data can be transferred. As described above, 180 bits are required to light each of the 6 light emitting elements of the surface emitting element array chips 1 to 15 at the same time. become. That is, by performing the data transfer of the package shown in FIG. 15(b) ten times, the six light emitting elements corresponding to the six pixels of the surface light emitting element array chips 1 to 15 can be lit simultaneously.

18-bit image data in one package are assigned to positions A0 to A3, B0 to B6, and C0 to C6 shown in FIG. assigned to. Also, the value of each position is replaced with a fixed value ('0' or '1') or other data in one package. FIG. 16(b) shows a diagram explaining allocation of 21-bit data for each package when data transfer is performed 10 times.

[Assignment processing of image data in data transmission unit]
Next, allocation processing of image data for 180-bit data transmitted in the transfer of 10 packages performed by the transmission format conversion unit 1101 will be described. FIG. 17 is a flow chart for explaining the control method of the image forming apparatus of the embodiment. The processing of FIG. 17 corresponds to the processing of transmission format conversion section 1101 . Each step is realized by executing the stored control program by the CPU 400 . 18 is a block configuration of transmission format conversion section 1101 of data transmission section 405. As shown in FIG. Each block will be described in accordance with the processing in FIG.

As shown in FIG. 18 , transmission format conversion section 1101 has data acquisition section 1800 , rearrangement section 1803 , and transmission signal formation section 1805 . The data acquisition unit 1800 has a buf1_a unit 1801 and a buf1_b unit 1802 . Rearrangement section 1803 has buf2 section 1804 . Transmission signal forming section 1805 has buf3 section 1806 .

In step (hereinafter referred to as S) 1700, the data acquisition unit 1800 of the transmission format conversion unit 1101 receives the image data (line data) (12 bits (bit)×1 surface emitting element array chip (chip)) from the chip data shift unit 404. to 15). As described above, the data acquisition unit 1800 acquires 15 surface emitting element array chips, that is, 180 bits of 12-bit data necessary for simultaneously lighting six light emitting elements.
The data acquisition unit 1800 stores the 180-bit image data input from the chip data shift unit 404 in the buf1_a unit 1801 and the buf1_b unit 1802 in the order of the surface emitting element array chips 1 to 15 and in the image arrangement order. Here, the data acquisition unit 1800 acquires image data for 12 pixels each (6 pixels×2) from the image data (516 pixels each×2: 2400 dpi). The data acquisition unit 1800 obtains the above-described image from image data (each 516 pixels x 2: 2400 dpi) obtained by dividing the image data whose positional deviation in the sub-scanning direction has been adjusted by the chip data shift unit 404 into units of surface emitting element array chips. Get data.

FIG. 19(a) is a diagram for explaining the pixel arrangement of the divided surface emitting element array chips 1 to 15, and is a diagram showing data stored in the chip data shift unit 404 (chip divided image data). Chip1 to chip15 indicate surface emitting element array chips 1 to 15. FIG. Chip[0] to chip[1031] correspond to 1032 pixels. In addition, 1 to 86 indicate block numbers (1032/12=86) obtained by dividing 1032 pixels (=512×2) into 12-pixel (12-bit) units. are written as chip1[1] to chip1[86]. Further, for example, 12 pixels in one block obtained by dividing 1032 pixels of the surface emitting element array chip 1 into 86 are described as chip1_pix[0] to chip1_pix[11].

The chip data conversion unit 403 divides the image data into surface emitting element array chip units. The chip data shifter 404 adjusts the positional deviation in the sub-scanning direction of the surface emitting array chips arranged in a zigzag pattern. The image data subjected to such processing by the chip data shifter 404 are each 516 pixels×2 (=1032 pixels). Therefore, when the data acquisition unit 1800 acquires the image data of one surface emitting element array chip in units of 12 pixels, the entire image for 1 to 15 minutes of the surface emitting element array chip can be obtained by acquiring 86 times (=1032/12). Data acquisition becomes possible.

Here, assuming that "*" represents "1" and "15" of the surface emitting element array chips 1 to 15, the character strings in FIG. 19(a) mean the following. For example, numbers in parentheses such as chip*[1] to chip*[86] mean the number of acquisition times of image data in units of 12 pixels. Also, for example, chip*_pix[1] to chip*_pix[11] are position information indicating the order of pixels input to the data acquisition unit 1800 . Specifically, the data acquisition unit 1800 of the transmission format conversion unit 1101 acquires the pixel position from the image data corresponding to each of the surface emitting element array chips 1 to 15 for every 12 pixels based on the following (Equation 2). , the range (chip*_pix) is determined.
chip*_pix[12×(n−1)] to chip*_pix[12×n−1] (Equation 2)
Here, * denotes the surface emitting element array chips 1 to 15. Also, n represents the number of times 12 pixels have been acquired (n=1 to 86), and is counted up by +1 until all image data of each surface emitting element array chip is acquired in S1704. For example, when the number of acquisitions for 12 pixels is 1 (n=1), chip*_pix[0] to chip*_pix[11] are obtained, and the data for the 0th to 11th pixels of each surface emitting element array chip is is obtained. Data for 12 pixels in the range obtained by (Equation 2) are obtained for 1 to 15 pixels of the surface emitting element array chip in one process.

FIG. 19B is a diagram illustrating a method of storing image data in the buf1_a section 1801 and the buf1_b section 1802, which is the processing of the data acquisition section 1800. As shown in FIG. The data acquisition unit 1800 stores the 12-pixel image data acquired from the chip data shift unit 404 in the buf1_a unit 1801 and the buf1_b unit 1802, which are arrays for storing the image data in the order of the surface emitting element array chip and in the order of the pixel arrangement. . The array has two parts, a buf1_a portion 1801 and a buf1_b portion 1802 . According to an instruction from the CPU 400, the data acquisition unit 1800 stores the image data in the buf1_a unit 1801 when the number of acquisitions of 12-pixel image data among the 180-bit image data (hereinafter referred to as the number of acquisitions) is an odd number. . The data acquisition unit 1800 stores the image data in the buf1_b unit 1802 when the number of acquisitions of image data of 12 pixels is an even number. In this embodiment, 12 pixels of each of the surface emitting element array chips 1 to 15 are stored in the buf1_a section 1801 and the buf1_b section 1802 when the acquisition times n are 1 and 2, respectively. With respect to buf1_a[0] to buf1_a[179] and buf1_b[0] to buf1_b[179], the order of surface emitting element array chips 1 to 15 and the order of pixels are arranged in ascending order (buf1_a section 1801, buf1_b section 1802 ).

It should be noted that storage control to the array (buf1_a portion 1801, buf1_b portion 1802) is performed each time image data for 180 pixels is stored. Image data for 12 pixels of each of the surface emitting element array chips 1 to 15 corresponding to the number of image data acquisition times (1 to 86) are sequentially stored in the buf1_a section 1801 and the buf1_b section 1802 . Therefore, the buf1_a portion 1801 and the buf1_b portion 1802 alternately store data for 180 pixels. The above is the processing of S1700.

In step S<b>1701 , the rearrangement unit 1803 of the transmission format conversion unit 1101 rearranges the image array according to an instruction from the CPU 400 . When data for 180 pixels is stored in the buf1_a portion 1801 or buf1_b portion 1802, the rearrangement unit 1803 sorts the stored image data for the 180 pixels in a predetermined order that is neither the surface light emitting element array chip order nor the pixel order. Sort image data according to rules. The rearranged image data is stored in the buf2 section 1804 of the rearrangement section 1803 . FIG. 20(a) shows an example in which the image data of 180 pixels are rearranged in an array that is neither in the order of surface emitting element array chips nor in the order of pixels. buf2[0] to buf2[179] indicate the 180 storage areas of the buf2 portion 1804 . For example, buf2[0] stores chip6_pix[4], which is the fifth image data of 1032 pixels for the surface emitting element array chip 6 . Also, for example, buf2[17] stores chip9_pix[2], which is the third image data of 1032 pixels for the surface emitting element array chip 9 .

Further, the predetermined rule, which is neither the order of surface emitting element array chips nor the order of pixels, is, for example, the following rule. This rule is obtained by randomly rearranging the data array of 180 pixels in advance in order of surface emitting element array chip and pixel order using an external tool or the like, and the arrangement is irregular. Specific rules can be generated using spreadsheet software, etc. Values generated using the RAND function or the like that generates random numerical values for 180 pixels arranged in the order of surface emitting element array chips and in the order of pixels. are assigned to 180 pixels one by one, and rearranged in ascending or descending order. As a result, the rearrangement unit 1803 generates a random rearrangement rule. Therefore, this rule is fixed once the rearrangement arrangement is determined. It should be noted that other tools may be used to create a random arrangement.

In step S1702, the transmission signal formation unit 1805 of the transmission format conversion unit 1101 extracts 18 pixels corresponding to the data for one transfer from the data (buf2 unit 1804) whose arrangement of the image data has been rearranged by the rearrangement unit 1803. Get image data every time. Specifically, transmission signal formation section 1805 of transmission format conversion section 1101 determines a predetermined range based on (Equation 3), and acquires data for every 18 pixels according to the number of transfers.
buf2[18×(i−1)] to buf2[18×i−1] (equation 3)
It should be noted that i is the number of transfers and starts from 1.

In S1703, the transmission signal formation section 1805 of the transmission format conversion section 1101 refers to the value of the number i of transfers and determines whether or not 10 transfers have been performed. If the transmission signal forming unit 1805 of the transmission format conversion unit 1101 determines in S1703 that 10 transfers have not been performed, the processing returns to S1702, and i is incremented by +1 each time image data is transferred. (i=i+1). If transmission signal formation section 1805 of transmission format conversion section 1101 determines in S1703 that 10 transfers have been performed, the process advances to S1704.

Also, the LVDS transmission unit 1102 is a channel link SerDes, which has a format for transferring 21-bit data as described above. Therefore, the transmission format conversion unit 1101 forms 21-bit data by adding 2-bit preliminary data and a 1-bit Line synchronization signal to 18 pixels (1 pixel: 1 bit) of image data at a specific array position. (See FIG. 16(b)). LVDS transmission section 1102 transfers the 21-bit data formed by transmission format conversion section 1101 .

FIG. 20B is a diagram for explaining buf3 section 1806 when 3-bit data is added in transmission signal formation section 1805 of transmission format conversion section 1101 . In the example of FIG. 20B, the transmission signal forming unit 1805 converts 18-bit image data (buf2[18×(i−1)] to buf2[18×i−1]) into buf3[0] to buf3[ 17]. In addition, transmission signal forming section 1805 adds preliminary data to buf3[18] and buf3[19], and adds the Line synchronization signal to buf3[20]. In the following description, it is assumed that 21-bit data is transferred in the arrangement of the buf3 unit 1806 in FIG. 20(b).

In S1704, the CPU 400 determines whether all image data (516 pixels×2) corresponding to the surface emitting element array chips 1 to 15 have been acquired (acquisition status). If the CPU 400 determines in S1704 that all the image data of 516 pixels×2 of the surface emitting element array chips 1 to 15 have not been acquired, the process returns to S1700. If the CPU 400 determines in S1704 that all 516 pixels×2 of the surface emitting element array chips 1 to 15 have been acquired, the series of processing ends.

The control described above with reference to FIG. 17 indicates the processing for the surface emitting element array chips 1 to 15 among the surface emitting element array chips 1 to 29 . However, similar circuits are configured for the remaining surface emitting element array chips 16-29, and similar processing is performed in parallel with the processing for the surface emitting element array chips 1-15. Also, control for one line of input image data is shown, and in practice, control of the number of input lines is repeatedly executed according to instructions from the CPU 400 in accordance with the processing of S1700 to S1703.

[Description of reception format conversion part]
FIG. 21(a) is a block configuration of the data receiving section 407. FIG. The data reception section 407 has an LVDS reception section 1201 and a reception format conversion section 1202 . The reception format conversion section 1202 has a data acquisition section 2200 and a rearrangement section 2203 . The data acquisition unit 2200 has a buf4_a unit 2201 and a buf4_b unit 2202 . The rearrangement section 2203 has a buf5 section 2204 .

The LVDS receiver 1201 of the data receiver 407 receives the serial signal transmitted from the differential transmitter 1303 by the differential receiver 1304 (see FIG. 15A). Then, in the serial-parallel converter 1306, it is converted into parallel signals in the arrangement (buf3 unit 1806) described in FIG. 20(b).

Data acquisition section 2200 of reception format conversion section 1202 stores the lower 18 bits of the 21-bit data output from LVDS reception section 1201 in 180-bit buffers (buf4_a section 2201 and buf4_b section 2202). FIG. 21B is a diagram showing a method of storing 180-bit image data obtained by ten transfers in the data acquisition section 2200 of the reception format conversion section 1202. As shown in FIG. The data acquisition unit 2200 stores the received image data in the buf4_a unit 2201 and the buf4_b unit 2202 in order of the number of transfers from the lower bit so that the data is arranged in the order described in FIG.

Note that the storage of the image data in the buf4_a section 2201 and the buf4_b section 2202 is performed alternately each time a counter (not shown) provided in the data acquisition section 2200 and incremented by +1 every 10 transfers is counted up. The storage destination is switched to . For example, when 180-bit image data is stored in the buf4_a section 2201 , the storage destination of the image data is switched to the buf4_b section 2202 . As a result, the next 18-bit image data is stored in the buf4_b portion 2202, and is sequentially stored in the buf4_b portion 2202 until 180-bit image data is finally stored. During this time, the rearrangement section 2203 of the reception format conversion section 1202 rearranges the image data stored in the buf4_a section 2201 . When the 180-bit image data is stored in the buf4_b section 2202, the storage destination of the image data is switched to the buf4_a section 2201 again. Then, 18-bit image data is sequentially stored in the buf4_a portion 2201 until 180 bits are stored. During this time, the rearrangement section 2203 of the reception format conversion section 1202 rearranges the image data stored in the buf4_b section 2202 .

The rearrangement unit 2203 of the reception format conversion unit 1202 performs the following processing on the image data of the buf4_a portion 2201 or the buf4_b portion 2202 storing 180-bit image data. Rearranging section 2203 performs inverse conversion of the rules converted by transmission format converting section 1101 (random arrangement in FIG. 20(a)). The rearrangement unit 2203 restores image data of 12 pixels for each of the surface emitting element array chips 1 to 15 (arrangement in FIG. 19), and stores the restored image data in the buf5 unit 2204 . The reception format conversion unit 1202 generates a line synchronization signal from the most significant bit of the 21-bit data, and the timing control unit 412 adjusts the timing of the generated line synchronization signal with respect to the image data.

[Effect of Example]
FIG. 22(a) is a conventional graph when the transmission format conversion unit 1101 transfers screen image data in the order of surface emitting element array chips and in the order of pixels (arrangement in FIG. 19(b)). FIG. 22( a ) shows the FFT (Fast Fourier Transform) analysis results for data transferred between the connector 416 and the connector 305 . The screen image data is image data of 2400 dpi and 190 lines. In FIG. 22(a), the horizontal axis indicates frequency [MHz], and the vertical axis indicates amplitude. As shown in FIG. 22(a), when image data is transferred in the order of surface emitting element array chips and in the order of pixels, there are frequencies with large amplitude especially in the low frequency region, which can become radiation noise sources.

On the other hand, FIG. 22(b) shows the FFT analysis result for the data transferred between the connector 416 and the connector 305 when the image data is transferred in the order neither in the surface emitting element array chip order nor in the pixel order of this embodiment. The horizontal axis and vertical axis of FIG. 22(b) are the same as those of FIG. 22(a). As shown in FIG. 22(b), the repetition period due to the image pattern is dispersed, the amplitude becomes small especially in the low frequency region, and there is an effect of suppressing the radiation noise source. Note that the FFT analysis in FIG. 22 uses a sampling frequency of 80 MHz and 8192 samples.

As described above, according to the processing of the present embodiment, the data transmission unit 405 rearranges the image data in an order neither in order of surface emitting element array chips nor in order of pixels, and transfers the data. As a result, noise factors in the input image pattern can be dispersed as shown in FIG. 22(b). Therefore, radiation noise in data transfer can be reduced, and the quality of the image forming apparatus can be improved. In addition, since the number of components for dealing with radiation noise can be reduced, cost reduction can be achieved.

As described above, according to the embodiments, the radiation noise can be reduced regardless of the pattern of the input image data.

Note that in FIG. 4, the CPU 400, the integrated circuit 401A, and the integrated circuit 402A may be included in one integrated circuit. Further, the CPU 400 and the integrated circuits 401A and 402A may be different integrated circuits.

[Modification of FIG. 4]
As a modified example 1 of FIG. 4, for example, as shown in FIG.
As a modification 2 of FIG. 4, for example, as shown in FIG. In this case, the resolution is converted from 2400 dpi to 1200 dpi on the control board 415 side. However, even with these configurations, when transferring image data equivalent to 1200 dpi, there is a configuration in which the image data is rearranged in an order that is not the order of the surface emitting element array chips and that is not the order of the pixels. can be applied.

202 drive board 415 control board 1101 transmission format converter 1102 LVDS transmitter 1201 LVDS receiver 1202 reception format converter

Claims (7)

a photosensitive member that is rotationally driven;
an exposure head having a chip having a plurality of light emitting elements for exposing the photoreceptor, wherein the plurality of chips are arranged at different positions in a cross direction crossing the rotation direction of the photoreceptor;
generating pixel data corresponding to each pixel corresponding to a second resolution higher than the first resolution based on input image data in order to drive the plurality of light emitting elements of the plurality of chips; a first generating means;
and forming an image of the first resolution corresponding to the arrangement interval of the plurality of light emitting elements in the cross direction,
a first conversion unit that acquires the pixel data generated by the first generation means, executes an encoding process in which the order of arrangement of the pixel data is rearranged, and converts the pixel data into a signal;
a transmitter that transmits the signal converted by the first converter;
a control board on which the first generation means, the first conversion unit, and the transmission unit are mounted;
a receiving unit that receives the signal transmitted from the transmitting unit;
a second conversion unit that performs decoding processing for restoring the pixel data from the signal received by the reception unit;
a driving unit that drives the plurality of light emitting elements of the plurality of chips based on the pixel data restored by the second conversion unit;
a driving substrate on which the receiving section, the second converting section, and the driving section are mounted;
a cable connecting the control board and the drive board, the cable transmitting the signal;
with
The first conversion unit divides the pixel data generated by the first generation means into a plurality of blocks in units of a predetermined number of pixels for each of the plurality of chips, and divides the pixel data into a plurality of blocks with the same block numbers of the plurality of chips. The arrangement order of all pixel data in the block is not arranged in the order of the chips in the cross direction and is not in order of pixels corresponding to the arrangement order of the light emitting elements in the block in the cross direction. perform the encoding process,
The second conversion unit converts the pixel data encoded by the first conversion unit to the order of arrangement of the pixel data in the order of arrangement of the chips in the cross direction and the order of arrangement of the light emitting elements in the cross direction. An image forming apparatus, wherein restoration is performed in pixel order corresponding to the arrangement order in the image forming apparatus. 2. The image forming apparatus according to claim 1, wherein the first conversion unit encodes the pixel data by randomly arranging the pixel data. 3. The image forming apparatus according to claim 1, wherein data transfer between said transmitting section and said receiving section is performed by a small-amplitude differential signaling system. a second generating means for generating a periodic signal for one line corresponding to the resolution in the rotational direction of the photoreceptor;
4. The image forming apparatus according to claim 3, wherein the first conversion unit converts data including the pixel data and the periodic signal generated by the second generation unit into the signal. The first conversion unit converts the pixel data rearranged in an order that is not in the order in which the chips are arranged in the cross direction and in a pixel order that does not correspond to the order in which the light emitting elements are arranged in the cross direction, through the cable. 5. The image forming apparatus according to claim 4 , wherein the data is divided into the number of bits that can be transferred in a single transfer through the network. The transmission unit includes a parallel-serial conversion unit that converts the signal converted by the first conversion unit from a parallel signal to a serial signal, and a cable that transmits the serial signal converted by the parallel-serial conversion unit. 6. The image forming apparatus according to any one of claims 3 to 5 , further comprising a differential transmission unit that transmits data via a differential transmission unit. The receiving unit includes a differential receiving unit that receives the serial signal transmitted from the differential transmitting unit via the cable, and converts the serial signal received by the differential receiving unit into the parallel signal. 7. The image forming apparatus according to claim 6 , further comprising a serial-parallel converter.

Images