JP7130455B2 - image forming device - Google Patents

Description

The present invention relates to an electrophotographic image forming apparatus.

2. Description of the Related Art In printers, which are electrophotographic image forming apparatuses, a method of forming a latent image by exposing a photosensitive drum using an exposure head is generally known. For the exposure head, an LED (Light Emitting Diode), an organic EL (Oganic Electro Luminescence), or the like is used. The exposure head is composed of a row of light emitting elements arranged in the longitudinal direction of the photosensitive drum and a rod lens array that forms an image of the light from the row of light emitting elements on the photosensitive drum. LEDs and organic ELs are known to have a surface emitting shape in which the direction of light emitted from the light emitting surface is the same as that of the rod lens array. Here, the length of the light emitting element row is determined according to the width of the image area on the photosensitive drum, and the interval between the light emitting elements is determined according to the resolution of the printer. For example, for a 1200 dpi printer, the pixel spacing is 21.16 μm, so the spacing between light emitting elements also corresponds to 21.16 μm. A printer using such an exposure head uses fewer parts than a laser scanning printer that scans a photosensitive drum with a laser beam deflected by a rotating polygonal mirror, resulting in a smaller device. , the cost can be easily reduced. Also, in a printer using an exposure head, noise caused by the rotation of a rotating polygonal mirror is reduced.

In a configuration using such an exposure head, since the exposure head has a large number of light emitting elements, the number of signal lines for transmitting data between the controller section and the exposure head is enormous in order to light each light emitting element of the exposure head. becomes. For this reason, a method is generally known in which a data communication module for serializing image data and transmitting/receiving it is used as an interface unit between a controller unit that outputs image data and an exposure head. For example, Patent Document 1 describes a method of multiplexing and transmitting image data for controlling light emission timing of a plurality of light emitting elements, and generating a signal corresponding to the light emission pulse width of each light emitting element on the receiving side. .

Japanese Patent No. 4432920

However, when the controller unit transmits image data to the exposure head and the exposure head side generates a pulse signal corresponding to the pulse width corresponding to the light emission amount of the light emitting element, the communication speed between the controller unit and the exposure head is , increases in proportion to the amount of data sent and received. For example, if the controller unit increases the number of gradations of one pixel in order to improve the image quality such as the gradation of the image, the amount of data to be sent and received will increase. an increase in

The image data transfer speed (unit: Hz), which is the communication speed between the controller section and the exposure head, can be calculated by the following (Equation 1).

Transfer rate = (number of surface emitting elements x number of gradations)/(one line cycle x number of data lines) (Formula 1)
Here, the number of surface light emitting elements is the number of light emitting elements that the exposure head has, and the number of gradations is the number of bits for expressing the gradation of one pixel (for example, 1 bit in the case of binary), and the period of one line. is the time for exposing one line of the photosensitive drum in the main scanning direction. The number of data wirings is the number of signal lines for transferring image data between the controller section and the exposure head. For example, in the case of an exposure head that prints in binary (0, 1), the 1-line period TL is 100 μs (microseconds), the number of surface emitting elements is 14,964 (1200 dpi, image width is about 316 mm), and the number of data wiring is is 6 lines. When the transfer speed of image data is calculated using (Equation 1), the transfer speed is approximately 25 MHz. On the other hand, in the case of an exposure head that prints in multiple values (the number of gradations representing the gradation of one pixel is 8 bits), the 1-line period TL is 100 μs, and the number of surface emitting elements is 14,964 (1200 dpi, image width approximately 316 mm), and the number of data wiring is 6 lines. When the image data transfer rate is calculated using (Equation 1), the transfer rate is approximately 200 MHz. By making the gradation of one pixel multilevel in this way, the transfer speed is increased. Therefore, if the number of wirings for transferring data between the controller section and the exposure head is increased in order to lower the transfer speed, the number of wirings increases, resulting in an increase in parts and costs. In addition, an increase in transfer speed requires the addition of radiation noise countermeasure parts, resulting in an increase in cost.

SUMMARY OF THE INVENTION It is an object of the present invention to improve image quality by increasing the gradation of image data while suppressing the cost of an interface unit between a controller unit and an exposure head.

In order to solve the above problems, the present invention has the following configuration.

(1) having a photoreceptor rotating in a first direction and a plurality of surface emitting elements arranged in a second direction orthogonal to the first direction, and exposing the photoreceptor with the surface emitting elements; An image forming apparatus comprising: an exposure unit; and a control unit that outputs image data to the exposure unit and controls image formation, wherein the control unit controls a second resolution that is larger than a first resolution of the surface emitting element. a controller having generating means for generating the binary image data at a resolution of , and transmitting means for transmitting the binary image data generated by the generating means to the exposure unit; a control board to be mounted, wherein the exposure unit has receiving means for receiving the image data of the second resolution and the binary value transmitted from the control unit; and a drive board on which the driver is mounted, the control board and the drive board are connected by a cable, and the controller connects the second driver to the driver via the cable. The resolution and the binary image data are transmitted by serial communication, and the driver changes the resolution in the second direction of the binary image data received by the receiving means from the second resolution to the conversion means for converting the resolution in the second direction of the image data to the first resolution; The binary image data is converted to a value larger than the binary value by converting the density of a pixel by an interpolation process that interpolates based on the density of the pixel before conversion and the density of a pixel adjacent to the pixel before conversion. An image forming apparatus characterized by converting into multivalued image data.

According to the present invention, the image quality can be improved by increasing the gradation of the image data while suppressing the cost of the interface section between the controller section and the exposure head.

Schematic cross-sectional view showing the configuration of an image forming apparatus according to an embodiment FIG. 4 is a diagram for explaining the positional relationship between the exposure head and the photosensitive drum of the embodiment, and a diagram for explaining the configuration of the exposure head; Schematic diagram of a drive substrate of an embodiment and a diagram for explaining the structure of a surface emitting element array chip Control block diagram of the control board and drive board of the embodiment Control Block Diagram and Timing Chart of Chip Data Conversion Unit of Embodiment FIG. 4 is a diagram for explaining interface signals between a control board and a drive board in the embodiment; Diagram for explaining filter processing of the embodiment Diagram for explaining filter processing of the embodiment FIG. 4 is a diagram for explaining the pulse response characteristics of the light-emitting thyristor of the example; FIG. 4 is a diagram for explaining the temperature characteristics of the light-emitting thyristor of the example; A diagram for explaining the lookup table of the embodiment. Conversion table showing an example of the lookup table of the embodiment FIG. 4 is a diagram for explaining the circuit of the surface emitting element array chip of the embodiment; FIG. 4 is a diagram for explaining the distribution state of the gate potential of the shift thyristor of the embodiment; FIG. 4 is a diagram showing drive signal waveforms of the surface emitting element array chip of the embodiment; The figure which shows the cross section of the surface emitting thyristor of an Example

BEST MODE FOR CARRYING OUT THE INVENTION Below, embodiments of the present invention will be described in detail with reference to the drawings.

[Configuration of Image Forming Apparatus]
FIG. 1 is a schematic cross-sectional view showing the configuration of an electrophotographic image forming apparatus according to the first embodiment. The image forming apparatus shown in FIG. 1 is a multifunction peripheral (MFP) having a scanner function and a printer function. It is composed of a control unit (not shown). The scanner unit 100 illuminates a document placed on a document platen to optically read the document image, converts the read image into an electrical signal, and creates image data.

The image forming units 103 are arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K) along the rotation direction (counterclockwise direction) of the endless conveying belt 111 . A series of imaging stations are provided. The four image forming stations have the same configuration, and each image forming station includes a photosensitive drum 102 that rotates in the direction of the arrow (clockwise), an exposure head 106, a charger 107, and a developer 108. there is The suffixes a, b, c, and d of the photosensitive drum 102, the exposure head 106, the charger 107, and the developer 108 are black (K), yellow (Y), magenta (M), and cyan (Y) of the image forming station, respectively. It shows that the configuration corresponds to C). Note that suffixes of reference numerals are omitted below unless they refer to a specific photosensitive drum or the like.

The image forming unit 103 rotates the photosensitive drum 102 and charges the photosensitive drum 102 with the charger 107 . The exposure head 106, which is an exposure unit, emits light from the arrayed LED array according to image data, and the light emitted from the chip surface of the LED array is condensed onto the photosensitive drum 102 (on the photosensitive member) by the rod lens array. to form an electrostatic latent image. A developing device 108 develops the electrostatic latent image formed on the photosensitive drum 102 with toner. Then, the developed toner image is transferred onto the recording paper on the transport belt 111 that transports the recording paper. A series of such electrophotographic processes are performed at each image forming station. During image formation, the magenta (M), yellow (Y), and black (K) image forming stations are sequentially formed after a predetermined time has passed since the image forming station for cyan (C) started forming images. , the image forming operation is executed.

The image forming apparatus shown in FIG. 1 includes internal paper feed units 109a and 109b included in a paper feed/conveyance unit 105, an external paper feed unit 109c as a large-capacity paper feed unit, and an external paper feed unit 109c. A manual sheet feeding unit 109d is provided. At the time of image formation, recording paper is fed from a paper feeding unit that has been instructed in advance, and the fed recording paper is conveyed to registration rollers 110 . The registration roller 110 conveys the recording paper to the conveying belt 111 at the timing when the toner image formed by the image forming unit 103 is transferred to the recording paper. A toner image formed on the photosensitive drum 102 of each image forming station is sequentially transferred onto the recording paper conveyed by the conveying belt 111 . The recording paper onto which the unfixed toner image has been transferred is conveyed to fixing section 104 . The fixing unit 104 incorporates a heat source such as a halogen heater, and heats and presses the toner image on the recording paper with two rollers to fix the toner image on the recording paper. The recording paper on which the toner image is fixed by the fixing unit 104 is discharged to the outside of the image forming apparatus by the discharge roller 112 .

An optical sensor 113, which is a second detecting means, is arranged at a position facing the conveying belt 111 on the downstream side of the black (K) image forming station in the recording paper conveying direction. The optical sensor 113 detects the position of the test image formed on the conveying belt 111 in order to derive the amount of color misregistration of the toner images between the image forming stations. The amount of color misregistration derived by the optical sensor 113 is notified to the CPU 400 (see FIG. 4) of the control board 415, which will be described later, and the image positions of the respective colors are adjusted so that a full-color toner image without color misregistration is transferred onto the recording paper. corrected. In addition, a printer control unit (not shown) controls the scanner unit 100, the image forming unit 103, the fixing unit 104, the feeder unit 100, and the image forming unit 103 according to an instruction from an MFP control unit (not shown) that controls the entire multifunction peripheral (MFP). An image forming operation is executed while controlling the paper/conveyance unit 105 and the like. Further, in the vicinity of the imaging unit 103, a thermistor 421 serving as first detection means is provided for measuring the ambient temperature of an exposure head 106 (see FIG. 2), which will be described later, provided above the photosensitive drum 102. is provided.

Here, as an example of an electrophotographic image forming apparatus, an image forming apparatus that directly transfers the toner image formed on the photosensitive drum 102 of each image forming station onto the recording paper on the conveying belt 111 has been described. The present invention is not limited to printers that directly transfer the toner image on the photosensitive drum 102 to the recording paper. For example, the present invention can also be applied to an image forming apparatus having a primary transfer section that transfers the toner image on the photosensitive drum 102 to an intermediate transfer belt and a secondary transfer section that transfers the toner image on the intermediate transfer belt to recording paper. can do.

[Configuration of Exposure Head]
Next, the exposure head 106 that exposes the photosensitive drum 102 will be described with reference to FIG. FIG. 2A is a perspective view showing the positional relationship between the exposure head 106 and the photosensitive drum 102, and FIG. 2B shows the internal structure of the exposure head 106 and how the light beam from the exposure head 106 passes through the rod lens array. FIG. 2 is a diagram for explaining how light is focused on a photosensitive drum 102 by a light 203; As shown in FIG. 2A, the exposure head 106 is attached to the image forming apparatus by an attachment member (not shown) at a position facing the photosensitive drum 102 on the upper portion of the photosensitive drum 102 rotating in the direction of the arrow. (Fig. 1).

As shown in FIG. 2B, the exposure head 106 comprises a driving substrate 202, a surface emitting element array element group 201 mounted on the driving substrate 202, a rod lens array 203, and a housing 204. As shown in FIG. A rod lens array 203 and a driving substrate 202 are attached to the housing 204 . The rod lens array 203 converges the light flux from the surface emitting element array element group 201 onto the photosensitive drum 102 . At the factory, the exposure head 106 alone is assembled and adjusted, and the focus and light amount of each spot are adjusted. Here, assembly adjustment is performed so that the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the surface emitting element array element group 201 are at predetermined intervals. As a result, light from the surface emitting element array element group 201 forms an image on the photosensitive drum 102 . Therefore, when adjusting the focus at the factory, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the surface emitting element array element group 201 becomes a predetermined value. Further, when adjusting the amount of light in the factory, the light emitting elements of the surface light emitting element array element group 201 are sequentially caused to emit light, and the light condensed on the photosensitive drum 102 via the rod lens array 203 reaches a predetermined light amount. The driving current of each light emitting element is adjusted so that

[Structure of Surface Emitting Element Array Element Group]
FIG. 3 is a diagram for explaining the surface emitting element array element group 201. As shown in FIG. FIG. 3A is a schematic diagram showing the configuration of the surface of the driving substrate 202 on which the surface emitting element array element group 201 is mounted, and FIG. is a schematic diagram showing the configuration of the surface (second surface) opposite to the surface (first surface) on which is mounted.

As shown in FIG. 3A, in the surface emitting element array element group 201 mounted on the driving substrate 202, 29 surface emitting element array chips 1 to 29 are staggered along the longitudinal direction of the driving substrate 202. It has a configuration arranged in two rows in a shape. In FIG. 3A, the vertical direction indicates the sub-scanning direction (the rotation direction of the photosensitive drum 102), which is the first direction, and the horizontal direction indicates the main scanning direction, which is the second direction perpendicular to the sub-scanning direction. The direction (longitudinal direction of the exposure head 106) is shown. Inside each surface emitting element array chip, each element of the surface emitting element array chip having a total of 516 light emitting points is arranged at a predetermined resolution pitch in the longitudinal direction of the surface emitting element array chip. In this embodiment, the pitch of each element of the surface emitting element array chip is approximately 21.16 μm (≈2.54 cm/1200 dots), which is the pitch of the first resolution of 1200 dpi. As a result, the interval from end to end of the 516 light emitting points in one surface emitting element array chip is approximately 10.9 mm (≈21.16 μm×516). The surface emitting element array element group 201 is composed of 29 surface emitting element array chips. The number of light emitting elements that can be exposed in the surface emitting element array element group 201 is 14,964 elements (=516 elements x 29 chips), corresponding to an image width of approximately 316 mm (approximately 10.9 mm x 29 chips) in the main scanning direction. It is possible to form an image with

FIG. 3(c) is a view showing the boundary between chips of the surface emitting element array chips arranged in two rows in the longitudinal direction. It is the longitudinal direction of the group 201 . As shown in FIG. 3(c), wire bonding pads to which control signals are input are arranged at the ends of the surface emitting element array chip, and signals input from the wire bonding pads control the transfer section and the light emission. The element is driven. Also, the surface emitting element array chip has a plurality of light emitting elements. Even at the boundary between the surface emitting element array chips, the pitch of the light emitting elements in the longitudinal direction (the distance between the center points of the two light emitting elements) is approximately 21.16 μm, which is the pitch of the resolution of 1200 dpi. . In addition, the surface emitting element array chips arranged in two vertical rows have an interval (indicated by an arrow S in the figure) between the light emitting points of the upper and lower surface emitting element array chips of about 84 μm (4 pixels at 1200 dpi, 8 pixels at 2400 dpi). are arranged so that the distance is an integral multiple of each resolution of minutes).

Further, as shown in FIG. 3B, on the surface of the driving substrate 202 opposite to the surface on which the surface emitting element array element group 201 is mounted, driving units 303a and 303b and a connector 305 are mounted. there is Driving units 303a and 303b arranged on both sides of the connector 305 are driver ICs for driving the surface emitting element array chips 1 to 15 and the surface emitting element array chips 16 to 29, respectively. Drive units 303a and 303b are connected to connector 305 via patterns 304a and 304b, respectively. The connector 305 is connected to signal lines, power supply voltage, and ground for controlling the drive units 303a and 303b from a control board 415 (see FIG. 4), which will be described later, and is connected to the drive units 303a and 303b. Wiring for driving the surface emitting element array element group 201 passes through the inner layer of the driving substrate 202 from the driving units 303a and 303b, and the surface emitting element array chips 1 to 15 and the surface emitting element array chips 16 to 29 are connected to the surface emitting element array chips 1 to 15. It is connected to the.

[Control configuration of control board and drive board]
FIG. 4 shows a control board 415 that processes image data and outputs it to the drive board 202 of the exposure head 106, and a drive board of the exposure head 106 that exposes the photosensitive drum 102 based on the image data input from the control board 415. 202 is a control block diagram. As for the driving substrate 202, the surface emitting element array chips 1 to 15 controlled by the driving section 303a shown in FIG. 4 will be described. The surface emitting element array chips 16 to 29 controlled by the driving section 303b (not shown in FIG. 4) also operate in the same manner as the surface emitting element array chips 1 to 15 controlled by the driving section 303a. In order to simplify the explanation, image processing for one color will be described here, but in the image forming apparatus of the present embodiment, similar processing is performed simultaneously for four colors in parallel. The control board 415 shown in FIG. 4 has a connector 416 for transmitting signals for controlling the exposure head 106 to the drive board 202 . From the connector 416, image data, a Line synchronizing signal, which will be described later, and a control signal from the CPU 400 of the control board 415 are transmitted via cables 417, 418, and 419 connected to the connector 305 of the drive board 202, respectively.

[Configuration of control board]
In the control board 415 , image data processing and print timing processing, and temperature data acquisition from the thermistor 421 are performed by the CPU 400 as a controller. The control board 415 is composed of functional blocks of an image data generator 401 , a line data shifter 402 , a chip data converter 403 , a chip data shifter 404 , a data transmitter 405 and a sync signal generator 406 . In this embodiment, it is assumed that the image data generator 401 is composed of one integrated circuit (IC). Also, the line data shifter 402, the chip data converter 403, the chip data shifter 404, the data transmitter 405, and the sync signal generator 406 are integrated in one integrated circuit ( IC). Note that the image data generator 401, the line data shifter 402, the chip data converter 403, the chip data shifter 404, the data transmitter 405, and the sync signal generator 406 represent modules inside an integrated circuit (IC). . The CPU 400 is an integrated circuit different from these integrated circuits, and a control board 415 is mounted with the CPU 400, an integrated circuit having an image data generation section 401, an integrated circuit having a line data shift section 402 and the like, and a connector 416. ing. Note that the image data generator 401, the line data shifter 402, the chip data converter 403, the chip data shifter 404, the data transmitter 405, and the sync signal generator 406 may be included in one integrated circuit. Furthermore, the image data generator 401, the line data shifter 402, the chip data converter 403, the chip data shifter 404, the data transmitter 405, the sync signal generator 406, and the CPU 400 are included in one integrated circuit. good too. Processing in each functional block will be described below in the order in which image data is processed in the control board 415 .

(Image data generator)
An image data generation unit 401, which is data generation means, performs dithering processing on input image data received from an external computer connected to the scanner unit 100 or the image forming apparatus at a resolution designated by the CPU 400, and converts the image data into image data. Generate. In this embodiment, the image data generation unit 401 performs dithering processing at a resolution of 2400 dpi, which is the second resolution. That is, the image data generated by the image data generation unit 401 is pixel data equivalent to 2400 dpi. Pixel data equivalent to 2400 dpi in this embodiment is assumed to be 1 bit, but one pixel may be represented by a plurality of bits. The pixel data generated by the image data generation unit 401 is line data corresponding to a line corresponding to 2400 dpi in the sub-scanning direction (which is also the rotating direction of the photosensitive drum 102 and the conveying direction of the recording paper). Then, the image data generation unit 401 generates pixel data corresponding to each pixel with a resolution equivalent to 2400 dpi in association with the position of the pixel in the main scanning direction (longitudinal direction of the exposure head 106).

(Line data shift section)
Based on the amount of color misregistration detected by the optical sensor 113, the CPU 400 determines the amount of image shift in the main scanning direction and the sub-scanning direction in units of 2400 dpi. The image shift amount is determined by the CPU 400 based on, for example, the relative amount of color shift between colors calculated based on the detection result of the color shift detection pattern image by the optical sensor 113 . Then, the CPU 400 instructs the image shift amount to the line data shifter 402, which is the deviation correction means. Based on the image shift amount instructed by the CPU 400, the line data shift unit 402 shifts the image data (also called line data) input from the image data generation unit 401 to the entire image area within one page of the recording paper. Shift processing is performed in units of 2400 dpi. The shift processing corrects the image formation position. Note that the line data shift unit 402 may divide the image area in one page of the recording paper into a plurality of areas, and perform shift processing for each of the divided image areas.

(synchronization signal generator)
A synchronization signal generation unit 406 generates a periodic signal for one line in the rotation direction of the photosensitive drum 102 (hereinafter referred to as a line synchronization signal) in synchronization with the rotational speed of the photosensitive drum 102 . The CPU 400 instructs the synchronization signal generation unit 406 to generate a pixel size of 2400 dpi (approximately 10 pixels) on the surface of the photosensitive drum 102 in the rotation direction (sub-scanning direction) with respect to the period of the Line synchronization signal, that is, the predetermined rotation speed of the photosensitive drum 102 . .5 μm) indicate the time to move. For example, when printing at a speed of 200 mm/sec in the sub-scanning direction, the CPU 400 sets the cycle of the line synchronization signal (the cycle of one line in each main scanning direction in the sub-scanning direction) to approximately 52.9 μs (≈(25 .4 mm/2400 dots)/200 mm) is instructed to the synchronization signal generator 406 . If the image forming apparatus has a detection unit that detects the rotational speed of the photosensitive drum 102, the CPU 400 detects the rotation speed of the photosensitive drum in the sub-scanning direction based on the detection result of the detection unit (the generation cycle of the signal output by the encoder). 102 is calculated, and the cycle of the line synchronization signal is determined based on the calculation result. The detection unit here is, for example, an encoder installed on the rotating shaft of the photosensitive drum. On the other hand, if the image forming apparatus does not have a detection unit that detects the rotational speed of the photosensitive drum 102, the rotational speed of the photosensitive drum 102 is calculated based on the following information. That is, the CPU 400 determines the period of the line synchronization signal based on the sheet basis weight (g/cm 2 ), the sheet size, and other sheet type information input by the user from the operation unit.

(Chip data converter)
The chip data conversion unit 403 reads line data from the line data shift unit 402 in synchronization with the line synchronization signal for each line in the sub-scanning direction of the photosensitive drum 102 in the main scanning direction . Then, the chip data conversion unit 403 executes data processing for dividing the read line data into line data for each chip.

FIG. 5A is a block diagram showing the configuration of the chip data conversion section 403. As shown in FIG. In FIG. 5( a ), the Line synchronizing signal output from the synchronizing signal generator 406 is input to the counter 530 . The counter 530 includes a frequency modulation circuit that modulates the input Line synchronizing signal to generate a CLK signal having a higher frequency than the Line synchronizing signal. The counter 530 may incorporate an oscillator that generates a clock signal (CLK) having a higher frequency than the Line synchronization signal instead of the frequency modulation circuit. A configuration in which the chip data conversion unit 403 reads line data from the line data shift unit 402 will be exemplified below, but the embodiment is not limited to this. That is, by supplying the line synchronization signal to the line data shifter 402 and generating the clock signal internally by the line data shifter 402 , the line data shifter voluntarily shifts the line data to the chip data converter 403 . may be configured to transmit

When the Line synchronizing signal is input, the counter 530 resets the count value to 0, and then increments the counter value in synchronization with the number of pulses of the CLK (clock) signal (see FIG. 5(b)). The frequency of the CLK signal generated by the counter 530 is determined by the capacity (number of bits) of pixel data to be read by the chip data conversion unit 403 within one cycle of the Line synchronization signal, the data processing speed of the chip data conversion unit 403 described later, determined at the design stage based on For example, as described above, the surface emitting element array element group 201 has 14,964 light emitting elements (converted to 1200 dpi) for exposing one line in the main scanning direction. On the other hand, the image data generation unit 401 performs dithering processing at a resolution of 2400 dpi. Therefore, the number of pixels in one line of image data in the main scanning direction output from the line data shift unit 402 is 29,928 pixels (=14,964×(2400 dpi/1200 dpi)). The chip data conversion unit 403 reads out line data for one line in the main scanning direction and writes it to a line memory 500, which will be described later, and writes image data to memories 501 to 529, which will be described later, during the line synchronization signal. . Therefore, the counter 530 counts twice the number of pixels (29,928) included in one line of line data (59,856). The period during which the count value of the counter 530 is from 1 to 29,928 is Tm1, and the period during which the count value is from 29,929 to 59,856 is Tm2 (see FIG. 5B). The READ control section 531 reads line data from the line data shift section 402 according to the count value of the counter 530 . That is, the READ control unit 531 stores line data (29,928 pixels) for one line in the main scanning direction in the line memory 500 during the period Tm1 when the count value of the counter 530 is from 1 to 29,928. Further, the WR control unit 532 divides the line data for one line in the main scanning direction stored in the line memory 500 into the memories 501 to 529 during the period Tm2 when the count value of the counter 530 is 29,929 to 59,856. write. Memories 501 to 529 have a smaller storage capacity than the line memory 500, and store line data (divided line data) divided for each chip. The memories 501-529 are FIFO (First In First Out) memories provided corresponding to the surface emitting element array chips 1-29. That is, the memory 501 stores line data corresponding to the surface emitting element array chip 1, the memory 502 stores line data corresponding to the surface emitting element array chip 2, . store line data corresponding to .

Next, the writing of the line data read from the line data shift unit 402 to the memories 501 to 529 and the output of the image data written to the memories 501 to 529 executed by the chip data conversion unit 403 will be described. FIG. 5(b) is a time chart for explaining input/output timing of line data in the chip data conversion unit 403. As shown in FIG. In FIG. 5B, the line synchronization signal indicates a pulse signal output from the synchronization signal generator 406. In FIG. In the figure, TL1, TL2 , . One period of the Line synchronization signal is divided into periods Tm1 and Tm2 according to the counter value of the counter 530 . Input data to the line memory 500 indicates image data from the line data shifter 402, and is input from the line data shifter 402 during the period Tm1 of the cycles TL1, TL2, . . . TL10. The first line data in FIG. 5B indicates the line data of the first line in the sub-scanning direction (for one line in the main scanning direction). Similarly , the 2nd line data , . minutes).

5(b), among the line data for one line in the main scanning direction stored in the line memory 500, the line data corresponding to the surface emitting element array chip 1 is The timing of writing to the memory 501 is shown. Similarly, input data to the memory 502, input data to the memory 503, . 503, . . . , 529 are shown. The first line data of the input data to the memory 501 is line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1, not all line data for one line in the main scanning direction. pointing. The same applies to the input data of the memories 502 to 529. FIG.

'Output data from memory 501' shown in FIG. Similarly, 'output data from memory 502', . . . 'output data from memory 529' shown in FIG. It shows the timing of reading for output. Note that the first line data of the output data from the memory 501 is line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1, not all line data for one line in the main scanning direction. pointing. The same applies to output data from the memories 502 to 529. FIG.

In this embodiment, line data for one line in the main scanning direction are sequentially read out from the line memory 500 , and first, the line data of the surface emitting element array chip 1 are written into the memory 501 . Next, writing is performed to the memory 502 that stores the image data of the surface emitting element array chip 2, and thereafter, writing is continuously performed sequentially up to the memory 529 that stores the image data of the surface emitting element array chip 29. . A chip data shifter 404 subsequent to the chip data converter 403 performs data shift processing in the sub-scanning direction for each surface emitting element array chip. Therefore, it is assumed that the memories 501 to 529 store line data for 10 lines in the sub-scanning direction.

Furthermore, the line data stored in the memories 501 to 529 are the line data for one chip corresponding to each surface emitting element array chip, and the pixel data obtained by copying the pixel data at the edge of the adjacent surface emitting element array chip. Data is also stored together. For example, the memory 502 stores the following pixel data at each end of the line data corresponding to the surface emitting element array chip 2 . That is, the pixel data of the edge of the surface emitting element array chip 2 on the surface emitting element array chip 1 and the pixel data of the edge of the surface emitting element array chip 3 on the surface emitting element array chip 2 side are added. and stored in the memory 502 . As a result, the number of image data corresponding to the surface emitting element array chip 2 is equal to the number of light emitting elements of the surface emitting element array chip 2 (516) and the light emitted from the edges of the adjacent surface emitting element array chips 1 and 3. It becomes 518 (=516+1+1) by adding the image data of the elements one by one.

In the memory 501, pixel data of the edge of the surface emitting element array chip 2 on the side of the surface emitting element array chip 1 is added to the edge of the line data corresponding to the surface emitting element array chip 1 and stored. . In addition, in the memory 529, the end of the line data corresponding to the surface emitting element array chip 29 is added with the pixel data of the edge of the surface emitting element array chip 28 on the side of the surface emitting element array chip 29 and stored. .

As described above, in this embodiment, the pixel data of the edge of the surface emitting element array chip adjacent to each surface emitting element array chip is added to both ends of the line data of the corresponding surface emitting element array chip, and the memory 501 ~529. By the operation of the chip data conversion unit 403 described above, the line data for one line in the main scanning direction is stored in the memories 501 to 529 provided corresponding to the surface emitting element array chips 1 to 29, and the adjacent surface emitting element array chips. is stored with the pixel data at the end of the . Note that the pixel data at the edge of the adjacent surface emitting element array chip is used in the filter processing section 408, which will be described later.

(Chip data shift part)
The chip data shifter 404, which is a deviation correcting means, performs the following control. That is, based on the data (2400 dpi unit) regarding the image shift amount in the sub-scanning direction for each surface emitting element array chip instructed in advance by the CPU 400, the relative readout timing of the line data from the memories 501 to 529 is controlled. The image shift processing in the sub-scanning direction executed by the chip data shift unit 404 will be specifically described below.

In the longitudinal direction of the exposure head 106, it is desirable that the mounting positions of the even-numbered surface emitting element array chips do not deviate. Similarly, in the longitudinal direction of the exposure head 106 as well, it is desirable that the mounting positions of the odd-numbered surface emitting element array chips do not deviate. Further, the mounting positional relationship in the sub-scanning direction between the even-numbered surface-emitting element array chips and the odd-numbered surface-emitting element array chips is equivalent to 2400 dpi and has a predetermined number of pixels (e.g., 8 pixels) by design. preferable. Furthermore, it is preferable that the arrangement positions of the light emitting element arrays in the sub-scanning direction in each surface emitting element array chip are constant without individual differences. However, the mounting position of the surface emitting element array chip and the arrangement position of the light emitting element array include errors, and these errors may lead to deterioration of the image quality of the output image.

In the memory 420 (ROM) shown in FIG. 4, a correction calculated from the relative positional relationship in the sub-scanning direction of the light emitting element arrays of the surface emitting element array chips 1 to 29 mounted on the drive substrate 202 in a zigzag pattern. data is stored. For example, the memory 420 stores correction data based on the following measurement data. Each light emitting element array of the other surface light emitting element array chips 2 to 29 is driven with a shift of several pixels corresponding to 2400 dpi in the sub scanning direction with respect to the light emitting element array of the surface light emitting element array chip 1 serving as the reference of the position in the sub scanning direction. Correction data indicating whether or not it is mounted on the board 202 is stored. After the surface emitting element array chips 2 to 29 are mounted on the drive substrate 202, the measurement data is obtained by turning on the light emitting element of each surface emitting element array chip with a measuring device and measuring based on the light reception result. The CPU 400 sets the correction data read from the memory 420 in the internal register of the chip data shift section 404 in response to the power of the image forming apparatus being turned on. The chip data shifter 404 shifts the line data stored in the memories 501 to 529 to form the same line based on the correction data set in the internal register. For example, when the light emitting element arrays of the surface light emitting element array chip 2 are mounted on the drive substrate with a 2400 dpi equivalent to the light emitting element arrays of the surface light emitting element array chip 1 and are shifted by 8 pixels in the sub-scanning direction, the chip data The shift unit 404 performs the following processing. That is, the chip data shift unit 404 shifts the output timing of the line data corresponding to the surface emitting element array chips 2 forming the same line to the output timing of the line data corresponding to the surface emitting element array chips 1 to the driving substrate 202. delays by 8 pixels. Therefore, the chip data shifter 404 shifts all the line data corresponding to the surface emitting element array chip 2 with respect to the line data corresponding to the surface emitting element array chip 1 .

(data transmitter)
A data transmission unit 405, which is a transmission unit, transmits the line data after performing data processing on the series of line data described above to the drive board 202 of the exposure head 106. FIG. The transmission timing of image data will be described with reference to FIG. As shown in FIG. 3A, among the surface emitting element array chips, odd-numbered surface emitting element array chips 1, 3, 5, . are arranged downstream in the sub-scanning direction. In the time chart shown in FIG. 5(b), writing image data to the memories 501, . . . It is performed in a period (TL1 in the figure). Then, during the period of the next Line synchronizing signal (TL2 in the figure), one line in the sub-scanning direction is read from the memories 501, . . . Readout of the line data for the second eye is performed. Similarly, during the period of the next Line synchronizing signal, line data of the second line in the sub-scanning direction is read from the memories 501, . . . is read out. Then, during the period of the tenth line synchronization signal (TL10 in the figure), from the memory 501, . . . Line data of the line is read out. In addition, the memory 502 corresponding to the even-numbered surface emitting element array chip 2 has a period (TL10 in the figure) after nine pulses of the Line synchronization signal from the period TL1 during which the image data is written to the memory 502. Image data is read from the memory 502 .

The data transmission section 405 transmits the line data processed by the chip data shift section 404 to the drive substrate 202 . The data transmission unit 405 includes a frequency modulation circuit instead of an oscillator that modulates the input line synchronization signal to generate a clock signal having a higher frequency than the line synchronization signal. Also, the data transmission unit 405 may incorporate an oscillator that generates a clock signal having a higher frequency than the line synchronization signal instead of the frequency modulation circuit. In this embodiment, the clock signal (CLK in FIG. 5B) is adjusted so that the count value becomes 59,856 (twice the number of pixel data in one line) or more within one cycle of the Line synchronizing signal. determines the frequency. As a result, it is possible to input (write) image data to the line memory 500 and output (write) image data from the line memory 500 to the memories 501 to 529 within one period of the line synchronization signal.

On the other hand, reading out data from the memories 501 to 529 is carried out within one period of the line synchronizing signal. Output data in parallel. Therefore, the speed of reading image data from the memories 501 to 529 may be slower than the speed of writing to the memory. For example, in this embodiment, it is assumed that the image data is read from the memories 501-529 at a cycle that is 58 times longer than the cycle of the clock signal when writing the image data to the memories 501-529.

[Interface between control board and drive board]
FIG. 6 is a timing chart illustrating an input signal to the data transmission unit 405 of the control board 415 and an interface signal, which is a serial signal transmitted and received between the control board 415 and the drive board 202. FIG. In FIG. 6, 518 pieces of image data stored in memories 501 to 529 are input to the data transmission unit 405 during one cycle of the Line synchronization signal indicating the scanning period for one line in the main scanning direction. . In this embodiment, the interface signal is 1-bit image data of 2400 dpi (binary values of 0 and 1 can be displayed), and image data of 29 surface emitting element array chips is transferred. Also, in order to save space and reduce costs, it is necessary to minimize the number of wires between the control board 415 and the drive board 202 for transmitting interface signals. Therefore, the data transmission unit 405 performs parallel-serial conversion on the image data for 29 chips, superimposes it on six signal lines (communication paths), and transmits it. Here, the six signal lines are associated so as to transmit image data of surface emitting element array chips 1 to 5, 6 to 10, 11 to 15, 16 to 20, 21 to 25, and 26 to 29. signal line. In FIG. 6, the output signal from the data transmission unit 405 transmitted to the driving unit 303a of the driving substrate 202 is image data transmitted to the surface emitting element array chips 1 to 5, 6 to 10, and 11 to 15 in order from the top. indicates Similarly, the output signal from the data transmission section 405 transmitted to the drive section 303b of the drive substrate 202 is the image data transmitted to the surface emitting element array chips 16 to 20, 21 to 25, and 26 to 29 in order from the top. show. The data receiving unit 407 of the driving unit 303a of the driving substrate 202 on the side of the exposure head 106 serial-parallel converts the image data received via the six signal lines so as to correspond to each surface emitting element array chip. It is configured to restore the original image data.

A signal data name corresponding to each chip in FIG. 6 is represented by M_N. M indicates the chip number (1 to 29) of the surface emitting element array chip, and N indicates the number of image data (1 to 518) in one chip of the surface emitting element array chip. The signal data name emp indicates that the corresponding surface emitting element array chip is unused (unmounted). In the data transmission unit 405, the image data of the light emitting elements at the end of the adjacent surface emitting element array chip is added to the number of surface emitting elements in one chip, 516, by the processing in the chip data conversion unit 403 described above, resulting in 518 data. Data for one pixel is transmitted as one chip. The image data is transmitted sequentially from the first pixel of each surface emitting element array in synchronization with the line synchronization signal generated by the synchronization signal generation unit 406 . The data transmission unit 405 has a parallel-serial conversion circuit for distributing image data corresponding to 29 surface emitting element array chips to 6 signal lines. The parallel-serial conversion circuit converts image data (parallel data) of five surface emitting element array chips into serial signals transmitted via the same signal line. The parallel-serial conversion circuit enables image data communication between the data transmission unit 405 and the data reception unit 407 using six signal lines. Parallel-serial conversion of image data and serial communication can reduce the number of wires between the data transmission unit 405 and the data reception unit 407, while the transfer speed of the interface signal for transmitting the image data is reduced. Speed up.

In this embodiment, the number of gradations of each pixel is 1 bit, the line period TL is 100 μs, the number of surface emitting elements of the surface emitting element array chips 1 to 29 is 14,964 (1200 dpi and the image width is about 316 mm), and the number of chips is is 29 chips. When the frequency of the input signal to the data transmission unit 405 is calculated using the above-described (Equation 1), the calculated frequency is approximately 5 MHz. Furthermore, assuming that the number of wiring lines for transmitting image data between the data transmission unit 405 and the data reception unit 407 is 6, the frequency of the interface signal to the data transmission unit 405 is about 25 MHz according to (Equation 1). Also, in order to improve the gradation, if the number of bits indicating the number of gradations of each pixel is increased, the frequency of the output signal becomes the frequency when the number of gradations is 1 bit, and the number of bits indicating the number of gradations increases. The frequency is multiplied by , and the speed is further increased. Therefore, in this embodiment, processing for increasing the number of bits of image data is performed after the data receiving unit 407, that is, inside the drive board 202 of the exposure head 106, in order to improve the gradation. Note that the frequency of the interface signal to the data transmission unit 405 in this embodiment is about 25 MHz, which is not a frequency that requires the components for the radiation noise countermeasures described above. Therefore, parallel-serial conversion for reducing the number of wires for data transmission/reception between the control board 415 and the drive board 202 does not increase the cost.

[Construction of drive substrate for exposure head]
Next, processing inside the drive unit 303a mounted on the drive board 202 of the exposure head 106 will be described. The driving unit 303 a is composed of functional blocks of a data receiving unit 407 , a filtering unit 408 , an LUT 410 , a PWM signal generating unit 411 , a timing control unit 412 , a control signal generating unit 413 and a driving voltage generating unit 414 . The processing of each functional block will be described below in the order in which the image data is processed in the driving unit 303a.

(Data receiver)
A data receiving unit 407 of the driving unit 303a, which is a receiving means, is a serial-parallel conversion circuit that converts image data (serial data) of five surface emitting element array chips into parallel signals for each of the five surface emitting element array chips. have. The data receiving section 407 receives the interface signal composed of the serial signal transmitted from the data transmitting section 405 . Then, the data receiving unit 407 parallel-converts the received interface signal (serial data) into an image data string for each surface emitting element array chip (1 to 15) by a serial-parallel conversion circuit. The processing blocks subsequent to the driving unit 303a are configured to parallelly process the image data for 15 chips of the surface emitting element array chips 1 to 15. FIG.

(filter processing part)
The filter processing unit 408, which is a conversion means, performs interpolation processing by filtering in the main scanning direction on the image data for each surface emitting element array chip, and converts the resolution in the main scanning direction from 2400 dpi to 1200 dpi. FIG. 7 is a diagram for explaining how filtering is performed by the filtering unit 408. As shown in FIG. In FIG. 7, D1 to D9 represent image data (2400 dpi input data) of the surface emitting element array chip. Here, the image data D1 to D8 are the image data of the corresponding surface emitting element array chip, and the image data D9 is the edge pixel data of the adjacent surface emitting element array chip. D1' to D4' indicate image data (output data of 1200 dpi) after filtering by the filter processing unit 408. FIG. The resolution of the output data (1200 dpi) is half the resolution of the input data (2400 dpi), and the formula for calculating the image data of each pixel is expressed by (Formula 2 ) below.
Dn′=D(2×n−1)×K2+D(2×n)×K1+D(2×n+1)×K2 (Formula 2)
Here, n corresponds to the number of surface emitting elements 516 inside each surface emitting element array chip, and image data is calculated in each light emitting element sequentially in the order of n=1 to 516 based on the lighting order of the light emitting elements. is done. The first coefficient K1 is a weighting coefficient for output data and input data at the same coordinate position in the main scanning direction. The second coefficient K2 is a weighting coefficient for input data whose coordinates are shifted by 1/2 pixel in the main scanning direction from the output data. In this embodiment, interpolation calculation (filtering) is performed with values of K1=0.5 and K2=0.25, but weighting coefficients different from those in this embodiment may be used. In this embodiment, by setting the weighting factor K2 to a value greater than 0, the information of the image data generated at a resolution (2400 dpi) higher than the resolution (1200 dpi) of the output data can be reflected in the output data. Specifically, the processing from the image data generation unit 401 of the control board 415 to the data reception unit 407 of the exposure head 106 moves the image position in the main scanning direction at 2400 dpi, and the filter processing unit 408 in the subsequent stage processes the image data. Convert the resolution to 1200dpi. As a result, it is possible to generate an image of 1200 dpi while maintaining image movement accuracy in units of 2400 dpi.

FIG. 8 is a diagram for explaining the shift of image data before and after filtering, and the change in image data due to filtering. FIG. 8A is a diagram showing 2400 dpi image data after dithering the surface emitting element array chips 1, 2 and 3 in the image data generator 401 of the control board 415. FIG. In FIG. 8(a), the image data is shown in two gradations of black and white. The vertical axis in FIG. 8A indicates the sub-scanning direction, and m to m+3 indicate lines in the sub-scanning direction. The horizontal axis of FIG. 8(a) indicates the main scanning direction, and 1, 2 to n−1, n indicate the arrangement order of the light emitting elements in the surface emitting element array chip at 2400 dpi. FIG. 8(b) is a diagram showing image data after the image data shown in FIG. 8(a) has been shifted in units of 2400 dpi by the line data shifter 402 and the chip data shifter 404 of the control board 415. is. FIG. 8B shows an image corresponding to the surface emitting element array chip 1 by shifting the image data shown in FIG. An example in which data is shifted downward in the sub-scanning direction by one pixel in units of array chips is shown.

In FIG. 8C, the image data shifted in the main scanning direction and the sub-scanning direction in FIG. The image data after resolution conversion from 2400 dpi to 1200 dpi is shown. , 1', 2', ..., n/2-1, n on the horizontal axis indicate the arrangement order of the light emitting elements of the surface light emitting element array chip after resolution conversion to 1200 dpi. Also, the size of each pixel (1200 dpi) in the main scanning direction after resolution conversion in FIG. 8C is twice the size of one pixel (2400 dpi) shown in FIG. 8B. Furthermore, the position of each pixel is shifted to the right by half a pixel in FIG. 8B (position advanced by half a pixel in the main scanning direction). does not change. For example, the size and position of pixel 1′ of surface emitting element array chip 1 after resolution conversion in FIG. It has the size and position of half the pixel plus the pixel at pixel position 2 plus half the pixel at pixel position 3 . Similarly, the size and position of the pixel 2' of the surface emitting element array chip 1 after resolution conversion in FIG. plus half the pixel at pixel position 4 and half the pixel at pixel position 5.

Also, the size and position of the pixel (n/2-1) of the surface emitting element array chip 1 after resolution conversion in FIG. 8(c) are as follows. That is, half of the pixel position (n-3) of the surface emitting element array chip 1 before resolution conversion in FIG. 8B, the pixel position (n-2), and the pixel position (n-1) is the size and position of half of the pixels of . Similarly, the size and position of the pixel (n/2) of the surface emitting element array chip 1 after resolution conversion in FIG. 8(c) are as follows. That is, half of the pixels at the pixel position (n−1) of the surface emitting element array chip 1 before resolution conversion in FIG. It has the size and position of half the pixel at pixel position 1 plus. The number in each pixel in FIG. 8(c) indicates the density value of each pixel. In this embodiment, it is assumed that processing is performed with the number of gradations of 8 bits after resolution conversion. Assuming that the density value of the black portion in the drawing is 100% and the density value of the white portion (including the frame portion not shown in the drawing) is 0%, the density value of each pixel is calculated by the above-mentioned (Equation 2 ). Then, the density value is represented by five values of 0%, 25%, 50%, 75% and 100%. In order to express the density value of one pixel with five values, the gradation needs 3 bits. By processing the number of gradations for one pixel after resolution conversion with 3 bits or more, smooth processing is possible without causing a density step. In the resolution conversion process, 1-bit data for 2 pixels in the main scanning direction with a resolution of 2400 dpi (2 bits in total) transmitted from the control board 415 is converted into 3-bit data with a resolution of 1200 dpi. Therefore, the bus width (number of bits) of the image data after the filter processing unit 408 is 1.5 times (=3 bits/2 bits).

For example, the density value of the pixel 1' of the surface emitting element array chip 1 in the (m+ 3 ) row of FIG. Calculated. That is, density value of pixel 1′=density of pixel 1 (1)×K2 (0.25)+density of pixel 2 (1)×K1 (0.5)+density of pixel 3 (0)×K2 (0 .25)=0.75 (75%). Similarly, the density value of the pixel 2′ of the surface emitting element array chip 1 in the (m+ 3 ) row of FIG. become. That is, density value of pixel 2′=density of pixel 3 (0)×K2 (0.25)+density of pixel 4 (0)×K1 (0.5)+density of pixel 5 (0)×K2 (0 .25)=0 (0%). Further, the density value of the pixel (n/ 2 ) of the surface emitting element array chip 1 on the (m+3) row in FIG. become that way. That is, density value of pixel (n/2)=density of pixel (n−1) (1)×K1 (0.25)+density of pixel (n) (1)×K1 (0.5)+surface emission The density of pixel 1 of element array chip 2 is (0)×K2(0.25)=0.751 (75%).

Further, when processing pixels at the edge of a surface emitting element array chip during filter processing, if there is no pixel data for the adjacent surface emitting element array chip, an image will be lost and an image defect will occur. Therefore, as described above, the chip data conversion unit 403 of the control board 415 adds the pixel data on the edge side of the adjacent surface emitting element array chips to arrange the image data, thereby preventing the image from missing. Filtering can be performed.

(LUT)
The LUT 410, which is light intensity correction means, converts data values (density data values) for each pixel into light intensity value data using a Look Up Table. As described above, the data after resolution conversion processing by the filter processing unit 408 is composed of 3 bits per pixel for switching between 0%, 25%, 50%, 75%, and 100% light intensity within one pixel. image data (density data). Therefore, the LUT 410 receives image data in which one pixel is 3 bits. For the 3-bit image data, the LUT 410 performs data conversion for adjusting the light emission time. The pulse response characteristics of the surface emitting element may vary depending on driving conditions, and the generated variation may cause image defects. Therefore, in the process of the LUT 410, when performing multi-value pulse width control within one pixel, the image data value (density data value). For example, when the pulse response of the surface emitting element is slow and the integrated amount of light is smaller than the target value, the LUT 410 performs conversion so that the density data value increases, and adjusts the amount of exposure (amount of light emission) to the target.

Further, in this embodiment, the values of the conversion table set in the lookup table are the setting value of the drive voltage of the surface light emitting element (light emitting thyristor) and the temperature detection result of the thermistor 421 installed near the surface light emitting element. It has a configuration that can be switched based on and. Also, switching of values in the conversion table is performed before image formation is started. Here, the drive voltage and temperature characteristics of the light-emitting thyristor will be described. In general, a light-emitting thyristor has a delay time from when a voltage is applied across its anode terminal to its cathode terminal until the thyristor turns on and starts to emit light. It is known that this delay time varies depending on the driving voltage applied between the anode terminal and the cathode terminal. In general, an image forming apparatus performs light amount control by switching the amount of exposure in order to maintain a constant density of an image to be formed against deterioration of the photosensitive drum 102 and toner over time. Since this embodiment adopts a method of switching the control voltage to control the amount of light, the above-described variation of the delay time occurs due to the switching of the control voltage.

FIG. 9 is a diagram for explaining the response characteristics of the light-emitting thyristor in this embodiment. ) pulse width (input PWM). The graph in FIG. 9 shows the pulse response characteristics of the light-emitting thyristor with respect to the input pulse in the case of control voltages 1 and 2, which are the control values of the driving voltage. In the case of the control voltage 1 for controlling to output a high amount of light, the minimum pulse width threshold (threshold 1) of the input pulse at which the light emitting thyristor starts to emit light is low. Therefore, it responds quickly to an input pulse with a narrower pulse width. On the other hand, in the case of the control voltage 2 that controls the output of a relatively low amount of light, the minimum pulse width threshold (threshold 2) at which the light emitting thyristor starts to emit light is higher than the threshold 1. ). Therefore, compared to the control voltage 1, the response to the input pulse is slower. Therefore, in order to set the minimum pulse width to a predetermined exposure amount, it is necessary to adjust the light emission time of the minimum pulse width with respect to the control voltage value. In this embodiment, the CPU 400 sets the control voltage in the drive voltage generator 414 and notifies the LUT 410 of the control voltage.

On the other hand, light-emitting thyristors have the characteristic that the amount of exposure decreases as the temperature of the element rises. FIG. 10 is a diagram for explaining the difference in exposure amount with respect to an input pulse when the light-emitting thyristor is at room temperature and when the temperature is raised. The vertical axis indicates the integrated light amount, and the horizontal axis indicates the pulse width of the PWM signal (input PWM). . From FIG. 10, the minimum pulse width (threshold value 1) of the input PWM pulse for turning on the light-emitting thyristor does not change at room temperature or at elevated temperature. However, the exposure amount of the light-emitting thyristor when the input PWM pulse has the maximum pulse width in one pixel is much lower at elevated temperature than at normal temperature. When the image forming apparatus has such temperature characteristics, the exposure amount of the light-emitting thyristor fluctuates when there is a self-heating inside the image forming apparatus or a change in the ambient temperature environment, resulting in density fluctuation. The LUT 410 determines the adjustment value of the minimum pulse width according to the control voltage and changes in the exposure amount due to the temperature change, which is the exposure control information described above, and determines the maximum pulse width according to the temperature detection result of the thermistor 421 . Determines the pulse width adjustment value. Then, in the LUT 410, the data values of the conversion table of the LUT 410 are determined by linearly interpolating data between the minimum pulse width and the maximum pulse width.

FIG. 11 is a diagram for explaining the relationship between input data and output data converted by a lookup table. The horizontal axis indicates input data (density value) represented by five values of 0%, 25%, 50%, 75%, and 100%, and the vertical axis indicates the amount of light in 256 steps of 8 bits. Output data (pulse width of PWM signal) is shown. As shown in FIG. 9, when the control voltage is 1, the light emission of the light-emitting thyristor starts from the pulse width of the threshold value 1. Therefore, for the minimum pulse width, data obtained by adding a predetermined offset to the input data is used. Output. On the other hand, the maximum pulse width is set narrow (small) at room temperature so that a predetermined amount of light is output for the maximum internal temperature of the image forming apparatus. The pulse width is set to be thick (large). In order to finely adjust the exposure amount using the pulse width of the PWM signal described above, the output data width (number of bits) of the LUT 410 is adjusted with an adjustment accuracy of 8 bits (256 steps). In the present embodiment, a system in which the surface light emitting element (light emitting thyristor) is driven by voltage has been described as an example. A conversion table for the LUT 410 may be determined.

FIG. 12 shows a table showing an example of a lookup table, and the LUT 410 converts pixel data equivalent to 1200 dpi into a PWM signal using one of the conversion tables shown in FIGS. do. The lookup table shown in FIG. 12 stores density values (five values of 0%, 25%, 50%, 75%, and 100%) of pixels, which are pixel data equivalent to 1200 dpi converted by the filtering unit 408. It is a conversion table for converting in association with 8-bit PWM data. "000", "001", "010", "011", and "100" in binary notation in the left column of the conversion tables shown in FIGS. , 25%, 50%, 75%, and 100%. The PWM data in the conversion tables shown in FIGS. 12A to 12C represent 8-bit data corresponding to pixel density values. "1" of the PWM data is ON data (light emission data) of the LED, and "0" is OFF data (non-light emission data). The PWM data corresponds to ΦW1 to ΦW4, which will be described later. For example, PWM data corresponding to "000" corresponding to a pixel density value of 0% is "00000000" in any of the conversion tables of FIGS. 12(a) to (c). The PWM data corresponding to "100" corresponding to the pixel density value of 100% is "11111111" in any of the conversion tables of FIGS. 12(a) to (c). On the other hand, PWM data corresponding to "001", "010", and "011" corresponding to pixel density values of 25%, 50%, and 75% are shown in FIGS. data. For example, the PWM data corresponding to "010" with a pixel density value of 50% is "00001111" in FIG. 12(a), "11110000" in FIG. 12(b), and " 00111100”.

(PWM signal generator, timing controller, control signal generator, drive voltage generator)
The subsequent PWM signal generation unit 411 generates a pulse width signal (hereinafter referred to as a PWM signal) corresponding to the emission time during which the surface emitting element array chip emits light within one pixel section according to the data value of each pixel. The timing of outputting the PWM signal is controlled by the timing control section 412 . The timing control unit 412 generates a synchronization signal corresponding to the pixel interval of each pixel from the line synchronization signal generated by the synchronization signal generation unit 406 of the control board 415 and outputs the synchronization signal to the PWM signal generation unit 411 . The drive voltage generator 414 generates a drive voltage for driving the surface emitting element array chip in synchronization with the PWM signal. The drive voltage generation unit 414 is configured so that the voltage level of the output signal can be adjusted around 5V by the CPU 400 so as to obtain a predetermined amount of light. In this embodiment, each surface emitting element array chip has a configuration capable of driving four light emitting elements independently at the same time. The drive voltage generator 414 supplies drive signals to 4 lines for each surface emitting element array chip, and 1 line (15 chips)×4=60 lines in a staggered configuration for the entire exposure head 106 . The driving signals supplied to each surface emitting element array chip are ΦW1 to ΦW4 (see FIG. 15). ΦW1 to ΦW4 are pulse signals for controlling light emission time in each pixel, and pulse widths are configured by adjusting data values in the LUT 410 described above (details will be described later). On the other hand, the operation of the shift thyristor (see FIG. 15), which will be described later, sequentially drives the surface emitting element chip array. The control signal generator 413 generates control signals Φs, Φ1, and Φ2 for transferring the shift thyristors for each pixel from the synchronization signals corresponding to the pixel intervals generated by the timing controller 412 (see FIG. 15).

[Description of SLED circuit]
FIG. 13 is an equivalent circuit of a part of the self-scanning LED (SLED) chip array of this embodiment. In FIG. 13, Ra and Rg are anode resistance and gate resistance, respectively, Tn is a shift thyristor, Dn is a transfer diode, and Ln is a light emitting thyristor. Gn represents the common gate of the corresponding shift thyristor Tn and the light-emitting thyristor Ln connected to the shift thyristor Tn. Here, n is an integer of 2 or more. Φ1 is the transmission line of the odd-numbered shift thyristors T, and Φ2 is the transmission line of the even-numbered shift thyristors T. In FIG. ΦW1 to ΦW4 are lighting signal lines for the light-emitting thyristors L, which are connected to resistors RW1 to RW4, respectively. VGK is the gate line and Φs is the start pulse line. As shown in FIG. 13, four light-emitting thyristors L4n-3 to L4n are connected to one shift thyristor Tn, and the four light-emitting thyristors L4n-3 to L4n can be lit at the same time. It has become.

[Operation of SLED circuit]
Next, the operation of the SLED circuit shown in FIG. 13 will be described. In the circuit diagram of FIG. 13, 5V is applied to the gate line VGK, and the voltages input to the transfer lines Φ1, Φ2 and the lighting signal lines ΦW1 to ΦW4 are also 5V. In FIG. 13, when the shift thyristor Tn is in the ON state, the potential of the common gate Gn of the shift thyristor Tn and the light-emitting thyristor Ln connected to the shift thyristor Tn is lowered to about 0.2V. Since the common gate Gn of the light emitting thyristor Ln and the common gate Gn+1 of the light emitting thyristor Ln+1 are connected by the coupling diode Dn, a potential difference substantially equal to the diffusion potential of the coupling diode Dn is generated. In this embodiment, the diffusion potential of the coupling diode Dn is about 1.5 V, so the potential of the common gate Gn+1 of the light emitting thyristor Ln+1 is 0.2 V of the potential of the common gate Gn of the light emitting thyristor Ln, and 1 of the diffusion potential. It becomes 1.7V (=0.2V+1.5V) by adding 0.5V. Similarly, the potential of the common gate Gn+2 of the light-emitting thyristor Ln+2 is 3.2 V (=1.7 V+1.5 V), and the potential of the common gate Gn+3 (not shown) of the light-emitting thyristor Ln+3 (not shown) is 4.7 V (= 3.2V+1.5V). However, the potential after the common gate Gn+4 of the light-emitting thyristor Ln+4 is 5V because the voltage of the gate line VGK is 5V and cannot reach a higher voltage. As for the potential of the common gate Gn-1 before the common gate Gn of the light-emitting thyristor Ln (on the left side of the common gate Gn in FIG. 13), since the coupling diode Dn-1 is in a reverse-biased state, the potential of the gate line The voltage of VGK is applied as it is and becomes 5V.

FIG. 14(a) is a diagram showing the distribution of the gate potential of the common gate Gn of each light-emitting thyristor Ln when the shift thyristor Tn described above is in the ON state. , refers to the common gate of the light-emitting thyristor L in FIG. The vertical axis of FIG. 14(a) indicates the gate potential. The voltage required to turn on each shift thyristor Tn (hereinafter referred to as threshold voltage) is obtained by adding the diffusion potential (1.5 V) to the gate potential of the common gate Gn of each light emitting thyristor Ln, Almost the same potential. When the shift thyristor Tn is on, the shift thyristor Tn+2 has the lowest common gate potential among the shift thyristors connected to the transfer line Φ2 of the same shift thyristor Tn. The potential of the common gate Gn+2 of the light-emitting thyristor Ln+2 connected to the shift thyristor Tn+2 is 3.2 V (=1.7 V+1.5 V) (FIG. 14(a)) as described above. Therefore, the threshold voltage of shift thyristor Tn+2 is 4.7V (=3.2V+1.5V). However, since the shift thyristor Tn is turned on, the potential of the transfer line Φ2 is drawn to about 1.5 V (diffusion potential), which is lower than the threshold voltage of the shift thyristor Tn+2, so the shift thyristor Tn+2 is turned on. Can not do it. Other shift thyristors connected to the same transfer line Φ2 cannot be similarly turned on because their threshold voltages are higher than that of shift thyristor Tn+2, and only shift thyristor Tn can be kept on.

Regarding the shift thyristors connected to the transfer line Φ1, the threshold voltage of the shift thyristor Tn+1, which has the lowest threshold voltage, is 3.2V (=1.7V+1.5V). The next lowest threshold voltage of the shift thyristor Tn+3 (not shown in FIG. 13) is 6.2V (=4.7V+1.5V). In this state, when 5V is input to the transfer line Φ1, only the shift thyristor Tn+1 can be turned on. In this state, the shift thyristor Tn and the shift thyristor Tn+1 are turned on at the same time. Therefore, the gate potentials of the shift thyristors Tn+1 to the shift thyristors Tn+2, Tn+3, etc. provided on the right side in the circuit diagram of FIG. 13 are lowered by the diffusion potential (1.5 V). However, since the voltage of the gate line VGK is 5V and the voltage of the common gate of the light-emitting thyristor L is limited by the voltage of the gate line VGK, the gate potential on the right side of the shift thyristor Tn+5 is 5V. FIG. 14(b) shows the gate voltage distribution of each of the common gates Gn−1 to Gn+4 at this time, and the vertical axis represents the gate potential. In this state, when the potential of the transfer line Φ2 is lowered to 0V, the shift thyristor Tn is turned off, and the potential of the common gate Gn of the shift thyristor Tn rises to the VGK potential. FIG. 14(c) is a diagram showing the gate voltage distribution at this time, and the vertical axis indicates the gate potential. Thus, the ON state transfer from the shift thyristor Tn to the shift thyristor Tn+1 is completed.

[Light emitting operation of light emitting thyristor]
Next, the light emitting operation of the light emitting thyristor will be described. When only the shift thyristor Tn is turned on, the gates of the four light emitting thyristors L4n-3 to L4n are commonly connected to the common gate Gn of the shift thyristor Tn. Therefore, the gate potential of the light-emitting thyristors L4n-3 to L4n is 0.2 V, which is the same as the common gate Gn. Therefore, the threshold value of each light-emitting thyristor is 1.7V (=0.2V+1.5V). L4n-3 to L4n can be lit. Therefore, by inputting lighting signals to the lighting signal lines ΦW1 to ΦW4 while the shift thyristor Tn is on, the four light emitting thyristors L4n-3 to L4n can be selectively caused to emit light. It is possible. At this time, the potential of the common gate Gn+1 of the shift thyristor Tn+1 adjacent to the shift thyristor Tn is 1.7 V, and the threshold voltage of the light-emitting thyristors L4n+1 to 4n+4 gate-connected to the common gate Gn+1 is 3.2 V (= 1.7V+1.5V). Since the lighting signal input from the lighting signal lines ΦW1 to ΦW4 is 5V, it is likely that the light emitting thyristors L4n+1 to L4n+4 will also light in the same lighting pattern as the light emitting thyristors L4n−3 to 4n. However, since the light-emitting thyristors L4n−3 to L4n have lower threshold voltages, they turn on earlier than the light-emitting thyristors L4n+1 to L4n+4 when the lighting signal is input from the lighting signal lines ΦW1 to ΦW4. Once the light-emitting thyristors L4n-3 to L4n are turned on, the connected lighting signal lines ΦW1 to ΦW4 are pulled down to approximately 1.5 V (diffusion potential). Therefore, the potentials of the lighting signal lines ΦW1 to ΦW4 become lower than the threshold voltages of the light emitting thyristors L4n+1 to L4n+4, so that the light emitting thyristors L4n+1 to L4n+4 cannot be turned on. By connecting a plurality of light-emitting thyristors L to one shift thyristor T in this manner, the plurality of light-emitting thyristors L can be lit simultaneously.

FIG. 15 is a timing chart of drive signals for the SLED circuit shown in FIG. FIG. 15 shows voltage waveforms of driving signals of the gate line VGK, the start pulse line Φs, the transmission lines Φ1 and Φ2 of the odd-numbered and even-numbered shift thyristors, and the lighting signal lines ΦW1 to ΦW4 of the light-emitting thyristors in order from the top. there is Each drive signal has a voltage of 5V when turned on and a voltage of 0V when turned off. Moreover, the horizontal axis of FIG. 15 indicates time. Also, Tc indicates the period of the clock signal Φ1, and Tc/2 indicates a period half (=1/2) of the period Tc.

5V is always supplied to the gate line VGK. The clock signal Φ1 for the odd-numbered shift thyristors and the clock signal Φ2 for the even-numbered shift thyristors are input at the same period Tc, and the signal Φs of 5V is supplied to the start pulse line. Shortly before the clock signal Φ1 for the odd-numbered shift thyristors first goes to 5V, the signal Φs on the start pulse line is dropped to 0V to create a voltage difference on the gate line VGK. As a result, the gate potential of the first shift thyristor Tn-1 is pulled from 5V to 1.7V, the threshold voltage becomes 3.2V, and the shift thyristor Tn-1 becomes ready to be turned on by a signal from the transfer line Φ1. A voltage of 5 V is applied to the transfer line Φ1, and after a short delay after the first shift thyristor Tn−1 is turned on, 5 V is supplied to the start pulse line Φs, and thereafter 5 V is supplied to the start pulse line Φs. continue.

The transfer line Φ1 and the transfer line Φ2 have a time Tov during which their ON states (here, 5 V) overlap, and are configured to have a substantially complementary relationship. The light-emitting thyristor lighting signal lines ΦW1 to ΦW4 are transmitted at half the cycle of the transmission lines Φ1 and Φ2, and are lit when 5 V is applied while the corresponding shift thyristors are in the ON state. For example, in period a, all four light-emitting thyristors connected to the same shift thyristor are lit, and in period b, three light-emitting thyristors are simultaneously lit. Further, all the light-emitting thyristors are turned off during period c, and two light-emitting thyristors are simultaneously turned on during period d. Only one light-emitting thyristor is lit during period e.

In this embodiment, the number of light-emitting thyristors connected to one shift thyristor is four, but the number is not limited to this, and may be less or more than four depending on the application. In the circuit described above, the circuit in which the cathodes of the thyristors are shared has been described, but the anode common circuit can also be applied by appropriately reversing the polarity.

[Structure of Surface Emitting Thyristor]
FIG. 16 is a schematic diagram of the surface emitting thyristor section of this embodiment. FIG. 16A is a plan view (schematic diagram) of a light-emitting element array in which a plurality of light-emitting elements formed in a mesa (trapezoidal) structure 922 are arranged. FIG. 16(b) is a schematic cross-sectional view of the light emitting element formed in the mesa structure 922 taken along line BB shown in FIG. 16(a). The mesa structures 922 formed with light-emitting elements are arranged at a predetermined pitch (interval between light-emitting elements) (for example, approximately 21.16 μm in the case of a resolution of 1200 dpi), and each mesa structure 922 has an element isolation groove. are separated from each other by 924 .

In FIG. 16(b), 900 is a compound semiconductor substrate of the first conductivity type, 902 is the same first conductivity type buffer layer as the substrate 900, and 904 is a stack of two types of first conductivity type semiconductor layers. Distributed Bragg Reflector (DBR) layer. 906 is a first semiconductor layer of the first conductivity type; 908 is a first semiconductor layer of a second conductivity type different from the first conductivity type; 910 is a second semiconductor layer of the first conductivity type; A second second conductivity type semiconductor layer. As shown in FIG. 16B, semiconductor layers 906, 908, 910, and 912 of different conductivity types are alternately laminated to form a pnpn-type (or npnp-type) thyristor structure. In this embodiment, an n-type GaAs substrate is used as the substrate 900, an n-type GaAs or n-type AlGaAs layer is used as the buffer layer 902, and n-type high Al composition AlGaAs and low Al composition AlGaAs are used as the DBR layer 904. A laminated structure of AlGaAs is used. The first semiconductor layer 906 of the first conductivity type on the DBR layer is made of n-type AlGaAs, and the first semiconductor layer 908 of the second conductivity type is made of p-type AlGaAs. In addition, n-type AlGaAs is used for the second semiconductor layer 910 of the first conductivity type, and p-type AlGaAs is used for the second semiconductor layer 912 of the second conductivity type.

In addition, in the mesa structure type surface light emitting device, a current constriction mechanism is used to prevent the current from flowing to the side surface of the mesa structure 922, thereby improving the luminous efficiency. Here, the current constriction mechanism in this embodiment will be described. As shown in FIG. 16(b), in this embodiment, a p-type GaP layer 914 is formed on the p-type AlGaAs that is the second second conductivity type semiconductor layer 912, and an n-type GaP layer 914 is formed thereon. An ITO layer 918 is formed which is a transparent conductor of the type. The p-type GaP layer 914 is formed with a sufficiently high impurity concentration in the portion that contacts the ITO layer 918, which is a transparent conductor. When a forward bias is applied to the light-emitting thyristor (for example, when the back electrode 926 is grounded and the front electrode 920 is applied with a positive voltage), the p-type GaP layer 914 is in contact with the transparent conductive ITO layer 918 . is formed with a sufficiently high impurity concentration, it becomes a tunnel junction. As a result, current flows. With such a structure, the p-type GaP layer 914 concentrates current in the portion in contact with the ITO layer 918, which is an n-type transparent conductor, forming a current constriction mechanism. Note that an interlayer insulating layer 916 is provided between the ITO layer 918 and the p-type AlGaAs layer 912 in this embodiment. However, the attached diode formed of the n-type ITO layer 918 and the p-type AlGaAs layer 912 is reverse biased with respect to the forward bias of the light emitting thyristor. Basically no current flows. Therefore, if the reverse withstand voltage of the attached diode formed of the n-type ITO layer 918 and the p-type AlGaAs layer 912 is sufficient for the application, it may be omitted. With such a configuration, the lower semiconductor lamination portion of the portion substantially equivalent to the portion where the p-type GaP layer 914 and the n-type transparent conductive ITO layer 918 are in contact emits light, and most of the light is emitted by the DBR layer 904. is reflected to the side opposite to the substrate 900 .

In the exposure head 106 of this embodiment, the density of light emitting points (interval between light emitting elements) is determined according to the resolution. Each light emitting element inside the surface emitting element array chip is separated into a mesa structure 922 by an element separating groove 924. For example, when forming an image with a resolution of 1200 dpi, the distance between the element centers of adjacent light emitting elements (light emitting points) is are arranged to be 21.16 μm.

As described above, in the present embodiment, the exposure head 106 converts the resolution of binary image data with a resolution of 2400 dpi into multi-valued 1200 dpi image data (density data) by the filtering unit 408 . Furthermore, in the processing of the LUT 410, the image quality can be improved by adjusting the pulse width of the PWM signal that controls the light amount of the surface emitting element according to the control voltage and temperature using a lookup table. Further, when the image data is multi-valued, the amount of data transfer increases, which increases the communication speed of the interface section between the control board 415 and the drive board 202, increasing the radiation noise countermeasure cost. In this embodiment, the image data transmitted from the control board 415 to the drive board 202 is binary, and the multilevel conversion of the image data is performed in the exposure head 106, thereby enabling multilevel data without increasing the communication speed. can be processed.

As described above, according to this embodiment, it is possible to increase the gradation of the image data and improve the image quality while suppressing the cost of the interface unit between the controller unit and the exposure head.

1 to 29 surface emitting element array chip 102 photosensitive drum 106 exposure head 202 drive substrate 303 drive section 400 CPU
415 control board

Claims (12)

a photoreceptor rotating in a first direction;
an exposure unit having a plurality of surface emitting elements arranged in a second direction orthogonal to the first direction, and exposing the photoreceptor with the surface emitting elements;
a control unit that outputs image data to the exposure unit and controls image formation;
An image forming apparatus comprising
The control unit
generating means for generating the binary image data at a second resolution higher than the first resolution of the surface emitting element; and transmitting the binary image data generated by the generating means to the exposure section. a controller having a transmission means for
a control board on which the controller is mounted;
has
The exposure unit is
a driver having receiving means for receiving the image data of the second resolution and the binary value transmitted from the control unit, and controlling light emission of the surface emitting element;
a drive board on which the driver is mounted;
has
The control board and the drive board are connected by a cable,
The controller transmits the image data of the second resolution and the binary value to the driver via the cable through serial communication;
the driver has conversion means for converting the resolution in the second direction of the binary image data received by the reception means from the second resolution to the first resolution;
When converting the resolution of the image data in the second direction from the second resolution to the first resolution, the conversion means converts the density of the pixel after conversion to the density of the pixel before conversion and the density of the pixel before conversion. The binary image data is converted into multivalued image data larger than the binary data by performing interpolation based on the densities of pixels adjacent to pixels before conversion. image forming apparatus. 2. The image forming apparatus according to claim 1, wherein said surface emitting element controls the amount of light emitted by a pulse width of an input signal. The driver includes light amount correction means for correcting the light amount of the surface emitting element based on the image data converted to the first resolution by the conversion means and exposure control information for determining exposure conditions. 3. The image forming apparatus according to claim 2. The exposure control information is a voltage value or a current value for driving the surface emitting element,
4. The image forming apparatus according to claim 3, wherein said light amount correction means determines a minimum pulse width of said input signal based on said voltage value or said current value. A first detection means for detecting the temperature of the exposure unit,
The exposure control information is the temperature of the exposure unit detected by the first detection means,
5. The image forming apparatus according to claim 4, wherein said light amount correction means determines the maximum pulse width of said input signal based on said temperature. the cable has a plurality of communication paths for transmitting the image data;
6. The apparatus according to any one of claims 1 to 5, wherein each of said communication paths is associated in advance with said surface emitting element whose light emission is controlled by said driver based on said image data. image forming device. The exposure unit has a plurality of chips having a plurality of the surface emitting elements,
When performing the interpolation processing for the density of the pixels at the edge of the chip , the conversion means performs the interpolation processing based on the density of the pixels at the edge of the chip adjacent to the edge of the chip . 7. The image forming apparatus according to any one of claims 1 to 6, wherein: The converting means converts the pixel image data at the first resolution after the conversion into a value obtained by multiplying the pixel image data at the second resolution before the conversion by a first coefficient; 8. The image forming apparatus according to claim 7, wherein the pixel data of a pixel adjacent to the pixel at the second resolution is multiplied by a second coefficient. The control unit controls the color shift in the first direction and the color shift in the second direction of the image data of the second resolution generated by the generation means, and the color shift in the second direction of the surface emitting element. 9. The image forming apparatus according to claim 1, further comprising misalignment correcting means for correcting the positional misalignment. a second detection means for detecting the amount of color shift in the first direction and the amount of color shift in the second direction of the image formed on the photoreceptor by the exposure unit;
The misregistration correction means generates the image data generated by the generating means based on the amount of color misregistration in the first direction and the amount of color misregistration in the second direction detected by the second detection means. 10. The image forming apparatus according to claim 9, wherein the color shift in the first direction and the color shift in the second direction are corrected. storage means for storing a positional deviation amount of the surface emitting element in the second direction with respect to the photoreceptor;
The misregistration correction means corrects the image data in which the color misregistration in the first direction and the color misregistration in the second direction are corrected based on the amount of misregistration stored in the storage means. 11. The image forming apparatus according to claim 10. The surface emitting elements of the exposure unit are arranged in two rows in the first direction, and the interval in the second direction between the surface emitting elements arranged in each row is an integral multiple of the second resolution. 12. The image forming apparatus according to any one of claims 1 to 11, wherein:

Images