JP2019201369A - Semiconductor device and electronic component including the semiconductor device, and electronic apparatus including the electronic component - Google Patents

Abstract

To provide a semiconductor device capable of achieving low power consumption and stable operation.SOLUTION: A semiconductor device includes a power supply circuit, a power supply management circuit, an arithmetic processing circuit, and a power switch. The power supply circuit has a function of generating a power supply potential, the power switch has a function that can control the supply and stop of the power supply potential to the arithmetic processing circuit, and the arithmetic processing circuit has a first circuit and a second circuit. The first circuit has a function that can hold data generated in the arithmetic processing circuit, and the second circuit has a function that can save and hold data held in the first circuit and a function that allows saved data to be returned in the first circuit. The second circuit and the power supply management circuit have a logic circuit including a transistor having metal oxide in a channel formation region.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device.

  One embodiment of the present invention relates to a semiconductor device. Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a memory device, an electro-optical device, a power storage device, a control system, a semiconductor circuit, and an electronic device may include a semiconductor device.

  A transistor in which a channel is formed using an oxide semiconductor such as an In—Ga—Zn oxide (In—Ga—Zn—O) (hereinafter also referred to as an OS transistor) is known. It is known that an off-state current of an OS transistor is extremely low because an oxide semiconductor has a larger band gap than silicon. Various semiconductor devices using the off-current characteristics of OS transistors have been proposed (for example, Patent Document 1).

  For example, Patent Document 1 discloses a semiconductor device in which power consumption is reduced by applying a PG (Power Gating) method in a memory circuit using an OS transistor as a cache memory.

US Patent Application Publication No. 2015/370313

  A power management unit (also referred to as PMU) for controlling the PG method may be configured by a transistor (hereinafter also referred to as a Si transistor) in which a channel is formed of silicon (Si). it can. However, since the Si transistor is exposed to high temperature and its electric characteristics fluctuate, there arises a problem that normal circuit operation cannot be maintained, and a problem that power consumption increases due to an increase in through current.

  An OS transistor which is applied to part of the memory circuit is provided in an upper layer of a region where a logic circuit including a Si transistor is provided. However, since logic circuits such as arithmetic circuits and power management circuits occupy a large area, there is a problem that a transistor pattern cannot be efficiently arranged in a layer where an OS transistor is provided, and a region where there is no circuit pattern (Dead Space) occurs. It was.

  In view of the above problems, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device that has low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device that can be downsized by efficiently arranging transistors.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention includes a power supply circuit, a power supply management circuit, an arithmetic processing circuit, and a power switch. The power supply circuit has a function of generating a power supply potential. The power switch includes an arithmetic processing circuit. The operation processing circuit has a first circuit and a second circuit, and the first circuit has a function capable of holding data generated by the operation processing circuit. The second circuit has a function of saving and holding the data held in the first circuit, and a function of returning the saved data to the first circuit. The power management circuit is a semiconductor device including a logic circuit including a transistor including a metal oxide in a channel formation region.

  In one embodiment of the present invention, the power management circuit is preferably a semiconductor device that is a programmable logic array including an input circuit, an AND gate circuit, and an OR gate circuit.

  In one embodiment of the present invention, an AND gate and an OR gate transistor each include a transistor including a metal oxide in a channel formation region, and the transistor has a function of storing charge in accordance with configuration data by being turned off. The semiconductor device which has is preferable.

  One embodiment of the present invention is an electronic component including the semiconductor device described above and a lead.

  One embodiment of the present invention is an electronic device including any one of the above semiconductor devices and the above electronic components, and at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing. is there.

  Note that other aspects of the present invention are described in the description and drawings in the following embodiments.

  One embodiment of the present invention can provide a highly reliable semiconductor device. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be downsized by efficiently arranging transistors can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 10 is a block diagram illustrating a structure example of a semiconductor device. FIG. 10 is a block diagram illustrating a structure example of a semiconductor device. FIG. 10 is a circuit diagram illustrating a structure example of a semiconductor device. FIG. 10 is a circuit diagram illustrating a structure example of a semiconductor device. FIG. 10 is a circuit diagram illustrating a structure example of a semiconductor device. FIG. 10 is a circuit diagram illustrating a structure example of a semiconductor device. FIG. 10 is a circuit diagram illustrating a structure example of a semiconductor device. 6 is a timing chart illustrating a configuration example of a semiconductor device. 6 is a timing chart illustrating a configuration example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structure example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structure example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structure example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structure example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structure example of a transistor. The flowchart and perspective schematic diagram which show an example of the preparation methods of an electronic component. : A diagram illustrating an example of an electronic device.

  Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In the present specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, the constituent elements referred to as “first” in one embodiment of the present specification and the like may be omitted in other embodiments or in the claims.

  Note that in the drawings, the same element, an element having a similar function, an element of the same material, an element formed at the same time, or the like may be denoted by the same reference numeral, and repeated description thereof may be omitted.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors), and the like.

  For example, in the case where a metal oxide is used for a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case where a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. That is, a transistor including a metal oxide in a channel formation region can be referred to as an “oxide semiconductor transistor” or an “OS transistor”. Similarly, the “transistor including an oxide semiconductor” described above is a transistor including a metal oxide in a channel formation region.

(Embodiment 1)
A structure of a semiconductor device which is one embodiment of the present invention is described.

  FIG. 1A is a block diagram of the semiconductor device of this embodiment. A semiconductor device 100 described in this embodiment includes an Si transistor layer 101 including an arithmetic processing circuit 111, a timer 112, and a switch 113, an OS transistor layer 102 including a power management circuit 121, and a memory circuit 122.

  The Si transistor layer 101 is a layer including a transistor including silicon in a channel formation region. The OS transistor layer 102 is a layer including a transistor including a metal oxide in a channel formation region. The Si transistor layer 101 is provided below the OS transistor layer 102. The OS transistor layer 102 is provided above the Si transistor layer 101.

  The semiconductor device 100 configures a programmable logic device using an OS transistor in an OS transistor layer 102 that is an upper layer of the Si transistor layer 101. In the OS transistor layer 102, not only the memory circuit but also the power management circuit 121 that performs arithmetic processing is provided, so that the area efficiency of the OS transistor layer 102 can be improved. In addition, the OS transistor layer 102 can have an arithmetic function and a memory function independent of the Si transistor layer 101. Therefore, as illustrated in FIG. 1A, the region of the OS transistor layer 102 which is a dead space can be efficiently used.

  As an example of a programmable logic device mounted on the OS transistor layer 102, PLA (Programmable Logic Array) is suitable. The PLA provided in the OS transistor layer 102 is preferable because internal connection information can be repeatedly changed by using an extremely low off-state current of an OS transistor described later.

  By adopting a hybrid process in which the OS transistor layer 102 is provided on the Si transistor layer 101, a power management circuit 121 that performs arithmetic processing can be provided in the BEOL (Back End Of Line) unit. A part of the function which has been used can be processed by the OS transistor layer 102.

  With the configuration of one embodiment of the present invention, for example, signal processing in a circuit such as the power management circuit 121 that does not require much operation speed is processed in the OS transistor layer 102, and thus used in the power control circuit. The gate elements for the Si transistor layer 101 are not necessary. Therefore, by using the gate element of the Si transistor layer 101 whose function is substituted for the OS transistor layer 102 and surplus, the circuit scale of the Si transistor layer 101 is expanded to improve the function of arithmetic processing, or it becomes unnecessary. The performance of the semiconductor device 100 can be improved, for example, by removing the gate element of the Si transistor layer 101 and reducing the circuit area.

  In addition, unlike the Si transistor, the OS transistor can maintain good transistor characteristics even in a high temperature environment. Therefore, the semiconductor device 100 that can operate satisfactorily even in a high temperature environment can be obtained.

  FIG. 1B is a block diagram for explaining the semiconductor device 100 of FIG.

  In FIG. 1B, in addition to the Si transistor layer 101 having the arithmetic processing circuit 111, the timer 112 and the switch 113, the power management circuit 121 and the OS transistor layer 102 having the memory circuit 122 illustrated in FIG. A power supply circuit 103 and an input circuit 104 are shown.

  The arithmetic processing circuit 111 includes an arithmetic processing unit (not shown) and memory circuits 122 and 123 capable of storing data generated by the arithmetic processing. For example, the arithmetic processing unit is a processor such as a CPU or a GPU. The memory circuit 123 is a register provided in the Si transistor layer 101 for temporarily storing data obtained by calculation. The memory circuit 123 has a function of holding data during a period when power supply voltage is supplied. In the memory circuit 123, data is lost during the period when the supply of the power supply voltage is stopped.

  The memory circuit 122 is provided in the OS transistor layer. The memory circuit 122 has a function of saving and holding the data held in the memory circuit 123 when the power supply voltage is stopped, and a function of returning the saved data to the memory circuit 123. For example, the memory circuit 122 includes an OS transistor and a capacitor, and can hold charges corresponding to data even when the supply of power supply voltage is stopped by utilizing the extremely low off-state current of the OS transistor. It has a function. Therefore, the arithmetic processing circuit 111 can keep holding the data generated by the arithmetic processing in a period before and after applying the PG method.

  The timer 112 has a function of generating a signal IN_t every predetermined period in accordance with the clock signal. Although the timer 112 is illustrated as being provided in the Si transistor layer 101, the timer 112 may be provided in the OS transistor layer 102 when it is not necessary to operate at high speed. The signal IN_t generated by the timer 112 is output to the power management circuit 121.

  The power supply circuit 103 has a function of generating and outputting a power supply potential for driving each circuit included in the Si transistor layer 101 and the OS transistor layer 102. In FIG. 1B, a voltage VDD and a voltage VSS (<VDD) are illustrated as power supply potentials.

  The switch 113 has a function as a power switch for applying the PG method to the arithmetic processing circuit 111. The switch 113 has a function of controlling whether to supply or stop the supply of the voltage VDD and the voltage VSS to the arithmetic processing circuit 111 in accordance with the signal OUT from the power management circuit 121. Although the switch 113 is illustrated as being provided in the Si transistor layer 101, the switch 113 may be provided in the OS transistor layer when it is not necessary to operate at high speed.

  The input circuit 104 is an external input unit such as a touch sensor or a sensing unit such as a temperature sensor. The signal IN_s generated by the input circuit 104 is output to the power management circuit 121.

  The power management circuit 121 has a function of generating an output signal OUT in accordance with an input signal such as the signal IN_s or the signal IN_t. The power management circuit 121 is a logic circuit including an OS transistor, that is, a transistor having a metal oxide in a channel formation region. Specifically, the signal can be processed by a programmable arithmetic circuit such as a programmable logic device. The power management circuit 121 does not need to be operated as fast as the arithmetic processing unit. Therefore, a desired function can be realized by the performance of the OS transistor.

  Unlike the arithmetic processing circuit 111, the power management circuit 121 needs to be continuously driven. Therefore, an operation with excellent reliability can be realized by configuring the circuit with an OS transistor whose transistor characteristic variation is small due to a change in environmental temperature or the like.

  As an example of a programmable logic device mounted on the OS transistor layer 102, PLA (Programmable Logic Array) is suitable. The PLA provided in the OS transistor layer 102 is preferable because internal connection information can be repeatedly changed by using an extremely low off-state current of an OS transistor described later.

  In addition, since the OS transistor has a very low current flowing between the source and the drain when it is off, so-called off current, the through current can be reduced. Therefore, since the through current can be further reduced when operated as a dynamic type unipolar PLA, low power consumption can be achieved.

  Next, a configuration example of a dynamic PLA that can be mounted using only OS transistors will be described with reference to FIGS. An example of a method for driving the dynamic PLA shown in FIGS. 2 to 7 will be described with reference to FIGS. A unipolar PLA with a small static current can be configured by using a dynamic PLA. A dynamic PLA described below will be described in a configuration in which it is operated in synchronization with the four-phase clocks of the clock signals PH1 to PH4.

  FIG. 2A is a block diagram of a power management circuit 121 that can operate as a dynamic PLA. The power management circuit 121 includes an input circuit 130, an AND gate circuit 140, and an OR gate circuit 150.

  A plurality of input signals IN_1 to IN_n (n is a natural number of 2 or more) are input to the input circuit 130 from the timer 112, the input circuit 104, and the like. The input circuit 130 has a function of outputting input signals IN_1 to IN_n and inverted input signals IN_1b to IN_nb. The input circuit 130 functions as a buffer circuit and an inverter circuit. Input circuit 130 receives clock signals PH1 and PH2 for controlling the operation.

  Input signals IN_1 to IN_n and inverted input signals IN_1b to IN_nb are input from the input circuit 130 to the AND gate circuit 140. The AND gate circuit 140 includes a programmable switch array capable of switching the number of input signals and a drive circuit. The AND gate circuit 140 outputs signals ANL_1 to ANL_j (j is a natural number equal to or greater than 2; ANL_j-1, ANL_j, and ANL_j + 1 are illustrated in FIG. 2A) corresponding to the logical product of the input signals. Clock signals PH2 and PH3 for controlling the operation are input to AND gate circuit 140. The AND gate circuit 140 is supplied with various control signals for inputting and outputting signals for switching the connection relationship in the programmable switch array via the bit line BL, the word line WL, and the wiring ANS. Note that the wiring ANS is a source line and has a function of supplying a ground potential.

  Signal input signals ANL_1 to ANL_j are input from the AND gate circuit 140 to the OR gate circuit 150. The OR gate circuit 150 includes a programmable switch array capable of switching the number of input signals and a drive circuit. The OR gate circuit 150 outputs signals OUT_1 to OUT_k (k is a natural number equal to or greater than 2; OUT_k−1, OUT_k, and OUT_k + 1 are illustrated in FIG. 2A) corresponding to the logical sum of the input signals. Clock signals PH3 and PH4 for controlling the operation are input to the OR gate circuit 150. Various control signals for inputting / outputting signals for switching the connection relationship in the programmable switch array are supplied to the OR gate circuit 150 via the bit line BL, the word line WL, and the wiring ORS. Note that the wiring ORS is a source line and has a function of supplying a ground potential.

  The input circuit 130, the AND gate circuit 140, and the OR gate circuit 150 illustrated in FIG. 2A can be represented as illustrated in FIG. In FIG. 2B, the AND gate circuit 140 includes a programmable switch array 141 and the OR gate circuit 150 includes a programmable switch array 151. Each of the programmable switch array 141 and the programmable switch array 151 has a function as a memory circuit for holding internal connection information as configuration data. The memory circuit is preferable because it can repeatedly change the internal connection information by using an extremely low off-state current of the OS transistor.

  FIG. 3A is a circuit diagram illustrating a configuration example of the input circuit 130.

  The input circuit 130 has a plurality of dynamic type unipolar inverter circuits. FIG. 3A illustrates one dynamic type unipolar inverter circuit. The dynamic unipolar inverter circuit includes a transistor Tr1, a transistor Tr2, and a transistor Tr3, and has a function of generating a signal INB obtained by inverting the input signal IN.

  The transistors Tr1 and Tr2 are controlled to be turned on or off according to the clock signals PH1 and PH2. The transistor Tr3 is controlled to be turned on or off according to the input signal IN. The dynamic unipolar inverter circuit can output a signal INB in accordance with whether each transistor is on or off.

  Note that the dynamic unipolar inverter circuit included in the input circuit 130 may have a structure of the input circuit 130A illustrated in FIG. FIG. 3B illustrates a structure in which the gate and the back gate of each transistor included in the dynamic unipolar inverter circuit are connected. With this structure, the amount of current flowing through the transistor can be increased.

  Alternatively, the dynamic unipolar inverter circuit included in the input circuit 130 may have a structure of the input circuit 130B illustrated in FIG. In FIG. 3C, a different potential (Vbg) is applied to the back gate of each transistor included in the dynamic unipolar inverter circuit. With this structure, the threshold voltage of the transistor can be controlled.

  In the following description and drawings, the back gate of the OS transistor is omitted as shown in FIG. 3A, but the back gate is provided as shown in FIGS. 3B and 3C. You can also

  FIG. 4 shows a configuration example of the programmable switch array 141 included in the AND gate circuit 140.

  In FIG. 4, as an example of the programmable switch array 141, the programmable switch circuit S [i−1, j−1], the programmable switch circuit S [i−1, j], and the programmable switch circuit S [i−1, j + 1] are illustrated for the sake of explanation. , Programmable switch circuit S [i-1, j + 2], programmable switch circuit S [i, j-1], programmable switch circuit S [i, j], programmable switch circuit S [i, j + 1], programmable switch circuit S [ i, j + 2], programmable switch circuit S [i + 1, j-1], programmable switch circuit S [i + 1, j], programmable switch circuit S [i + 1, j + 1], programmable switch circuit S [i + 2, j + 2] Show.

  Each of the programmable switch circuits S includes a transistor Tr4, a transistor Tr5, a transistor Tr6, and a capacitor C1.

  FIG. 5 shows a configuration example in which the drive circuit included in the AND gate circuit 140 and the above-described programmable switch array 141 are combined.

  The drive circuit includes a drive circuit R [i−1], a drive circuit R [i], and a drive circuit R [i + 1].

  The drive circuit R includes a transistor Tr7 and a transistor Tr8.

  FIG. 6 shows a configuration example of the programmable switch array 151 included in the OR gate circuit 150.

  In FIG. 6, as a programmable switch array 151, a programmable switch circuit S [i−1, k−1], a programmable switch circuit S [i−1, k], and a programmable switch circuit S [i−1, k + 1] are illustrated for the sake of explanation. , Programmable switch circuit S [i, k−1], programmable switch circuit S [i, k], programmable switch circuit S [i, k + 1], programmable switch circuit S [i + 1, k−1], programmable switch circuit S [ i + 1, k] and programmable switch circuit S [i + 1, k + 1] are illustrated.

  Each of the programmable switch circuits S includes a transistor Tr4, a transistor Tr5, a transistor Tr6, and a capacitor C1.

  FIG. 7 shows a configuration example in which the drive circuit included in the OR gate circuit 150 and the above-described programmable switch array 151 are combined.

  The programmable OR drive circuit includes a drive circuit R [k−1], a drive circuit R [k], and a drive circuit R [k + 1].

  FIG. 8 is a timing chart for explaining the operation of the dynamic unipolar PLA having the circuits described in FIGS. 3 to 7 described above. FIG. 8 illustrates an operation of writing configuration data for setting a connection relationship.

  At time T1, the word line WL [i−1] is set to an H level potential, the bit line BL [j−1], the bit line BL [j], the bit line BL [j + 1], the bit line BL [j + 2], the bit Voltages representing desired data d1, data d4, data d7, data d10, data d13, data d16, and data d19 on line BL [k−1], bit line BL [k], and bit line BL [k + 1], respectively. Supply. Holding node N [i−1, j−1], holding node N [i−1, j], holding node N [i−1, j + 1], holding node N [i−1, j + 2], holding node N [ i-1, k-1], holding node N [i-1, k], holding node N [i-1, k + 1] include data d1, data d4, data d7, data d10, data d13, data d16 and data d19 are respectively written.

  At time T2, the word line WL [i-1] is set to an L level potential, whereby writing to the programmable switch circuit connected to the word line WL [i-1] is completed.

  At time T3, the word line WL [i] is set to an H level potential, the bit line BL [j−1], the bit line BL [j], the bit line BL [j + 1], the bit line BL [j + 2], and the bit line BL Voltages representing desired data d2, data d5, data d8, data d11, data d14, data d17, and data d20 are supplied to [k−1], bit line BL [k], and bit line BL [k + 1], respectively. Then, holding node N [i, j-1], holding node N [i, j], holding node N [i, j + 1], holding node N [i, j + 2], holding node N [i, k-1] , Data d2, data d5, data d8, data d11, data d14, data d17, and data d20 are written to holding node N [i, k] and holding node N [i, k + 1], respectively.

  At time T4, the word line WL [i] is set to an L-level potential, whereby writing to the programmable switch circuit connected to the word line WL [i] is completed.

  At time T5, the word line WL [i + 1] is set to an H level potential, the bit line BL [j-1], the bit line BL [j], the bit line BL [j + 1], the bit line BL [j + 2], and the bit line BL Voltages representing desired data d3, data d6, data d9, data d12, data d15, data d18, and data d21 are supplied to [k−1], bit line BL [k], and bit line BL [k + 1], respectively. Then, holding node N [i + 1, j−1], holding node N [i + 1, j], holding node N [i + 1, j + 1], holding node N [i + 1, j + 2], holding node N [i + 1, k−1] , Holding node N [i + 1, k] and holding node N [i + 1, k + 1] have data d3, data d6, data d9, data d12, data d15, data d18, and data d21. Re respectively are written.

  At time T6, the word line WL [i + 1] is set to an L-level potential, whereby writing to the programmable switch circuit connected to the word line WL [i + 1] is completed.

  FIG. 9 shows an example of a timing chart for explaining an operation when performing a logical operation of a dynamic unipolar PLA having the circuits described in FIGS. 3 to 7 described above.

  At time T7, the input signal in1 and the input signal in3 are supplied to the AND input signal line IN [n-1] and the AND input signal line IN [n].

  At time T8, the clock signal PH1 is set to the H level potential, and the AND input signal line INB connected to the output terminals of the dynamic unipolar inverter circuit INV [n-1] and the dynamic unipolar inverter circuit INV [n]. [J] and the AND input signal line INB [j + 2] are precharged to the H level potential.

  At time T9, the clock signal PH1 is set to the L level potential, whereby the precharge of the AND input signal line INB [j] and the AND input signal line INB [j + 2] is completed.

  At time T10, the clock signal PH2 is set to an H-level potential, whereby inverted signals of the input signal in1 and the input signal in3 are supplied to the AND input signal line INB [j] and the AND input signal line INB [j + 2], respectively. Is done. The drive circuit R [i-1], the drive circuit R [i], and the drive circuit R [i + 1] are used to generate an AND output signal line ANL [i-1], an AND output signal line ANL [i], and an AND output signal line. ANL [i + 1] is precharged to High.

  At time T11, the clock signal PH2 is set to the L level potential, whereby the voltage supply of the AND input signal line INB [j] and the AND input signal line INB [j + 2] and the AND output signal line ANL [i−1] are obtained. The precharge of the AND output signal line ANL [i] and the AND output signal line ANL [i + 1] is completed.

  At a time T12, the clock signal PH3 is set to an H level potential, whereby the AND output signal line ANL [i−1] is generated by the drive circuit R [i−1], the drive circuit R [i], and the drive circuit R [i + 1]. , AND output signal line ANL [i], AND output signal line ANL [i + 1], a potential a1 representing the result of the logical operation of input signal in1, input signal in3 according to the logic function programmed in the programmable AND memory array, Transition to potential a3 and potential a5. Further, an OR output signal line OUT [k−1], an OR output signal line OUT [k], and an OR output signal line by the drive circuit R [k−1], the drive circuit R [k], and the drive circuit R [k + 1]. OUT [k + 1] is precharged to H level.

  At time T13, the clock signal PH3 is set to an L level potential, whereby voltage supply to the AND output signal line ANL [i−1], the AND output signal line ANL [i], and the AND output signal line ANL [i + 1] , OR output signal line OUT [k−1], OR output signal line OUT [k], and OR output signal line OUT [k + 1] are precharged.

  At time T14, the clock signal PH4 is set to an H level potential, whereby the OR output signal line OUT [k−1] is generated by the drive circuit R [k−1], the drive circuit R [k], and the drive circuit R [k + 1]. , OR output signal line OUT [k], OR output signal line OUT [k + 1], potential ao1 representing the result of the logical operation of input signal in1 and input signal in3 according to the logic function programmed in the programmable OR memory array, Transition to potential ao3 and potential ao5.

  At time 15, the clock signal PH4 is set to the L level potential, so that the voltage supply to the OR output signal line OUT [k−1], the OR output signal line OUT [k], and the OR output signal line OUT [k + 1] is performed. finish. As described above, at time 7 to time T8, one logical operation represented by the main additive standard form for the input signal in1 and the input signal in3 is completed. The input signal in2 and the input signal in4 are supplied to the AND input signal line IN [n-1] and the AND input signal line input terminal IN [n].

  At time T <b> 16, the clock signal PH <b> 1 is set to the H level potential so that the AND input connected to the output terminals of the dynamic unipolar inverter circuit INV [n−1] and the dynamic unipolar inverter circuit INV [n]. The signal line INB [j] and the AND input signal line INB [j + 2] are precharged to the H level.

  At time T <b> 17, the clock signal PH <b> 1 is set to an L level potential, whereby the precharge of the AND input signal line INB [j] and the AND input signal line INB [j + 2] is completed.

  At time T18, the clock signal PH2 is set to an H level potential so that the inverted signals of the input signal in2 and the input signal in4 are supplied to the AND input signal line INB [j] and the AND input signal line INB [j + 2], respectively. Is done. The drive circuit R [i-1], the drive circuit R [i], and the drive circuit R [i + 1] are used to generate an AND output signal line ANL [i-1], an AND output signal line ANL [i], and an AND output signal line. ANL [i + 1] is precharged to H level.

  At time T19, the clock signal PH2 is set to the L level potential, whereby the voltage supply of the AND input signal line INB [j] and the AND input signal line INB [j + 2] and the AND output signal line ANL [i-1] are obtained. The precharge of the AND output signal line ANL [i] and the AND output signal line ANL [i + 1] is completed.

  At a time T20, the clock signal PH3 is set to an H level potential, whereby the AND output signal line ANL [i−1] is generated by the drive circuit R [i−1], the drive circuit R [i], and the drive circuit R [i + 1]. , AND output signal line ANL [i], AND output signal line ANL [i + 1], potential a2 representing the result of the logical operation of input signal in2, input signal in4 according to the logic function programmed in the programmable AND memory array, Transition to potential a4 and potential a6. Further, an OR output signal line OUT [k−1], an OR output signal line OUT [k], and an OR output signal line by the drive circuit R [k−1], the drive circuit R [k], and the drive circuit R [k + 1]. OUT [k + 1] is precharged to H level.

  At time T21, the clock signal PH3 is set to an L level potential, whereby voltage supply to the AND output signal line ANL [i−1], the AND output signal line ANL [i], and the AND output signal line ANL [i + 1] , OR output signal line OUT [k−1], OR output signal line OUT [k], and OR output signal line OUT [k + 1] are precharged.

  At time T22, the clock signal PH4 is set to an H level potential, whereby the OR output signal line OUT [k−1] is generated by the driver circuit R [k−1], the driver circuit R [k], and the driver circuit R [k + 1]. ], An output signal line OUT [k], an OR output signal line OUT [k + 1], a potential ao2 representing the result of the logical operation of the input signal in2 and the input signal in4 according to the logic function programmed in the programmable OR memory array, Transition to potential ao4 and potential ao6.

  At time 23, the clock signal PH4 is set to the L level potential, whereby the voltage supply to the OR output signal line OUT [k−1], the OR output signal line OUT [k], and the OR output signal line OUT [k + 1] is increased. finish. As described above, at time 16 to time T23, one logical operation expressed in the main additive standard form with respect to the input signal in2 and the input signal in4 is completed.

  With the above structure, a dynamic unipolar PLA can be mounted on the OS transistor layer. By configuring the power management circuit 121 with an OS transistor having a small variation in transistor characteristics, it is possible to reduce a variation in electrical characteristics due to a change in environmental temperature, so that an operation with excellent reliability can be realized. In addition, the PLA provided in the OS transistor layer 102 can repeatedly change the internal connection information by using an extremely low off-state current of the OS transistor.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, structural examples of a Si transistor applicable to the transistor of the Si transistor layer 101 described in the above embodiment and an OS transistor applicable to the transistor of the OS transistor layer 102 are described.

<Configuration example of semiconductor device>
The semiconductor device illustrated in FIG. 10 includes a transistor 300, a transistor 500, and a capacitor 600. 11A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 11B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 11C is a cross-sectional view of the transistor 300 in the channel width direction. FIG.

  The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). Since the transistor 500 has a low off-state current, stored data can be held for a long time by using the transistor 500 for a semiconductor device. That is, since the frequency of the refresh operation is low or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.

  The semiconductor device described in this embodiment includes a transistor 300, a transistor 500, and a capacitor 600 as illustrated in FIG. The transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistor 300 and the transistor 500.

  The transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.

  In the transistor 300, as illustrated in FIG. 11C, the upper surface of the semiconductor region 313 and the side surface in the channel width direction are covered with a conductor 316 with an insulator 315 interposed therebetween. In this manner, when the transistor 300 is of the Fin type, an effective channel width is increased, whereby the on-state characteristics of the transistor 300 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 300 can be improved.

  Note that the transistor 300 may be either a p-channel type or an n-channel type.

  The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, by using GaAs, GaAlAs, or the like, the transistor 300 may be a HEMT (High Electron Mobility Transistor).

  The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

  The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

  Note that Vth of the transistor can be adjusted by determining a work function depending on a material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

  Note that the transistor 300 illustrated in FIGS. 10A and 10B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method. For example, like the transistor 500, the transistor 300 may be formed using an oxide semiconductor.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.

  As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

  The insulator 322 may function as a planarization film for planarizing a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

  The insulator 324 is preferably formed using a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

  As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 500, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

  Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 324 is preferably equal to or less than 0.7 times that of the insulator 326, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with the capacitor 600 or the conductor 328 connected to the transistor 500, the conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 10, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. The insulator 350, the insulator 352, and the insulator 354 are each provided with a conductor 356. The conductor 356 functions as a plug connected to the transistor 300 or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 500 can be suppressed.

  For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

  A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 10, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 500 can be suppressed.

  A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 10, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. In addition, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 370. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 500 can be suppressed.

  A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 10, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 500 can be suppressed.

  In the above description, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described. However, the semiconductor device according to this embodiment It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

  Over the insulator 384, the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are sequentially stacked. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

  For example, the insulator 510 and the insulator 514 are formed using a film having a barrier property such that hydrogen or an impurity does not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 500 is provided. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

  As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 500, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  As the film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500.

  For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 512 and the insulator 516, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  A conductor 518 and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In particular, the insulator 510 and the conductor 518 in a region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

  A transistor 500 is provided above the insulator 516.

  As illustrated in FIGS. 11A and 11B, the transistor 500 includes an insulator 520 provided over the insulator 516, an insulator 522 provided over the insulator 520, and the insulator 522. The insulator 524 disposed above, the oxide 530a disposed on the insulator 524, the oxide 530b disposed on the oxide 530a, and the oxide 530b are disposed apart from each other. A conductor 542a and a conductor 542b; an insulator 580 which is disposed over the conductor 542a and the conductor 542b and has an opening formed between the conductor 542a and the conductor 542b; Conductor 560, oxide 530b, conductor 542a, conductor 542b, insulator 580, insulator 550 disposed between conductor 560, oxide 530b, conductor 5 With 2a, conductor 542b, and an insulator 580, an insulator 550, and a oxide 530c disposed between.

  11A and 11B, the insulator 544 is preferably provided between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. . 11A and 11B, the conductor 560 includes a conductor 560a provided inside the insulator 550 and a conductor provided so as to be embedded inside the conductor 560a. 560b. 11A and 11B, an insulator 574 is preferably provided over the insulator 580, the conductor 560, and the insulator 550.

  Hereinafter, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as an oxide 530. The conductor 542a and the conductor 542b may be collectively referred to as a conductor 542.

  Note that in the transistor 500, a structure in which three layers of the oxide 530a, the oxide 530b, and the oxide 530c are stacked in the vicinity of the region where the channel is formed is described; however, the present invention is not limited thereto. It is not a thing. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a stacked structure of four or more layers may be provided. In the transistor 500, the conductor 560 is illustrated as a two-layer structure; however, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure including three or more layers. In addition, the transistor 500 illustrated in FIGS. 10A to 11B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  Here, the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be disposed in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

  Further, since the conductor 560 is formed in a self-aligned manner in a region between the conductors 542a and 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Accordingly, parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Thus, the switching speed of the transistor 500 can be improved and high frequency characteristics can be obtained.

  The insulator 550 functions as a gate insulating film.

  Here, the insulator 524 in contact with the oxide 530 is preferably an insulator containing more oxygen than that in the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has a thickness of 0.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

  In the case where the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).

  The insulator 522 has a function of suppressing diffusion of oxygen and impurities, so that the oxygen included in the oxide 530 does not diffuse to the insulator 520 side and is preferable.

For example, the insulator 522 is so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to a thinner gate insulating film. By using a high-k material for the insulator functioning as a gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.

  In particular, an insulator including one or both of oxides of aluminum and hafnium, which is an insulating material having a function of suppressing diffusion of impurities and oxygen (the oxygen hardly transmits), may be used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator 522 is formed using such a material, the insulator 522 suppresses release of oxygen from the oxide 530 and entry of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Acts as a layer.

  Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  In addition, the insulator 520 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high dielectric constant can be obtained by combining an insulator of a high-k material and the insulator 520. Can do.

  Note that the insulator 520, the insulator 522, and the insulator 524 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.

  In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including a channel formation region. For example, the oxide 530 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium) It is preferable to use a metal oxide such as one or a plurality selected from hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 530, an In—Ga oxide or an In—Zn oxide may be used.

  A metal oxide functioning as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.

  When the oxide 530 includes the oxide 530a below the oxide 530b, diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b can be suppressed. In addition, by including the oxide 530c over the oxide 530b, diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b can be suppressed.

  Note that the oxide 530 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 530b. It is preferable. In the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. In the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a. For the oxide 530c, a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.

  The energy at the lower end of the conduction band of the oxide 530a and the oxide 530c is preferably higher than the energy at the lower end of the conduction band of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than the electron affinity of the oxide 530b.

  Here, at the junction of the oxide 530a, the oxide 530b, and the oxide 530c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band in the junction of the oxide 530a, the oxide 530b, and the oxide 530c is continuously changed or continuously joined. In order to achieve this, the density of defect states in the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c is preferably low.

  Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed. be able to. For example, in the case where the oxide 530b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 530a and the oxide 530c.

  At this time, the main path of carriers is the oxide 530b. When the oxide 530a and the oxide 530c have the above structure, the density of defect states at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 500 can obtain a high on-state current.

  Over the oxide 530b, a conductor 542 (a conductor 542a and a conductor 542b) functioning as a source electrode and a drain electrode is provided. As the conductor 542, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. It is preferable. Also, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.

  In addition, as illustrated in FIG. 11A, a region 543 (a region 543a and a region 543b) may be formed as a low resistance region at and near the interface between the oxide 530 and the conductor 542. is there. At this time, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. In addition, a channel formation region is formed in a region between the region 543a and the region 543b.

  When the conductor 542 is provided so as to be in contact with the oxide 530, the oxygen concentration in the region 543 may be reduced in some cases. In addition, a metal compound layer including the metal contained in the conductor 542 and the component of the oxide 530 may be formed in the region 543 in some cases. In such a case, the carrier density in the region 543 increases, and the region 543 becomes a low resistance region.

  The insulator 544 is provided so as to cover the conductor 542 and suppresses oxidation of the conductor 542. At this time, the insulator 544 may be provided so as to cover a side surface of the oxide 530 and to be in contact with the insulator 524.

  As the insulator 544, a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like is used. it can.

  In particular, the insulator 544 is preferably formed using aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process. Note that the insulator 544 is not an essential component in the case where the conductor 542 is a material having oxidation resistance or the conductivity is not significantly lowered even when oxygen is absorbed. What is necessary is just to design suitably according to the transistor characteristic to request | require.

The insulator 550 functions as a gate insulating film. The insulator 550 is preferably provided in contact with the inside (upper surface and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator from which oxygen is released by heating. For example, in the temperature programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorbed oxygen converted to oxygen molecules is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ^19. An oxide film having atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.

  Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

  An insulator from which oxygen is released by heating is provided as the insulator 550 so as to be in contact with the top surface of the oxide 530c, so that oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Can be supplied. Further, similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

  Further, a metal oxide may be provided between the insulator 550 and the conductor 560 in order to efficiently supply excess oxygen included in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing the metal oxide that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

  The conductor 560 functioning as a gate electrode is illustrated as a two-layer structure in FIGS. 11A and 11B, but may have a single-layer structure or a stacked structure including three or more layers.

The conductor 560a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N ₂ O, NO, NO _{2, and the} like) and a copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules). When the conductor 560a has a function of suppressing the diffusion of oxygen, the conductivity of the conductor 560b can be suppressed from being oxidized by oxygen contained in the insulator 550 and thus reduced. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion.

  The conductor 560b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b also functions as a wiring, and thus a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.

  The insulator 580 is provided over the conductor 542 with the insulator 544 provided therebetween. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

  The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

  The opening of the insulator 580 is formed so as to overlap with a region between the conductors 542a and 542b. Thus, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.

  In miniaturization of a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, when the thickness of the conductor 560 is increased, the conductor 560 can have a shape with a high aspect ratio. In this embodiment mode, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, the conductor 560 can be formed without collapsing during the process even when the conductor 560 has a high aspect ratio. Can do.

  The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By depositing the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Accordingly, oxygen can be supplied into the oxide 530 from the excess oxygen region.

  For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. Can do.

  In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by a sputtering method can serve as an oxygen supply source and function as a barrier film for impurities such as hydrogen.

  In addition, an insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. As in the case of the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

  The conductors 540a and 540b are provided in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same structure as a conductor 546 and a conductor 548 described later.

  An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500.

  An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include the conductor 546, the conductor 548, and the like. Is embedded.

  The conductor 546 and the conductor 548 function as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

  The conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug connected to the transistor 500 or a wiring. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

  The conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements as a component (Tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

  In FIGS. 10A and 10B, the conductor 612 and the conductor 610 have single-layer structures; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

  A conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

  An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may function as a planarization film that covers the concave and convex shapes below the insulator 650.

  By using this structure, in a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

<Example of transistor structure>
Note that the transistor 500 of the semiconductor device described in this embodiment is not limited to the above structure. Hereinafter, structural examples that can be used for the transistor 500 will be described.

<Structure Example 1 of Transistor>
A structural example of the transistor 510A will be described with reference to FIGS. 12A, 12B, and 12C. FIG. 12A is a top view of the transistor 510A. FIG. 12B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 12C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 12A, some elements are omitted for clarity.

  12A, 12B, and 12C, the transistor 510A, the insulator 511 functioning as an interlayer film, the insulator 512, the insulator 514, the insulator 516, the insulator 580, the insulator 582, and the insulator A body 584 is shown. In addition, a conductor 546 (a conductor 546a and a conductor 546b) that is electrically connected to the transistor 510A and functions as a contact plug is illustrated.

  The transistor 510A includes a conductor 560 functioning as a gate electrode (conductors 560a and 560b), an insulator 550 functioning as a gate insulating film, and an oxide 530 (oxide 530a) having a region where a channel is formed. , An oxide 530b, and an oxide 530c), a conductor 542a functioning as one of a source and a drain, a conductor 542b functioning as the other of a source and a drain, and an insulator 574.

  In the transistor 510A illustrated in FIG. 12, the oxide 530c, the insulator 550, and the conductor 560 are provided in an opening provided in the insulator 580 with an insulator 574 interposed therebetween. The oxide 530c, the insulator 550, and the conductor 560 are disposed between the conductor 542a and the conductor 542b.

  The insulator 511 and the insulator 512 function as an interlayer film.

As the interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) An insulator such as TiO ₃ (BST) can be used in a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  For example, the insulator 511 preferably functions as a barrier film which prevents impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, the insulator 511 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom (the impurity is difficult to transmit). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). For example, aluminum oxide, silicon nitride, or the like may be used as the insulator 511. With this structure, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side than the insulator 511 can be suppressed.

  For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  In the transistor 510A, the conductor 560 may function as a gate electrode.

  The insulator 514 and the insulator 516 function as interlayer films similarly to the insulator 511 or the insulator 512. For example, the insulator 514 preferably functions as a barrier film which prevents impurities such as water or hydrogen from entering the transistor 510A from the substrate side. With this structure, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side than the insulator 514 can be suppressed. For example, the insulator 516 preferably has a lower dielectric constant than the insulator 514. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The insulator 522 preferably has a barrier property. Since the insulator 522 has a barrier property, the insulator 522 functions as a layer that suppresses entry of impurities such as hydrogen from the peripheral portion of the transistor 510A to the transistor 510A.

The insulator 522 includes, for example, aluminum oxide, hafnium oxide, aluminum and an oxide containing hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or ( An insulator including a so-called high-k material such as Ba, Sr) TiO ₃ (BST) is preferably used in a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to a thinner gate insulating film. By using a high-k material for the insulator functioning as a gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.

  For example, the insulator 521 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high relative dielectric constant can be obtained by combining an insulator of a high-k material and an insulator 522. Can do.

  The oxide 530 having a region functioning as a channel formation region includes an oxide 530a, an oxide 530b over the oxide 530a, and an oxide 530c over the oxide 530b. By including the oxide 530a below the oxide 530b, diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b can be suppressed. In addition, by including the oxide 530c over the oxide 530b, diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor which is a kind of the metal oxide described above can be used.

  Note that the oxide 530c is preferably provided in the opening provided in the insulator 580 with the insulator 574 interposed therebetween. In the case where the insulator 574 has barrier properties, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.

  One of the conductors 542 functions as a source electrode and the other functions as a drain electrode.

  For the conductor 542a and the conductor 542b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the metal as a main component can be used. . In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

  Further, although a single layer structure is shown in FIG. 12, a stacked structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film are preferably stacked. Further, a titanium film and an aluminum film may be stacked. Also, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and a tungsten film A two-layer structure in which copper films are stacked may be used.

  In addition, a titanium film or a titanium nitride film and a three-layer structure in which an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film and an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

  Further, a barrier layer may be provided over the conductor 542. The barrier layer is preferably formed using a substance having a barrier property against oxygen or hydrogen. With this structure, the conductor 542 can be prevented from being oxidized when the insulator 574 is formed.

  For the barrier layer, for example, a metal oxide can be used. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used.

  By having the barrier layer, the material selection range of the conductor 542 can be widened. For example, the conductor 542 can be formed using a material that has low oxidation resistance but high conductivity, such as tungsten or aluminum. For example, a conductor that can be easily formed or processed can be used.

  The insulator 550 functions as a gate insulating film. The insulator 550 is preferably provided in the opening provided in the insulator 580 with the oxide 530c and the insulator 574 interposed therebetween.

  As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to a thinner gate insulating film. In that case, the insulator 550 may have a stacked structure. The insulator that functions as a gate insulating film has a stacked structure of a high-k material and a thermally stable material, so that the gate potential during transistor operation can be reduced while maintaining the physical film thickness. It becomes. In addition, it is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant.

  The conductor 560 functioning as a gate electrode includes a conductor 560a and a conductor 560b over the conductor 560a. For the conductor 560a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.

  When the conductor 560a has a function of suppressing diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by including the conductor 560a, oxidation of the conductor 560b can be suppressed and reduction in conductivity can be prevented.

  As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. As the conductor 560a, an oxide semiconductor that can be used as the oxide 530 can be used. In that case, by forming the conductor 560b by a sputtering method, the electrical resistance value of the conductor 560a can be reduced to obtain a conductor. This can be called an OC (Oxide Conductor) electrode.

  The conductor 560b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In addition, since the conductor 560 functions as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

  An insulator 574 is provided between the insulator 580 and the transistor 510A. As the insulator 574, an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

  By including the insulator 574, it is possible to suppress diffusion of water and impurities such as hydrogen included in the insulator 580 into the oxide 530b through the oxide 530c and the insulator 550. Further, the conductor 560 can be prevented from being oxidized by excess oxygen which the insulator 580 has.

  The insulator 580, the insulator 582, and the insulator 584 function as an interlayer film.

  The insulator 582 preferably functions as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor 510A from the outside, like the insulator 514.

  The insulator 580 and the insulator 584 preferably have a dielectric constant lower than that of the insulator 582 as in the case of the insulator 516. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The transistor 510A may be electrically connected to another structure through a plug or a wiring such as the insulator 580, the insulator 582, and the conductor 546 embedded in the insulator 584.

  As a material of the conductor 546, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or a stacked layer. For example, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  For example, as the conductor 546, for example, by using a stacked structure of tantalum nitride which is a conductor having a barrier property against hydrogen and oxygen and tungsten having high conductivity, conductivity as a wiring is increased. While being held, diffusion of impurities from outside can be suppressed.

  With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

<Structural Example 2 of Transistor>
A structural example of the transistor 510B will be described with reference to FIGS. 13A, 13B, and 13C. FIG. 13A is a top view of the transistor 510B. FIG. 13B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 13C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 13A, some elements are omitted for clarity.

  The transistor 510B is a modification of the transistor 510A. Therefore, in order to prevent repetition of description, points different from the transistor 510A are mainly described.

  The transistor 510B includes a region where the conductor 542 (the conductor 542a and the conductor 542b) overlaps with the oxide 530c, the insulator 550, and the conductor 560. With such a structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

  The conductor 560 functioning as a gate electrode includes a conductor 560a and a conductor 560b over the conductor 560a. For the conductor 560a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules).

  When the conductor 560a has a function of suppressing diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by including the conductor 560a, oxidation of the conductor 560b can be suppressed and reduction in conductivity can be prevented.

  The insulator 574 is preferably provided so as to cover the top surface and the side surface of the conductor 560, the side surface of the insulator 550, and the side surface of the oxide 530c. Note that the insulator 574 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

  By providing the insulator 574, oxidation of the conductor 560 can be suppressed. Further, with the insulator 574, diffusion of water and impurities such as hydrogen included in the insulator 580 into the transistor 510B can be suppressed.

  Further, an insulator 576 having a barrier property (the insulator 576a and the insulator 576b) may be provided between the conductor 546 and the insulator 580. By providing the insulator 576, it is possible to suppress the oxygen of the insulator 580 from reacting with the conductor 546 and oxidizing the conductor 546.

  In addition, by providing the insulator 576 having a barrier property, the selection range of a material for a conductor used for a plug or a wiring can be widened. For example, a low power consumption semiconductor device can be provided by using a metal material that absorbs oxygen and has high conductivity for the conductor 546. Specifically, a material having high conductivity while having low oxidation resistance such as tungsten or aluminum can be used. For example, a conductor that can be easily formed or processed can be used.

<Structure Example 3 of Transistor>
An example of a structure of the transistor 510C is described with reference to FIGS. 14A, 14B, and 14C. FIG. 14A is a top view of the transistor 510C. FIG. 14B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 14C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 14A, some elements are omitted for clarity.

  The transistor 510C is a modification of the transistor 510A. Therefore, in order to prevent repetition of description, points different from the transistor 510A are mainly described.

  In the transistor 510C illustrated in FIG. 14, the conductor 547a is disposed between the conductor 542a and the oxide 530b, and the conductor 547b is disposed between the conductor 542b and the oxide 530b. Here, the conductor 542a (conductor 542b) extends beyond the upper surface of the conductor 547a (conductor 547b) and the side surface on the conductor 560 side, and has a region in contact with the upper surface of the oxide 530b. Here, as the conductor 547, a conductor that can be used for the conductor 542 may be used. Further, the thickness of the conductor 547 is preferably greater than that of the conductor 542 at least.

  The transistor 510C illustrated in FIG. 14 has the above structure, whereby the conductor 542 can be closer to the conductor 560 than the transistor 510A. Alternatively, the conductor 560 can overlap the end portion of the conductor 542a and the end portion of the conductor 542b. Thus, the substantial channel length of the transistor 510C can be shortened, and the on-state current and frequency characteristics can be improved.

  The conductor 547a (conductor 547b) is preferably provided so as to overlap with the conductor 542a (conductor 542b). With such a structure, in etching for forming an opening in which the conductor 546a (conductor 546b) is embedded, the conductor 547a (conductor 547b) functions as a stopper, and the oxide 530b is over-etched. Can be prevented.

  Further, the transistor 510C illustrated in FIG. 14 may have a structure in which the insulator 545 is provided in contact with the insulator 544. The insulator 544 preferably functions as a barrier insulating film which suppresses entry of impurities such as water or hydrogen and excess oxygen into the transistor 510C from the insulator 580 side. As the insulator 545, an insulator that can be used for the insulator 544 can be used. As the insulator 544, for example, a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide may be used.

<Structural Example 4 of Transistor>
A structural example of the transistor 510D will be described with reference to FIGS. 15A, 15B, and 15C. FIG. 15A is a top view of the transistor 510D. FIG. 15B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 15C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 15A, some elements are omitted for clarity.

  A transistor 510D is a modification of the transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.

  15A to 15C, the insulator 550 is provided over the oxide 530c, and the metal oxide 552 is provided over the insulator 550. In addition, the conductor 560 is provided over the metal oxide 552 and the insulator 570 is provided over the conductor 560. In addition, the insulator 571 is provided over the insulator 570.

  The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 that suppresses diffusion of oxygen between the insulator 550 and the conductor 560, diffusion of oxygen into the conductor 560 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductor 560 due to oxygen can be suppressed.

  Note that the metal oxide 552 may function as part of the gate. For example, an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552. In that case, by forming the conductor 560 by a sputtering method, the electric resistance value of the metal oxide 552 can be reduced to form a conductive layer. This can be called an OC (Oxide Conductor) electrode.

  The metal oxide 552 may function as a part of the gate insulating film. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 550, the metal oxide 552 is preferably a metal oxide that is a high-k material with a high relative dielectric constant. By setting it as the said laminated structure, it can be set as the laminated structure stable with respect to a heat | fever, and a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. Further, the equivalent oxide thickness (EOT) of the insulating layer functioning as the gate insulating film can be reduced.

  In the transistor 510D, the metal oxide 552 is illustrated as a single layer; however, a stacked structure including two or more layers may be employed. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulating film may be stacked.

  In the case where the metal oxide 552 serves as the gate electrode, the on-state current of the transistor 510D can be improved without weakening the influence of the electric field from the conductor 560. Alternatively, in the case of functioning as a gate insulating film, the distance between the conductor 560 and the oxide 530 is maintained by the physical thickness of the insulator 550 and the metal oxide 552, so that the conductor 560 Leakage current with the oxide 530 can be suppressed. Therefore, by providing a stacked structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the electric field strength applied from the conductor 560 to the oxide 530 can be reduced. It can be easily adjusted as appropriate.

  Specifically, the metal oxide 552 can be used as the metal oxide 552 by reducing the resistance of an oxide semiconductor that can be used for the oxide 530. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

  In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulating layer containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process. Note that the metal oxide 552 is not an essential component. What is necessary is just to design suitably according to the transistor characteristic to request | require.

  The insulator 570 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxidation of the conductor 560 with oxygen from above the insulator 570 can be suppressed. In addition, impurities such as water or hydrogen from above the insulator 570 can be prevented from entering the oxide 530 through the conductor 560 and the insulator 550.

  The insulator 571 functions as a hard mask. By providing the insulator 571, when the conductor 560 is processed, the side surface of the conductor 560 is substantially vertical. Specifically, the angle formed between the side surface of the conductor 560 and the substrate surface is 75 ° to 100 °, Preferably, it can be set to 80 degrees or more and 95 degrees or less.

  Note that the insulator 571 may also have a function as a barrier layer by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 570 is not necessarily provided.

  By using the insulator 571 as a hard mask, a part of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c is selectively removed, so that these side surfaces are substantially matched. In addition, a part of the surface of the oxide 530b can be exposed.

  In addition, the transistor 510D includes a region 531a and a region 531b in part of the exposed oxide 530b surface. One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region.

  The formation of the region 531a and the region 531b is performed by introducing an impurity element such as phosphorus or boron into the exposed oxide 530b surface by using, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment. This can be achieved. Note that the “impurity element” in this embodiment and the like refers to an element other than the main component elements.

  In addition, a metal film is formed after part of the surface of the oxide 530b is exposed, and then heat treatment is performed, whereby elements contained in the metal film are diffused into the oxide 530b, so that the regions 531a and 531b are formed. You can also

  In the region where the impurity element of the oxide 530b is introduced, the electrical resistivity decreases. Therefore, the region 531a and the region 531b may be referred to as “impurity region” or “low resistance region”.

  By using the insulator 571 and / or the conductor 560 as a mask, the region 531a and the region 531b can be formed in a self-alignment manner. Thus, the region 531a and / or the region 531b and the conductor 560 do not overlap with each other, and parasitic capacitance can be reduced. Further, no offset region is formed between the channel formation region and the source / drain region (the region 531a or the region 531b). By forming the region 531a and the region 531b in a self-aligned manner, an increase in on-state current, a reduction in threshold voltage, an improvement in operating frequency, and the like can be realized.

  Note that an offset region may be provided between the channel formation region and the source / drain region in order to further reduce the off-state current. The offset region is a region having a high electrical resistivity and is a region where the impurity element is not introduced. The offset region can be formed by introducing the impurity element described above after the insulator 575 is formed. In this case, the insulator 575 functions as a mask similarly to the insulator 571 and the like. Therefore, the impurity element is not introduced into the region overlapping with the insulator 575 of the oxide 530b, and the electrical resistivity of the region can be kept high.

  The transistor 510D includes the insulator 575 on the side surfaces of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c. The insulator 575 is preferably an insulator having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having voids, or resin Preferably there is. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having a hole for the insulator 575 because an excess oxygen region can be easily formed in the insulator 575 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. The insulator 575 preferably has a function of diffusing oxygen.

  In addition, the transistor 510D includes the insulator 574 over the insulator 575 and the oxide 530. The insulator 574 is preferably formed by a sputtering method. By using a sputtering method, an insulator with few impurities such as water or hydrogen can be formed. For example, aluminum oxide may be used as the insulator 574.

  Note that an oxide film formed by a sputtering method may extract hydrogen from a deposition target structure. Therefore, the insulator 574 absorbs hydrogen and water from the oxide 530 and the insulator 575, whereby the hydrogen concentration in the oxide 530 and the insulator 575 can be reduced.

<Structure Example 5 of Transistor>
A structural example of the transistor 510E will be described with reference to FIGS. FIG. 16A is a top view of the transistor 510E. FIG. 16B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. FIG. 16C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 16A, some elements are omitted for clarity.

  The transistor 510E is a modified example of the transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.

  16A to 16C, the conductor 542 is not provided and a region 531a and a region 531b are included in part of the exposed surface of the oxide 530b. One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region. An insulator 573 is provided between the oxide 530b and the insulator 574.

  A region 531 (a region 531a and a region 531b) illustrated in FIG. 16 is a region where the following element is added to the oxide 530b. The region 531 can be formed by using, for example, a dummy gate.

  Specifically, a dummy gate may be provided over the oxide 530b, and the dummy gate may be used as a mask, and an element for reducing the resistance of the oxide 530b may be added. In other words, the element is added to a region where the oxide 530 does not overlap with the dummy gate, so that the region 531 is formed. In addition, as an addition method of the element, an ion implantation method in which an ionized source gas is added by mass separation, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like Can be used.

  Note that typically, boron or phosphorus is given as an element for reducing the resistance of the oxide 530. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, or the like may be used. Typical examples of the rare gas element include helium, neon, argon, krypton, and xenon. The concentration of the element may be measured using secondary ion mass spectrometry (SIMS) or the like.

  In particular, boron and phosphorus are preferable because an amorphous silicon or low-temperature polysilicon production line apparatus can be used. Existing equipment can be diverted, and capital investment can be suppressed.

  Subsequently, an insulating film to be the insulator 573 and an insulating film to be the insulator 574 may be formed over the oxide 530b and the dummy gate. By stacking the insulating film to be the insulator 573 and the insulating film to be the insulator 574, a region where the region 531 overlaps with the oxide 530c and the insulator 550 can be provided.

  Specifically, after an insulating film to be the insulator 580 is provided over the insulating film to be the insulator 574, a CMP (Chemical Mechanical Polishing) process is performed on the insulating film to be the insulator 580, whereby the insulator 580 and the insulator 580 are formed. A part of the insulating film is removed to expose the dummy gate. Subsequently, when the dummy gate is removed, part of the insulator 573 in contact with the dummy gate may be removed. Therefore, the insulator 574 and the insulator 573 are exposed on the side surface of the opening provided in the insulator 580, and a part of the region 531 provided in the oxide 530b is exposed on the bottom surface of the opening. To do. Next, after an oxide film to be the oxide 530c, an insulating film to be the insulator 550, and a conductive film to be the conductor 560 are sequentially formed in the opening, CMP treatment or the like is performed until the insulator 580 is exposed. The transistor illustrated in FIG. 16 can be formed by removing part of the oxide film to be the oxide 530c, the insulating film to be the insulator 550, and the conductive film to be the conductor 560.

  Note that the insulator 573 and the insulator 574 are not essential components. What is necessary is just to design suitably according to the transistor characteristic to request | require.

  In the transistor illustrated in FIGS. 16A and 16B, an existing device can be diverted and the conductor 542 is not provided, so that cost can be reduced.

  Note that this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
In this embodiment, a structure of a metal oxide that can be used for the OS transistor described in the above embodiment will be described.

<Composition of metal oxide>
In the present specification and the like, there are cases where they are described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers and the insulating function is a carrier. This function prevents electrons from flowing. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

  Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of metal oxide>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, for example, a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), or a pseudo-amorphous oxide semiconductor (a-liquid oxide semiconductor) is used. OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

  As the oxide semiconductor used for the semiconductor of the transistor, a thin film with high crystallinity is preferably used. By using the thin film, the stability or reliability of the transistor can be improved. Examples of the thin film include a single crystal oxide semiconductor thin film and a polycrystalline oxide semiconductor thin film. However, in order to form a single crystal oxide semiconductor thin film or a polycrystalline oxide semiconductor thin film on a substrate, a high temperature or laser heating step is required. Therefore, the cost of the manufacturing process increases and the throughput also decreases.

  It was reported in Non-Patent Document 2 and Non-Patent Document 3 that an In—Ga—Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009. Here, it has been reported that CAAC-IGZO can be formed on a substrate at a low temperature with c-axis orientation, crystal grain boundaries are not clearly confirmed. Furthermore, it has been reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.

  In 2013, an In—Ga—Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 4). Here, it is reported that nc-IGZO has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and regularity is not observed in crystal orientation between different regions. Yes.

  Non-Patent Document 5 and Non-Patent Document 6 show the transition of the average crystal size due to electron beam irradiation on the thin films of CAAC-IGZO, nc-IGZO, and IGZO having low crystallinity. In an IGZO thin film with low crystallinity, crystalline IGZO of about 1 nm has been observed even before irradiation with an electron beam. Therefore, it is reported here that the existence of a complete amorphous structure in IGZO could not be confirmed. Furthermore, it has been shown that the CAAC-IGZO thin film and the nc-IGZO thin film have higher stability against electron beam irradiation than the low crystalline IGZO thin film. Therefore, a CAAC-IGZO thin film or an nc-IGZO thin film is preferably used as a semiconductor of the transistor.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

  Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.

  The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

  The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable even at a high temperature (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be increased.

  The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

  Oxide semiconductors have various structures and different properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<Transistor with oxide semiconductor>
Next, the case where the above oxide semiconductor is used for a transistor is described.

  Note that by using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

In addition, a transistor including the oxide semiconductor has extremely small leakage current in a non-conducting state. Specifically, an off-current per 1 μm of channel width of the transistor is on the order of yA / μm (10 ⁻²⁴ A / μm). This is shown in Non-Patent Document 7. For example, a low power consumption CPU using a characteristic in which a transistor including an oxide semiconductor has low leakage current is disclosed (see Non-Patent Document 8).

  In addition, an application of a transistor using an oxide semiconductor to a display device using a characteristic of low leakage current of the transistor has been reported (see Non-Patent Document 9). In the display device, the displayed image is switched several tens of times per second. The number of switching of images per second is called a refresh rate. In addition, the refresh rate may be referred to as a drive frequency. Such high-speed screen switching that is difficult for human eyes to perceive is considered as a cause of eye fatigue. In view of this, it has been proposed to reduce the number of times of image rewriting by lowering the refresh rate of the display device. In addition, power consumption of the display device can be reduced by driving at a reduced refresh rate. Such a driving method is called idling stop (IDS) driving.

For the transistor, an oxide semiconductor with low carrier density is preferably used. In the case where the carrier density of the oxide semiconductor film is decreased, the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

  In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.

  In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

  Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in an adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

<Impurity>
Here, the influence of each impurity in the oxide semiconductor is described.

In the oxide semiconductor, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density is increased, and the oxide semiconductor is likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Accordingly, nitrogen in the oxide semiconductor is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ^{3 in} SIMS, preferably 5 × 10 ^18. atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

  By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

  The discovery of the CAAC structure and the nc structure contributes to improvement in electrical characteristics and reliability of a transistor including an oxide semiconductor having a CAAC structure or an nc structure, and a reduction in manufacturing process cost and throughput. In addition, research on application of the transistor to a display device and an LSI utilizing the characteristic that the leakage current of the transistor is low is underway.

  Note that this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
In this embodiment, an electronic component, an electronic device including the electronic component, and the like will be described as an example of a semiconductor device.

<Example of electronic component manufacturing method>
FIG. 17A is a flowchart illustrating an example of a method for manufacturing an electronic component. The electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

  A semiconductor device including a transistor is completed by combining a plurality of parts that can be attached to and detached from a printed circuit board through an assembly process (post-process). The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step S31), the back surface of the substrate is ground (step S32). By reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and reduce the size of the component.

  A dicing process is performed in which the back surface of the substrate is ground to separate the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S33). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

  Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected with a thin metal wire (step S34). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

  The wire-bonded chip is subjected to a molding process that is sealed with an epoxy resin or the like (step S35). By performing the molding process, the inside of the electronic component is filled with resin, and it is possible to reduce damage to built-in circuit parts and wires due to mechanical external force, and to reduce deterioration of characteristics due to moisture and dust. it can.

  Next, the lead of the lead frame is plated. Then, the lead is cut and molded (step S36). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

  Next, a printing process (marking) is performed on the surface of the package (step S37). An electronic component is completed through a final inspection process (step S38) (step S39).

  The electronic component described above can include the semiconductor device described in the above embodiment. Therefore, an electronic component with reduced power consumption and reduced size can be realized.

  A perspective schematic view of the completed electronic component is shown in FIG. FIG. 17B is a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. As shown in FIG. 17B, the electronic component 700 includes a lead 701 and a circuit portion 703. The electronic component 700 is mounted on a printed circuit board 702, for example. A plurality of such electronic components 700 are combined and each is electrically connected on the printed circuit board 702 so that the electronic component 700 can be mounted inside the electronic device. The completed circuit board 704 is provided inside an electronic device or the like. For example, the electronic component 700 can be used as a random access memory that stores data and a processing unit that executes various processes such as an MCU (microcontroller unit) and an RFID tag.

  Therefore, the electronic component 700 includes digital signal processing, software defined radio, avionics (electronic equipment related to aviation such as communication equipment, navigation system, autopilot, and flight management system), ASIC prototyping, medical image processing, voice recognition, It can be applied to electronic parts (IC chips) of electronic devices in a wide range of fields such as cryptography, bioinformatics (biological information science), emulators of mechanical devices, and radio telescopes in radio astronomy. Such an electronic device includes a display device, a personal computer (PC), an image playback device including a recording medium (typically a display that can play back a recording medium such as a DVD: Digital Versatile Disc, and display the image. Apparatus). In addition, as an electronic device that can use the electronic component according to one embodiment of the present invention, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a camera (a video camera, a digital still camera, or the like), Wearable type display device or terminal (head mount type, goggles type, glasses type, armband type, bracelet type, necklace type, etc.), navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer , Printer multifunction peripherals, automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.

<Electronic equipment>
18A to 18F illustrate examples of electronic devices each including a display portion and driven by a battery.

  A portable game machine 900 illustrated in FIG. 18A includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, and the like. The display unit 903 is provided with a touch screen as an input device and can be operated with a stylus 908 or the like.

  An information terminal 910 illustrated in FIG. 18B includes a display portion 912, a microphone 917, a speaker portion 914, a camera 913, an external connection portion 916, an operation button 915, and the like in a housing 911. The display portion 912 includes a display panel using a flexible substrate and a touch screen. The information terminal 910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet PC, an electronic book terminal, or the like.

  A laptop PC 920 illustrated in FIG. 18C includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

  A video camera 940 illustrated in FIG. 18D includes a housing 941, a housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided on the housing 941, and the display portion 943 is provided on the housing 942. The housing 941 and the housing 942 are connected to each other by a connection portion 946. The angle between the housing 941 and the housing 942 can be changed by the connection portion 946. Depending on the angle of the housing 942 with respect to the housing 941, the orientation of the image displayed on the display portion 943 can be changed and the display / non-display of the image can be switched.

  FIG. 18E illustrates an example of a bangle information terminal. The information terminal 950 includes a housing 951, a display unit 952, and the like. The display portion 952 is supported by a housing 951 having a curved surface. Since the display portion 952 includes a display panel using a flexible substrate, an information terminal 950 that is flexible, light, and easy to use can be provided.

  FIG. 18F illustrates an example of a wristwatch-type information terminal. The information terminal 960 includes a housing 961, a display portion 962, a band 963, a buckle 964, operation buttons 965, an input / output terminal 966, and the like. The information terminal 960 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games.

  The display surface of the display portion 962 is curved, and display can be performed along the curved display surface. The display portion 962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be activated by touching an icon 967 displayed on the display unit 962. The operation button 965 can have various functions in addition to time setting, such as power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release. . For example, the function of the operation button 965 can be set by an operating system incorporated in the information terminal 960.

  In addition, the information terminal 960 can execute short-range wireless communication conforming to the communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the information terminal 960 includes an input / output terminal 966, and can directly exchange data with other information terminals via a connector. Charging can also be performed through the input / output terminal 966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 966.

  FIG. 18G illustrates an electric refrigerator-freezer as an example of a home appliance. The electric refrigerator-freezer 970 includes a housing 971, a refrigerator door 972, a refrigerator door 973, and the like.

  FIG. 18H is an external view illustrating an example of a structure of an automobile. The automobile 980 includes a vehicle body 981, wheels 982, a dashboard 983, lights 984, and the like.

  An electronic component including the semiconductor device according to any of the above embodiments is mounted on the electronic device described in this embodiment. Therefore, it is possible to provide an electronic device with reduced power consumption or capable of stable operation.

  Note that this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

(Additional notes regarding the description of this specification etc.)
The above embodiment and description of each component in the embodiment will be added below.

  The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined as appropriate.

  Note that the content (may be a part of content) described in one embodiment is different from the content (may be a part of content) described in the embodiment and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

  Further, in the present specification and the like, in the block diagram, the constituent elements are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground voltage (ground voltage), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  In this specification and the like, the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap with each other, or a channel is formed. This is the distance between the source and drain in the region.

  In this specification and the like, the channel width refers to, for example, a source in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed And the length of the part where the drain faces.

  In this specification and the like, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Si transistor layer 102 OS transistor layer 103 Power supply circuit 104 Input circuit 111 Arithmetic processing circuit 112 Timer 113 Switch 121 Power supply management circuit 122 Memory circuit 123 Memory circuit 130 Input circuit 130A Input circuit 130B Input circuit 140 AND gate circuit 141 Programmable Switch array 150 OR gate circuit 151 programmable switch array 300 transistor 311 substrate 313 semiconductor region 314a low resistance region 314b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 conductor 350 Insulator 352 insulator 354 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 conductor 370 insulator 372 insulator 74 insulator 376 conductor 380 insulator 382 insulator 384 insulator 386 conductor 500 transistor 510 insulator 510A transistor 510B transistor 510C transistor 510D transistor 510E transistor 511 insulator 512 insulator 514 insulator 516 insulator 518 conductor 520 insulator Body 521 insulator 522 insulator 524 insulator 530 oxide 530a oxide 530b oxide 530c oxide 531 region 531a region 531b region 540a conductor 540b conductor 542 conductor 542a conductor 542b conductor 543 region 543a region 543b region 544 Insulator 545 insulator 546 conductor 546a conductor 546b conductor 547 conductor 547a conductor 547b conductor 548 conductor 550 insulator 552 gold Metal oxide 560 Conductor 560a Conductor 560b Conductor 570 Insulator 571 Insulator 573 Insulator 574 Insulator 575 Insulator 576 Insulator 576a Insulator 576b Insulator 580 Insulator 581 Insulator 582 Insulator 584 Insulator 586 Insulator Body 600 capacitor 610 conductor 612 conductor 620 conductor 630 insulator 650 insulator 700 electronic component 701 lead 702 printed circuit board 703 circuit portion 704 circuit board 900 portable game machine 901 housing 902 housing 903 display portion 904 display portion 905 Microphone 906 Speaker 907 Operation key 908 Stylus 910 Information terminal 911 Case 912 Display portion 913 Camera 914 Speaker portion 915 Button 916 External connection portion 917 Microphone 921 Case 922 Display portion 923 Keyboard 924 Poi Video device 941 Case 942 Case 943 Display unit 944 Operation key 945 Lens 946 Connection unit 950 Information terminal 951 Case 952 Display unit 960 Information terminal 961 Case 962 Display unit 963 Band 964 Buckle 965 Operation button 966 Input / output Terminal 967 Icon 970 Electric refrigerator-freezer 971 Housing 972 Refrigeration room door 973 Freezing room door 980 Car 981 Car body 982 Wheel 983 Dashboard 984 Light

Claims (5)

A power circuit;
A power management circuit;
An arithmetic processing circuit;
A power switch,
The power supply circuit has a function of generating a power supply potential,
The power switch has a function of controlling supply and stop of the power supply potential to the arithmetic processing circuit,
The arithmetic processing circuit has a first circuit and a second circuit,
The first circuit has a function of holding data generated by the arithmetic processing circuit,
The second circuit has a function of saving and holding the data held in the first circuit, and a function of returning the saved data to the first circuit,
The semiconductor device, wherein the second circuit and the power management circuit include a logic circuit including a transistor including a metal oxide in a channel formation region. In claim 1,
The power supply management circuit is a semiconductor device which is a programmable logic array having an input circuit, an AND gate circuit, and an OR gate circuit. In claim 2,
The AND gate circuit and the OR gate circuit each include a transistor having a metal oxide in a channel formation region, and the transistor has a function of storing charges according to configuration data by turning off the transistor. A semiconductor device according to any one of claims 1 to 3;
And an electronic component having a lead. Any one of the semiconductor device according to claim 1 and the electronic component according to claim 4;
An electronic apparatus having at least one of a display device, a touch panel, a microphone, a speaker, operation keys, and a housing.