JP2019192729A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2019192729A
JP2019192729A JP2018082156A JP2018082156A JP2019192729A JP 2019192729 A JP2019192729 A JP 2019192729A JP 2018082156 A JP2018082156 A JP 2018082156A JP 2018082156 A JP2018082156 A JP 2018082156A JP 2019192729 A JP2019192729 A JP 2019192729A
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JP
Japan
Prior art keywords
heat
substrate
semiconductor device
conductive film
active element
Prior art date
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Pending
Application number
JP2018082156A
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Japanese (ja)
Inventor
将夫 近藤
Masao Kondo
将夫 近藤
大部　功
Isao Obe
功 大部
梅本　康成
Yasunari Umemoto
康成 梅本
山本靖久
Yasuhisa Yamamoto
靖久 山本
雅博 柴田
Masahiro Shibata
雅博 柴田
孝幸 筒井
Takayuki Tsutsui
孝幸 筒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
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Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2018082156A priority Critical patent/JP2019192729A/en
Priority to CN201910221467.1A priority patent/CN110391196B/en
Priority to TW108110313A priority patent/TWI708338B/en
Priority to US16/374,674 priority patent/US10957617B2/en
Publication of JP2019192729A publication Critical patent/JP2019192729A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

To provide a semiconductor device capable of efficiently dissipating heat diffused inside a substrate to the outside.SOLUTION: A semiconductor chip is mounted on a printed board. In the semiconductor chip, an active element is formed on a first surface opposed to the printed board. At a position different from the active element, a thermally conductive film made of a material having a coefficient of thermal conductivity higher than that of the substrate is provided. An insulating film covering the active element and the thermally conductive film is arranged on the first surface. A bump electrically connected to the thermally conductive film is provided on the insulating film. A through-via hole reaching the thermally conductive film from a second surface at an opposite side of the first surface is provided. A thermally conductive member made of a material having a coefficient of thermal conductivity higher than that of the substrate is continuously arranged from a region of the second surface overlapping with the active element in a plan view to an inner surface of the through-via hole. A bump of the semiconductor chip is connected to a land of the printed board, and the semiconductor chip is sealed by a sealing resin.SELECTED DRAWING: Figure 2

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

半導体チップに組み込まれた電力増幅器の動作時にトランジスタが自己発熱し、半導体チップの性能がトランジスタの動作温度の上昇とともに劣化する場合がある。半導体チップの劣化を抑制するために、発熱源であるトランジスタから半導体チップの外部に効率的に放熱することが望まれる。   When the power amplifier incorporated in the semiconductor chip is operated, the transistor self-heats, and the performance of the semiconductor chip may be deteriorated as the operating temperature of the transistor is increased. In order to suppress the deterioration of the semiconductor chip, it is desired to efficiently dissipate heat from the transistor which is a heat source to the outside of the semiconductor chip.

特許文献１に、モジュール基板に実装した半導体チップからの伝熱経路についての記載がある。特許文献１に記載された発明では、半導体チップのバンプから、モジュール基板の上面に形成された端子、及びモジュール基板の上面から下面まで達する放熱ビアを介して、モジュール基板の下面に形成された接地用の電極に至る伝熱経路が形成される。   Patent Document 1 describes a heat transfer path from a semiconductor chip mounted on a module substrate. In the invention described in Patent Document 1, the grounding formed on the lower surface of the module substrate through the bumps of the semiconductor chip, the terminals formed on the upper surface of the module substrate, and the heat radiation via extending from the upper surface to the lower surface of the module substrate. A heat transfer path leading to the electrode is formed.

接地用の電極には、トタンジスタのエミッタまたはソースが接続される。従って、エミッタやソースが伝熱経路の一部に含まれる。バンプに接続されて伝熱経路となるエミッタやソースは、通常、小面積であり、伝熱経路のうちエミッタやソースに接続される箇所が隘路になってしまう。このため、伝熱経路の熱抵抗を十分低くすることが困難である。   The emitter or source of the transistor is connected to the grounding electrode. Therefore, the emitter and the source are included in a part of the heat transfer path. The emitter or source that is connected to the bump and becomes the heat transfer path usually has a small area, and a portion connected to the emitter or source in the heat transfer path becomes a bottleneck. For this reason, it is difficult to sufficiently reduce the thermal resistance of the heat transfer path.

特許文献２に、放熱特性を向上させた半導体装置が開示されている。特許文献２に開示された半導体装置においては、外部接続パッドから、活性素子が形成された半導体基板の上面まで達する放熱構造が設けられている。半導体基板の上面に形成されたトランジスタで発生した熱は、放熱構造が配置された位置まで半導体基板の上面に沿って横方向に伝わり、その後、放熱構造を介して放熱される。   Patent Document 2 discloses a semiconductor device with improved heat dissipation characteristics. The semiconductor device disclosed in Patent Document 2 is provided with a heat dissipation structure that extends from an external connection pad to the upper surface of a semiconductor substrate on which an active element is formed. The heat generated in the transistor formed on the upper surface of the semiconductor substrate is transmitted laterally along the upper surface of the semiconductor substrate to the position where the heat dissipation structure is disposed, and then is radiated through the heat dissipation structure.

特開２０１１−１９８８６６号公報JP 2011-198866 A 特開２０１４−９９４７０号公報JP 2014-99470 A

トランジスタ等の発熱源で発生した熱は、半導体基板の上面に沿って横方向に伝わるほかに、半導体基板を厚さ方向にも伝わる。従来の半導体装置では、半導体基板の表面の発熱源で発生し、半導体基板の内部に拡散する熱を効率的に外部に放熱することが困難であった。   In addition to being transmitted laterally along the upper surface of the semiconductor substrate, heat generated by a heat source such as a transistor is also transmitted in the thickness direction of the semiconductor substrate. In the conventional semiconductor device, it is difficult to efficiently dissipate the heat generated by the heat source on the surface of the semiconductor substrate and diffusing inside the semiconductor substrate to the outside.

本発明の目的は、基板の内部に拡散する熱を効率的に外部に放熱することが可能な半導体装置を提供することである。   An object of the present invention is to provide a semiconductor device capable of efficiently dissipating heat diffusing inside a substrate to the outside.

本発明の一観点によると、
実装面にランドが設けられたプリント基板と、
前記プリント基板に実装された半導体チップと
を有し、
前記半導体チップは、
基板の、前記プリント基板に対向する第１面に形成された能動素子と、
前記基板の前記第１面の、前記能動素子とは異なる位置に設けられ、前記基板より熱伝導率の高い材料からなる熱伝導膜と、
前記基板の前記第１面の上に配置され、前記能動素子及び前記熱伝導膜を覆う絶縁膜と、
前記絶縁膜の上に配置され、前記熱伝導膜に電気的に接続されたバンプと、
前記基板の前記第１面とは反対側の第２面から前記熱伝導膜まで達する貫通ビアホールと、
平面視において前記能動素子と重なる前記第２面の領域から、前記貫通ビアホールの内面まで連続して配置され、前記基板より熱伝導率の高い材料からなる熱伝導部材と
を有し、
前記バンプが前記ランドに接続されており、前記半導体チップが封止樹脂で封止されている半導体装置が提供される。 According to one aspect of the invention,
A printed circuit board with a land on the mounting surface;
A semiconductor chip mounted on the printed circuit board;
The semiconductor chip is
An active element formed on a first surface of the substrate facing the printed circuit board;
A thermally conductive film made of a material having a higher thermal conductivity than the substrate, provided at a position different from the active element on the first surface of the substrate;
An insulating film disposed on the first surface of the substrate and covering the active element and the heat conducting film;
A bump disposed on the insulating film and electrically connected to the thermal conductive film;
A through via hole reaching from the second surface opposite to the first surface of the substrate to the heat conductive film;
A heat conduction member made of a material having a higher thermal conductivity than the substrate, which is continuously arranged from the region of the second surface overlapping the active element in plan view to the inner surface of the through via hole;
There is provided a semiconductor device in which the bump is connected to the land, and the semiconductor chip is sealed with a sealing resin.

本発明の他の観点によると、
基板の第１面に形成された能動素子と、
前記基板の前記第１面の、前記能動素子とは異なる位置に設けられ、前記基板より熱伝導率の高い材料からなる熱伝導膜と、
前記基板の前記第１面の上に配置され、前記能動素子及び前記熱伝導膜を覆う絶縁膜と、
前記絶縁膜の上に配置され、前記熱伝導膜に電気的に接続されたバンプと、
前記基板の前記第１面とは反対側の第２面に設けられ、平面視において前記能動素子及び前記熱伝導膜と少なくとも部分的に重なる凹部と、
前記凹部の内面に設けられ、前記基板より熱伝導率の高い材料からなる熱伝導部材と
を有し、
前記凹部の底面に配置された前記熱伝導部材と前記熱伝導膜とは、前記基板の一部分を挟んで対向している半導体装置が提供される。 According to another aspect of the invention,
An active element formed on the first surface of the substrate;
A thermally conductive film made of a material having a higher thermal conductivity than the substrate, provided at a position different from the active element on the first surface of the substrate;
An insulating film disposed on the first surface of the substrate and covering the active element and the heat conducting film;
A bump disposed on the insulating film and electrically connected to the thermal conductive film;
A concave portion provided on a second surface opposite to the first surface of the substrate, and at least partially overlapping the active element and the heat conductive film in plan view;
A heat conductive member provided on the inner surface of the concave portion and made of a material having a higher thermal conductivity than the substrate;
There is provided a semiconductor device in which the heat conducting member and the heat conducting film disposed on the bottom surface of the recess are opposed to each other with a part of the substrate interposed therebetween.

能動素子で発生して基板側に拡散する熱が、熱伝導部材、熱伝導膜、及びバンプを通って外部に放熱される。このため、基板の内部に拡散する熱を効率的に外部に放熱することができる。   The heat generated by the active element and diffused to the substrate side is radiated to the outside through the heat conducting member, the heat conducting film, and the bump. For this reason, the heat diffused inside the substrate can be efficiently radiated to the outside.

図１Ａは、第１実施例による半導体装置のブロック図であり、図１Ｂは、第１実施例による半導体装置の各回路のレイアウトを示す平面図であり、図１Ｃは、第１実施例による半導体装置の概略断面図である。1A is a block diagram of the semiconductor device according to the first embodiment, FIG. 1B is a plan view showing a layout of each circuit of the semiconductor device according to the first embodiment, and FIG. 1C is a semiconductor according to the first embodiment. It is a schematic sectional drawing of an apparatus. 図２Ａは、第１実施例による半導体装置に含まれる半導体チップに形成されている出力段増幅回路の平面図であり、図２Ｂは、図２Ａの一点鎖線２Ｂ−２Ｂにおける断面図である。2A is a plan view of an output stage amplifier circuit formed in a semiconductor chip included in the semiconductor device according to the first embodiment, and FIG. 2B is a cross-sectional view taken along one-dot chain line 2B-2B in FIG. 2A. 図３は、第１実施例による半導体装置のバンプの近傍の断面図である。FIG. 3 is a cross-sectional view of the vicinity of the bump of the semiconductor device according to the first embodiment. 図４は、第２実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 4 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the second embodiment. 図５Ａは、第３実施例による半導体装置に含まれる半導体チップに形成されている出力段増幅回路の平面図であり、図５Ｂは、図５Ａの一点鎖線５Ｂ−５Ｂにおける断面図である。5A is a plan view of an output stage amplifier circuit formed in a semiconductor chip included in the semiconductor device according to the third embodiment, and FIG. 5B is a cross-sectional view taken along one-dot chain line 5B-5B in FIG. 5A. 図６は、第４実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 6 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the fourth embodiment. 図７Ａは、第５実施例による半導体装置に含まれる半導体チップの断面図であり、図７Ｂは、第５実施例による半導体装置の各回路のレイアウトを示す平面図である。FIG. 7A is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the fifth embodiment, and FIG. 7B is a plan view showing a layout of each circuit of the semiconductor device according to the fifth embodiment. 図８は、第６実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 8 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the sixth embodiment. 図９は、第６実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 9 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the sixth embodiment.

［第１実施例］
図１Ａから図３までの図面を参照して、第１実施例による半導体装置について説明する。
図１Ａは、第１実施例による半導体装置のブロック図である。入力信号が、入力端子１５からインピーダンス整合回路１０を介してドライバ段増幅回路１１に入力される。ドライバ段増幅回路１１で増幅された信号が、インピーダンス整合回路１２を介して出力段増幅回路１３に入力される。出力段増幅回路１３で増幅された信号が出力端子１６から出力される。ドライバ段増幅回路１１にインダクタ１７を介して直流電力が供給される。出力段増幅回路１３にインダクタ１８を介して直流電力が供給される。 [First embodiment]
A semiconductor device according to the first embodiment will be described with reference to FIGS. 1A to 3.
FIG. 1A is a block diagram of the semiconductor device according to the first embodiment. An input signal is input from the input terminal 15 to the driver stage amplifier circuit 11 via the impedance matching circuit 10. The signal amplified by the driver stage amplifier circuit 11 is input to the output stage amplifier circuit 13 via the impedance matching circuit 12. The signal amplified by the output stage amplifier circuit 13 is output from the output terminal 16. DC power is supplied to the driver stage amplifier circuit 11 via the inductor 17. DC power is supplied to the output stage amplifier circuit 13 via the inductor 18.

図１Ｂは、第１実施例による半導体装置に含まれる半導体チップ３０の各回路のレイアウトを示す平面図である。半導体基板４０の表面に、インピーダンス整合回路１０、１２、ドライバ段増幅回路１１、出力段増幅回路１３、及び制御回路１４が形成されている。出力段増幅回路１３が形成されている領域に、半導体基板４０を厚さ方向に貫通する貫通ビアホール４１が設けられている。   FIG. 1B is a plan view showing a layout of each circuit of the semiconductor chip 30 included in the semiconductor device according to the first embodiment. Impedance matching circuits 10 and 12, a driver stage amplifier circuit 11, an output stage amplifier circuit 13, and a control circuit 14 are formed on the surface of the semiconductor substrate 40. A through via hole 41 that penetrates the semiconductor substrate 40 in the thickness direction is provided in a region where the output stage amplifier circuit 13 is formed.

貫通ビアホール４１は、後述するように、出力段増幅回路１３を構成するトランジスタで発生する熱を効率的に半導体チップ３０の外部まで伝導させる機能を持つ。ドライバ段増幅回路１１のトランジスタの発熱量は、出力段増幅回路１３のトランジスタの発熱量に比べて少ない。このため、出力段増幅回路１３に対応して貫通ビアホール４１を設けることが好ましい。ドライバ段増幅回路１１に対しては、貫通ビアホールを設けてもよいし、設けなくてもよい。   As will be described later, the through via hole 41 has a function of efficiently conducting heat generated by the transistors constituting the output stage amplifier circuit 13 to the outside of the semiconductor chip 30. The amount of heat generated by the transistor of the driver stage amplifier circuit 11 is smaller than the amount of heat generated by the transistor of the output stage amplifier circuit 13. For this reason, it is preferable to provide the through via hole 41 corresponding to the output stage amplifier circuit 13. A through via hole may or may not be provided for the driver stage amplifier circuit 11.

図１Ｃは、第１実施例による半導体装置の概略断面図である。プリント基板２０の実装面（図１Ｂにおいて上面）に半導体チップ３０が実装されている。半導体チップ３０は、半導体基板４０のプリント基板２０に対向する面（以下、第１面という。）に形成された複数のバンプ３１を含む。プリント基板２０は、実装面に形成された複数のランド２１、及び下面（実装面とは反対側の面）に形成された外部接続用の複数の電極２３を含む。   FIG. 1C is a schematic cross-sectional view of the semiconductor device according to the first embodiment. The semiconductor chip 30 is mounted on the mounting surface (the upper surface in FIG. 1B) of the printed circuit board 20. The semiconductor chip 30 includes a plurality of bumps 31 formed on a surface (hereinafter referred to as a first surface) of the semiconductor substrate 40 facing the printed circuit board 20. The printed circuit board 20 includes a plurality of lands 21 formed on the mounting surface and a plurality of electrodes 23 for external connection formed on the lower surface (the surface opposite to the mounting surface).

複数のランド２１のうち少なくとも１つはグランド用のランド２１であり、複数の電極２３のうち少なくとも１つはグランド用の電極２３である。グランド用のランド２１とグランド用の電極２３とが、複数のビア導体２４及び内層の配線２５を介して電気的に接続されている。   At least one of the plurality of lands 21 is a ground land 21, and at least one of the plurality of electrodes 23 is a ground electrode 23. A ground land 21 and a ground electrode 23 are electrically connected via a plurality of via conductors 24 and an inner layer wiring 25.

半導体チップ３０のバンプ３１がプリント基板２０のランド２１に接続されている。半導体チップ３０の複数のバンプ３１のうち少なくとも１つはグランド用のバンプ３１であり、グランド用のバンプ３１は、プリント基板２０のグランド用のランド２１に接続されている。半導体チップ３０は、封止樹脂２８によって封止されている。   The bumps 31 of the semiconductor chip 30 are connected to the lands 21 of the printed circuit board 20. At least one of the plurality of bumps 31 of the semiconductor chip 30 is a ground bump 31, and the ground bump 31 is connected to the ground land 21 of the printed circuit board 20. The semiconductor chip 30 is sealed with a sealing resin 28.

図２Ａは、第１実施例による半導体装置に含まれる半導体チップ３０に形成されている出力段増幅回路１３（図１Ａ）の平面図である。出力段増幅回路１３は、例えば相互に並列に接続され、一列に配列した４個のトランジスタ４２（能動素子）を含む。以下、トランジスタ４２が配列する方向を、単に「配列方向」という。トランジスタ４２は、例えばヘテロ接合バイポーラトランジスタである。   FIG. 2A is a plan view of the output stage amplifier circuit 13 (FIG. 1A) formed in the semiconductor chip 30 included in the semiconductor device according to the first embodiment. The output stage amplifier circuit 13 includes, for example, four transistors 42 (active elements) connected in parallel to each other and arranged in a line. Hereinafter, the direction in which the transistors 42 are arranged is simply referred to as “arrangement direction”. The transistor 42 is, for example, a heterojunction bipolar transistor.

トランジスタ４２の各々は、エミッタ電極Ｅ０、ベース電極Ｂ０、及びコレクタ電極Ｃ０を含む。図２Ａにおいて、エミッタ電極Ｅ０、ベース電極Ｂ０、及びコレクタ電極Ｃ０の領域にハッチングを付している。１つのトランジスタ４２に着目すると、配列方向に関してエミッタ電極Ｅ０の両側にそれぞれベース電極Ｂ０の一部分が配置され、さらにその両側にそれぞれコレクタ電極Ｃ０が配置されている。エミッタ電極Ｅ０の両側に配置されたベース電極Ｂ０の一部分は、エミッタ電極Ｅ０の外側で相互に連続している。例えば、ベース電極Ｂ０は、平面視においてエミッタ電極Ｅ０を三方向からＵ字状に取り囲んでいる。相互に隣り合うトランジスタ４２は、１つのコレクタ電極Ｃ０を共用している。   Each of the transistors 42 includes an emitter electrode E0, a base electrode B0, and a collector electrode C0. In FIG. 2A, regions of the emitter electrode E0, the base electrode B0, and the collector electrode C0 are hatched. Focusing on one transistor 42, a part of the base electrode B0 is disposed on both sides of the emitter electrode E0 in the arrangement direction, and further a collector electrode C0 is disposed on both sides thereof. Part of the base electrode B0 disposed on both sides of the emitter electrode E0 is continuous with the outside of the emitter electrode E0. For example, the base electrode B0 surrounds the emitter electrode E0 in a U shape from three directions in plan view. The transistors 42 adjacent to each other share one collector electrode C0.

複数の１層目のエミッタ配線Ｅ１が、それぞれ複数のエミッタ電極Ｅ０と重なるように配置されている。複数の１層目のベース配線Ｂ１が、それぞれ複数のベース電極Ｂ０の一部に重なり、重なり箇所から外側に引き出されている。線状部と複数の櫛歯部とを含む１層目のコレクタ配線Ｃ１の複数の櫛歯部が、それぞれ複数のコレクタ電極Ｃ０と重なっている。コレクタ配線Ｃ１の線状部は、コレクタ電極Ｃ０に隣接して、配列方向に関して一方の端のトランジスタ４２が配置された位置から他方の端のトランジスタ４２が配置された位置まで及び、複数の櫛歯部の各々に接続されている。   The plurality of first-layer emitter wirings E1 are arranged so as to overlap with the plurality of emitter electrodes E0, respectively. The plurality of first-layer base wirings B1 overlap with parts of the plurality of base electrodes B0, respectively, and are drawn out from the overlapping portions. The plurality of comb-teeth portions of the first-layer collector wiring C1 including the linear portion and the plurality of comb-teeth portions overlap with the plurality of collector electrodes C0, respectively. The linear portion of the collector wiring C1 is adjacent to the collector electrode C0 and extends from the position where the transistor 42 at one end in the arrangement direction is disposed to the position where the transistor 42 at the other end is disposed. Connected to each of the parts.

トランジスタ４２とは異なる位置に、熱伝導膜４３が配置されている。例えば、トランジスタ４２から見て１層目のコレクタ配線Ｃ１の線状部とは反対側に、熱伝導膜４３が配置されている。熱伝導膜４３は配列方向に長い形状を持ち、配列方向に関して一方の端のトランジスタ４２が配置された位置から他方の端のトランジスタ４２が配置された位置まで及んでいる。熱伝導膜４３は、１層目のベース配線Ｂ１、エミッタ配線Ｅ１、及びコレクタ配線Ｃ１と同一の金属材料、例えばＡｕで形成されており、同一の工程で成膜される。平面視において熱伝導膜４３の内側に貫通ビアホール４１が配置されている。   A heat conductive film 43 is disposed at a position different from that of the transistor 42. For example, the heat conductive film 43 is disposed on the opposite side to the linear portion of the first-layer collector wiring C <b> 1 when viewed from the transistor 42. The heat conductive film 43 has a long shape in the arrangement direction, and extends from the position where the transistor 42 at one end is arranged to the position where the transistor 42 at the other end is arranged in the arrangement direction. The heat conductive film 43 is made of the same metal material, for example, Au, as the first layer base wiring B1, emitter wiring E1, and collector wiring C1, and is formed in the same process. The through via hole 41 is disposed inside the heat conductive film 43 in plan view.

２層目のコレクタ配線Ｃ２が１層目のコレクタ配線Ｃ１の線状部と重なるように配置されている。２層目のエミッタ配線Ｅ２が、１層目のエミッタ配線Ｅ１及び熱伝導膜４３に重なるように配置されている。   The second-layer collector wiring C2 is arranged so as to overlap the linear portion of the first-layer collector wiring C1. The second-layer emitter wiring E2 is disposed so as to overlap the first-layer emitter wiring E1 and the heat conductive film 43.

最上層にバンプ３１が配置されている。バンプ３１は、平面視において２層目のエミッタ配線Ｅ２と重なるとともに、複数のエミッタ電極Ｅ０及び熱伝導膜４３と部分的に、または複数のエミッタ電極Ｅ０及び熱伝導膜４３の全体に重なる。   Bumps 31 are arranged on the uppermost layer. The bump 31 overlaps with the emitter wiring E2 of the second layer in plan view, and partially overlaps with the plurality of emitter electrodes E0 and the heat conduction film 43 or entirely over the plurality of emitter electrodes E0 and the heat conduction film 43.

図２Ｂは、図２Ａの一点鎖線２Ｂ−２Ｂにおける断面図である。半導体基板４０の上面（第１面）にトランジスタ４２が形成されている。半導体基板４０は、例えば半絶縁性のＧａＡｓからなる支持基板と、その上にエピタキシャル成長されたＧａＡｓからなるエピタキシャル成長層とを含む。エピタキシャル成長層のうち、トランジスタ４２が配置された領域には導電性が付与され、その他の領域は絶縁性とされている。   2B is a cross-sectional view taken along one-dot chain line 2B-2B in FIG. 2A. A transistor 42 is formed on the upper surface (first surface) of the semiconductor substrate 40. The semiconductor substrate 40 includes, for example, a support substrate made of semi-insulating GaAs and an epitaxial growth layer made of GaAs epitaxially grown thereon. In the epitaxial growth layer, the region where the transistor 42 is disposed is given conductivity, and the other regions are insulative.

トランジスタ４２は、コレクタ層、ベース層、及びエミッタ層からなる半導体メサと、ベース電極Ｂ０、及びエミッタ電極Ｅ０を含む。コレクタ電極Ｃ０（図２Ａ）は図２Ｂの断面には現れていない。半導体基板４０の上面の上に、トランジスタ４２を覆うＳｉＮ等の絶縁膜４５が配置されている。絶縁膜４５の上に、１層目のエミッタ配線Ｅ１、ベース配線Ｂ１、コレクタ配線Ｃ１、及び熱伝導膜４３が配置されている。１層目のエミッタ配線Ｅ１及びベース配線Ｂ１は、それぞれ絶縁膜４５に設けられた開口内を経由してエミッタ電極Ｅ０及びベース電極Ｂ０に接続されている。図２Ｂに示した断面においては、１層目のコレクタ配線Ｃ１の直下の絶縁膜４５には開口が設けられていない。熱伝導膜４３は、絶縁膜４５に設けられた開口内を経由して半導体基板４０の上面に接している。   The transistor 42 includes a semiconductor mesa composed of a collector layer, a base layer, and an emitter layer, a base electrode B0, and an emitter electrode E0. The collector electrode C0 (FIG. 2A) does not appear in the cross section of FIG. 2B. An insulating film 45 such as SiN covering the transistor 42 is disposed on the upper surface of the semiconductor substrate 40. On the insulating film 45, a first-layer emitter wiring E1, a base wiring B1, a collector wiring C1, and a heat conductive film 43 are arranged. The first-layer emitter wiring E1 and the base wiring B1 are connected to the emitter electrode E0 and the base electrode B0 through the openings provided in the insulating film 45, respectively. In the cross section shown in FIG. 2B, no opening is provided in the insulating film 45 immediately below the first-layer collector wiring C1. The heat conductive film 43 is in contact with the upper surface of the semiconductor substrate 40 through an opening provided in the insulating film 45.

１層目のエミッタ配線Ｅ１、ベース配線Ｂ１、コレクタ配線Ｃ１、及び熱伝導膜４３には、例えばＡｕ等の金属が用いられる。熱伝導膜４３に用いられる金属の熱伝導率は、半導体基板４０の熱伝導率より高い。   For the emitter wiring E1, the base wiring B1, the collector wiring C1, and the heat conductive film 43 in the first layer, for example, a metal such as Au is used. The heat conductivity of the metal used for the heat conductive film 43 is higher than the heat conductivity of the semiconductor substrate 40.

絶縁膜４５の上に、１層目のエミッタ配線Ｅ１、ベース配線Ｂ１、コレクタ配線Ｃ１、及び熱伝導膜４３を覆うように、絶縁膜４６が配置されている。絶縁膜４６は、例えばＳｉＮ膜と樹脂膜との２層構造を有し、絶縁膜４６の上面は平坦化されている。   An insulating film 46 is disposed on the insulating film 45 so as to cover the first-layer emitter wiring E 1, base wiring B 1, collector wiring C 1, and thermal conductive film 43. The insulating film 46 has, for example, a two-layer structure of a SiN film and a resin film, and the upper surface of the insulating film 46 is flattened.

絶縁膜４６の上に、２層目のエミッタ配線Ｅ２及び２層目のコレクタ配線Ｃ２が配置されている。２層目のエミッタ配線Ｅ２は、絶縁膜４６に設けられた開口内を経由して１層目のエミッタ配線Ｅ１に接続されるとともに、他の開口内を経由して熱伝導膜４３にも接続されている。２層目のコレクタ配線Ｃ２は、絶縁膜４６に設けられた開口内を経由して１層目のコレクタ配線Ｃ１に接続されている。   On the insulating film 46, a second-layer emitter wiring E2 and a second-layer collector wiring C2 are arranged. The second-layer emitter wiring E2 is connected to the first-layer emitter wiring E1 through the opening provided in the insulating film 46, and is also connected to the heat conductive film 43 through the other opening. Has been. The second-layer collector wiring C2 is connected to the first-layer collector wiring C1 through an opening provided in the insulating film 46.

絶縁膜４６の上に、絶縁膜４７が配置されている。絶縁膜４７に、２層目のエミッタ配線Ｅ２の一部を露出させる開口が設けられ、開口内の２層目のエミッタ配線Ｅ２の上、及び開口の周囲の絶縁膜４７の上にバンプ３１が配置されている。バンプ３１には、例えば、Ｃｕピラー３２と、その上面に設けられたはんだバンプ３３とを含むＣｕピラーバンプが用いられる。エミッタ配線Ｅ２、Ｅ１を介してエミッタ電極Ｅ０に接続されているバンプ３１はグランド用のバンプである。   An insulating film 47 is disposed on the insulating film 46. The insulating film 47 is provided with an opening exposing a part of the second-layer emitter wiring E2, and the bumps 31 are formed on the second-layer emitter wiring E2 in the opening and on the insulating film 47 around the opening. Is arranged. For example, a Cu pillar bump including a Cu pillar 32 and a solder bump 33 provided on the upper surface thereof is used as the bump 31. A bump 31 connected to the emitter electrode E0 via the emitter wirings E2 and E1 is a ground bump.

半導体基板４０に、その下面（第２面）から熱伝導膜４３まで達する貫通ビアホール４１が形成されている。平面視において、半導体基板４０の下面の、トランジスタ４２と重なる領域から、貫通ビアホール４１の内面まで連続して熱伝導部材５１が配置されている。熱伝導部材５１として、例えば、Ａｕ等の金属膜が用いられる。一例として、熱伝導部材５１は、半導体基板４０の下面の全域を覆い、貫通ビアホール４１の側面及び底面の全域を覆う。貫通ビアホール４１の底面には熱伝導膜４３が露出しているため、熱伝導部材５１は熱伝導膜４３に接触する。   A through via hole 41 extending from the lower surface (second surface) to the heat conductive film 43 is formed in the semiconductor substrate 40. In a plan view, the heat conducting member 51 is continuously arranged from the region of the lower surface of the semiconductor substrate 40 that overlaps the transistor 42 to the inner surface of the through via hole 41. As the heat conducting member 51, for example, a metal film such as Au is used. As an example, the heat conducting member 51 covers the entire lower surface of the semiconductor substrate 40 and covers the entire side surface and bottom surface of the through via hole 41. Since the heat conductive film 43 is exposed on the bottom surface of the through via hole 41, the heat conductive member 51 is in contact with the heat conductive film 43.

次に、図３を参照して第１実施例の優れた効果について説明する。
図３は、第１実施例による半導体装置のバンプ３１の近傍の断面図である。半導体チップ３０のグランド用のバンプ３１がプリント基板２０のグランド用のランド２１に電気的に接続されるとともに、機械的に固定されている。ランド２１は、プリント基板２０に設けられている内層の複数の配線２５及び複数のビア導体２４を介して、実装面とは反対側の面に形成された外部接続用の電極２３に接続されている。 Next, an excellent effect of the first embodiment will be described with reference to FIG.
FIG. 3 is a sectional view of the vicinity of the bump 31 of the semiconductor device according to the first embodiment. The ground bumps 31 of the semiconductor chip 30 are electrically connected to the ground lands 21 of the printed circuit board 20 and mechanically fixed. The land 21 is connected to an external connection electrode 23 formed on the surface opposite to the mounting surface through a plurality of inner layer wirings 25 and a plurality of via conductors 24 provided on the printed circuit board 20. Yes.

トランジスタ４２の動作時に、平面視においてエミッタ電極Ｅ０と重なる半導体領域に動作電流が流れることにより、熱が発生する。平面視において、トランジスタ４２の半導体領域のうちエミッタ電極Ｅ０と重なる部分が発熱源４８となる。半導体基板４０の厚さ方向に関しては、トランジスタ４２のコレクタ層、ベース層、及びエミッタ層からなる領域が発熱源４８となる。発熱源４８で発生し、半導体基板４０とは反対側に流れる熱は、エミッタ電極Ｅ０、エミッタ配線Ｅ１、Ｅ２、及びバンプ３１で構成される熱経路Ｔ０を経由してプリント基板２０のランド２１まで伝導する。   During the operation of the transistor 42, heat is generated by the operating current flowing through the semiconductor region overlapping the emitter electrode E0 in plan view. In a plan view, a portion of the semiconductor region of the transistor 42 that overlaps the emitter electrode E0 serves as a heat source 48. With respect to the thickness direction of the semiconductor substrate 40, a region including the collector layer, the base layer, and the emitter layer of the transistor 42 becomes the heat source 48. The heat generated by the heat generation source 48 and flowing to the opposite side of the semiconductor substrate 40 passes to the land 21 of the printed circuit board 20 via the heat path T0 formed by the emitter electrode E0, the emitter wirings E1 and E2, and the bumps 31. Conduct.

さらに、発熱源４８で発生した熱の一部は、半導体基板４０の内部に拡散する。半導体基板４０の内部に拡散した熱は、半導体基板４０、熱伝導部材５１、熱伝導膜４３、２層目のエミッタ配線Ｅ２、及びバンプ３１で構成される熱経路Ｔ１を経由してプリント基板２０のランド２１まで伝導する。   Further, part of the heat generated by the heat source 48 diffuses inside the semiconductor substrate 40. The heat diffused inside the semiconductor substrate 40 passes through the heat path T1 constituted by the semiconductor substrate 40, the heat conduction member 51, the heat conduction film 43, the second-layer emitter wiring E2, and the bumps 31, and the printed board 20 Conducted up to the land 21.

プリント基板２０のランド２１まで伝わった熱は、ビア導体２４及び配線２５を経由して、外部接続用の電極２３まで伝わる。電極２３は、例えばマザーボード等の大きなグランド導体に接続される。従って、電極２３まで伝わった熱は、半導体チップ３０に比べて十分大きな熱容量を持つ外部のグランド導体に向かって排出される。   The heat transmitted to the land 21 of the printed circuit board 20 is transmitted to the external connection electrode 23 via the via conductor 24 and the wiring 25. The electrode 23 is connected to a large ground conductor such as a mother board. Accordingly, the heat transmitted to the electrode 23 is discharged toward the external ground conductor having a sufficiently large heat capacity as compared with the semiconductor chip 30.

第１実施例では、発熱源４８で発生し半導体基板４０を横方向（厚さ方向に対して直交する方向）に拡散する熱は、貫通ビアホール４１の側面を覆う熱伝導部材５１まで伝わり、その後、熱伝導膜４３まで伝わる。発熱源４８で発生し、半導体基板４０を厚さ方向に拡散する熱は、半導体基板４０の実装面とは反対側の面を覆う熱伝導部材５１まで伝わり、その後、熱伝導部材５１を経由して熱伝導膜４３まで伝わる。熱伝導部材５１には、半導体基板４０よりも熱伝導率の高い材料が用いられているため、熱伝導部材５１を配置しない構成と比べて熱経路Ｔ１の熱抵抗を低減させることができる。   In the first embodiment, the heat generated in the heat generation source 48 and diffused in the lateral direction (direction perpendicular to the thickness direction) of the semiconductor substrate 40 is transmitted to the heat conduction member 51 covering the side surface of the through via hole 41, and thereafter The heat conduction film 43 is transmitted. The heat generated in the heat generation source 48 and diffused in the thickness direction of the semiconductor substrate 40 is transmitted to the heat conduction member 51 that covers the surface opposite to the mounting surface of the semiconductor substrate 40, and then passes through the heat conduction member 51. To the heat conductive film 43. Since a material having a higher thermal conductivity than that of the semiconductor substrate 40 is used for the heat conducting member 51, the thermal resistance of the heat path T1 can be reduced compared to a configuration in which the heat conducting member 51 is not disposed.

第１実施例では、熱経路Ｔ０のみならず、半導体基板４０内に拡散する熱を熱経路Ｔ１を経由して外部に放熱させるため、トランジスタ４２の温度上昇を抑制することができる。熱伝導部材５１と熱伝導膜４３とが、絶縁材料や半導体材料を介することなく直接接触しているため、熱経路Ｔ１の熱抵抗の上昇が抑制される。このため、熱経路Ｔ１を経由して効率的に放熱を行うことができる。   In the first embodiment, not only the heat path T0 but also the heat diffused in the semiconductor substrate 40 is radiated to the outside through the heat path T1, so that the temperature rise of the transistor 42 can be suppressed. Since the heat conducting member 51 and the heat conducting film 43 are in direct contact with no insulating material or semiconductor material interposed therebetween, an increase in the thermal resistance of the heat path T1 is suppressed. For this reason, heat can be efficiently radiated via the heat path T1.

熱経路Ｔ１の熱抵抗を低減させるために、平面視において、貫通ビアホール４１及び熱伝導膜４３を、絶縁膜４６に設けられた開口及びバンプ３１に少なくとも部分的に重ねて配置することが好ましい。さらに、平面視において、プリント基板２０のグランド用のランド２１をグランド用の電極２３と少なくとも部分的に重ねて配置することが好ましい。ここで、「少なくとも部分的に重ねる」とは、平面視において、一方の部材の一部と他方の部材の一部とを重ねる状態、一方の部材の全域を他方の部材の一部に重ねる状態、及び一方の部材の全域を他方の部材の全域に重ねる状態のいずれかを意味する。熱経路Ｔ１の一部を構成するバンプ３１として、他のバンプに比べて大きな面積を持つグランド用のバンプを用いることが好ましい。   In order to reduce the thermal resistance of the heat path T1, it is preferable to dispose the through via hole 41 and the heat conductive film 43 at least partially overlapping the openings and the bumps 31 provided in the insulating film 46 in a plan view. Furthermore, it is preferable to arrange the ground land 21 of the printed circuit board 20 at least partially overlapping the ground electrode 23 in plan view. Here, “at least partially overlap” means a state in which a part of one member and a part of the other member are overlapped in a plan view, and a state in which the entire area of one member is overlapped with a part of the other member. , And one of the states in which the entire area of one member is overlapped with the entire area of the other member. As the bump 31 constituting a part of the heat path T1, it is preferable to use a bump for ground having a larger area than other bumps.

次に、第１実施例の変形例について説明する。
第１実施例では、半導体基板４０として例えばＧａＡｓからなる基板を用いたが、その他の半導体からなる基板を用いてもよし、能動素子の半導体領域をエピタキシャル成長させることが可能な絶縁性基板を用いてもよい。また、第１実施例では、トランジスタ４２としてヘテロ接合バイポーラトランジスタを用いたが、その他の能動素子、例えばＭＩＳトランジスタ、ＭＥＳトランジスタ、高電子移動度トランジスタ（ＨＥＭＴ）等を用いてもよい。また、第１実施例では、バンプ３１としてＣｕピラーバンプを用いたが、その他の構造のバンプを用いてもよい。 Next, a modification of the first embodiment will be described.
In the first embodiment, a substrate made of GaAs, for example, is used as the semiconductor substrate 40. However, a substrate made of another semiconductor may be used, and an insulating substrate capable of epitaxially growing the semiconductor region of the active element is used. Also good. In the first embodiment, a heterojunction bipolar transistor is used as the transistor 42, but other active elements such as a MIS transistor, a MES transistor, and a high electron mobility transistor (HEMT) may be used. In the first embodiment, Cu pillar bumps are used as the bumps 31. However, bumps having other structures may be used.

［第２実施例］
次に、図４を参照して第２実施例による半導体装置について説明する。以下、第１実施例による半導体装置（図１Ａから図２Ｂ）と共通の構成については説明を省略する。 [Second Embodiment]
Next, a semiconductor device according to the second embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the semiconductor device according to the first embodiment (FIGS. 1A to 2B) will be omitted.

図４は、第２実施例による半導体装置に含まれる半導体チップの断面図である。第１実施例では、貫通ビアホール４１（図２Ｂ）の側面と底面が熱伝導部材５１で覆われており、貫通ビアホール４１内の残りの部分は空洞であるか、または封止樹脂（図１Ｃ）で充填されていた。第２実施例では、貫通ビアホール４１内の残りの部分に熱伝導性ペースト４９が埋め込まれている。ここで、「埋め込まれている」とは、貫通ビアホール４１内の空間が熱伝導性ペースト４９で完全に充填されていることを意味しない。例えば、熱伝導性ペースト４９の表面がやや窪んでいるような場合でも、「埋め込まれている」ということができる。   FIG. 4 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the second embodiment. In the first embodiment, the side surface and the bottom surface of the through via hole 41 (FIG. 2B) are covered with the heat conducting member 51, and the remaining portion in the through via hole 41 is hollow or is a sealing resin (FIG. 1C). It was filled with. In the second embodiment, the heat conductive paste 49 is embedded in the remaining part of the through via hole 41. Here, “being embedded” does not mean that the space in the through via hole 41 is completely filled with the heat conductive paste 49. For example, even when the surface of the heat conductive paste 49 is slightly depressed, it can be said that it is “embedded”.

熱伝導性ペースト４９の熱伝導率は、封止樹脂２８の熱伝導率よりも高い。熱伝導性ペースト４９として、ペースト状物質に、金属やセラミックの粉末を分散させたものを用いることができる。ペースト状物質には、例えばエポキシ樹脂等の樹脂を用いることができる。金属やセラミックの粉末には、例えば銀、ＳｉＣ、ＡｌＮ等を用いることができる。「ペースト」とは、一般的に流動性と高い粘性を持つ物質を意味するが、本明細書において、ペーストが加熱等によって硬化されたものもペーストと呼ぶ。   The thermal conductivity of the thermal conductive paste 49 is higher than the thermal conductivity of the sealing resin 28. As the heat conductive paste 49, a paste-like substance in which metal or ceramic powder is dispersed can be used. As the paste-like substance, for example, a resin such as an epoxy resin can be used. As the metal or ceramic powder, for example, silver, SiC, AlN or the like can be used. “Paste” generally means a substance having fluidity and high viscosity, but in the present specification, a paste cured by heating or the like is also called a paste.

次に、第２実施例の優れた効果について説明する。第２実施例では、貫通ビアホール４１内の熱伝導性ペースト４９が、熱経路Ｔ１（図３）の一部として機能する。このため、熱経路Ｔ１の断面積が大きくなり、熱抵抗が低下する。その結果、熱経路Ｔ１を経由した熱伝導の効率を高めることができる。   Next, the excellent effect of the second embodiment will be described. In the second embodiment, the heat conductive paste 49 in the through via hole 41 functions as a part of the heat path T1 (FIG. 3). For this reason, the cross-sectional area of the heat path T1 increases, and the thermal resistance decreases. As a result, the efficiency of heat conduction via the heat path T1 can be increased.

熱伝導性ペースト４９は、硬化後においても、半導体基板４０よりも低いヤング率を持つ。熱伝導性ペースト４９は、半導体基板４０の熱変形に応じて柔軟に変形するため、貫通ビアホール４１内に金属部材を充填する構成と比べて、半導体基板４０が熱変形しても半導体チップ３０が損傷を受けにくいという効果が得られる。   The thermally conductive paste 49 has a Young's modulus lower than that of the semiconductor substrate 40 even after curing. Since the thermal conductive paste 49 is flexibly deformed in accordance with the thermal deformation of the semiconductor substrate 40, the semiconductor chip 30 is not deformed even when the semiconductor substrate 40 is thermally deformed as compared with the configuration in which the through via hole 41 is filled with a metal member. The effect that it is hard to receive damage is acquired.

［第３実施例］
次に、図５Ａ及び図５Ｂを参照して、第３実施例による半導体装置について説明する。以下、第１実施例による半導体装置（図１Ａから図２Ｂ）と共通の構成については説明を省略する。 [Third embodiment]
Next, a semiconductor device according to a third embodiment will be described with reference to FIGS. 5A and 5B. Hereinafter, the description of the configuration common to the semiconductor device according to the first embodiment (FIGS. 1A to 2B) will be omitted.

図５Ａは、第３実施例による半導体装置に含まれる半導体チップ３０に形成されている出力段増幅回路１３（図１Ａ）平面図である。図５Ｂは、図５Ａの一点鎖線５Ｂ−５Ｂにおける断面図である。第３実施例では、半導体基板４０の底面に凹部６０が形成されている。凹部６０は、半導体基板４０の上面までは到達していない。平面視において、凹部６０はトランジスタ４２と少なくとも部分的に重なり、凹部６０の領域内に貫通ビアホール４１が配置されている。図５Ａでは、平面視においてトランジスタ４２が凹部６０の内部に配置されている例を示している。貫通ビアホール４１は、凹部６０の底面から熱伝導膜４３まで達する。   FIG. 5A is a plan view of the output stage amplifier circuit 13 (FIG. 1A) formed in the semiconductor chip 30 included in the semiconductor device according to the third embodiment. 5B is a cross-sectional view taken along one-dot chain line 5B-5B in FIG. 5A. In the third embodiment, a recess 60 is formed on the bottom surface of the semiconductor substrate 40. The recess 60 does not reach the upper surface of the semiconductor substrate 40. In plan view, the recess 60 at least partially overlaps the transistor 42, and the through via hole 41 is disposed in the region of the recess 60. FIG. 5A shows an example in which the transistor 42 is disposed inside the recess 60 in plan view. The through via hole 41 reaches the heat conductive film 43 from the bottom surface of the recess 60.

半導体基板４０の下面、凹部６０の側面と底面、及び貫通ビアホール４１の側面と底面が、熱伝導部材５１で覆われている。   The lower surface of the semiconductor substrate 40, the side surface and the bottom surface of the recess 60, and the side surface and the bottom surface of the through via hole 41 are covered with the heat conducting member 51.

次に、第３実施例の優れた効果について説明する。第３実施例では、半導体基板４０に凹部６０が形成されているため、半導体基板４０の厚さ方向に関して発熱源４８から熱伝導部材５１までの距離が、第１実施例の場合と比べて短くなる。熱経路Ｔ１が短くなることにより熱抵抗が低下するため、熱経路Ｔ１を通した熱伝導の効率を高めることができる。半導体基板４０を薄くしてしまうと、半導体チップ３０の機械的強度が低下してしまうが、第３実施例では、熱経路Ｔ１として機能する領域以外では、半導体基板４０を薄くしていない。このため、半導体チップ３０の十分な機械的強度を維持することができる。   Next, the excellent effect of the third embodiment will be described. In the third embodiment, since the recess 60 is formed in the semiconductor substrate 40, the distance from the heat generation source 48 to the heat conducting member 51 in the thickness direction of the semiconductor substrate 40 is shorter than that in the first embodiment. Become. Since the heat resistance is lowered by shortening the heat path T1, the efficiency of heat conduction through the heat path T1 can be increased. If the semiconductor substrate 40 is thinned, the mechanical strength of the semiconductor chip 30 is lowered. However, in the third embodiment, the semiconductor substrate 40 is not thin except in a region functioning as the heat path T1. For this reason, sufficient mechanical strength of the semiconductor chip 30 can be maintained.

熱伝導部材５１の熱伝導度は半導体基板４０の熱伝導度より十分高いと見なすことができる。このとき、熱経路Ｔ１の熱抵抗を低下させることによる十分な効果を得るために、発熱源４８から凹部６０の底面までの距離Ｌ２を、発熱源４８から貫通ビアホール４１までの横方向の距離Ｌ１より短くすることが好ましい。発熱源４８から貫通ビアホール４１までの距離Ｌ１の起点は、エミッタ電極Ｅ０の端部と定義するとよい。発熱源４８から凹部６０の底面までの距離Ｌ２の起点は、トランジスタ４２を構成するコレクタ層の下面と定義するとよい。   It can be considered that the thermal conductivity of the thermal conductive member 51 is sufficiently higher than the thermal conductivity of the semiconductor substrate 40. At this time, in order to obtain a sufficient effect by reducing the thermal resistance of the heat path T1, the distance L2 from the heat source 48 to the bottom surface of the recess 60 is set as the lateral distance L1 from the heat source 48 to the through via hole 41. It is preferable to make it shorter. The starting point of the distance L1 from the heat generation source 48 to the through via hole 41 may be defined as the end of the emitter electrode E0. The starting point of the distance L2 from the heat source 48 to the bottom surface of the recess 60 may be defined as the lower surface of the collector layer that constitutes the transistor 42.

［第４実施例］
次に、図６を参照して、第４実施例による半導体装置について説明する。以下、第３実施例による半導体装置（図５Ａ、図５Ｂ）と共通の構成については説明を省略する。 [Fourth embodiment]
Next, a semiconductor device according to the fourth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the semiconductor device according to the third embodiment (FIGS. 5A and 5B) will be omitted.

図６は、第４実施例による半導体装置に含まれる半導体チップ３０の断面図である。第４実施例では、凹部６０及び貫通ビアホール４１の内部が熱伝導性ペースト６１で埋め込まれている。熱伝導性ペースト６１として、例えば第２実施例による半導体装置に用いられている熱伝導性ペースト４９（図４）と同一のものを用いるとよい。   FIG. 6 is a sectional view of a semiconductor chip 30 included in the semiconductor device according to the fourth embodiment. In the fourth embodiment, the recess 60 and the inside of the through via hole 41 are filled with the heat conductive paste 61. As the thermal conductive paste 61, for example, the same thermal conductive paste 49 (FIG. 4) used in the semiconductor device according to the second embodiment may be used.

次に、第４実施例の優れた効果について説明する。第４実施例では、凹部６０及び貫通ビアホール４１の内部が熱伝導性ペースト６１で埋め込まれているため、第２実施例と同様に、熱伝導の効率を高めることができる。その結果、トランジスタ４２の温度上昇を抑制することができる。   Next, the excellent effect of the fourth embodiment will be described. In the fourth embodiment, since the inside of the recess 60 and the through via hole 41 is embedded with the heat conductive paste 61, the efficiency of heat conduction can be increased as in the second embodiment. As a result, the temperature rise of the transistor 42 can be suppressed.

また、熱伝導性ペースト６１は、硬化後においても、半導体基板４０よりも低いヤング率を持つ。熱伝導性ペースト６１は、半導体基板４０の熱変形に応じて柔軟に変形するため、貫通ビアホール４１と凹部６０との内部に金属部材を充填する構成と比べて、半導体基板４０が熱変形しても半導体チップ３０が損傷を受けにくいという効果が得られる。   Further, the thermally conductive paste 61 has a Young's modulus lower than that of the semiconductor substrate 40 even after curing. Since the thermally conductive paste 61 is flexibly deformed in accordance with the thermal deformation of the semiconductor substrate 40, the semiconductor substrate 40 is thermally deformed as compared with the configuration in which the metal member is filled in the through via hole 41 and the recess 60. In this case, the semiconductor chip 30 can be hardly damaged.

さらに、凹部６０に埋め込まれた熱伝導性ペースト６１により、凹部６０が設けられたことにより半導体基板４０が薄くなった部分の機械的強度の低下を補償することができる。これにより、チップダイシング等の加工工程で機械的応力が加わることによる半導体チップの破損を抑制することができる。   Further, the thermal conductive paste 61 embedded in the recess 60 can compensate for a decrease in mechanical strength of the portion where the semiconductor substrate 40 has become thinner due to the provision of the recess 60. Thereby, damage to the semiconductor chip due to mechanical stress applied in a processing step such as chip dicing can be suppressed.

［第５実施例］
次に、図７Ａ及び図７Ｂを参照して、第５実施例による半導体装置について説明する。以下、第１実施例による半導体装置（図１Ａから図２Ｂ）と共通の構成については説明を省略する。 [Fifth embodiment]
Next, with reference to FIGS. 7A and 7B, a semiconductor device according to a fifth embodiment will be described. Hereinafter, the description of the configuration common to the semiconductor device according to the first embodiment (FIGS. 1A to 2B) will be omitted.

図７Ａは、第５実施例による半導体装置に含まれる半導体チップ３０の断面図である。第１実施例では半導体基板４０に下面から上面の熱伝導膜４３（図２Ｂ）まで達する貫通ビアホール４１が設けられていた。第５実施例では、貫通ビアホールは設けられておらず、半導体基板４０の下面に、上面まで達しない凹部６０が設けられている。凹部６０の側面及び底面が熱伝導部材５１で覆われている。平面視において、凹部６０は、トランジスタ４２のエミッタ電極Ｅ０及び熱伝導膜４３と少なくとも部分的に重なっている。凹部６０の底面に配置された熱伝導部材５１と熱伝導膜４３とは、半導体基板４０の一部分を挟んで対向しており、接触はしていない。凹部６０には、封止樹脂２８（図１Ｃ）が埋め込まれる。   FIG. 7A is a cross-sectional view of a semiconductor chip 30 included in the semiconductor device according to the fifth embodiment. In the first embodiment, the through via hole 41 extending from the lower surface to the heat conductive film 43 (FIG. 2B) on the upper surface is provided in the semiconductor substrate 40. In the fifth embodiment, no through via hole is provided, and a recess 60 that does not reach the upper surface is provided on the lower surface of the semiconductor substrate 40. The side surface and the bottom surface of the recess 60 are covered with the heat conducting member 51. In plan view, the recess 60 at least partially overlaps the emitter electrode E 0 and the heat conductive film 43 of the transistor 42. The heat conducting member 51 and the heat conducting film 43 disposed on the bottom surface of the recess 60 are opposed to each other with a part of the semiconductor substrate 40 interposed therebetween, and are not in contact with each other. Sealing resin 28 (FIG. 1C) is embedded in the recess 60.

図７Ｂは、第５実施例による半導体装置の各回路のレイアウトを示す平面図である。第１実施例では、出力段増幅回路１３が配置された領域に貫通ビアホール４１（図１Ｂ）が配置されていた。第５実施例では、出力段増幅回路１３を内部に含むよう凹部６０が配置されている。   FIG. 7B is a plan view showing a layout of each circuit of the semiconductor device according to the fifth embodiment. In the first embodiment, the through via hole 41 (FIG. 1B) is disposed in the region where the output stage amplifier circuit 13 is disposed. In the fifth embodiment, the recess 60 is disposed so as to include the output stage amplifier circuit 13 therein.

次に、第５実施例の優れた効果について説明する。第５実施例では、第１実施例の熱経路Ｔ０（図３）と同様に、発熱源４８からエミッタ電極Ｅ０、及びエミッタ配線Ｅ１、Ｅ２を経由してバンプ３１に至る熱経路Ｔ０が形成される。その他に、発熱源４８から半導体基板４０を横方向に伝わり、熱伝導膜４３、２層目のエミッタ配線Ｅ２を経由してバンプ３１に至る熱経路Ｔ２が形成される。さらに、発熱源４８で発生した熱が半導体基板４０を厚さ方向に拡散し、熱伝導部材５１を横方向に伝導し、その後、半導体基板４０を厚さ方向に伝導してバンプ３１に至る熱経路Ｔ３が形成される。   Next, the excellent effect of the fifth embodiment will be described. In the fifth embodiment, similarly to the heat path T0 (FIG. 3) of the first embodiment, a heat path T0 from the heat source 48 to the bump 31 via the emitter electrode E0 and the emitter wirings E1 and E2 is formed. The In addition, a heat path T2 is formed which travels laterally from the heat generation source 48 through the semiconductor substrate 40 and reaches the bumps 31 via the heat conduction film 43 and the second-layer emitter wiring E2. Further, the heat generated by the heat source 48 diffuses the semiconductor substrate 40 in the thickness direction, conducts the heat conducting member 51 in the lateral direction, and then conducts the semiconductor substrate 40 in the thickness direction to reach the bumps 31. A path T3 is formed.

熱経路Ｔ３の一部を構成する熱伝導部材５１の熱伝導率は、半導体基板４０の熱伝導率より高い。また、凹部６０を設けると、熱経路Ｔ３のうち熱伝導率の低い半導体基板４０によって構成される部分が短くなる。このため、熱経路Ｔ３の熱抵抗が低くなり、熱経路Ｔ３を経由する熱伝導の効率を高めることができる。   The thermal conductivity of the heat conducting member 51 constituting a part of the heat path T3 is higher than the heat conductivity of the semiconductor substrate 40. Moreover, when the recessed part 60 is provided, the part comprised with the semiconductor substrate 40 with low heat conductivity among heat paths T3 will become short. For this reason, the thermal resistance of the heat path T3 is lowered, and the efficiency of heat conduction via the heat path T3 can be increased.

半導体基板４０の全体を薄くすると、十分な機械的強度が確保できなくなる。第５実施例では、熱経路Ｔ３として機能する領域以外では、半導体基板４０を薄くしていない。このため、半導体チップ３０の十分な機械的強度を維持することができる。   If the entire semiconductor substrate 40 is thinned, sufficient mechanical strength cannot be secured. In the fifth embodiment, the semiconductor substrate 40 is not thinned except for the region functioning as the heat path T3. For this reason, sufficient mechanical strength of the semiconductor chip 30 can be maintained.

［第６実施例］
次に、図８を参照して第６実施例による半導体装置について説明する。以下、第５実施例による半導体装置（図７Ａ、図７Ｂ）と共通の構成については説明を省略する。 [Sixth embodiment]
Next, a semiconductor device according to a sixth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to that of the semiconductor device according to the fifth embodiment (FIGS. 7A and 7B) will be omitted.

図８は、第６実施例による半導体装置に含まれる半導体チップ３０の断面図である。第５実施例では、平面視において凹部６０（図７Ａ）が発熱源４８及び熱伝導膜４３の両方に、少なくとも部分的に重なっていた。第６実施例では、凹部６０が発熱源４８及び熱伝導膜４３の両方に重なっているとは限らない。図８では、平面視において凹部６０が発熱源４８と重なり、熱伝導膜４３とは重なっていない例を示している。凹部６０は、平面視において発熱源４８と熱伝導膜４３とに挟まれた領域と部分的に重なって配置される。   FIG. 8 is a sectional view of a semiconductor chip 30 included in the semiconductor device according to the sixth embodiment. In the fifth embodiment, the recess 60 (FIG. 7A) at least partially overlaps both the heat source 48 and the heat conductive film 43 in plan view. In the sixth embodiment, the recess 60 does not necessarily overlap both the heat source 48 and the heat conductive film 43. FIG. 8 shows an example in which the recess 60 overlaps the heat generation source 48 and does not overlap the heat conductive film 43 in plan view. The recess 60 is disposed so as to partially overlap a region sandwiched between the heat generation source 48 and the heat conductive film 43 in plan view.

第６実施例においても、熱伝導部材５１が、発熱源４８で発生して半導体基板４０に拡散する熱をバンプ３１まで伝導させる熱経路の一部を構成する。   Also in the sixth embodiment, the heat conducting member 51 constitutes a part of the heat path for conducting the heat generated by the heat generation source 48 and diffusing to the semiconductor substrate 40 to the bumps 31.

次に、凹部６０、発熱源４８、及び熱伝導膜４３の好ましい相対的位置関係について説明する。発熱源４８から凹部６０の底面に配置された熱伝導部材５１までの最短距離をＬ３で表す。熱伝導膜４３から熱伝導部材５１までの最短距離をＬ４で表す。平面視において、発熱源４８の幾何学的重心位置から熱伝導膜４３までの最短距離をＬ５で表す。熱伝導部材５１の熱伝導度は半導体基板４０の熱伝導度より十分高いと見なすことができる。このとき、凹部６０を形成して熱伝導部材５１を配置することによる十分な効果を得るために、Ｌ３＋Ｌ４がＬ５以下になるように、凹部６０の位置及び深さを設定することが好ましい。   Next, the preferable relative positional relationship of the recessed part 60, the heat-generation source 48, and the heat conductive film 43 is demonstrated. The shortest distance from the heat source 48 to the heat conducting member 51 disposed on the bottom surface of the recess 60 is represented by L3. The shortest distance from the heat conductive film 43 to the heat conductive member 51 is represented by L4. In a plan view, the shortest distance from the geometric gravity center position of the heat generation source 48 to the heat conducting film 43 is represented by L5. It can be considered that the thermal conductivity of the thermal conductive member 51 is sufficiently higher than the thermal conductivity of the semiconductor substrate 40. At this time, in order to obtain a sufficient effect by forming the recess 60 and disposing the heat conducting member 51, it is preferable to set the position and depth of the recess 60 so that L3 + L4 is L5 or less.

［第７実施例］
次に、図９を参照して第７実施例による半導体装置について説明する。以下、第５実施例による半導体装置（図７Ａ、図７Ｂ）と共通の構成については説明を省略する。 [Seventh embodiment]
Next, a semiconductor device according to a seventh embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to that of the semiconductor device according to the fifth embodiment (FIGS. 7A and 7B) will be omitted.

図９は、第６実施例による半導体装置に含まれる半導体チップ３０の断面図である。第５実施例では、半導体チップ３０をプリント基板２０（図１Ｃ）に実装した後に、凹部６０の内部に封止樹脂２８（図１Ｃ）が埋め込まれる。第７実施例では、凹部６０の内部が、熱伝導性ペースト６２で埋め込まれている。熱伝導性ペースト６２には、例えば、第２実施例による半導体装置で用いた熱伝導性ペースト４９（図４）と同一のものを用いることができる。   FIG. 9 is a sectional view of a semiconductor chip 30 included in the semiconductor device according to the sixth embodiment. In the fifth embodiment, after the semiconductor chip 30 is mounted on the printed circuit board 20 (FIG. 1C), the sealing resin 28 (FIG. 1C) is embedded in the recess 60. In the seventh embodiment, the inside of the recess 60 is embedded with the heat conductive paste 62. As the heat conductive paste 62, for example, the same material as the heat conductive paste 49 (FIG. 4) used in the semiconductor device according to the second embodiment can be used.

次に、第７実施例の優れた効果について説明する。第７実施例では、熱伝導性ペースト６２が、熱経路Ｔ３のうち熱伝導部材５１を横方向に延びる部分の断面積を拡大させる役割を持つ。このため、熱経路Ｔ３の熱抵抗が低下し、熱経路Ｔ３を経由する熱伝導の効率を高めることができる。その結果、トランジスタ４２の温度上昇を抑制することができる。
Next, the excellent effect of the seventh embodiment will be described. In the seventh embodiment, the heat conductive paste 62 has a role of expanding the cross-sectional area of the portion of the heat path T3 extending in the lateral direction of the heat conductive member 51. For this reason, the thermal resistance of the heat path T3 is lowered, and the efficiency of heat conduction via the heat path T3 can be increased. As a result, the temperature rise of the transistor 42 can be suppressed.

また、凹部６０に埋め込まれた熱伝導性ペースト６２により、凹部６０を設けることにより半導体基板４０が薄くなった部分の機械的強度の低下を補償することができる。これにより、チップダイシング等の加工工程で機械的応力が加わることによる半導体基板４０の破損を抑制することができる。   In addition, by providing the recess 60 with the heat conductive paste 62 embedded in the recess 60, it is possible to compensate for a decrease in mechanical strength of the portion where the semiconductor substrate 40 is thinned. Thereby, damage to the semiconductor substrate 40 due to mechanical stress applied in a processing step such as chip dicing can be suppressed.

上述の各実施例は例示であり、異なる実施例で示した構成の部分的な置換または組み合わせが可能であることは言うまでもない。複数の実施例の同様の構成による同様の作用効果については実施例ごとには逐次言及しない。さらに、本発明は上述の実施例に制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。   Each of the above-described embodiments is an exemplification, and needless to say, partial replacement or combination of the configurations shown in the different embodiments is possible. About the same effect by the same composition of a plurality of examples, it does not refer to every example one by one. Furthermore, the present invention is not limited to the embodiments described above. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

１０ インピーダンス整合回路
１１ ドライバ段増幅回路
１２ インピーダンス整合回路
１３ 出力段増幅回路
１４ 制御回路
１５ 入力端子
１６ 出力端子
１７、１８ インダクタ
２０ プリント基板
２１ ランド
２３ 外部接続用の電極
２４ ビア導体
２５ 内層の配線
２８ 封止樹脂
３０ 半導体チップ
３１ バンプ
３２ Ｃｕピラー
３３ はんだバンプ
４０ 半導体基板
４１ 貫通ビアホール
４２ トランジスタ（能動素子）
４３ 熱伝導膜
４５、４６、４７ 絶縁膜
４８ 発熱源
４９ 熱伝導性ペースト
５１ 熱伝導部材
６０ 凹部
６１、６２ 熱伝導性ペースト
Ｂ０ ベース電極
Ｂ１ １層目のベース配線
Ｃ０ コレクタ電極
Ｃ１ １層目のコレクタ配線
Ｃ２ ２層目のコレクタ配線
Ｅ０ エミッタ電極
Ｅ１ １層目のエミッタ配線
Ｅ２ ２層目のコレクタ配線
Ｔ０、Ｔ１、Ｔ２、Ｔ３ 熱経路 DESCRIPTION OF SYMBOLS 10 Impedance matching circuit 11 Driver stage amplifier circuit 12 Impedance matching circuit 13 Output stage amplifier circuit 14 Control circuit 15 Input terminal 16 Output terminals 17, 18 Inductor 20 Printed circuit board 21 Land 23 Electrode for external connection 24 Via conductor 25 Inner layer wiring 28 Sealing resin 30 Semiconductor chip 31 Bump 32 Cu pillar 33 Solder bump 40 Semiconductor substrate 41 Through-via hole 42 Transistor (active element)
43 Thermal conductive films 45, 46, 47 Insulating film 48 Heat source 49 Thermal conductive paste 51 Thermal conductive member 60 Recess 61, 62 Thermal conductive paste B0 Base electrode B1 First layer base wiring C0 Collector electrode C1 First layer Collector wiring C2 Second-layer collector wiring E0 Emitter electrode E1 First-layer emitter wiring E2 Second-layer collector wiring T0, T1, T2, T3 Thermal path

接地用の電極には、トランジスタのエミッタまたはソースが接続される。従って、エミッタやソースが伝熱経路の一部に含まれる。バンプに接続されて伝熱経路となるエミッタやソースは、通常、小面積であり、伝熱経路のうちエミッタやソースに接続される箇所が隘路になってしまう。このため、伝熱経路の熱抵抗を十分低くすることが困難である。
The emitter or source of the transistor is connected to the grounding electrode. Therefore, the emitter and the source are included in a part of the heat transfer path. The emitter or source that is connected to the bump and becomes the heat transfer path usually has a small area, and a portion connected to the emitter or source in the heat transfer path becomes a bottleneck. For this reason, it is difficult to sufficiently reduce the thermal resistance of the heat transfer path.

図１Ａは、第１実施例による半導体装置のブロック図であり、図１Ｂは、第１実施例による半導体装置の各回路のレイアウトを示す平面図であり、図１Ｃは、第１実施例による半導体装置の概略断面図である。1A is a block diagram of the semiconductor device according to the first embodiment, FIG. 1B is a plan view showing a layout of each circuit of the semiconductor device according to the first embodiment, and FIG. 1C is a semiconductor according to the first embodiment. It is a schematic sectional drawing of an apparatus. 図２Ａは、第１実施例による半導体装置に含まれる半導体チップに形成されている出力段増幅回路の平面図であり、図２Ｂは、図２Ａの一点鎖線２Ｂ−２Ｂにおける断面図である。2A is a plan view of an output stage amplifier circuit formed in a semiconductor chip included in the semiconductor device according to the first embodiment, and FIG. 2B is a cross-sectional view taken along one-dot chain line 2B-2B in FIG. 2A. 図３は、第１実施例による半導体装置のバンプの近傍の断面図である。FIG. 3 is a cross-sectional view of the vicinity of the bump of the semiconductor device according to the first embodiment. 図４は、第２実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 4 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the second embodiment. 図５Ａは、第３実施例による半導体装置に含まれる半導体チップに形成されている出力段増幅回路の平面図であり、図５Ｂは、図５Ａの一点鎖線５Ｂ−５Ｂにおける断面図である。5A is a plan view of an output stage amplifier circuit formed in a semiconductor chip included in the semiconductor device according to the third embodiment, and FIG. 5B is a cross-sectional view taken along one-dot chain line 5B-5B in FIG. 5A. 図６は、第４実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 6 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the fourth embodiment. 図７Ａは、第５実施例による半導体装置に含まれる半導体チップの断面図であり、図７Ｂは、第５実施例による半導体装置の各回路のレイアウトを示す平面図である。FIG. 7A is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the fifth embodiment, and FIG. 7B is a plan view showing a layout of each circuit of the semiconductor device according to the fifth embodiment. 図８は、第６実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 8 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the sixth embodiment. 図９は、第７実施例による半導体装置に含まれる半導体チップの断面図である。FIG. 9 is a cross-sectional view of a semiconductor chip included in the semiconductor device according to the seventh embodiment.

図１Ｃは、第１実施例による半導体装置の概略断面図である。プリント基板２０の実装面（図１Ｃにおいて上面）に半導体チップ３０が実装されている。半導体チップ３０は、半導体基板４０のプリント基板２０に対向する面（以下、第１面という。）に形成された複数のバンプ３１を含む。プリント基板２０は、実装面に形成された複数のランド２１、及び下面（実装面とは反対側の面）に形成された外部接続用の複数の電極２３を含む。
FIG. 1C is a schematic cross-sectional view of the semiconductor device according to the first embodiment. A semiconductor chip 30 is mounted on the mounting surface (the upper surface in FIG. 1C ) of the printed circuit board 20. The semiconductor chip 30 includes a plurality of bumps 31 formed on a surface (hereinafter referred to as a first surface) of the semiconductor substrate 40 facing the printed circuit board 20. The printed circuit board 20 includes a plurality of lands 21 formed on the mounting surface and a plurality of electrodes 23 for external connection formed on the lower surface (the surface opposite to the mounting surface).

図９は、第７実施例による半導体装置に含まれる半導体チップ３０の断面図である。第５実施例では、半導体チップ３０をプリント基板２０（図１Ｃ）に実装した後に、凹部６０の内部に封止樹脂２８（図１Ｃ）が埋め込まれる。第７実施例では、凹部６０の内部が、熱伝導性ペースト６２で埋め込まれている。熱伝導性ペースト６２には、例えば、第２実施例による半導体装置で用いた熱伝導性ペースト４９（図４）と同一のものを用いることができる。 FIG. 9 is a sectional view of a semiconductor chip 30 included in the semiconductor device according to the seventh embodiment. In the fifth embodiment, after the semiconductor chip 30 is mounted on the printed circuit board 20 (FIG. 1C), the sealing resin 28 (FIG. 1C) is embedded in the recess 60. In the seventh embodiment, the inside of the recess 60 is embedded with the heat conductive paste 62. As the heat conductive paste 62, for example, the same material as the heat conductive paste 49 (FIG. 4) used in the semiconductor device according to the second embodiment can be used.

Claims (9)

実装面にランドが設けられたプリント基板と、
前記プリント基板に実装された半導体チップと
を有し、
前記半導体チップは、
基板の、前記プリント基板に対向する第１面に形成された能動素子と、
前記基板の前記第１面の、前記能動素子とは異なる位置に設けられ、前記基板より熱伝導率の高い材料からなる熱伝導膜と、
前記基板の前記第１面の上に配置され、前記能動素子及び前記熱伝導膜を覆う絶縁膜と、
前記絶縁膜の上に配置され、前記熱伝導膜に電気的に接続されたバンプと、
前記基板の前記第１面とは反対側の第２面から前記熱伝導膜まで達する貫通ビアホールと、
平面視において前記能動素子と重なる前記第２面の領域から、前記貫通ビアホールの内面まで連続して配置され、前記基板より熱伝導率の高い材料からなる熱伝導部材と
を有し、
前記バンプが前記ランドに接続されており、前記半導体チップが封止樹脂で封止されている半導体装置。 A printed circuit board with a land on the mounting surface;
A semiconductor chip mounted on the printed circuit board;
The semiconductor chip is
An active element formed on a first surface of the substrate facing the printed circuit board;
A thermally conductive film made of a material having a higher thermal conductivity than the substrate, provided at a position different from the active element on the first surface of the substrate;
An insulating film disposed on the first surface of the substrate and covering the active element and the heat conducting film;
A bump disposed on the insulating film and electrically connected to the thermal conductive film;
A through via hole reaching from the second surface opposite to the first surface of the substrate to the heat conductive film;
A heat conduction member made of a material having a higher thermal conductivity than the substrate, continuously disposed from the region of the second surface overlapping the active element in plan view to the inner surface of the through via hole;
A semiconductor device in which the bump is connected to the land, and the semiconductor chip is sealed with a sealing resin. 前記バンプと前記熱伝導膜とが、平面視において少なくとも部分的に重なって配置されている請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the bump and the heat conductive film are disposed so as to overlap at least partially in a plan view. 前記半導体チップは、さらに、前記基板の前記第２面に形成された凹部を有し、
前記凹部は、平面視において前記能動素子と少なくとの部分的に重なり、前記凹部の領域内に前記貫通ビアホールが配置されており、前記凹部の内面に前記熱伝導部材が配置されている請求項１または２に記載の半導体装置。 The semiconductor chip further has a recess formed in the second surface of the substrate,
The concave portion overlaps at least partially with the active element in a plan view, the through via hole is disposed in the region of the concave portion, and the heat conducting member is disposed on an inner surface of the concave portion. 3. The semiconductor device according to 1 or 2. 前記熱伝導部材は、前記貫通ビアホールの内面を覆っており、
さらに、前記貫通ビアホールの内部に埋め込まれた熱伝導性ペーストを有する請求項１乃至３のいずれか１項に記載の半導体装置。 The heat conducting member covers an inner surface of the through via hole;
The semiconductor device according to claim 1, further comprising a heat conductive paste embedded in the through via hole. 前記熱伝導部材は、前記貫通ビアホール及び前記凹部の内面を覆っており、
さらに、前記貫通ビアホールの内部及び前記凹部の内部に埋め込まれた熱伝導性ペーストを有する請求項３に記載の半導体装置。 The heat conducting member covers the inner surface of the through via hole and the recess,
The semiconductor device according to claim 3, further comprising a thermally conductive paste embedded in the through via hole and in the recess. 基板の第１面に形成された能動素子と、
前記基板の前記第１面の、前記能動素子とは異なる位置に設けられ、前記基板より熱伝導率の高い材料からなる熱伝導膜と、
前記基板の前記第１面の上に配置され、前記能動素子及び前記熱伝導膜を覆う絶縁膜と、
前記絶縁膜の上に配置され、前記熱伝導膜に電気的に接続されたバンプと、
前記基板の前記第１面とは反対側の第２面に設けられ、平面視において前記能動素子及び前記熱伝導膜と少なくとも部分的に重なる凹部と、
前記凹部の内面に設けられ、前記基板より熱伝導率の高い材料からなる熱伝導部材と
を有し、
前記凹部の底面に配置された前記熱伝導部材と前記熱伝導膜とは、前記基板の一部分を挟んで対向している半導体装置。 An active element formed on the first surface of the substrate;
A thermally conductive film made of a material having a higher thermal conductivity than the substrate, provided at a position different from the active element on the first surface of the substrate;
An insulating film disposed on the first surface of the substrate and covering the active element and the heat conducting film;
A bump disposed on the insulating film and electrically connected to the thermal conductive film;
A concave portion provided on a second surface opposite to the first surface of the substrate, and at least partially overlapping the active element and the heat conductive film in plan view;
A heat conductive member provided on the inner surface of the concave portion and made of a material having a higher thermal conductivity than the substrate;
The semiconductor device in which the heat conducting member and the heat conducting film disposed on the bottom surface of the recess are opposed to each other with a part of the substrate interposed therebetween. 前記バンプと前記熱伝導膜とが、平面視において少なくとも部分的に重なって配置されている請求項６に記載の半導体装置。   The semiconductor device according to claim 6, wherein the bump and the heat conductive film are disposed so as to overlap at least partially in plan view. さらに、前記凹部の内部に埋め込まれた熱伝導性ペーストを有する請求項６または７に記載の半導体装置。   Furthermore, the semiconductor device of Claim 6 or 7 which has the heat conductive paste embedded inside the said recessed part. 前記能動素子の発熱源から前記熱伝導部材までの最短距離と、前記熱伝導膜から前記熱伝導部材までの最短距離との和が、前記発熱源から前記熱伝導膜までの距離以下である請求項６乃至８のいずれか１項に記載の半導体装置。   The sum of the shortest distance from the heat source of the active element to the heat conductive member and the shortest distance from the heat conductive film to the heat conductive member is equal to or less than the distance from the heat source to the heat conductive film. Item 9. The semiconductor device according to any one of Items 6 to 8.
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