JP2019165152A - Semiconductor device, semiconductor device manufacturing method, and semiconductor integrated circuit device manufacturing method - Google Patents

Semiconductor device, semiconductor device manufacturing method, and semiconductor integrated circuit device manufacturing method Download PDF

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JP2019165152A
JP2019165152A JP2018052937A JP2018052937A JP2019165152A JP 2019165152 A JP2019165152 A JP 2019165152A JP 2018052937 A JP2018052937 A JP 2018052937A JP 2018052937 A JP2018052937 A JP 2018052937A JP 2019165152 A JP2019165152 A JP 2019165152A
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semiconductor substrate
semiconductor
chemical solution
integrated circuit
outer periphery
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祐一 宮島
Yuichi Miyajima
祐一 宮島
晃紀 奥
Akinori Oku
晃紀 奥
康之 宮原
Yasuyuki Miyahara
康之 宮原
宗高 吉村
Munetaka Yoshimura
宗高 吉村
一矢 古賀
Kazuya Koga
一矢 古賀
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Ablic Inc
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Ablic Inc
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  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)

Abstract

To provide a semiconductor device that reduces the influence of the outer knife edge shape caused by backside grinding of a semiconductor substrate and suppresses an increase in the number of obtained semiconductor integrated circuit devices and the deterioration in quality, a semiconductor device manufacturing method, and a semiconductor integrated circuit device manufacturing method.SOLUTION: A semiconductor device includes a semiconductor substrate 101 provided with a chamfered portion 104 on the outer periphery, and a chamfering compensation unit 107 provided on the surface of the chamfered portion 104 and formed to have a substantially rectangular shape in a cross-sectional view.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置及び半導体装置の製造方法及び半導体集積回路装置の製造方法に関する。   The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and a semiconductor integrated circuit device manufacturing method.

近年の電子部品の小型化に伴い、その電子部品に搭載される半導体集積回路装置も、小型化の要請を常に受けている。そのような要請に答えるために、半導体集積回路装置の製造においては、平面方向におけるチップサイズの縮小と同時に高さ方向の厚さの縮小が図られる。半導体集積回路装置の高さ方向の縮小を実現するために、半導体基板を個々の半導体集積回路装置に分割する前に、半導体基板の裏面を研削して厚さが薄くなるように加工される。   With the recent miniaturization of electronic components, semiconductor integrated circuit devices mounted on the electronic components have always received requests for miniaturization. In order to meet such a demand, in the manufacture of a semiconductor integrated circuit device, the thickness in the height direction can be reduced simultaneously with the reduction in the chip size in the planar direction. In order to reduce the height of the semiconductor integrated circuit device, before the semiconductor substrate is divided into individual semiconductor integrated circuit devices, the back surface of the semiconductor substrate is ground so that the thickness is reduced.

図6(a)に示すように、一般に半導体基板201の外周には半円弧状の面取り部204が形成されている。そのため、半導体基板201の裏面をその厚さの半分の量を越えて研削し厚さを薄くすると、図6(b)に示すように残存する面取り部204が鋭利な、所謂ナイフエッジ形状が発生する。そのため、半導体基板の裏面を研削している間、もしくは後の工程において、この面取り部に周囲への接触や振動によって亀裂や欠けが発生し、その亀裂や欠けによって半導体基板201表面の外周に形成されている半導体集積回路装置の品質が低下する恐れがある。   As shown in FIG. 6A, a semicircular chamfered portion 204 is generally formed on the outer periphery of the semiconductor substrate 201. Therefore, when the back surface of the semiconductor substrate 201 is ground to a thickness that is less than half of its thickness and the thickness is reduced, a so-called knife edge shape in which the remaining chamfered portion 204 is sharp as shown in FIG. 6B is generated. To do. Therefore, during grinding of the back surface of the semiconductor substrate or in a later process, the chamfered portion is cracked or chipped due to contact or vibration to the periphery, and formed on the outer periphery of the surface of the semiconductor substrate 201 by the crack or chipped. There is a risk that the quality of the semiconductor integrated circuit device being used will be deteriorated.

特許文献1には、半導体基板の裏面を研削する前に、面取り部を切削ブレードによって除去し、面取り部の形状を表面と裏面に対して直角の形状に加工することで、半導体基板の裏面研削後におけるナイフエッジ形状の発生を抑制する技術が開示されている。   In Patent Document 1, before grinding the back surface of the semiconductor substrate, the chamfered portion is removed by a cutting blade, and the shape of the chamfered portion is processed into a shape perpendicular to the front surface and the back surface. A technique for suppressing the occurrence of a knife edge shape later is disclosed.

特開2011−103389号公報JP 2011-103389 A

特許文献1に示される加工方法は、面取り部の除去時に半導体基板の最外周より内側の領域であって、半導体集積回路装置が形成されている領域の外側の領域を切削することで、切削中の振動等による亀裂や欠けの発生を抑制する。しかしながら、切削における振動が完全に抑制されるわけではないので、半導体集積回路装置の亀裂や欠けによる品質の低下を完全になくすことは困難である。また、この加工方法において切削する領域は、半導体基板の最外周から内側の領域であるので、そのような余裕領域確保のために半導体集積回路装置を余裕領域のさらに内側に設置する必要がある。従って、1枚の半導体基板から得られる半導体集積回路装置の個数を増加させることが困難である。   In the processing method disclosed in Patent Document 1, the region inside the outermost periphery of the semiconductor substrate at the time of removing the chamfered portion is cut by cutting the region outside the region where the semiconductor integrated circuit device is formed. Suppresses the generation of cracks and chips due to vibrations. However, since vibration in cutting is not completely suppressed, it is difficult to completely eliminate the deterioration in quality due to cracks or chips in the semiconductor integrated circuit device. In addition, since the region to be cut in this processing method is a region inside from the outermost periphery of the semiconductor substrate, it is necessary to install the semiconductor integrated circuit device further inside the margin region in order to secure such a margin region. Therefore, it is difficult to increase the number of semiconductor integrated circuit devices obtained from one semiconductor substrate.

本発明は、上記の点に鑑み、半導体装置の裏面研削後のナイフエッジ形状の影響を低減し、亀裂や欠けによる品質低下の抑制と半導体集積回路装置の取れ個数の増加が実現できる、半導体装置及び半導体装置の製造方法及び半導体集積回路装置の製造方法を提供することを目的とする。   In view of the above points, the present invention reduces the influence of the knife edge shape after back grinding of a semiconductor device, and can realize a reduction in quality due to cracks and chipping and an increase in the number of semiconductor integrated circuit devices that can be taken. An object of the present invention is to provide a method for manufacturing a semiconductor device and a method for manufacturing a semiconductor integrated circuit device.

上記の課題を解決するために、本発明は以下のような半導体装置及び半導体装置の製造方法及び半導体集積回路装置の製造方法とする。   In order to solve the above problems, the present invention provides the following semiconductor device, semiconductor device manufacturing method, and semiconductor integrated circuit device manufacturing method.

すなわち、外周に面取り部を備えた半導体基板と、前記面取り部の表面に備えられ、断面視において略長方形の形状をなすように形成された面取り補償部と、を有することを特徴とする、半導体装置とする。   That is, a semiconductor comprising: a semiconductor substrate having a chamfered portion on the outer periphery; and a chamfer compensating portion provided on a surface of the chamfered portion and formed in a substantially rectangular shape in a sectional view. A device.

また、半導体集積回路装置が表面に形成され外周に面取り部を備えた半導体基板を、凹部を有する半導体基板支持装置の前記凹部の底面に、前記半導体基板の表面が対向するように設置し、前記半導体基板支持装置の前記凹部の内側面と前記半導体基板の外周との間の隙間に薬液を供給する工程と、前記薬液を硬化させ、断面視において略長方形の形状となすように面取り補償部を形成する工程と、前記半導体基板の裏面を研削し、厚さを減じる工程と、を含むことを特徴とする半導体装置の製造方法とする。   In addition, a semiconductor integrated circuit device is formed on the surface, and a semiconductor substrate having a chamfered portion on the outer periphery is installed such that the surface of the semiconductor substrate faces the bottom surface of the recess of the semiconductor substrate support device having a recess, Supplying a chemical solution to a gap between the inner surface of the recess of the semiconductor substrate support device and the outer periphery of the semiconductor substrate; and curing the chemical solution so that the chamfering compensation unit has a substantially rectangular shape in a cross-sectional view. A method of manufacturing a semiconductor device, comprising: a step of forming; and a step of grinding a back surface of the semiconductor substrate to reduce a thickness thereof.

さらに、前記半導体装置の表面の前記半導体集積回路が形成されている領域の間の領域をダイシングする工程と、を含むことを特徴とする半導体集積回路装置の製造方法とする。   And a step of dicing the region between the regions where the semiconductor integrated circuit is formed on the surface of the semiconductor device.

本発明によれば、半導体基板の外周の面取り部の表面に面取り補償部を備え、断面視において略長方形の形状の半導体装置とし、ナイフエッジ形状の影響を低減することによって、半導体集積回路装置の亀裂や欠けによる品質低下を抑制できる。また半導体基板の外周に面取り部を加工するための余裕領域を確保する必要が無く、半導体集積回路装置を半導体基板の外周にまで形成する事が出来る。そのため、半導体集積回路装置の取れ個数の増加を実現できる。   According to the present invention, a chamfer compensation portion is provided on the surface of a chamfered portion on the outer periphery of a semiconductor substrate, and a semiconductor device having a substantially rectangular shape in a cross-sectional view is obtained. Quality degradation due to cracks and chips can be suppressed. Further, there is no need to secure a margin area for processing the chamfered portion on the outer periphery of the semiconductor substrate, and the semiconductor integrated circuit device can be formed up to the outer periphery of the semiconductor substrate. Therefore, an increase in the number of semiconductor integrated circuit devices can be realized.

(a)は、本発明の実施形態における半導体装置を示す平面図であり、(b)は、図1(a)に示すA−A’の要部における裏面研削前の断面図であり、(c)は、図1(a)に示すA−A’の要部における裏面研削後の断面図である。(A) is a top view which shows the semiconductor device in embodiment of this invention, (b) is sectional drawing before the back surface grinding in the principal part of AA 'shown to Fig.1 (a), ( (c) is sectional drawing after back surface grinding in the principal part of AA 'shown to Fig.1 (a). 本発明の実施形態における半導体基板の外周加工装置である。1 is a peripheral processing apparatus for a semiconductor substrate in an embodiment of the present invention. (a)は、本発明の実施形態における半導体基板を設置した型枠の平面図であり、(b)は、図2(a)に示すB−B’における断面図である。(A) is a top view of the formwork which installed the semiconductor substrate in embodiment of this invention, (b) is sectional drawing in B-B 'shown to Fig.2 (a). 本発明の実施形態における半導体装置及び半導体集積回路装置の製造方法の主要工程を示すフローチャート図である。It is a flowchart figure which shows the main processes of the manufacturing method of the semiconductor device and semiconductor integrated circuit device in embodiment of this invention. 図3(a)に示すB−B’の要部における樹脂充填後の断面図であり、(b)は、図3(a)に示すB−B’の要部における樹脂充填後の別の断面図である。It is sectional drawing after resin filling in the principal part of BB 'shown to Fig.3 (a), (b) is another after the resin filling in the principal part of BB' shown to Fig.3 (a). It is sectional drawing. (a)は、従来の半導体基板の要部における裏面研削前の断面図であり、(b)は、従来の半導体基板の要部における裏面研削後の断面図である。(A) is sectional drawing before the back surface grinding in the principal part of the conventional semiconductor substrate, (b) is sectional drawing after the back surface grinding in the principal part of the conventional semiconductor substrate.

以下、本発明の実施形態を、図面を適宜参照しながら詳細に説明する。以下の説明で用いる図面は、本発明の特徴を分かりやすくするために、一部省略または拡大して示している場合があり、実際の寸法比とは異なっていることがある。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate. The drawings used in the following description may be partially omitted or enlarged for easy understanding of the features of the present invention, and may differ from actual dimensional ratios.

図1(a)は、本発明の実施形態に係る表面に半導体集積回路装置(不図示)を備えた半導体装置10の平面図である。また、図1(b)は、図1(a)において、半導体装置10をA−A’線に沿って切断したときの外周部分を拡大した裏面研削前の断面図であり、図1(c)は、裏面研削後の断面図である(半導体基板101の裏面を紙面上側としている)。図1(c)においては、図1(b)の状態から、紙面上側の半導体基板101の裏面が研削され、その厚さが減じられている。   FIG. 1A is a plan view of a semiconductor device 10 having a semiconductor integrated circuit device (not shown) on its surface according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of the outer peripheral portion when the semiconductor device 10 is cut along the line AA ′ in FIG. ) Is a cross-sectional view after the back surface grinding (the back surface of the semiconductor substrate 101 is the upper side in the drawing). In FIG. 1C, from the state of FIG. 1B, the back surface of the semiconductor substrate 101 on the upper side of the paper is ground to reduce its thickness.

図1(a)に示すように、半導体装置10は、半導体基板101と、その外周に付加された面取り補償部107とを備える。   As shown in FIG. 1A, the semiconductor device 10 includes a semiconductor substrate 101 and a chamfering compensation unit 107 added to the outer periphery thereof.

半導体基板101は、平面視において円形形状を有し、その外周の一部にオリエンタルフラットやノッチなどの不連続部分105が形成されている。半導体基板101の表面には、格子状に形成されたダイシングラインと呼ばれる分割予定ラインと、そのダイシングラインに区画された領域に半導体集積回路装置とが形成されている(不図示)。半導体基板101の外周には断面視において角部が丸められ、半円弧状の形状をなす面取り部が備えられている。この面取り部の形状は、図6(a)に示す面取り部204と同様である。   The semiconductor substrate 101 has a circular shape in plan view, and a discontinuous portion 105 such as an oriental flat or a notch is formed on a part of the outer periphery thereof. On the surface of the semiconductor substrate 101, division planned lines called dicing lines formed in a lattice shape and a semiconductor integrated circuit device are formed in a region partitioned by the dicing lines (not shown). The outer periphery of the semiconductor substrate 101 is provided with a chamfered portion that is rounded in a sectional view and has a semicircular arc shape. The shape of the chamfered portion is the same as that of the chamfered portion 204 shown in FIG.

図1(b)に示すように、半導体基板101の外周には、半導体基板101の中心から外周に向かう方向の面取り部の表面に、面取り補償部107が備えられている。面取り補償部107は、平面視において半導体基板101の外周の円形形状の部分と不連続部分105とに沿って切れ目無く形成されている。半導体基板101と面取り補償部107を合わせた半導体装置10は、断面視において略長方形の形状をなし、裏面研削を行った後でもその形状が略長方形であることは変わらない。すなわち、その形状は、全ての角部が90度である完全な長方形である必要は無く、例えば角部が丸められている形状であっても構わない。   As shown in FIG. 1B, a chamfer compensator 107 is provided on the outer periphery of the semiconductor substrate 101 on the surface of the chamfered portion in the direction from the center of the semiconductor substrate 101 to the outer periphery. The chamfer compensator 107 is formed without a break along the circular portion and the discontinuous portion 105 on the outer periphery of the semiconductor substrate 101 in plan view. The semiconductor device 10 in which the semiconductor substrate 101 and the chamfering compensation unit 107 are combined has a substantially rectangular shape in a cross-sectional view, and the shape remains substantially rectangular even after the back surface grinding. That is, the shape does not have to be a complete rectangle with all corners being 90 degrees, and may be a shape with rounded corners, for example.

面取り補償部107は、樹脂などの薬液を硬化させたものであり、その物理的強度は、半導体基板101とほぼ等しい。そのため、後の半導体基板101の裏面の研削時には、同時に研削される面取り補償部107によってその研削速度や研削途中の形状が変化する事はない。   The chamfering compensation unit 107 is obtained by curing a chemical solution such as a resin, and its physical strength is substantially equal to that of the semiconductor substrate 101. Therefore, at the time of subsequent grinding of the back surface of the semiconductor substrate 101, the grinding speed and the shape during grinding are not changed by the chamfering compensation unit 107 ground at the same time.

図1(c)に示すように、裏面が研削されたあとの半導体装置10において、半導体基板101は、その外周の面取り部104が鋭利な所謂ナイフエッジ形状となっている。図1(c)に示す面取り部104の形状は、図6(b)に示す面取り部204と同様である。   As shown in FIG. 1C, in the semiconductor device 10 after the back surface is ground, the semiconductor substrate 101 has a so-called knife edge shape with a sharp chamfer 104 on the outer periphery thereof. The shape of the chamfer 104 shown in FIG. 1C is the same as that of the chamfer 204 shown in FIG.

面取り部104の表面には、このナイフエッジ形状を解消するように半導体基板101とともに厚さが減じられた面取り補償部107が付加されている。この半導体基板101と面取り補償部107を合わせた全体の形状は、裏面研削後も断面視において略長方形の形状をなしている。本実施形態の半導体装置10は、裏面の研削によって厚さをどのように変えても、断面視においてその形状が略長方形であることは変わらず、ナイフエッジ形状が発生することもない。   On the surface of the chamfered portion 104, a chamfer compensator 107 having a thickness reduced together with the semiconductor substrate 101 is added so as to eliminate the knife edge shape. The overall shape of the semiconductor substrate 101 and the chamfering compensation unit 107 is substantially rectangular in cross-sectional view even after back grinding. The semiconductor device 10 according to the present embodiment does not change its thickness in a cross-sectional view and does not generate a knife edge shape no matter how the thickness is changed by grinding the back surface.

裏面研削によってナイフエッジ形状が発生しない本実施形態の半導体装置10は、裏面研削やダイシング中の振動等による亀裂や欠けの発生を抑制できる。そのため、半導体基板101の表面の外周付近に形成された半導体集積回路装置の品質の低下が抑制される。また、面取り部104を除去する必要が無いので、半導体集積回路装置を半導体基板101の外周から余裕領域を設けて内側に設置する特許文献1に比べ、1枚の半導体基板から得られる半導体集積回路装置の個数の増加が実現できる。   The semiconductor device 10 according to the present embodiment in which the knife edge shape is not generated by the back surface grinding can suppress the generation of cracks or chips due to the back surface grinding or vibration during dicing. Therefore, the deterioration of the quality of the semiconductor integrated circuit device formed near the outer periphery of the surface of the semiconductor substrate 101 is suppressed. Further, since it is not necessary to remove the chamfered portion 104, the semiconductor integrated circuit obtained from one semiconductor substrate is compared with Patent Document 1 in which the semiconductor integrated circuit device is provided with a margin area from the outer periphery of the semiconductor substrate 101 and installed inside. An increase in the number of devices can be realized.

図2は、本発明の実施形態に係る半導体基板の外周加工装置100の主要構成の断面図である。半導体基板の外周加工装置100は、チャンバ17、回転ステージ16、型枠102、供給ノズル12、バルブ13、薬液供給装置14、薬液が充填されている薬液タンク15を備える。   FIG. 2 is a cross-sectional view of the main configuration of the semiconductor substrate peripheral processing apparatus 100 according to the embodiment of the present invention. The semiconductor substrate peripheral processing apparatus 100 includes a chamber 17, a rotary stage 16, a mold 102, a supply nozzle 12, a valve 13, a chemical liquid supply apparatus 14, and a chemical liquid tank 15 filled with the chemical liquid.

回転ステージ16は、チャンバ17内に設置され、回転ステージ16上に設置された型枠102を固定し、回転させる。回転ステージ16は、型枠102を例えば真空吸着によって固定する。その場合、回転ステージ16は、その表面に空気を吸引するための吸着穴を多数備えている。   The rotary stage 16 is installed in the chamber 17, and fixes and rotates the mold 102 installed on the rotary stage 16. The rotary stage 16 fixes the mold 102 by, for example, vacuum suction. In that case, the rotary stage 16 has a large number of suction holes for sucking air on the surface thereof.

型枠102は、半導体基板101を設置できる大きさの凹部106を備えている。そして、回転ステージ16が回転している間、回転ステージ16に設置された型枠102と同時に型枠102の凹部106内に設置された半導体基板101が回転する。   The mold 102 is provided with a recess 106 having a size capable of installing the semiconductor substrate 101. While the rotary stage 16 is rotating, the semiconductor substrate 101 installed in the recess 106 of the mold 102 rotates simultaneously with the mold 102 installed on the rotary stage 16.

供給ノズル12は、型枠102の凹部106における外周領域の上部に設置され、凹部106内の半導体基板101の外周と、凹部106の内側面の間の隙間に薬液11を供給する。供給ノズル12は、回転ステージ16が回転する間の数秒から数10秒程度の一定期間に薬液11を供給し、半導体基板101の外周部と型枠102の凹部106の内側面の間の隙間を全て薬液11で満たす。後にこの薬液11は、半導体基板研削後のナイフエッジ形状の影響を低減するための面取り補償部となる。   The supply nozzle 12 is installed in the upper part of the outer peripheral area of the recess 106 of the mold 102, and supplies the chemical solution 11 to the gap between the outer periphery of the semiconductor substrate 101 in the recess 106 and the inner surface of the recess 106. The supply nozzle 12 supplies the chemical solution 11 for a certain period of about several seconds to several tens of seconds while the rotary stage 16 rotates, and a gap between the outer peripheral portion of the semiconductor substrate 101 and the inner surface of the concave portion 106 of the mold 102 is formed. All are filled with chemical solution 11. This chemical solution 11 later becomes a chamfering compensation unit for reducing the influence of the knife edge shape after semiconductor substrate grinding.

バルブ13、薬液供給装置14は、回転ステージ16が回転している間に薬液タンク15から薬液11を供給するように制御される。薬液供給装置14は、例えばポンプ方式や加圧方式により薬液11を薬液タンク15からバルブ13に送る。薬液供給装置14からバルブ13に送られた薬液11は、バルブ13が閉から開に切り替わることで供給ノズル12に供給される。   The valve 13 and the chemical solution supply device 14 are controlled so as to supply the chemical solution 11 from the chemical solution tank 15 while the rotary stage 16 is rotating. The chemical solution supply device 14 sends the chemical solution 11 from the chemical solution tank 15 to the valve 13 by, for example, a pump method or a pressurization method. The chemical solution 11 sent from the chemical solution supply device 14 to the valve 13 is supplied to the supply nozzle 12 when the valve 13 is switched from closed to open.

薬液11は、可塑性をもち、供給ノズル12からの供給によって半導体基板101の外周と型枠102の凹部106の内側面の間の隙間全てに充填される。また、同時に薬液11は、硬化性をもち、後の熱の印加よって半導体基板101の外周に固着し、半導体基板101と同程度の物理強度まで硬化させることができる。   The chemical solution 11 has plasticity, and is filled in the entire gap between the outer periphery of the semiconductor substrate 101 and the inner surface of the recess 106 of the mold 102 by being supplied from the supply nozzle 12. At the same time, the chemical solution 11 has curability and can be fixed to the outer periphery of the semiconductor substrate 101 by the subsequent application of heat to be cured to a physical strength comparable to that of the semiconductor substrate 101.

薬液11は、このような性質をもつものであればどの材質のものでも構わない。例えば、加熱によって硬化するポリイミド樹脂を採用してもよい。また、熱硬化付与型紫外線樹脂でもよい。熱硬化付与型紫外線樹脂を採用した場合、加熱と紫外線照射によって硬化させるので、硬化時間を加熱だけの場合よりも短縮でき、製造コストを削減することができる。あるいは、SiO2を材質とする粒状のシリカフィラーを含むプラスチック樹脂でもよい。このようなプラスチック樹脂を採用した場合、シリカフィラーの含有割合を適宜変えることによって、硬化後の物理強度を調整することができ、半導体基板101の物理強度と合わせることが容易となる。従って、半導体基板101の裏面研削の際、半導体基板101と硬化させた薬液11との物理強度の違いによる研削むらと、それによる半導体集積回路装置の厚さばらつきを低減しやすい。 The chemical solution 11 may be made of any material as long as it has such properties. For example, you may employ | adopt the polyimide resin hardened | cured by heating. Moreover, a thermosetting imparting ultraviolet resin may be used. When the thermosetting imparting type ultraviolet resin is employed, curing is performed by heating and ultraviolet irradiation, so that the curing time can be shortened compared to the case of heating alone, and the manufacturing cost can be reduced. Alternatively, a plastic resin containing granular silica filler made of SiO 2 may be used. When such a plastic resin is employed, the physical strength after curing can be adjusted by appropriately changing the content ratio of the silica filler, and it becomes easy to match the physical strength of the semiconductor substrate 101. Therefore, when grinding the back surface of the semiconductor substrate 101, it is easy to reduce grinding unevenness due to a difference in physical strength between the semiconductor substrate 101 and the hardened chemical solution 11 and thickness variations of the semiconductor integrated circuit device due to this.

次に、半導体基板101の外周における面取り補償部の形成について詳細に説明する。図3(a)は、型枠102に半導体基板101を設置したときの平面図である。図3(b)は、図3(a)に示す半導体基板101が設置された型枠102をB−B’線に沿って切断したときの断面図である。   Next, the formation of the chamfer compensation part on the outer periphery of the semiconductor substrate 101 will be described in detail. FIG. 3A is a plan view when the semiconductor substrate 101 is installed on the mold 102. FIG. 3B is a cross-sectional view of the mold 102 on which the semiconductor substrate 101 shown in FIG. 3A is installed, cut along the line B-B ′.

型枠102は、外周部にオリエンタルフラットやノッチなどの不連続部分105が形成された半導体基板101を設置できる凹部106を備えている。この凹部106の円形形状における半径は、半導体基板101の円形形状の半径より1mm程度まで大きく形成される。また、半導体基板101の不連続部分105においては、その部分の形状に合わせ、1mm程度まで大きくした平面形状としている。半導体基板101の外周と凹部106の内側面の隙間の大きさは任意に変えてよく、その隙間の大きさによって面取り補償部の大きさが変えられる。   The mold 102 is provided with a recess 106 in which a semiconductor substrate 101 in which a discontinuous portion 105 such as an oriental flat or a notch is formed on the outer peripheral portion can be placed. The radius of the recess 106 in the circular shape is formed to be about 1 mm larger than the radius of the circular shape of the semiconductor substrate 101. In addition, the discontinuous portion 105 of the semiconductor substrate 101 has a planar shape enlarged to about 1 mm in accordance with the shape of the portion. The size of the gap between the outer periphery of the semiconductor substrate 101 and the inner side surface of the recess 106 may be arbitrarily changed, and the size of the chamfering compensation portion is changed depending on the size of the gap.

また、凹部106の深さは裏面研削を施す前の半導体基板101の厚さと同一もしくはそれより浅い深さとなっている。凹部106の深さが半導体基板101の厚さよりも深いと、その後の薬液11の供給時に半導体基板101の裏面に薬液11が溜まり、半導体基板101を含めた厚さが、半導体基板101の厚さを越えてしまう。半導体基板101の厚さに対し付着した薬液11の分の厚さが増すと、半導体基板101の裏面研削に要する時間が長くなる。そのため、凹部106の深さは半導体基板101の厚さと同一もしくはそれより浅い深さであることが好ましい。   The depth of the recess 106 is the same as or shallower than the thickness of the semiconductor substrate 101 before the back surface grinding. If the depth of the recess 106 is deeper than the thickness of the semiconductor substrate 101, the chemical solution 11 accumulates on the back surface of the semiconductor substrate 101 during the subsequent supply of the chemical solution 11, and the thickness including the semiconductor substrate 101 is the thickness of the semiconductor substrate 101. Will be exceeded. When the thickness of the chemical solution 11 attached to the thickness of the semiconductor substrate 101 increases, the time required for the back surface grinding of the semiconductor substrate 101 becomes longer. Therefore, the depth of the recess 106 is preferably the same as or shallower than the thickness of the semiconductor substrate 101.

また型枠102は、凹部106の底面に、型枠102の裏面まで貫通する吸着穴108を複数備えている。この吸着穴108により、回転ステージ16の真空吸着において、半導体基板101が型枠102に吸着固定される。型枠102の吸着穴108以外の裏面においては、回転ステージ16の吸着穴による型枠102の真空吸着のため、型枠102が回転ステージ16に固定化される。型枠102は、回転ステージ16が回転している間に半導体基板101の位置ずれが発生しないように固定化する役割をもつ、半導体基板支持装置と言える。   The mold 102 is provided with a plurality of suction holes 108 penetrating to the back surface of the mold 102 on the bottom surface of the recess 106. With this suction hole 108, the semiconductor substrate 101 is sucked and fixed to the mold 102 in the vacuum suction of the rotary stage 16. On the back surface other than the suction holes 108 of the mold 102, the mold 102 is fixed to the rotary stage 16 because of vacuum suction of the mold 102 by the suction holes of the rotary stage 16. It can be said that the mold 102 is a semiconductor substrate supporting device having a role of fixing the semiconductor substrate 101 so as not to be displaced while the rotary stage 16 is rotating.

型枠102における凹部106の底面は、セラミックや有機高分子、樹脂などによる多孔質構造としても構わない。その場合、型枠102は、多数個の吸着穴108を1つずつ加工形成するよりも安価となり、しかも高い吸着力を備えることができる。   The bottom surface of the recess 106 in the mold 102 may have a porous structure made of ceramic, organic polymer, resin, or the like. In that case, the mold 102 is cheaper than processing and forming a large number of suction holes 108 one by one, and can have a high suction force.

半導体基板101は、この型枠102の凹部106内に、半導体集積回路装置が形成された表面を紙面下側に向けて、凹部106の底面に対向するように設置される。そのため、後の半導体基板101の外周部における薬液11の充填時には、半導体基板101の表面が露出しておらず、また真空吸着によって凹部106の底面に強固に密着しているので、薬液11の半導体基板101表面への付着が抑制される。従って、半導体基板101表面のボンディングパッドや、レーザートリミング、光検出素子への光透過などが必要な部分に樹脂が付着し、ボンディング不良等、半導体集積回路装置に対し様々な不具合が発生することを防止することが出来る。   The semiconductor substrate 101 is placed in the recess 106 of the mold 102 so that the surface on which the semiconductor integrated circuit device is formed faces downward on the paper surface and faces the bottom surface of the recess 106. Therefore, when the chemical solution 11 is filled in the outer peripheral portion of the semiconductor substrate 101 later, the surface of the semiconductor substrate 101 is not exposed and is firmly adhered to the bottom surface of the concave portion 106 by vacuum suction. Adhesion to the surface of the substrate 101 is suppressed. Accordingly, the resin adheres to bonding pads on the surface of the semiconductor substrate 101, laser trimming, light transmission to the light detection element, etc., and various problems occur in the semiconductor integrated circuit device such as bonding failure. Can be prevented.

一方、半導体基板101の裏面においては、その厚さが過剰に厚くなるほどでなければ薬液11が付着しても構わない。半導体基板101の裏面に薬液11が付着しても、半導体基板101の裏面の研削時に同時に除去されるので、半導体集積回路装置の機能を損なうようなことはない。   On the other hand, the chemical solution 11 may adhere to the back surface of the semiconductor substrate 101 unless the thickness is excessively increased. Even if the chemical solution 11 adheres to the back surface of the semiconductor substrate 101, it is removed at the time of grinding the back surface of the semiconductor substrate 101, so that the function of the semiconductor integrated circuit device is not impaired.

図4(a)、(b)は、半導体基板101の外周と型枠102の凹部106における内側面との間の隙間に薬液11を充填した後の面取り部104付近を拡大した断面図である。図4(a)に示すように、この隙間を全て薬液11で満たすと、半円弧状の面取り部104が薬液11で補われ、半導体基板101を含めた全体の断面形状が略長方形となる。このため、後の工程において半導体基板101を裏面から研削してもナイフエッジ形状が発生することはない。   4A and 4B are enlarged cross-sectional views of the vicinity of the chamfered portion 104 after the chemical liquid 11 is filled in the gap between the outer periphery of the semiconductor substrate 101 and the inner surface of the concave portion 106 of the mold 102. . As shown in FIG. 4A, when all the gaps are filled with the chemical solution 11, the semicircular chamfered portion 104 is supplemented with the chemical solution 11, and the entire cross-sectional shape including the semiconductor substrate 101 becomes a substantially rectangular shape. For this reason, even if the semiconductor substrate 101 is ground from the back surface in a later process, a knife edge shape does not occur.

本発明の実施形態における半導体装置及び半導体集積回路装置の製造方法の主要工程を表すフローチャートを図5に示す。図5に示すように、本発明の実施形態における半導体装置の製造方法は、半導体基板支持装置設置工程(S101)と薬液供給工程(S102)と薬液硬化工程(S103)と裏面研削工程(S104)という一連の工程を含む。本発明の実施形態における半導体集積回路の製造方法は、さらにダイシング工程(S105)を含む。   FIG. 5 is a flowchart showing the main steps of the semiconductor device and semiconductor integrated circuit device manufacturing method according to the embodiment of the present invention. As shown in FIG. 5, the semiconductor device manufacturing method according to the embodiment of the present invention includes a semiconductor substrate support device installation step (S101), a chemical solution supply step (S102), a chemical solution curing step (S103), and a back grinding step (S104). Including a series of steps. The method for manufacturing a semiconductor integrated circuit in the embodiment of the present invention further includes a dicing step (S105).

まず、半導体基板支持装置設置工程(S101)として、半導体集積回路装置が表面に形成され、外周に面取り部を備えた半導体基板101が凹部106に設置された型枠102を、回転ステージ16上に設置する。凹部106は、平面形状が半導体基板101と同様の円形形状と不連続形状を有しており、深さが半導体基板101の厚さと同一もしくはそれより浅い。半導体基板101は、その凹部106の底面に、半導体基板101において半導体集積回路装置が形成された表面を対向するように設置する。   First, as a semiconductor substrate support device installation step (S101), a mold 102 on which a semiconductor integrated circuit device is formed on the surface and a semiconductor substrate 101 having a chamfered portion on the outer periphery is installed in a recess 106 is placed on the rotary stage 16. Install. The recess 106 has a circular shape and a discontinuous shape similar to those of the semiconductor substrate 101 in the planar shape, and the depth is the same as or shallower than the thickness of the semiconductor substrate 101. The semiconductor substrate 101 is placed on the bottom surface of the recess 106 so that the surface of the semiconductor substrate 101 on which the semiconductor integrated circuit device is formed is opposed.

次に、薬液供給工程(S102)として、型枠102の凹部106の内側面と、半導体基板101の外周との間の隙間に薬液11を供給する。薬液11は、凹部106の内側面と、半導体基板101の外周との間の隙間に入り込む可塑性と、後の処理で半導体基板101と同程度の物理強度が得られる硬化性を併せ持つ樹脂等を採用する。薬液11は、型枠102の凹部106における外周の上部に設置された供給ノズル12から、回転ステージ16を回転させながら供給されることで、半導体基板101との隙間に満遍なく均一に充填される。   Next, as a chemical solution supply step (S <b> 102), the chemical solution 11 is supplied to the gap between the inner surface of the recess 106 of the mold 102 and the outer periphery of the semiconductor substrate 101. The chemical solution 11 employs a resin having both the plasticity that enters the gap between the inner side surface of the recess 106 and the outer periphery of the semiconductor substrate 101 and the curability that can obtain the same physical strength as the semiconductor substrate 101 in the subsequent processing. To do. The chemical solution 11 is supplied from the supply nozzle 12 installed at the upper part of the outer periphery of the concave portion 106 of the mold 102 while rotating the rotary stage 16, so that the gap between the chemical solution 11 and the semiconductor substrate 101 is uniformly filled.

薬液11の供給量の調整は、型枠102の凹部106の内側面と、半導体基板101の外周との間の隙間における薬液11の高さが検出できる液面センサを設置することで高精度に行う事ができる(不図示)。そしてその供給量は、半導体基板101の裏面の高さをやや越える程度までとする事が好ましい。このようにして薬液11を半導体基板101との隙間に充填した後に、供給ノズル12からの薬液11の供給を止め、回転ステージ16を回転し続けることで、その遠心力により半導体基板101の裏面上に残る薬液11を除去する。このようにすることで薬液供給工程終了後には、図4(a)に示すように、型枠102の凹部106の内側面と、半導体基板101の外周の面取り部104との間の隙間に薬液11が充填される。この薬液11は、面取り部104近傍において型枠102の内側面に沿った形状となる。すなわち、断面視において半導体基板101を含めた全体として略長方形の形状を形成する事ができる。また、紙面の上側となる半導体基板101の裏面には、薬液11は、残留しない。   The supply amount of the chemical solution 11 is adjusted with high accuracy by installing a liquid level sensor that can detect the height of the chemical solution 11 in the gap between the inner surface of the recess 106 of the mold 102 and the outer periphery of the semiconductor substrate 101. Can be done (not shown). The supply amount is preferably set to a level slightly exceeding the height of the back surface of the semiconductor substrate 101. After filling the chemical solution 11 in the gap with the semiconductor substrate 101 in this way, the supply of the chemical solution 11 from the supply nozzle 12 is stopped, and the rotary stage 16 is continuously rotated. The remaining chemical solution 11 is removed. In this way, after the chemical solution supply process is finished, as shown in FIG. 4A, the chemical solution is placed in the gap between the inner surface of the recess 106 of the mold 102 and the chamfered portion 104 on the outer periphery of the semiconductor substrate 101. 11 is filled. This chemical solution 11 has a shape along the inner surface of the mold 102 in the vicinity of the chamfered portion 104. That is, a substantially rectangular shape as a whole including the semiconductor substrate 101 can be formed in a cross-sectional view. Further, the chemical solution 11 does not remain on the back surface of the semiconductor substrate 101 which is the upper side of the paper surface.

次に、薬液硬化工程(S103)として、半導体基板101が設置された型枠102に対し加熱処理や紫外線照射等を行い、薬液11を半導体基板101と同程度の物理強度になるまで硬化させ、面取り補償部107を形成する。この加熱は、加熱された炉の中に設置する方法でもよく、ホットプレートに設置する方法でも構わない。またはレーザー照射による薬液11の部分のみの局所的な加熱でもよい。   Next, as a chemical solution curing step (S103), the mold 102 on which the semiconductor substrate 101 is installed is subjected to heat treatment, ultraviolet irradiation, etc., and the chemical solution 11 is cured until it has a physical strength comparable to that of the semiconductor substrate 101, A chamfer compensation unit 107 is formed. This heating may be a method of installing in a heated furnace or a method of installing on a hot plate. Or the local heating only of the part of the chemical | medical solution 11 by laser irradiation may be sufficient.

薬液11を硬化させた後は、面取り部104に面取り補償部107が固着した半導体基板101を、型枠102から取り外す。通常、樹脂からなる薬液11に熱を印加した場合、硬化させる過程で同時に体積収縮が発生し、型枠102の凹部106内側面から樹脂が内側に離れる。従って、その後に型枠102から、面取り補償部107が固着した半導体基板101を取り外すことは容易である。但し、シリカフィラーを含むプラスチック樹脂の場合は、シリカフィラーの含有割合が大きくなるほど体積収縮の発生が抑制される。その場合は、型枠102からの面取り補償部107の剥離を容易にするために樹脂を充填する前に離型剤を付加する等の対策を行っておくことが望ましい。この半導体装置10は、通常の半導体基板101と同様に処理することが出来る。   After the chemical solution 11 is cured, the semiconductor substrate 101 with the chamfering compensation unit 107 fixed to the chamfering unit 104 is removed from the mold 102. Usually, when heat is applied to the chemical solution 11 made of resin, volume shrinkage occurs simultaneously in the curing process, and the resin is separated from the inner surface of the concave portion 106 of the mold 102 to the inside. Therefore, after that, it is easy to remove the semiconductor substrate 101 to which the chamfering compensation portion 107 is fixed from the mold 102. However, in the case of a plastic resin containing a silica filler, the occurrence of volume shrinkage is suppressed as the silica filler content increases. In that case, it is desirable to take measures such as adding a release agent before filling the resin in order to facilitate the peeling of the chamfering compensation portion 107 from the mold 102. This semiconductor device 10 can be processed in the same manner as a normal semiconductor substrate 101.

次に、裏面研削工程(S104)として、半導体装置10を、裏面から研削し、所望の厚さまで薄くする。このとき、半導体装置10の断面視における外周の形状は略長方形形状となっているので、どのような厚さまで減じたとしてもナイフエッジ形状が発生することはない。   Next, as a back surface grinding step (S104), the semiconductor device 10 is ground from the back surface and thinned to a desired thickness. At this time, since the outer peripheral shape of the semiconductor device 10 in a cross-sectional view is a substantially rectangular shape, a knife edge shape does not occur even if the thickness is reduced to any thickness.

次に、半導体集積回路装置の製造のためのダイシング工程(S105)として、半導体装置10の、半導体集積回路装置が形成されている領域の間の領域をダイシングし、分割する。このとき、半導体基板101と同様に面取り補償部107がダイシングブレード等によって分割される。面取り補償部107は、半導体基板101と同様の物理強度を有するので、チッピングなどのダイシング不良が抑制される。この面取り補償部107は、半導体基板101の外周の残骸などとともにダイシング工程後に廃棄される。   Next, as a dicing step (S105) for manufacturing the semiconductor integrated circuit device, a region between the regions of the semiconductor device 10 where the semiconductor integrated circuit device is formed is diced and divided. At this time, like the semiconductor substrate 101, the chamfering compensation unit 107 is divided by a dicing blade or the like. Since the chamfering compensation unit 107 has the same physical strength as that of the semiconductor substrate 101, dicing defects such as chipping are suppressed. The chamfering compensation unit 107 is discarded after the dicing process together with debris on the outer periphery of the semiconductor substrate 101 and the like.

以上のような半導体装置及び半導体集積回路装置の製造方法を採用することで、半導体装置において、半導体基板101の裏面を研削した後のナイフエッジ形状の影響を面取り補償部107によって低減でき、半導体集積回路装置の亀裂や欠けによる品質低下を抑制できる。また半導体基板101の外周に面取り部104を加工するための余裕領域を確保する必要が無く、半導体集積回路装置を半導体基板101表面の外周にまで形成する事ができる。そのため、1枚の半導体基板から得られる半導体集積回路装置の個数を増加させ、半導体集積回路装置のコストの低減を実現できる。   By adopting the manufacturing method of the semiconductor device and the semiconductor integrated circuit device as described above, the influence of the knife edge shape after grinding the back surface of the semiconductor substrate 101 in the semiconductor device can be reduced by the chamfer compensation unit 107, and the semiconductor integrated Quality degradation due to cracks or chipping in the circuit device can be suppressed. Further, it is not necessary to secure a margin area for processing the chamfered portion 104 on the outer periphery of the semiconductor substrate 101, and the semiconductor integrated circuit device can be formed up to the outer periphery of the surface of the semiconductor substrate 101. Therefore, the number of semiconductor integrated circuit devices obtained from one semiconductor substrate can be increased, and the cost of the semiconductor integrated circuit device can be reduced.

本発明については、上記実施形態に限定されず、本発明の趣旨を逸脱しない範囲において種々の変更が可能であることは言うまでもない。   Needless to say, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

例えば、半導体装置の製造方法における薬液供給工程(S102)において、薬液11の供給量は、半導体基板101の裏面の高さをやや越える程度までとしたが、その方法に限られない。   For example, in the chemical solution supplying step (S102) in the method for manufacturing a semiconductor device, the supply amount of the chemical solution 11 is set to be slightly higher than the height of the back surface of the semiconductor substrate 101, but the method is not limited thereto.

図4(b)は、薬液11の供給量を、半導体基板101の厚さの半分をやや越える程度までとした場合の半導体基板101の外周の要部を示す断面図である。薬液11の供給量を減らすことで、材料コストを抑制することができる。一方、薬液11が充填されている半導体基板101の外周における面取り部104の下側表面において、薬液11が型枠102の凹部106の内側面の形状に沿った矩形の形状をなしている。そのため、半導体基板101の裏面研削において、半導体基板101の厚さの半分を越える量の研削を行っても、この矩形の薬液11を硬化させることによってできる面取り補償部107によってナイフエッジ形状が発生することはない。   FIG. 4B is a cross-sectional view showing the main part of the outer periphery of the semiconductor substrate 101 when the supply amount of the chemical solution 11 is set to a value slightly exceeding half of the thickness of the semiconductor substrate 101. By reducing the supply amount of the chemical solution 11, the material cost can be suppressed. On the other hand, on the lower surface of the chamfered portion 104 on the outer periphery of the semiconductor substrate 101 filled with the chemical solution 11, the chemical solution 11 has a rectangular shape along the shape of the inner surface of the recess 106 of the mold 102. Therefore, even when grinding of the back surface of the semiconductor substrate 101 is performed in an amount exceeding half of the thickness of the semiconductor substrate 101, a knife edge shape is generated by the chamfer compensator 107 which can be obtained by curing the rectangular chemical solution 11. There is nothing.

また、型枠102の凹部106は、半導体基板101の厚さと同一の深さであることが
好ましいとした。しかしながら、図4(b)のように薬液11の供給量を半導体基板101の裏面の高さまで充填しない場合は、その充填高さに応じて凹部106の深さを半導体基板101の厚さよりも浅くしても構わない。
In addition, the recess 106 of the mold 102 is preferably the same depth as the thickness of the semiconductor substrate 101. However, when the supply amount of the chemical solution 11 is not filled up to the height of the back surface of the semiconductor substrate 101 as shown in FIG. 4B, the depth of the recess 106 is shallower than the thickness of the semiconductor substrate 101 according to the filling height. It doesn't matter.

11 薬液
12 供給ノズル
13 バルブ
14 薬液供給装置
15 薬液タンク
16 回転ステージ
17 チャンバ
101、201 半導体基板
102 型枠
104、204 面取り部
105 不連続部分
106 凹部
107 面取り補償部
108 吸着穴
DESCRIPTION OF SYMBOLS 11 Chemical solution 12 Supply nozzle 13 Valve 14 Chemical solution supply apparatus 15 Chemical solution tank 16 Rotation stage 17 Chamber 101, 201 Semiconductor substrate 102 Mold frame 104, 204 Chamfer 105 Discontinuous part 106 Recess 107 Chamfer compensation part 108 Adsorption hole

Claims (6)

外周に面取り部を備えた半導体基板と、
前記面取り部の表面に備えられ、断面視において略長方形の形状をなすように形成された面取り補償部と、を有することを特徴とする半導体装置。
A semiconductor substrate having a chamfered portion on the outer periphery;
A chamfer compensator provided on a surface of the chamfered portion and formed to have a substantially rectangular shape in a cross-sectional view.
前記面取り補償部が、シリカフィラーを含む樹脂であることを特徴とする請求項1に記載の半導体装置。   The semiconductor device according to claim 1, wherein the chamfer compensation unit is a resin containing a silica filler. 半導体集積回路装置が表面に形成され外周に面取り部を備えた半導体基板を、凹部を有する半導体基板支持装置の前記凹部の底面に、前記半導体基板の表面が対向するように設置し、前記半導体基板支持装置の前記凹部の内側面と前記半導体基板の外周との間の隙間に薬液を供給する工程と、
前記薬液を硬化させ、断面視において略長方形の形状となすように面取り補償部を形成する工程と、
前記半導体基板の裏面を研削し、厚さを減じる工程と、を含むことを特徴とする半導体装置の製造方法。
A semiconductor substrate having a semiconductor integrated circuit device formed on the surface and having a chamfered portion on the outer periphery is placed on the bottom surface of the recess of the semiconductor substrate support device having a recess so that the surface of the semiconductor substrate faces the semiconductor substrate. Supplying a chemical to the gap between the inner surface of the recess of the support device and the outer periphery of the semiconductor substrate;
Curing the chemical solution and forming a chamfering compensation portion so as to have a substantially rectangular shape in cross-sectional view;
Grinding the back surface of the semiconductor substrate to reduce the thickness, and a method for manufacturing a semiconductor device.
前記薬液がシリカフィラーを含む樹脂であり、前記薬液に対し熱の印加を行うことよって硬化させることを特徴とする請求項3に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 3, wherein the chemical solution is a resin containing a silica filler and is cured by applying heat to the chemical solution. 前記薬液が熱硬化付与型紫外線樹脂であり、前記薬液に対し熱の印加と紫外線照射を行うことによって硬化させること特徴とする請求項3に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 3, wherein the chemical solution is a thermosetting imparting ultraviolet resin, and the chemical solution is cured by applying heat and irradiating with ultraviolet rays. 前記半導体装置の表面の前記半導体集積回路が形成されている領域の間の領域をダイシングする工程と、を含むことを特徴とする請求項3乃至5のいずれか一項に記載の半導体集積回路装置の製造方法。   6. A semiconductor integrated circuit device according to claim 3, further comprising a step of dicing a region between the regions where the semiconductor integrated circuit is formed on the surface of the semiconductor device. Manufacturing method.
JP2018052937A 2018-03-20 2018-03-20 Semiconductor device, semiconductor device manufacturing method, and semiconductor integrated circuit device manufacturing method Pending JP2019165152A (en)

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